FEC: Allow multiple FECes
This patch allows user to register multiple FEC controllers. To preserve compatibility with older boards, the mxcfec_register() call is still in place. To use multiple controllers, new macro is in place, the mxcfec_register_multi(), which takes more arguments. The syntax is: mxcfec_register_multi(bd, FEC ID, FEC PHY ID on the MII bus, base address); To disable the fecmxc_register() compatibility stuff, define the macro CONFIG_FEC_MXC_MULTI. This will remove the requirement for defining IMX_FEC_BASE and CONFIG_FEC_MXC_PHYADDR. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Marek Vasut
Albert ARIBAUD
parent
d133b881b9
commit
9e27e9dca1
@ -51,18 +51,6 @@ struct nbuf {
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uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
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};
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struct fec_priv gfec = {
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.eth = (struct ethernet_regs *)IMX_FEC_BASE,
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.xcv_type = MII100,
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.rbd_base = NULL,
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.rbd_index = 0,
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.tbd_base = NULL,
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.tbd_index = 0,
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.bd = NULL,
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.rdb_ptr = NULL,
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.base_ptr = NULL,
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};
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/*
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* MII-interface related functions
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*/
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@ -164,26 +152,27 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
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static int miiphy_restart_aneg(struct eth_device *dev)
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{
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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/*
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* Wake up from sleep if necessary
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* Reset PHY, then delay 300ns
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*/
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#ifdef CONFIG_MX27
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF);
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miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
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#endif
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
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miiphy_write(dev->name, fec->phy_id, MII_BMCR,
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BMCR_RESET);
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udelay(1000);
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE,
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miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
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miiphy_write(dev->name, fec->phy_id, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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return 0;
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}
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@ -191,6 +180,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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{
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uint32_t start;
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uint16_t status;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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/*
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* Wait for AN completion
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@ -202,7 +192,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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return -1;
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}
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if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
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if (miiphy_read(dev->name, fec->phy_id,
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MII_BMSR, &status)) {
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printf("%s: Autonegotiation failed. status: 0x%04x\n",
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dev->name, status);
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@ -390,8 +380,8 @@ static int fec_open(struct eth_device *edev)
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#endif
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miiphy_wait_aneg(edev);
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miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
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miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
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miiphy_speed(edev->name, fec->phy_id);
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miiphy_duplex(edev->name, fec->phy_id);
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/*
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* Enable SmartDMA receive task
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@ -406,7 +396,9 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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{
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uint32_t base;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
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uint32_t rcntrl;
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int i;
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/* Initialize MAC address */
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fec_set_hwaddr(dev);
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@ -477,9 +469,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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/* clear MIB RAM */
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long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
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while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
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*mib_ptr++ = 0;
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for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
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writel(0, i);
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/* FIFO receive start register */
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writel(0x520, &fec->eth->r_fstart);
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@ -513,7 +504,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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*/
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static void fec_halt(struct eth_device *dev)
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{
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struct fec_priv *fec = &gfec;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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int counter = 0xffff;
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/*
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@ -694,19 +685,28 @@ static int fec_recv(struct eth_device *dev)
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return len;
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}
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static int fec_probe(bd_t *bd)
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static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
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{
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struct eth_device *edev;
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struct fec_priv *fec = &gfec;
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struct fec_priv *fec;
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unsigned char ethaddr[6];
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/* create and fill edev struct */
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edev = (struct eth_device *)malloc(sizeof(struct eth_device));
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if (!edev) {
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puts("fec_mxc: not enough malloc memory\n");
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puts("fec_mxc: not enough malloc memory for eth_device\n");
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return -ENOMEM;
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}
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fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
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if (!fec) {
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puts("fec_mxc: not enough malloc memory for fec_priv\n");
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return -ENOMEM;
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}
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memset(edev, 0, sizeof(*edev));
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memset(fec, 0, sizeof(*fec));
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edev->priv = fec;
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edev->init = fec_init;
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edev->send = fec_send;
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@ -714,7 +714,7 @@ static int fec_probe(bd_t *bd)
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edev->halt = fec_halt;
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edev->write_hwaddr = fec_set_hwaddr;
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fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
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fec->eth = (struct ethernet_regs *)base_addr;
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fec->bd = bd;
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fec->xcv_type = CONFIG_FEC_XCV_TYPE;
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@ -744,7 +744,14 @@ static int fec_probe(bd_t *bd)
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FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
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fec_mii_setspeed(fec);
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sprintf(edev->name, "FEC");
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if (dev_id == -1) {
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sprintf(edev->name, "FEC");
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fec->dev_id = 0;
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} else {
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sprintf(edev->name, "FEC%i", dev_id);
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fec->dev_id = dev_id;
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}
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fec->phy_id = phy_id;
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miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
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@ -758,12 +765,24 @@ static int fec_probe(bd_t *bd)
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return 0;
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}
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#ifndef CONFIG_FEC_MXC_MULTI
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int fecmxc_initialize(bd_t *bd)
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{
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int lout = 1;
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debug("eth_init: fec_probe(bd)\n");
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lout = fec_probe(bd);
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lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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return lout;
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}
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#endif
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int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
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{
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int lout = 1;
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debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
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lout = fec_probe(bd, dev_id, phy_id, addr);
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return lout;
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}
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@ -275,6 +275,8 @@ struct fec_priv {
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bd_t *bd;
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void *rdb_ptr;
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void *base_ptr;
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int dev_id;
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int phy_id;
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};
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/**
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@ -61,8 +61,8 @@ int ep93xx_eth_initialize(u8 dev_num, int base_addr);
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int eth_3com_initialize (bd_t * bis);
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int ethoc_initialize(u8 dev_num, int base_addr);
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int fec_initialize (bd_t *bis);
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int fecmxc_initialize (bd_t *bis);
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int fecmxc_initialize(bd_t *bis);
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int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
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int ftgmac100_initialize(bd_t *bits);
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int ftmac100_initialize(bd_t *bits);
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int greth_initialize(bd_t *bis);
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