qe: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
2098a3b8fe
commit
9e0bcf8043
@ -2,6 +2,6 @@
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#
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# Copyright (C) 2006 Freescale Semiconductor, Inc.
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obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
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obj-$(CONFIG_QE) += qe.o
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obj-$(CONFIG_U_QE) += qe.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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@ -1,509 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/immap_qe.h>
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#include "uccf.h"
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#include <fsl_qe.h>
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#if !defined(CONFIG_DM_ETH)
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void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
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{
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out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
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}
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u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
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{
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switch (ucc_num) {
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case 0:
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return QE_CR_SUBBLOCK_UCCFAST1;
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case 1:
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return QE_CR_SUBBLOCK_UCCFAST2;
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case 2:
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return QE_CR_SUBBLOCK_UCCFAST3;
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case 3:
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return QE_CR_SUBBLOCK_UCCFAST4;
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case 4:
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return QE_CR_SUBBLOCK_UCCFAST5;
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case 5:
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return QE_CR_SUBBLOCK_UCCFAST6;
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case 6:
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return QE_CR_SUBBLOCK_UCCFAST7;
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case 7:
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return QE_CR_SUBBLOCK_UCCFAST8;
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default:
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return QE_CR_SUBBLOCK_INVALID;
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}
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}
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static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
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u8 *reg_num, u8 *shift)
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{
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switch (ucc_num) {
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case 0: /* UCC1 */
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*p_cmxucr = &qe_immr->qmx.cmxucr1;
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*reg_num = 1;
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*shift = 16;
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break;
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case 2: /* UCC3 */
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*p_cmxucr = &qe_immr->qmx.cmxucr1;
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*reg_num = 1;
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*shift = 0;
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break;
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case 4: /* UCC5 */
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*p_cmxucr = &qe_immr->qmx.cmxucr2;
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*reg_num = 2;
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*shift = 16;
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break;
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case 6: /* UCC7 */
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*p_cmxucr = &qe_immr->qmx.cmxucr2;
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*reg_num = 2;
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*shift = 0;
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break;
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case 1: /* UCC2 */
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*p_cmxucr = &qe_immr->qmx.cmxucr3;
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*reg_num = 3;
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*shift = 16;
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break;
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case 3: /* UCC4 */
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*p_cmxucr = &qe_immr->qmx.cmxucr3;
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*reg_num = 3;
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*shift = 0;
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break;
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case 5: /* UCC6 */
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*p_cmxucr = &qe_immr->qmx.cmxucr4;
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*reg_num = 4;
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*shift = 16;
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break;
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case 7: /* UCC8 */
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*p_cmxucr = &qe_immr->qmx.cmxucr4;
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*reg_num = 4;
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*shift = 0;
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break;
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default:
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break;
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}
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}
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static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
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{
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u32 *p_cmxucr = NULL;
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u8 reg_num = 0;
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u8 shift = 0;
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u32 clk_bits;
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u32 clk_mask;
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int source = -1;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
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return -EINVAL;
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if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
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printf("%s: bad comm mode type passed\n", __func__);
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return -EINVAL;
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}
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ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
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switch (reg_num) {
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case 1:
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switch (clock) {
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case QE_BRG1:
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source = 1;
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break;
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case QE_BRG2:
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source = 2;
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break;
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case QE_BRG7:
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source = 3;
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break;
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case QE_BRG8:
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source = 4;
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break;
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case QE_CLK9:
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source = 5;
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break;
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case QE_CLK10:
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source = 6;
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break;
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case QE_CLK11:
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source = 7;
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break;
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case QE_CLK12:
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source = 8;
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break;
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case QE_CLK15:
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source = 9;
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break;
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case QE_CLK16:
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source = 10;
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break;
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default:
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source = -1;
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break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_BRG5:
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source = 1;
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break;
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case QE_BRG6:
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source = 2;
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break;
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case QE_BRG7:
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source = 3;
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break;
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case QE_BRG8:
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source = 4;
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break;
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case QE_CLK13:
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source = 5;
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break;
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case QE_CLK14:
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source = 6;
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break;
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case QE_CLK19:
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source = 7;
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break;
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case QE_CLK20:
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source = 8;
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break;
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case QE_CLK15:
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source = 9;
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break;
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case QE_CLK16:
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source = 10;
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break;
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default:
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source = -1;
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break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_BRG9:
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source = 1;
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break;
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case QE_BRG10:
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source = 2;
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break;
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case QE_BRG15:
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source = 3;
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break;
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case QE_BRG16:
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source = 4;
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break;
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case QE_CLK3:
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source = 5;
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break;
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case QE_CLK4:
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source = 6;
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break;
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case QE_CLK17:
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source = 7;
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break;
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case QE_CLK18:
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source = 8;
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break;
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case QE_CLK7:
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source = 9;
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break;
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case QE_CLK8:
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source = 10;
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break;
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case QE_CLK16:
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source = 11;
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break;
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default:
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source = -1;
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break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_BRG13:
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source = 1;
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break;
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case QE_BRG14:
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source = 2;
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break;
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case QE_BRG15:
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source = 3;
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break;
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case QE_BRG16:
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source = 4;
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break;
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case QE_CLK5:
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source = 5;
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break;
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case QE_CLK6:
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source = 6;
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break;
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case QE_CLK21:
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source = 7;
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break;
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case QE_CLK22:
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source = 8;
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break;
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case QE_CLK7:
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source = 9;
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break;
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case QE_CLK8:
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source = 10;
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break;
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case QE_CLK16:
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source = 11;
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break;
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default:
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source = -1;
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break;
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}
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break;
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default:
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source = -1;
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break;
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}
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if (source == -1) {
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printf("%s: Bad combination of clock and UCC\n", __func__);
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return -ENOENT;
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}
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clk_bits = (u32)source;
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clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
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if (mode == COMM_DIR_RX) {
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clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
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clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
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}
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clk_bits <<= shift;
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clk_mask <<= shift;
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out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
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return 0;
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}
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static uint ucc_get_reg_baseaddr(int ucc_num)
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{
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uint base = 0;
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/* check if the UCC number is in range */
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if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
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printf("%s: the UCC num not in ranges\n", __func__);
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return 0;
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}
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switch (ucc_num) {
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case 0:
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base = 0x00002000;
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break;
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case 1:
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base = 0x00003000;
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break;
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case 2:
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base = 0x00002200;
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break;
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case 3:
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base = 0x00003200;
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break;
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case 4:
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base = 0x00002400;
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break;
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case 5:
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base = 0x00003400;
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break;
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case 6:
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base = 0x00002600;
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break;
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case 7:
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base = 0x00003600;
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break;
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default:
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break;
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}
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base = (uint)qe_immr + base;
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return base;
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}
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void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
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{
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ucc_fast_t *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Enable reception and/or transmission on this UCC. */
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gumr = in_be32(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr |= UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 1;
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}
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if (mode & COMM_DIR_RX) {
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gumr |= UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 1;
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}
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out_be32(&uf_regs->gumr, gumr);
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}
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void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
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{
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ucc_fast_t *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Disable reception and/or transmission on this UCC. */
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gumr = in_be32(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr &= ~UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 0;
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}
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if (mode & COMM_DIR_RX) {
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gumr &= ~UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 0;
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}
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out_be32(&uf_regs->gumr, gumr);
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}
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int ucc_fast_init(struct ucc_fast_inf *uf_info,
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struct ucc_fast_priv **uccf_ret)
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{
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struct ucc_fast_priv *uccf;
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ucc_fast_t *uf_regs;
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if (!uf_info)
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return -EINVAL;
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if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
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printf("%s: Illagal UCC number!\n", __func__);
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return -EINVAL;
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}
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uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
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if (!uccf) {
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printf("%s: No memory for UCC fast data structure!\n",
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__func__);
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return -ENOMEM;
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}
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memset(uccf, 0, sizeof(struct ucc_fast_priv));
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/* Save fast UCC structure */
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uccf->uf_info = uf_info;
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uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
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if (!uccf->uf_regs) {
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printf("%s: No memory map for UCC fast controller!\n",
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__func__);
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return -ENOMEM;
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}
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uccf->enabled_tx = 0;
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uccf->enabled_rx = 0;
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uf_regs = uccf->uf_regs;
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uccf->p_ucce = (u32 *)&uf_regs->ucce;
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uccf->p_uccm = (u32 *)&uf_regs->uccm;
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/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
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out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
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| UCC_GUEMR_MODE_FAST_TX);
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/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
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out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
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/* Set the Giga ethernet VFIFO stuff */
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if (uf_info->eth_type == GIGA_ETH) {
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/* Allocate memory for Tx Virtual Fifo */
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uccf->ucc_fast_tx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* Allocate memory for Rx Virtual Fifo */
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uccf->ucc_fast_rx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
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UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* utfb, urfb are offsets from MURAM base */
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out_be32(&uf_regs->utfb,
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uccf->ucc_fast_tx_virtual_fifo_base_offset);
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out_be32(&uf_regs->urfb,
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uccf->ucc_fast_rx_virtual_fifo_base_offset);
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/* Set Virtual Fifo registers */
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out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
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out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
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out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
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out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
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out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
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out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
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}
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/* Set the Fast ethernet VFIFO stuff */
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if (uf_info->eth_type == FAST_ETH) {
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/* Allocate memory for Tx Virtual Fifo */
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uccf->ucc_fast_tx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_UTFS_INIT,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* Allocate memory for Rx Virtual Fifo */
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uccf->ucc_fast_rx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_URFS_INIT +
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UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* utfb, urfb are offsets from MURAM base */
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out_be32(&uf_regs->utfb,
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uccf->ucc_fast_tx_virtual_fifo_base_offset);
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out_be32(&uf_regs->urfb,
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uccf->ucc_fast_rx_virtual_fifo_base_offset);
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/* Set Virtual Fifo registers */
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out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
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out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
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out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
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out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
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out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
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out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
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}
|
||||
|
||||
/* Rx clock routing */
|
||||
if (uf_info->rx_clock != QE_CLK_NONE) {
|
||||
if (ucc_set_clk_src(uf_info->ucc_num,
|
||||
uf_info->rx_clock, COMM_DIR_RX)) {
|
||||
printf("%s: Illegal value for parameter 'RxClock'.\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Tx clock routing */
|
||||
if (uf_info->tx_clock != QE_CLK_NONE) {
|
||||
if (ucc_set_clk_src(uf_info->ucc_num,
|
||||
uf_info->tx_clock, COMM_DIR_TX)) {
|
||||
printf("%s: Illegal value for parameter 'TxClock'.\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear interrupt mask register to disable all of interrupts */
|
||||
out_be32(&uf_regs->uccm, 0x0);
|
||||
|
||||
/* Writing '1' to clear all of envents */
|
||||
out_be32(&uf_regs->ucce, 0xffffffff);
|
||||
|
||||
*uccf_ret = uccf;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -1,119 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
* based on source code of Shlomi Gridish
|
||||
*/
|
||||
|
||||
#ifndef __UCCF_H__
|
||||
#define __UCCF_H__
|
||||
|
||||
#include "common.h"
|
||||
#include "linux/immap_qe.h"
|
||||
#include <fsl_qe.h>
|
||||
|
||||
/* Fast or Giga ethernet */
|
||||
enum enet_type {
|
||||
FAST_ETH,
|
||||
GIGA_ETH,
|
||||
};
|
||||
|
||||
/* General UCC Extended Mode Register */
|
||||
#define UCC_GUEMR_MODE_MASK_RX 0x02
|
||||
#define UCC_GUEMR_MODE_MASK_TX 0x01
|
||||
#define UCC_GUEMR_MODE_FAST_RX 0x02
|
||||
#define UCC_GUEMR_MODE_FAST_TX 0x01
|
||||
#define UCC_GUEMR_MODE_SLOW_RX 0x00
|
||||
#define UCC_GUEMR_MODE_SLOW_TX 0x00
|
||||
/* Bit 3 must be set 1 */
|
||||
#define UCC_GUEMR_SET_RESERVED3 0x10
|
||||
|
||||
/* General UCC FAST Mode Register */
|
||||
#define UCC_FAST_GUMR_TCI 0x20000000
|
||||
#define UCC_FAST_GUMR_TRX 0x10000000
|
||||
#define UCC_FAST_GUMR_TTX 0x08000000
|
||||
#define UCC_FAST_GUMR_CDP 0x04000000
|
||||
#define UCC_FAST_GUMR_CTSP 0x02000000
|
||||
#define UCC_FAST_GUMR_CDS 0x01000000
|
||||
#define UCC_FAST_GUMR_CTSS 0x00800000
|
||||
#define UCC_FAST_GUMR_TXSY 0x00020000
|
||||
#define UCC_FAST_GUMR_RSYN 0x00010000
|
||||
#define UCC_FAST_GUMR_RTSM 0x00002000
|
||||
#define UCC_FAST_GUMR_REVD 0x00000400
|
||||
#define UCC_FAST_GUMR_ENR 0x00000020
|
||||
#define UCC_FAST_GUMR_ENT 0x00000010
|
||||
|
||||
/* GUMR [MODE] bit maps */
|
||||
#define UCC_FAST_GUMR_HDLC 0x00000000
|
||||
#define UCC_FAST_GUMR_QMC 0x00000002
|
||||
#define UCC_FAST_GUMR_UART 0x00000004
|
||||
#define UCC_FAST_GUMR_BISYNC 0x00000008
|
||||
#define UCC_FAST_GUMR_ATM 0x0000000a
|
||||
#define UCC_FAST_GUMR_ETH 0x0000000c
|
||||
|
||||
/* Transmit On Demand (UTORD) */
|
||||
#define UCC_SLOW_TOD 0x8000
|
||||
#define UCC_FAST_TOD 0x8000
|
||||
|
||||
/* Fast Ethernet (10/100 Mbps) */
|
||||
/* Rx virtual FIFO size */
|
||||
#define UCC_GETH_URFS_INIT 512
|
||||
/* 1/2 urfs */
|
||||
#define UCC_GETH_URFET_INIT 256
|
||||
/* 3/4 urfs */
|
||||
#define UCC_GETH_URFSET_INIT 384
|
||||
/* Tx virtual FIFO size */
|
||||
#define UCC_GETH_UTFS_INIT 512
|
||||
/* 1/2 utfs */
|
||||
#define UCC_GETH_UTFET_INIT 256
|
||||
#define UCC_GETH_UTFTT_INIT 128
|
||||
|
||||
/* Gigabit Ethernet (1000 Mbps) */
|
||||
/* Rx virtual FIFO size */
|
||||
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
|
||||
/* 1/2 urfs */
|
||||
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
|
||||
/* 3/4 urfs */
|
||||
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
|
||||
/* Tx virtual FIFO size */
|
||||
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
|
||||
/* 1/2 utfs */
|
||||
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
|
||||
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
|
||||
|
||||
/* UCC fast alignment */
|
||||
#define UCC_FAST_RX_ALIGN 4
|
||||
#define UCC_FAST_MRBLR_ALIGNMENT 4
|
||||
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
|
||||
|
||||
/* Sizes */
|
||||
#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
|
||||
|
||||
/* UCC fast structure. */
|
||||
struct ucc_fast_inf {
|
||||
int ucc_num;
|
||||
qe_clock_e rx_clock;
|
||||
qe_clock_e tx_clock;
|
||||
enum enet_type eth_type;
|
||||
};
|
||||
|
||||
struct ucc_fast_priv {
|
||||
struct ucc_fast_inf *uf_info;
|
||||
ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
|
||||
u32 *p_ucce; /* a pointer to the event register */
|
||||
u32 *p_uccm; /* a pointer to the mask register */
|
||||
int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
|
||||
int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
|
||||
u32 ucc_fast_tx_virtual_fifo_base_offset;
|
||||
u32 ucc_fast_rx_virtual_fifo_base_offset;
|
||||
};
|
||||
|
||||
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
|
||||
u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
|
||||
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
|
||||
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
|
||||
int ucc_fast_init(struct ucc_fast_inf *uf_info,
|
||||
struct ucc_fast_priv **uccf_ret);
|
||||
|
||||
#endif /* __UCCF_H__ */
|
||||
1436
drivers/qe/uec.c
1436
drivers/qe/uec.c
File diff suppressed because it is too large
Load Diff
692
drivers/qe/uec.h
692
drivers/qe/uec.h
@ -1,692 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
* based on source code of Shlomi Gridish
|
||||
*/
|
||||
|
||||
#ifndef __UEC_H__
|
||||
#define __UEC_H__
|
||||
|
||||
#include "uccf.h"
|
||||
#include <fsl_qe.h>
|
||||
#include <phy.h>
|
||||
|
||||
#define MAX_TX_THREADS 8
|
||||
#define MAX_RX_THREADS 8
|
||||
#define MAX_TX_QUEUES 8
|
||||
#define MAX_RX_QUEUES 8
|
||||
#define MAX_PREFETCHED_BDS 4
|
||||
#define MAX_IPH_OFFSET_ENTRY 8
|
||||
#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
|
||||
#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
|
||||
|
||||
/* UEC UPSMR (Protocol Specific Mode Register)
|
||||
*/
|
||||
#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
|
||||
#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
|
||||
#define UPSMR_PRO 0x00400000 /* Promiscuous */
|
||||
#define UPSMR_CAP 0x00200000 /* CAM polarity */
|
||||
#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
|
||||
#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
|
||||
#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
|
||||
#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
|
||||
#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
|
||||
#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
|
||||
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
|
||||
#define UPSMR_BRO 0x00000200 /* Broadcast Address */
|
||||
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
|
||||
#define UPSMR_SGMM 0x00000020 /* SGMII mode */
|
||||
|
||||
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
|
||||
|
||||
/* UEC MACCFG1 (MAC Configuration 1 Register)
|
||||
*/
|
||||
#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
|
||||
#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
|
||||
#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
|
||||
#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
|
||||
#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
|
||||
#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
|
||||
|
||||
#define MACCFG1_INIT_VALUE (0)
|
||||
|
||||
/* UEC MACCFG2 (MAC Configuration 2 Register)
|
||||
*/
|
||||
#define MACCFG2_PREL 0x00007000
|
||||
#define MACCFG2_PREL_SHIFT (31 - 19)
|
||||
#define MACCFG2_PREL_MASK 0x0000f000
|
||||
#define MACCFG2_SRP 0x00000080
|
||||
#define MACCFG2_STP 0x00000040
|
||||
#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
|
||||
#define MACCFG2_LC 0x00000010 /* Length Check */
|
||||
#define MACCFG2_MPE 0x00000008
|
||||
#define MACCFG2_FDX 0x00000001 /* Full Duplex */
|
||||
#define MACCFG2_FDX_MASK 0x00000001
|
||||
#define MACCFG2_PAD_CRC 0x00000004
|
||||
#define MACCFG2_CRC_EN 0x00000002
|
||||
#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
|
||||
#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
|
||||
#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
|
||||
#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
|
||||
#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
|
||||
#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
|
||||
|
||||
#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
|
||||
MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
|
||||
|
||||
/* UEC Event Register */
|
||||
#define UCCE_MPD 0x80000000
|
||||
#define UCCE_SCAR 0x40000000
|
||||
#define UCCE_GRA 0x20000000
|
||||
#define UCCE_CBPR 0x10000000
|
||||
#define UCCE_BSY 0x08000000
|
||||
#define UCCE_RXC 0x04000000
|
||||
#define UCCE_TXC 0x02000000
|
||||
#define UCCE_TXE 0x01000000
|
||||
#define UCCE_TXB7 0x00800000
|
||||
#define UCCE_TXB6 0x00400000
|
||||
#define UCCE_TXB5 0x00200000
|
||||
#define UCCE_TXB4 0x00100000
|
||||
#define UCCE_TXB3 0x00080000
|
||||
#define UCCE_TXB2 0x00040000
|
||||
#define UCCE_TXB1 0x00020000
|
||||
#define UCCE_TXB0 0x00010000
|
||||
#define UCCE_RXB7 0x00008000
|
||||
#define UCCE_RXB6 0x00004000
|
||||
#define UCCE_RXB5 0x00002000
|
||||
#define UCCE_RXB4 0x00001000
|
||||
#define UCCE_RXB3 0x00000800
|
||||
#define UCCE_RXB2 0x00000400
|
||||
#define UCCE_RXB1 0x00000200
|
||||
#define UCCE_RXB0 0x00000100
|
||||
#define UCCE_RXF7 0x00000080
|
||||
#define UCCE_RXF6 0x00000040
|
||||
#define UCCE_RXF5 0x00000020
|
||||
#define UCCE_RXF4 0x00000010
|
||||
#define UCCE_RXF3 0x00000008
|
||||
#define UCCE_RXF2 0x00000004
|
||||
#define UCCE_RXF1 0x00000002
|
||||
#define UCCE_RXF0 0x00000001
|
||||
|
||||
#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
|
||||
UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
|
||||
#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
|
||||
UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
|
||||
#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
|
||||
UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
|
||||
#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
|
||||
UCCE_RXC | UCCE_TXC | UCCE_TXE)
|
||||
|
||||
/* UEC TEMODR Register */
|
||||
#define TEMODER_SCHEDULER_ENABLE 0x2000
|
||||
#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
|
||||
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
|
||||
#define TEMODER_RMON_STATISTICS 0x0100
|
||||
#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
|
||||
|
||||
#define TEMODER_INIT_VALUE 0xc000
|
||||
|
||||
/* UEC REMODR Register */
|
||||
#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
|
||||
#define REMODER_RX_EXTENDED_FEATURES 0x80000000
|
||||
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
|
||||
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
|
||||
#define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
|
||||
#define REMODER_RMON_STATISTICS 0x00001000
|
||||
#define REMODER_RX_EXTENDED_FILTERING 0x00000800
|
||||
#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
|
||||
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
|
||||
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
|
||||
#define REMODER_IP_CHECKSUM_CHECK 0x00000002
|
||||
#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
|
||||
|
||||
#define REMODER_INIT_VALUE 0
|
||||
|
||||
/* BMRx - Bus Mode Register */
|
||||
#define BMR_GLB 0x20
|
||||
#define BMR_BO_BE 0x10
|
||||
#define BMR_DTB_SECONDARY_BUS 0x02
|
||||
#define BMR_BDB_SECONDARY_BUS 0x01
|
||||
|
||||
#define BMR_SHIFT 24
|
||||
#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
|
||||
|
||||
/* UEC UCCS (Ethernet Status Register)
|
||||
*/
|
||||
#define UCCS_BPR 0x02
|
||||
#define UCCS_PAU 0x02
|
||||
#define UCCS_MPD 0x01
|
||||
|
||||
/* UEC MIIMCFG (MII Management Configuration Register)
|
||||
*/
|
||||
#define MIIMCFG_RESET_MANAGEMENT 0x80000000
|
||||
#define MIIMCFG_NO_PREAMBLE 0x00000010
|
||||
#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
|
||||
#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
|
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
|
||||
|
||||
#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
|
||||
MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
|
||||
|
||||
/* UEC MIIMCOM (MII Management Command Register)
|
||||
*/
|
||||
#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
|
||||
#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
|
||||
|
||||
/* UEC MIIMADD (MII Management Address Register)
|
||||
*/
|
||||
#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
|
||||
#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
|
||||
|
||||
/* UEC MIIMCON (MII Management Control Register)
|
||||
*/
|
||||
#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
|
||||
#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
|
||||
|
||||
/* UEC MIIMIND (MII Management Indicator Register)
|
||||
*/
|
||||
#define MIIMIND_NOT_VALID 0x00000004
|
||||
#define MIIMIND_SCAN 0x00000002
|
||||
#define MIIMIND_BUSY 0x00000001
|
||||
|
||||
/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
|
||||
*/
|
||||
#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
|
||||
#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
|
||||
|
||||
/* UEC UESCR (Ethernet Statistics Control Register)
|
||||
*/
|
||||
#define UESCR_AUTOZ 0x8000
|
||||
#define UESCR_CLRCNT 0x4000
|
||||
#define UESCR_MAXCOV_SHIFT (15 - 7)
|
||||
#define UESCR_SCOV_SHIFT (15 - 15)
|
||||
|
||||
/****** Tx data struct collection ******/
|
||||
/* Tx thread data, each Tx thread has one this struct. */
|
||||
struct uec_thread_data_tx {
|
||||
u8 res0[136];
|
||||
} __packed;
|
||||
|
||||
/* Tx thread parameter, each Tx thread has one this struct. */
|
||||
struct uec_thread_tx_pram {
|
||||
u8 res0[64];
|
||||
} __packed;
|
||||
|
||||
/* Send queue queue-descriptor, each Tx queue has one this QD */
|
||||
struct uec_send_queue_qd {
|
||||
u32 bd_ring_base; /* pointer to BD ring base address */
|
||||
u8 res0[0x8];
|
||||
u32 last_bd_completed_address; /* last entry in BD ring */
|
||||
u8 res1[0x30];
|
||||
} __packed;
|
||||
|
||||
/* Send queue memory region */
|
||||
struct uec_send_queue_mem_region {
|
||||
struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
|
||||
} __packed;
|
||||
|
||||
/* Scheduler struct */
|
||||
struct uec_scheduler {
|
||||
u16 cpucount0; /* CPU packet counter */
|
||||
u16 cpucount1; /* CPU packet counter */
|
||||
u16 cecount0; /* QE packet counter */
|
||||
u16 cecount1; /* QE packet counter */
|
||||
u16 cpucount2; /* CPU packet counter */
|
||||
u16 cpucount3; /* CPU packet counter */
|
||||
u16 cecount2; /* QE packet counter */
|
||||
u16 cecount3; /* QE packet counter */
|
||||
u16 cpucount4; /* CPU packet counter */
|
||||
u16 cpucount5; /* CPU packet counter */
|
||||
u16 cecount4; /* QE packet counter */
|
||||
u16 cecount5; /* QE packet counter */
|
||||
u16 cpucount6; /* CPU packet counter */
|
||||
u16 cpucount7; /* CPU packet counter */
|
||||
u16 cecount6; /* QE packet counter */
|
||||
u16 cecount7; /* QE packet counter */
|
||||
u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
|
||||
u32 rtsrshadow; /* temporary variable handled by QE */
|
||||
u32 time; /* temporary variable handled by QE */
|
||||
u32 ttl; /* temporary variable handled by QE */
|
||||
u32 mblinterval; /* max burst length interval */
|
||||
u16 nortsrbytetime; /* normalized value of byte time in tsr units */
|
||||
u8 fracsiz;
|
||||
u8 res0[1];
|
||||
u8 strictpriorityq; /* Strict Priority Mask register */
|
||||
u8 txasap; /* Transmit ASAP register */
|
||||
u8 extrabw; /* Extra BandWidth register */
|
||||
u8 oldwfqmask; /* temporary variable handled by QE */
|
||||
u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
|
||||
u32 minw; /* temporary variable handled by QE */
|
||||
u8 res1[0x70 - 0x64];
|
||||
} __packed;
|
||||
|
||||
/* Tx firmware counters */
|
||||
struct uec_tx_firmware_statistics_pram {
|
||||
u32 sicoltx; /* single collision */
|
||||
u32 mulcoltx; /* multiple collision */
|
||||
u32 latecoltxfr; /* late collision */
|
||||
u32 frabortduecol; /* frames aborted due to tx collision */
|
||||
u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
|
||||
u32 carriersenseertx; /* carrier sense error */
|
||||
u32 frtxok; /* frames transmitted OK */
|
||||
u32 txfrexcessivedefer;
|
||||
u32 txpkts256; /* total packets(including bad) 256~511 B */
|
||||
u32 txpkts512; /* total packets(including bad) 512~1023B */
|
||||
u32 txpkts1024; /* total packets(including bad) 1024~1518B */
|
||||
u32 txpktsjumbo; /* total packets(including bad) >1024 */
|
||||
} __packed;
|
||||
|
||||
/* Tx global parameter table */
|
||||
struct uec_tx_global_pram {
|
||||
u16 temoder;
|
||||
u8 res0[0x38 - 0x02];
|
||||
u32 sqptr;
|
||||
u32 schedulerbasepointer;
|
||||
u32 txrmonbaseptr;
|
||||
u32 tstate;
|
||||
u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
|
||||
u32 vtagtable[0x8];
|
||||
u32 tqptr;
|
||||
u8 res2[0x80 - 0x74];
|
||||
} __packed;
|
||||
|
||||
/****** Rx data struct collection ******/
|
||||
/* Rx thread data, each Rx thread has one this struct. */
|
||||
struct uec_thread_data_rx {
|
||||
u8 res0[40];
|
||||
} __packed;
|
||||
|
||||
/* Rx thread parameter, each Rx thread has one this struct. */
|
||||
struct uec_thread_rx_pram {
|
||||
u8 res0[128];
|
||||
} __packed;
|
||||
|
||||
/* Rx firmware counters */
|
||||
struct uec_rx_firmware_statistics_pram {
|
||||
u32 frrxfcser; /* frames with crc error */
|
||||
u32 fraligner; /* frames with alignment error */
|
||||
u32 inrangelenrxer; /* in range length error */
|
||||
u32 outrangelenrxer; /* out of range length error */
|
||||
u32 frtoolong; /* frame too long */
|
||||
u32 runt; /* runt */
|
||||
u32 verylongevent; /* very long event */
|
||||
u32 symbolerror; /* symbol error */
|
||||
u32 dropbsy; /* drop because of BD not ready */
|
||||
u8 res0[0x8];
|
||||
u32 mismatchdrop; /* drop because of MAC filtering */
|
||||
u32 underpkts; /* total frames less than 64 octets */
|
||||
u32 pkts256; /* total frames(including bad)256~511 B */
|
||||
u32 pkts512; /* total frames(including bad)512~1023 B */
|
||||
u32 pkts1024; /* total frames(including bad)1024~1518 B */
|
||||
u32 pktsjumbo; /* total frames(including bad) >1024 B */
|
||||
u32 frlossinmacer;
|
||||
u32 pausefr; /* pause frames */
|
||||
u8 res1[0x4];
|
||||
u32 removevlan;
|
||||
u32 replacevlan;
|
||||
u32 insertvlan;
|
||||
} __packed;
|
||||
|
||||
/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
|
||||
struct uec_rx_interrupt_coalescing_entry {
|
||||
u32 maxvalue;
|
||||
u32 counter;
|
||||
} __packed;
|
||||
|
||||
struct uec_rx_interrupt_coalescing_table {
|
||||
struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
|
||||
} __packed;
|
||||
|
||||
/* RxBD queue entry, each Rx queue has one this entry. */
|
||||
struct uec_rx_bd_queues_entry {
|
||||
u32 bdbaseptr; /* BD base pointer */
|
||||
u32 bdptr; /* BD pointer */
|
||||
u32 externalbdbaseptr; /* external BD base pointer */
|
||||
u32 externalbdptr; /* external BD pointer */
|
||||
} __packed;
|
||||
|
||||
/* Rx global parameter table */
|
||||
struct uec_rx_global_pram {
|
||||
u32 remoder; /* ethernet mode reg. */
|
||||
u32 rqptr; /* base pointer to the Rx Queues */
|
||||
u32 res0[0x1];
|
||||
u8 res1[0x20 - 0xc];
|
||||
u16 typeorlen;
|
||||
u8 res2[0x1];
|
||||
u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
|
||||
u32 rxrmonbaseptr; /* Rx RMON statistics base */
|
||||
u8 res3[0x30 - 0x28];
|
||||
u32 intcoalescingptr; /* Interrupt coalescing table pointer */
|
||||
u8 res4[0x36 - 0x34];
|
||||
u8 rstate;
|
||||
u8 res5[0x46 - 0x37];
|
||||
u16 mrblr; /* max receive buffer length reg. */
|
||||
u32 rbdqptr; /* RxBD parameter table description */
|
||||
u16 mflr; /* max frame length reg. */
|
||||
u16 minflr; /* min frame length reg. */
|
||||
u16 maxd1; /* max dma1 length reg. */
|
||||
u16 maxd2; /* max dma2 length reg. */
|
||||
u32 ecamptr; /* external CAM address */
|
||||
u32 l2qt; /* VLAN priority mapping table. */
|
||||
u32 l3qt[0x8]; /* IP priority mapping table. */
|
||||
u16 vlantype; /* vlan type */
|
||||
u16 vlantci; /* default vlan tci */
|
||||
u8 addressfiltering[64];/* address filtering data structure */
|
||||
u32 exf_global_param; /* extended filtering global parameters */
|
||||
u8 res6[0x100 - 0xc4]; /* Initialize to zero */
|
||||
} __packed;
|
||||
|
||||
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
|
||||
|
||||
/****** UEC common ******/
|
||||
/* UCC statistics - hardware counters */
|
||||
struct uec_hardware_statistics {
|
||||
u32 tx64;
|
||||
u32 tx127;
|
||||
u32 tx255;
|
||||
u32 rx64;
|
||||
u32 rx127;
|
||||
u32 rx255;
|
||||
u32 txok;
|
||||
u16 txcf;
|
||||
u32 tmca;
|
||||
u32 tbca;
|
||||
u32 rxfok;
|
||||
u32 rxbok;
|
||||
u32 rbyt;
|
||||
u32 rmca;
|
||||
u32 rbca;
|
||||
} __packed;
|
||||
|
||||
/* InitEnet command parameter */
|
||||
struct uec_init_cmd_pram {
|
||||
u8 resinit0;
|
||||
u8 resinit1;
|
||||
u8 resinit2;
|
||||
u8 resinit3;
|
||||
u16 resinit4;
|
||||
u8 res1[0x1];
|
||||
u8 largestexternallookupkeysize;
|
||||
u32 rgftgfrxglobal;
|
||||
u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
|
||||
u8 res2[0x38 - 0x30];
|
||||
u32 txglobal; /* tx global */
|
||||
u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
|
||||
u8 res3[0x1];
|
||||
} __packed;
|
||||
|
||||
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
|
||||
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
|
||||
|
||||
#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
|
||||
#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
|
||||
#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
|
||||
#define ENET_INIT_PARAM_SNUM_SHIFT 24
|
||||
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
|
||||
|
||||
/* structure representing 82xx Address Filtering Enet Address in PRAM */
|
||||
struct uec_82xx_enet_addr {
|
||||
u8 res1[0x2];
|
||||
u16 h; /* address (MSB) */
|
||||
u16 m; /* address */
|
||||
u16 l; /* address (LSB) */
|
||||
} __packed;
|
||||
|
||||
/* structure representing 82xx Address Filtering PRAM */
|
||||
struct uec_82xx_add_filtering_pram {
|
||||
u32 iaddr_h; /* individual address filter, high */
|
||||
u32 iaddr_l; /* individual address filter, low */
|
||||
u32 gaddr_h; /* group address filter, high */
|
||||
u32 gaddr_l; /* group address filter, low */
|
||||
struct uec_82xx_enet_addr taddr;
|
||||
struct uec_82xx_enet_addr paddr[4];
|
||||
u8 res0[0x40 - 0x38];
|
||||
} __packed;
|
||||
|
||||
/* Buffer Descriptor */
|
||||
struct buffer_descriptor {
|
||||
u16 status;
|
||||
u16 len;
|
||||
u32 data;
|
||||
} __packed;
|
||||
|
||||
#define SIZEOFBD sizeof(struct buffer_descriptor)
|
||||
|
||||
/* Common BD flags */
|
||||
#define BD_WRAP 0x2000
|
||||
#define BD_INT 0x1000
|
||||
#define BD_LAST 0x0800
|
||||
#define BD_CLEAN 0x3000
|
||||
|
||||
/* TxBD status flags */
|
||||
#define TX_BD_READY 0x8000
|
||||
#define TX_BD_PADCRC 0x4000
|
||||
#define TX_BD_WRAP BD_WRAP
|
||||
#define TX_BD_INT BD_INT
|
||||
#define TX_BD_LAST BD_LAST
|
||||
#define TX_BD_TXCRC 0x0400
|
||||
#define TX_BD_DEF 0x0200
|
||||
#define TX_BD_PP 0x0100
|
||||
#define TX_BD_LC 0x0080
|
||||
#define TX_BD_RL 0x0040
|
||||
#define TX_BD_RC 0x003C
|
||||
#define TX_BD_UNDERRUN 0x0002
|
||||
#define TX_BD_TRUNC 0x0001
|
||||
|
||||
#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
|
||||
|
||||
/* RxBD status flags */
|
||||
#define RX_BD_EMPTY 0x8000
|
||||
#define RX_BD_OWNER 0x4000
|
||||
#define RX_BD_WRAP BD_WRAP
|
||||
#define RX_BD_INT BD_INT
|
||||
#define RX_BD_LAST BD_LAST
|
||||
#define RX_BD_FIRST 0x0400
|
||||
#define RX_BD_CMR 0x0200
|
||||
#define RX_BD_MISS 0x0100
|
||||
#define RX_BD_BCAST 0x0080
|
||||
#define RX_BD_MCAST 0x0040
|
||||
#define RX_BD_LG 0x0020
|
||||
#define RX_BD_NO 0x0010
|
||||
#define RX_BD_SHORT 0x0008
|
||||
#define RX_BD_CRCERR 0x0004
|
||||
#define RX_BD_OVERRUN 0x0002
|
||||
#define RX_BD_IPCH 0x0001
|
||||
|
||||
#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
|
||||
RX_BD_CRCERR | RX_BD_OVERRUN)
|
||||
|
||||
/* BD access macros */
|
||||
#define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
|
||||
#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
|
||||
#define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
|
||||
#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
|
||||
#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
|
||||
#define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
|
||||
#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
|
||||
#define BD_ADVANCE(_bd, _status, _base) \
|
||||
(((_status) & BD_WRAP) ? (_bd) = \
|
||||
((struct buffer_descriptor *)(_base)) : ++(_bd))
|
||||
|
||||
/* Rx Prefetched BDs */
|
||||
struct uec_rx_pref_bds {
|
||||
struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
|
||||
} __packed;
|
||||
|
||||
/* Alignments */
|
||||
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
|
||||
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
|
||||
#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
|
||||
#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
|
||||
#define UEC_THREAD_DATA_ALIGNMENT 256
|
||||
#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
|
||||
#define UEC_SCHEDULER_ALIGNMENT 4
|
||||
#define UEC_TX_STATISTICS_ALIGNMENT 4
|
||||
#define UEC_RX_STATISTICS_ALIGNMENT 4
|
||||
#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
|
||||
#define UEC_RX_BD_QUEUES_ALIGNMENT 8
|
||||
#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
|
||||
#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
|
||||
#define UEC_RX_BD_RING_ALIGNMENT 32
|
||||
#define UEC_TX_BD_RING_ALIGNMENT 32
|
||||
#define UEC_MRBLR_ALIGNMENT 128
|
||||
#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
|
||||
#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
|
||||
#define UEC_RX_DATA_BUF_ALIGNMENT 64
|
||||
|
||||
#define UEC_VLAN_PRIORITY_MAX 8
|
||||
#define UEC_IP_PRIORITY_MAX 64
|
||||
#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
|
||||
#define UEC_RX_BD_RING_SIZE_MIN 8
|
||||
#define UEC_TX_BD_RING_SIZE_MIN 2
|
||||
|
||||
/* TBI / MII Set Register */
|
||||
enum enet_tbi_mii_reg {
|
||||
ENET_TBI_MII_CR = 0x00,
|
||||
ENET_TBI_MII_SR = 0x01,
|
||||
ENET_TBI_MII_ANA = 0x04,
|
||||
ENET_TBI_MII_ANLPBPA = 0x05,
|
||||
ENET_TBI_MII_ANEX = 0x06,
|
||||
ENET_TBI_MII_ANNPT = 0x07,
|
||||
ENET_TBI_MII_ANLPANP = 0x08,
|
||||
ENET_TBI_MII_EXST = 0x0F,
|
||||
ENET_TBI_MII_JD = 0x10,
|
||||
ENET_TBI_MII_TBICON = 0x11
|
||||
};
|
||||
|
||||
/* TBI MDIO register bit fields*/
|
||||
#define TBICON_CLK_SELECT 0x0020
|
||||
#define TBIANA_ASYMMETRIC_PAUSE 0x0100
|
||||
#define TBIANA_SYMMETRIC_PAUSE 0x0080
|
||||
#define TBIANA_HALF_DUPLEX 0x0040
|
||||
#define TBIANA_FULL_DUPLEX 0x0020
|
||||
#define TBICR_PHY_RESET 0x8000
|
||||
#define TBICR_ANEG_ENABLE 0x1000
|
||||
#define TBICR_RESTART_ANEG 0x0200
|
||||
#define TBICR_FULL_DUPLEX 0x0100
|
||||
#define TBICR_SPEED1_SET 0x0040
|
||||
|
||||
#define TBIANA_SETTINGS ( \
|
||||
TBIANA_ASYMMETRIC_PAUSE \
|
||||
| TBIANA_SYMMETRIC_PAUSE \
|
||||
| TBIANA_FULL_DUPLEX \
|
||||
)
|
||||
|
||||
#define TBICR_SETTINGS ( \
|
||||
TBICR_PHY_RESET \
|
||||
| TBICR_ANEG_ENABLE \
|
||||
| TBICR_FULL_DUPLEX \
|
||||
| TBICR_SPEED1_SET \
|
||||
)
|
||||
|
||||
/* UEC number of threads */
|
||||
enum uec_num_of_threads {
|
||||
UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
|
||||
UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
|
||||
UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
|
||||
UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
|
||||
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
|
||||
};
|
||||
|
||||
/* UEC initialization info struct */
|
||||
#define STD_UEC_INFO(num) \
|
||||
{ \
|
||||
.uf_info = { \
|
||||
.ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
|
||||
.rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
|
||||
.tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
|
||||
.eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
|
||||
}, \
|
||||
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
|
||||
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
|
||||
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
|
||||
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
|
||||
.tx_bd_ring_len = 16, \
|
||||
.rx_bd_ring_len = 16, \
|
||||
.phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
|
||||
.enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
|
||||
.speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
|
||||
}
|
||||
|
||||
struct uec_inf {
|
||||
struct ucc_fast_inf uf_info;
|
||||
enum uec_num_of_threads num_threads_tx;
|
||||
enum uec_num_of_threads num_threads_rx;
|
||||
unsigned int risc_tx;
|
||||
unsigned int risc_rx;
|
||||
u16 rx_bd_ring_len;
|
||||
u16 tx_bd_ring_len;
|
||||
u8 phy_address;
|
||||
phy_interface_t enet_interface_type;
|
||||
int speed;
|
||||
};
|
||||
|
||||
/* UEC driver initialized info */
|
||||
#define MAX_RXBUF_LEN 1536
|
||||
#define MAX_FRAME_LEN 1518
|
||||
#define MIN_FRAME_LEN 64
|
||||
#define MAX_DMA1_LEN 1520
|
||||
#define MAX_DMA2_LEN 1520
|
||||
|
||||
/* UEC driver private struct */
|
||||
struct uec_priv {
|
||||
struct uec_inf *uec_info;
|
||||
struct ucc_fast_priv *uccf;
|
||||
struct eth_device *dev;
|
||||
uec_t *uec_regs;
|
||||
uec_mii_t *uec_mii_regs;
|
||||
/* enet init command parameter */
|
||||
struct uec_init_cmd_pram *p_init_enet_param;
|
||||
u32 init_enet_param_offset;
|
||||
/* Rx and Tx parameter */
|
||||
struct uec_rx_global_pram *p_rx_glbl_pram;
|
||||
u32 rx_glbl_pram_offset;
|
||||
struct uec_tx_global_pram *p_tx_glbl_pram;
|
||||
u32 tx_glbl_pram_offset;
|
||||
struct uec_send_queue_mem_region *p_send_q_mem_reg;
|
||||
u32 send_q_mem_reg_offset;
|
||||
struct uec_thread_data_tx *p_thread_data_tx;
|
||||
u32 thread_dat_tx_offset;
|
||||
struct uec_thread_data_rx *p_thread_data_rx;
|
||||
u32 thread_dat_rx_offset;
|
||||
struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
|
||||
u32 rx_bd_qs_tbl_offset;
|
||||
/* BDs specific */
|
||||
u8 *p_tx_bd_ring;
|
||||
u32 tx_bd_ring_offset;
|
||||
u8 *p_rx_bd_ring;
|
||||
u32 rx_bd_ring_offset;
|
||||
u8 *p_rx_buf;
|
||||
u32 rx_buf_offset;
|
||||
struct buffer_descriptor *tx_bd;
|
||||
struct buffer_descriptor *rx_bd;
|
||||
/* Status */
|
||||
int mac_tx_enabled;
|
||||
int mac_rx_enabled;
|
||||
int grace_stopped_tx;
|
||||
int grace_stopped_rx;
|
||||
int the_first_run;
|
||||
/* PHY specific */
|
||||
struct uec_mii_info *mii_info;
|
||||
int oldspeed;
|
||||
int oldduplex;
|
||||
int oldlink;
|
||||
};
|
||||
|
||||
int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
|
||||
int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
|
||||
int uec_standard_init(struct bd_info *bis);
|
||||
#endif /* __UEC_H__ */
|
||||
@ -1,930 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Shlomi Gridish
|
||||
*
|
||||
* Description: UCC GETH Driver -- PHY handling
|
||||
* Driver for UEC on QE
|
||||
* Based on 8260_io/fcc_enet.c
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include <malloc.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/immap_qe.h>
|
||||
#include <asm/io.h>
|
||||
#include "uccf.h"
|
||||
#include "uec.h"
|
||||
#include "uec_phy.h"
|
||||
#include "miiphy.h"
|
||||
#include <fsl_qe.h>
|
||||
#include <phy.h>
|
||||
|
||||
#if !defined(CONFIG_DM_ETH)
|
||||
|
||||
#define ugphy_printk(format, arg...) \
|
||||
printf(format "\n", ## arg)
|
||||
|
||||
#define ugphy_dbg(format, arg...) \
|
||||
ugphy_printk(format, ## arg)
|
||||
#define ugphy_err(format, arg...) \
|
||||
ugphy_printk(format, ## arg)
|
||||
#define ugphy_info(format, arg...) \
|
||||
ugphy_printk(format, ## arg)
|
||||
#define ugphy_warn(format, arg...) \
|
||||
ugphy_printk(format, ## arg)
|
||||
|
||||
#ifdef UEC_VERBOSE_DEBUG
|
||||
#define ugphy_vdbg ugphy_dbg
|
||||
#else
|
||||
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
|
||||
#endif /* UEC_VERBOSE_DEBUG */
|
||||
|
||||
/*
|
||||
* --------------------------------------------------------------------
|
||||
* Fixed PHY (PHY-less) support for Ethernet Ports.
|
||||
*
|
||||
* Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
|
||||
*--------------------------------------------------------------------
|
||||
*
|
||||
* Some boards do not have a PHY for each ethernet port. These ports are known
|
||||
* as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
|
||||
* CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
|
||||
* When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
|
||||
* and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
|
||||
* speed and duplex should be for the port.
|
||||
*
|
||||
* Example board header configuration file:
|
||||
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
|
||||
* #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
|
||||
*
|
||||
* #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
|
||||
* #define CFG_SYS_UEC2_PHY_ADDR 0x02
|
||||
* #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
|
||||
* #define CFG_SYS_UEC4_PHY_ADDR 0x04
|
||||
*
|
||||
* #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
|
||||
* {name, speed, duplex},
|
||||
*
|
||||
* #define CONFIG_SYS_FIXED_PHY_PORTS \
|
||||
* CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
|
||||
* CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_FIXED_PHY
|
||||
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_FIXED_PHY_PORTS
|
||||
#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
|
||||
#endif
|
||||
|
||||
struct fixed_phy_port {
|
||||
char name[16]; /* ethernet port name */
|
||||
unsigned int speed; /* specified speed 10,100 or 1000 */
|
||||
unsigned int duplex; /* specified duplex FULL or HALF */
|
||||
};
|
||||
|
||||
static const struct fixed_phy_port fixed_phy_port[] = {
|
||||
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
|
||||
};
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------
|
||||
* BitBang MII support for ethernet ports
|
||||
*
|
||||
* Based from MPC8560ADS implementation
|
||||
*--------------------------------------------------------------------
|
||||
*
|
||||
* Example board header file to define bitbang ethernet ports:
|
||||
*
|
||||
* #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
|
||||
* #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
|
||||
*/
|
||||
#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
|
||||
#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BITBANGMII)
|
||||
static const char * const bitbang_phy_port[] = {
|
||||
CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
|
||||
};
|
||||
#endif /* CONFIG_BITBANGMII */
|
||||
|
||||
static void config_genmii_advert(struct uec_mii_info *mii_info);
|
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info);
|
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info);
|
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info);
|
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info);
|
||||
static int genmii_update_link(struct uec_mii_info *mii_info);
|
||||
static int genmii_read_status(struct uec_mii_info *mii_info);
|
||||
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
|
||||
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
|
||||
u16 val);
|
||||
|
||||
/*
|
||||
* Write value to the PHY for this device to the register at regnum,
|
||||
* waiting until the write is done before it returns. All PHY
|
||||
* configuration has to be done through the TSEC1 MIIM regs
|
||||
*/
|
||||
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
|
||||
int value)
|
||||
{
|
||||
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
|
||||
uec_mii_t *ug_regs;
|
||||
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
|
||||
u32 tmp_reg;
|
||||
|
||||
#if defined(CONFIG_BITBANGMII)
|
||||
u32 i = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
|
||||
if (strncmp(dev->name, bitbang_phy_port[i],
|
||||
sizeof(dev->name)) == 0) {
|
||||
(void)bb_miiphy_write(NULL, mii_id, regnum, value);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_BITBANGMII */
|
||||
|
||||
ug_regs = ugeth->uec_mii_regs;
|
||||
|
||||
/* Stop the MII management read cycle */
|
||||
out_be32 (&ug_regs->miimcom, 0);
|
||||
/* Setting up the MII Management Address Register */
|
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
out_be32 (&ug_regs->miimadd, tmp_reg);
|
||||
|
||||
/* Setting up the MII Management Control Register with the value */
|
||||
out_be32 (&ug_regs->miimcon, (u32)value);
|
||||
sync();
|
||||
|
||||
/* Wait till MII management write is complete */
|
||||
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads from register regnum in the PHY for device dev,
|
||||
* returning the value. Clears miimcom first. All PHY
|
||||
* configuration has to be done through the TSEC1 MIIM regs
|
||||
*/
|
||||
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
|
||||
{
|
||||
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
|
||||
uec_mii_t *ug_regs;
|
||||
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
|
||||
u32 tmp_reg;
|
||||
u16 value;
|
||||
|
||||
#if defined(CONFIG_BITBANGMII)
|
||||
u32 i = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
|
||||
if (strncmp(dev->name, bitbang_phy_port[i],
|
||||
sizeof(dev->name)) == 0) {
|
||||
(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
|
||||
return value;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_BITBANGMII */
|
||||
|
||||
ug_regs = ugeth->uec_mii_regs;
|
||||
|
||||
/* Setting up the MII Management Address Register */
|
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
out_be32 (&ug_regs->miimadd, tmp_reg);
|
||||
|
||||
/* clear MII management command cycle */
|
||||
out_be32 (&ug_regs->miimcom, 0);
|
||||
sync();
|
||||
|
||||
/* Perform an MII management read cycle */
|
||||
out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
|
||||
|
||||
/* Wait till MII management write is complete */
|
||||
while ((in_be32 (&ug_regs->miimind)) &
|
||||
(MIIMIND_NOT_VALID | MIIMIND_BUSY))
|
||||
;
|
||||
|
||||
/* Read MII management status */
|
||||
value = (u16)in_be32 (&ug_regs->miimstat);
|
||||
if (value == 0xffff)
|
||||
ugphy_vdbg
|
||||
("read wrong value : mii_id %d,mii_reg %d, base %08x",
|
||||
mii_id, mii_reg, (u32)&ug_regs->miimcfg);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->phyinfo->ack_interrupt)
|
||||
mii_info->phyinfo->ack_interrupt(mii_info);
|
||||
}
|
||||
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
|
||||
u32 interrupts)
|
||||
{
|
||||
mii_info->interrupts = interrupts;
|
||||
if (mii_info->phyinfo->config_intr)
|
||||
mii_info->phyinfo->config_intr(mii_info);
|
||||
}
|
||||
|
||||
/* Writes MII_ADVERTISE with the appropriate values, after
|
||||
* sanitizing advertise to make sure only supported features
|
||||
* are advertised
|
||||
*/
|
||||
static void config_genmii_advert(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u32 advertise;
|
||||
u16 adv;
|
||||
|
||||
/* Only allow advertising what this PHY supports */
|
||||
mii_info->advertising &= mii_info->phyinfo->features;
|
||||
advertise = mii_info->advertising;
|
||||
|
||||
/* Setup standard advertisement */
|
||||
adv = uec_phy_read(mii_info, MII_ADVERTISE);
|
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
|
||||
if (advertise & ADVERTISED_10baseT_Half)
|
||||
adv |= ADVERTISE_10HALF;
|
||||
if (advertise & ADVERTISED_10baseT_Full)
|
||||
adv |= ADVERTISE_10FULL;
|
||||
if (advertise & ADVERTISED_100baseT_Half)
|
||||
adv |= ADVERTISE_100HALF;
|
||||
if (advertise & ADVERTISED_100baseT_Full)
|
||||
adv |= ADVERTISE_100FULL;
|
||||
uec_phy_write(mii_info, MII_ADVERTISE, adv);
|
||||
}
|
||||
|
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 ctrl;
|
||||
u32 features = mii_info->phyinfo->features;
|
||||
|
||||
ctrl = uec_phy_read(mii_info, MII_BMCR);
|
||||
|
||||
ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
|
||||
BMCR_SPEED1000 | BMCR_ANENABLE);
|
||||
ctrl |= BMCR_RESET;
|
||||
|
||||
switch (mii_info->speed) {
|
||||
case SPEED_1000:
|
||||
if (features & (SUPPORTED_1000baseT_Half
|
||||
| SUPPORTED_1000baseT_Full)) {
|
||||
ctrl |= BMCR_SPEED1000;
|
||||
break;
|
||||
}
|
||||
mii_info->speed = SPEED_100;
|
||||
case SPEED_100:
|
||||
if (features & (SUPPORTED_100baseT_Half
|
||||
| SUPPORTED_100baseT_Full)) {
|
||||
ctrl |= BMCR_SPEED100;
|
||||
break;
|
||||
}
|
||||
mii_info->speed = SPEED_10;
|
||||
case SPEED_10:
|
||||
if (features & (SUPPORTED_10baseT_Half
|
||||
| SUPPORTED_10baseT_Full))
|
||||
break;
|
||||
default: /* Unsupported speed! */
|
||||
ugphy_err("%s: Bad speed!", mii_info->dev->name);
|
||||
break;
|
||||
}
|
||||
|
||||
uec_phy_write(mii_info, MII_BMCR, ctrl);
|
||||
}
|
||||
|
||||
/* Enable and Restart Autonegotiation */
|
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 ctl;
|
||||
|
||||
ctl = uec_phy_read(mii_info, MII_BMCR);
|
||||
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
uec_phy_write(mii_info, MII_BMCR, ctl);
|
||||
}
|
||||
|
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 adv;
|
||||
u32 advertise;
|
||||
|
||||
if (mii_info->autoneg) {
|
||||
/* Configure the ADVERTISE register */
|
||||
config_genmii_advert(mii_info);
|
||||
advertise = mii_info->advertising;
|
||||
|
||||
adv = uec_phy_read(mii_info, MII_CTRL1000);
|
||||
adv &= ~(ADVERTISE_1000FULL |
|
||||
ADVERTISE_1000HALF);
|
||||
if (advertise & SUPPORTED_1000baseT_Half)
|
||||
adv |= ADVERTISE_1000HALF;
|
||||
if (advertise & SUPPORTED_1000baseT_Full)
|
||||
adv |= ADVERTISE_1000FULL;
|
||||
uec_phy_write(mii_info, MII_CTRL1000, adv);
|
||||
|
||||
/* Start/Restart aneg */
|
||||
genmii_restart_aneg(mii_info);
|
||||
} else {
|
||||
genmii_setup_forced(mii_info);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_config_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
/*
|
||||
* The Marvell PHY has an errata which requires
|
||||
* that certain registers get written in order
|
||||
* to restart autonegotiation
|
||||
*/
|
||||
uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
|
||||
|
||||
uec_phy_write(mii_info, 0x1d, 0x1f);
|
||||
uec_phy_write(mii_info, 0x1e, 0x200c);
|
||||
uec_phy_write(mii_info, 0x1d, 0x5);
|
||||
uec_phy_write(mii_info, 0x1e, 0);
|
||||
uec_phy_write(mii_info, 0x1e, 0x100);
|
||||
|
||||
gbit_config_aneg(mii_info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->autoneg) {
|
||||
/*
|
||||
* Speed up the common case, if link is already up, speed and
|
||||
* duplex match, skip auto neg as it already matches
|
||||
*/
|
||||
if (!genmii_read_status(mii_info) && mii_info->link)
|
||||
if (mii_info->duplex == DUPLEX_FULL &&
|
||||
mii_info->speed == SPEED_100)
|
||||
if (mii_info->advertising &
|
||||
ADVERTISED_100baseT_Full)
|
||||
return 0;
|
||||
|
||||
config_genmii_advert(mii_info);
|
||||
genmii_restart_aneg(mii_info);
|
||||
} else {
|
||||
genmii_setup_forced(mii_info);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_update_link(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
|
||||
/* Status is read once to clear old link state */
|
||||
uec_phy_read(mii_info, MII_BMSR);
|
||||
|
||||
/*
|
||||
* Wait if the link is up, and autonegotiation is in progress
|
||||
* (ie - we're capable and it's not done)
|
||||
*/
|
||||
status = uec_phy_read(mii_info, MII_BMSR);
|
||||
if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
|
||||
!(status & BMSR_ANEGCOMPLETE)) {
|
||||
int i = 0;
|
||||
|
||||
while (!(status & BMSR_ANEGCOMPLETE)) {
|
||||
/*
|
||||
* Timeout reached ?
|
||||
*/
|
||||
if (i > UGETH_AN_TIMEOUT) {
|
||||
mii_info->link = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
i++;
|
||||
udelay(1000); /* 1 ms */
|
||||
status = uec_phy_read(mii_info, MII_BMSR);
|
||||
}
|
||||
mii_info->link = 1;
|
||||
} else {
|
||||
if (status & BMSR_LSTATUS)
|
||||
mii_info->link = 1;
|
||||
else
|
||||
mii_info->link = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_read_status(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (mii_info->autoneg) {
|
||||
status = uec_phy_read(mii_info, MII_STAT1000);
|
||||
|
||||
if (status & (LPA_1000FULL | LPA_1000HALF)) {
|
||||
mii_info->speed = SPEED_1000;
|
||||
if (status & LPA_1000FULL)
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
else
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
} else {
|
||||
status = uec_phy_read(mii_info, MII_LPA);
|
||||
|
||||
if (status & (LPA_10FULL | LPA_100FULL))
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
else
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
if (status & (LPA_100FULL | LPA_100HALF))
|
||||
mii_info->speed = SPEED_100;
|
||||
else
|
||||
mii_info->speed = SPEED_10;
|
||||
}
|
||||
mii_info->pause = 0;
|
||||
}
|
||||
/* On non-aneg, we assume what we put in BMCR is the speed,
|
||||
* though magic-aneg shouldn't prevent this case from occurring
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_init(struct uec_mii_info *mii_info)
|
||||
{
|
||||
struct eth_device *edev = mii_info->dev;
|
||||
struct uec_priv *uec = edev->priv;
|
||||
|
||||
gbit_config_aneg(mii_info);
|
||||
|
||||
if (uec->uec_info->enet_interface_type ==
|
||||
PHY_INTERFACE_MODE_RGMII_RXID &&
|
||||
uec->uec_info->speed == SPEED_1000) {
|
||||
u16 val;
|
||||
int cnt = 50;
|
||||
|
||||
/* Wait for aneg to complete. */
|
||||
do
|
||||
val = uec_phy_read(mii_info, MII_BMSR);
|
||||
while (--cnt && !(val & BMSR_ANEGCOMPLETE));
|
||||
|
||||
/* Set RDX clk delay. */
|
||||
uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
|
||||
|
||||
val = uec_phy_read(mii_info, 0x18);
|
||||
/* Set RDX-RXC skew. */
|
||||
val |= (1 << 8);
|
||||
val |= (7 | (7 << 12));
|
||||
/* Write bits 14:0. */
|
||||
val |= (1 << 15);
|
||||
uec_phy_write(mii_info, 0x18, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uec_marvell_init(struct uec_mii_info *mii_info)
|
||||
{
|
||||
struct eth_device *edev = mii_info->dev;
|
||||
struct uec_priv *uec = edev->priv;
|
||||
phy_interface_t iface = uec->uec_info->enet_interface_type;
|
||||
int speed = uec->uec_info->speed;
|
||||
|
||||
if (speed == SPEED_1000 &&
|
||||
(iface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
iface == PHY_INTERFACE_MODE_RGMII_RXID ||
|
||||
iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
|
||||
int temp;
|
||||
|
||||
temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
|
||||
if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
|
||||
} else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
|
||||
temp &= ~MII_M1111_TX_DELAY;
|
||||
temp |= MII_M1111_RX_DELAY;
|
||||
} else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
|
||||
temp &= ~MII_M1111_RX_DELAY;
|
||||
temp |= MII_M1111_TX_DELAY;
|
||||
}
|
||||
uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
|
||||
|
||||
temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
|
||||
temp &= ~MII_M1111_HWCFG_MODE_MASK;
|
||||
temp |= MII_M1111_HWCFG_MODE_RGMII;
|
||||
uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
|
||||
|
||||
uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_read_status(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* If the link is up, read the speed and duplex
|
||||
* If we aren't autonegotiating, assume speeds
|
||||
* are as set
|
||||
*/
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
int speed;
|
||||
|
||||
status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
|
||||
|
||||
/* Get the duplexity */
|
||||
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
else
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
|
||||
/* Get the speed */
|
||||
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
|
||||
switch (speed) {
|
||||
case MII_M1011_PHY_SPEC_STATUS_1000:
|
||||
mii_info->speed = SPEED_1000;
|
||||
break;
|
||||
case MII_M1011_PHY_SPEC_STATUS_100:
|
||||
mii_info->speed = SPEED_100;
|
||||
break;
|
||||
default:
|
||||
mii_info->speed = SPEED_10;
|
||||
break;
|
||||
}
|
||||
mii_info->pause = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Clear the interrupts by reading the reg */
|
||||
uec_phy_read(mii_info, MII_M1011_IEVENT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_config_intr(struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
|
||||
uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
|
||||
else
|
||||
uec_phy_write(mii_info, MII_M1011_IMASK,
|
||||
MII_M1011_IMASK_CLEAR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_init(struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Reset the PHY */
|
||||
uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
|
||||
BMCR_RESET);
|
||||
/* PHY and MAC connect */
|
||||
uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
|
||||
~BMCR_ISOLATE);
|
||||
|
||||
uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
|
||||
|
||||
config_genmii_advert(mii_info);
|
||||
/* Start/restart aneg */
|
||||
genmii_config_aneg(mii_info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_config_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_read_status(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
/*
|
||||
* If the link is up, read the speed and duplex
|
||||
* If we aren't autonegotiating assume speeds are as set
|
||||
*/
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
status = uec_phy_read(mii_info, MII_DM9161_SCSR);
|
||||
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
|
||||
mii_info->speed = SPEED_100;
|
||||
else
|
||||
mii_info->speed = SPEED_10;
|
||||
|
||||
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
else
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Clear the interrupt by reading the reg */
|
||||
uec_phy_read(mii_info, MII_DM9161_INTR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_config_intr(struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
|
||||
uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
|
||||
else
|
||||
uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dm9161_close(struct uec_mii_info *mii_info)
|
||||
{
|
||||
}
|
||||
|
||||
static int fixed_phy_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fixed_phy_read_status(struct uec_mii_info *mii_info)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
|
||||
if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
|
||||
strlen(mii_info->dev->name)) == 0) {
|
||||
mii_info->speed = fixed_phy_port[i].speed;
|
||||
mii_info->duplex = fixed_phy_port[i].duplex;
|
||||
mii_info->link = 1; /* Link is always UP */
|
||||
mii_info->pause = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int smsc_config_aneg(struct uec_mii_info *mii_info)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int smsc_read_status(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* If the link is up, read the speed and duplex
|
||||
* If we aren't autonegotiating, assume speeds
|
||||
* are as set
|
||||
*/
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
int val;
|
||||
|
||||
status = uec_phy_read(mii_info, 0x1f);
|
||||
val = (status & 0x1c) >> 2;
|
||||
|
||||
switch (val) {
|
||||
case 1:
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
mii_info->speed = SPEED_10;
|
||||
break;
|
||||
case 5:
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
mii_info->speed = SPEED_10;
|
||||
break;
|
||||
case 2:
|
||||
mii_info->duplex = DUPLEX_HALF;
|
||||
mii_info->speed = SPEED_100;
|
||||
break;
|
||||
case 6:
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
mii_info->speed = SPEED_100;
|
||||
break;
|
||||
}
|
||||
mii_info->pause = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_info phy_info_dm9161 = {
|
||||
.phy_id = 0x0181b880,
|
||||
.phy_id_mask = 0x0ffffff0,
|
||||
.name = "Davicom DM9161E",
|
||||
.init = dm9161_init,
|
||||
.config_aneg = dm9161_config_aneg,
|
||||
.read_status = dm9161_read_status,
|
||||
.close = dm9161_close,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_dm9161a = {
|
||||
.phy_id = 0x0181b8a0,
|
||||
.phy_id_mask = 0x0ffffff0,
|
||||
.name = "Davicom DM9161A",
|
||||
.features = MII_BASIC_FEATURES,
|
||||
.init = dm9161_init,
|
||||
.config_aneg = dm9161_config_aneg,
|
||||
.read_status = dm9161_read_status,
|
||||
.ack_interrupt = dm9161_ack_interrupt,
|
||||
.config_intr = dm9161_config_intr,
|
||||
.close = dm9161_close,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_marvell = {
|
||||
.phy_id = 0x01410c00,
|
||||
.phy_id_mask = 0xffffff00,
|
||||
.name = "Marvell 88E11x1",
|
||||
.features = MII_GBIT_FEATURES,
|
||||
.init = &uec_marvell_init,
|
||||
.config_aneg = &marvell_config_aneg,
|
||||
.read_status = &marvell_read_status,
|
||||
.ack_interrupt = &marvell_ack_interrupt,
|
||||
.config_intr = &marvell_config_intr,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_bcm5481 = {
|
||||
.phy_id = 0x0143bca0,
|
||||
.phy_id_mask = 0xffffff0,
|
||||
.name = "Broadcom 5481",
|
||||
.features = MII_GBIT_FEATURES,
|
||||
.read_status = genmii_read_status,
|
||||
.init = bcm_init,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_fixedphy = {
|
||||
.phy_id = CONFIG_FIXED_PHY,
|
||||
.phy_id_mask = CONFIG_FIXED_PHY,
|
||||
.name = "Fixed PHY",
|
||||
.config_aneg = fixed_phy_aneg,
|
||||
.read_status = fixed_phy_read_status,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_smsclan8700 = {
|
||||
.phy_id = 0x0007c0c0,
|
||||
.phy_id_mask = 0xfffffff0,
|
||||
.name = "SMSC LAN8700",
|
||||
.features = MII_BASIC_FEATURES,
|
||||
.config_aneg = smsc_config_aneg,
|
||||
.read_status = smsc_read_status,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_genmii = {
|
||||
.phy_id = 0x00000000,
|
||||
.phy_id_mask = 0x00000000,
|
||||
.name = "Generic MII",
|
||||
.features = MII_BASIC_FEATURES,
|
||||
.config_aneg = genmii_config_aneg,
|
||||
.read_status = genmii_read_status,
|
||||
};
|
||||
|
||||
static struct phy_info *phy_info[] = {
|
||||
&phy_info_dm9161,
|
||||
&phy_info_dm9161a,
|
||||
&phy_info_marvell,
|
||||
&phy_info_bcm5481,
|
||||
&phy_info_smsclan8700,
|
||||
&phy_info_fixedphy,
|
||||
&phy_info_genmii,
|
||||
NULL
|
||||
};
|
||||
|
||||
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
|
||||
{
|
||||
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
|
||||
}
|
||||
|
||||
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
|
||||
{
|
||||
mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
|
||||
}
|
||||
|
||||
/* Use the PHY ID registers to determine what type of PHY is attached
|
||||
* to device dev. return a struct phy_info structure describing that PHY
|
||||
*/
|
||||
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 phy_reg;
|
||||
u32 phy_ID;
|
||||
int i;
|
||||
struct phy_info *info = NULL;
|
||||
|
||||
/* Grab the bits from PHYIR1, and put them in the upper half */
|
||||
phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
|
||||
phy_ID = (phy_reg & 0xffff) << 16;
|
||||
|
||||
/* Grab the bits from PHYIR2, and put them in the lower half */
|
||||
phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
|
||||
phy_ID |= (phy_reg & 0xffff);
|
||||
|
||||
/* loop through all the known PHY types, and find one that */
|
||||
/* matches the ID we read from the PHY. */
|
||||
for (i = 0; phy_info[i]; i++)
|
||||
if (phy_info[i]->phy_id ==
|
||||
(phy_ID & phy_info[i]->phy_id_mask)) {
|
||||
info = phy_info[i];
|
||||
break;
|
||||
}
|
||||
|
||||
/* This shouldn't happen, as we have generic PHY support */
|
||||
if (!info) {
|
||||
ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
|
||||
return NULL;
|
||||
}
|
||||
ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
|
||||
|
||||
return info;
|
||||
}
|
||||
|
||||
void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
|
||||
int speed)
|
||||
{
|
||||
struct uec_priv *uec = (struct uec_priv *)dev->priv;
|
||||
struct uec_mii_info *mii_info;
|
||||
u16 status;
|
||||
|
||||
if (!uec->mii_info) {
|
||||
printf("%s: the PHY not initialized\n", __func__);
|
||||
return;
|
||||
}
|
||||
mii_info = uec->mii_info;
|
||||
|
||||
if (type == PHY_INTERFACE_MODE_RGMII) {
|
||||
if (speed == SPEED_100) {
|
||||
uec_phy_write(mii_info, 0x00, 0x9140);
|
||||
uec_phy_write(mii_info, 0x1d, 0x001f);
|
||||
uec_phy_write(mii_info, 0x1e, 0x200c);
|
||||
uec_phy_write(mii_info, 0x1d, 0x0005);
|
||||
uec_phy_write(mii_info, 0x1e, 0x0000);
|
||||
uec_phy_write(mii_info, 0x1e, 0x0100);
|
||||
uec_phy_write(mii_info, 0x09, 0x0e00);
|
||||
uec_phy_write(mii_info, 0x04, 0x01e1);
|
||||
uec_phy_write(mii_info, 0x00, 0x9140);
|
||||
uec_phy_write(mii_info, 0x00, 0x1000);
|
||||
mdelay(100);
|
||||
uec_phy_write(mii_info, 0x00, 0x2900);
|
||||
uec_phy_write(mii_info, 0x14, 0x0cd2);
|
||||
uec_phy_write(mii_info, 0x00, 0xa100);
|
||||
uec_phy_write(mii_info, 0x09, 0x0000);
|
||||
uec_phy_write(mii_info, 0x1b, 0x800b);
|
||||
uec_phy_write(mii_info, 0x04, 0x05e1);
|
||||
uec_phy_write(mii_info, 0x00, 0xa100);
|
||||
uec_phy_write(mii_info, 0x00, 0x2100);
|
||||
mdelay(1000);
|
||||
} else if (speed == SPEED_10) {
|
||||
uec_phy_write(mii_info, 0x14, 0x8e40);
|
||||
uec_phy_write(mii_info, 0x1b, 0x800b);
|
||||
uec_phy_write(mii_info, 0x14, 0x0c82);
|
||||
uec_phy_write(mii_info, 0x00, 0x8100);
|
||||
mdelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
/* handle 88e1111 rev.B2 erratum 5.6 */
|
||||
if (mii_info->autoneg) {
|
||||
status = uec_phy_read(mii_info, MII_BMCR);
|
||||
uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
|
||||
}
|
||||
/* now the B2 will correctly report autoneg completion status */
|
||||
}
|
||||
|
||||
void change_phy_interface_mode(struct eth_device *dev,
|
||||
phy_interface_t type, int speed)
|
||||
{
|
||||
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
|
||||
marvell_phy_interface_mode(dev, type, speed);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@ -1,214 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Shlomi Gridish <gridish@freescale.com>
|
||||
*
|
||||
* Description: UCC ethernet driver -- PHY handling
|
||||
* Driver for UEC on QE
|
||||
* Based on 8260_io/fcc_enet.c
|
||||
*/
|
||||
#ifndef __UEC_PHY_H__
|
||||
#define __UEC_PHY_H__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define MII_end ((u32)-2)
|
||||
#define MII_read ((u32)-1)
|
||||
|
||||
#define MIIMIND_BUSY 0x00000001
|
||||
#define MIIMIND_NOTVALID 0x00000004
|
||||
|
||||
#define UGETH_AN_TIMEOUT 2000
|
||||
|
||||
/* Cicada Extended Control Register 1 */
|
||||
#define MII_CIS8201_EXT_CON1 0x17
|
||||
#define MII_CIS8201_EXTCON1_INIT 0x0000
|
||||
|
||||
/* Cicada Interrupt Mask Register */
|
||||
#define MII_CIS8201_IMASK 0x19
|
||||
#define MII_CIS8201_IMASK_IEN 0x8000
|
||||
#define MII_CIS8201_IMASK_SPEED 0x4000
|
||||
#define MII_CIS8201_IMASK_LINK 0x2000
|
||||
#define MII_CIS8201_IMASK_DUPLEX 0x1000
|
||||
#define MII_CIS8201_IMASK_MASK 0xf000
|
||||
|
||||
/* Cicada Interrupt Status Register */
|
||||
#define MII_CIS8201_ISTAT 0x1a
|
||||
#define MII_CIS8201_ISTAT_STATUS 0x8000
|
||||
#define MII_CIS8201_ISTAT_SPEED 0x4000
|
||||
#define MII_CIS8201_ISTAT_LINK 0x2000
|
||||
#define MII_CIS8201_ISTAT_DUPLEX 0x1000
|
||||
|
||||
/* Cicada Auxiliary Control/Status Register */
|
||||
#define MII_CIS8201_AUX_CONSTAT 0x1c
|
||||
#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
|
||||
#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
|
||||
#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
|
||||
#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
|
||||
#define MII_CIS8201_AUXCONSTAT_100 0x0008
|
||||
|
||||
/* 88E1011 PHY Status Register */
|
||||
#define MII_M1011_PHY_SPEC_STATUS 0x11
|
||||
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
|
||||
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
|
||||
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
|
||||
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
|
||||
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
|
||||
#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
|
||||
|
||||
#define MII_M1011_IEVENT 0x13
|
||||
#define MII_M1011_IEVENT_CLEAR 0x0000
|
||||
|
||||
#define MII_M1011_IMASK 0x12
|
||||
#define MII_M1011_IMASK_INIT 0x6400
|
||||
#define MII_M1011_IMASK_CLEAR 0x0000
|
||||
|
||||
/* 88E1111 PHY Register */
|
||||
#define MII_M1111_PHY_EXT_CR 0x14
|
||||
#define MII_M1111_RX_DELAY 0x80
|
||||
#define MII_M1111_TX_DELAY 0x2
|
||||
#define MII_M1111_PHY_EXT_SR 0x1b
|
||||
#define MII_M1111_HWCFG_MODE_MASK 0xf
|
||||
#define MII_M1111_HWCFG_MODE_RGMII 0xb
|
||||
|
||||
#define MII_DM9161_SCR 0x10
|
||||
#define MII_DM9161_SCR_INIT 0x0610
|
||||
#define MII_DM9161_SCR_RMII_INIT 0x0710
|
||||
|
||||
/* DM9161 Specified Configuration and Status Register */
|
||||
#define MII_DM9161_SCSR 0x11
|
||||
#define MII_DM9161_SCSR_100F 0x8000
|
||||
#define MII_DM9161_SCSR_100H 0x4000
|
||||
#define MII_DM9161_SCSR_10F 0x2000
|
||||
#define MII_DM9161_SCSR_10H 0x1000
|
||||
|
||||
/* DM9161 Interrupt Register */
|
||||
#define MII_DM9161_INTR 0x15
|
||||
#define MII_DM9161_INTR_PEND 0x8000
|
||||
#define MII_DM9161_INTR_DPLX_MASK 0x0800
|
||||
#define MII_DM9161_INTR_SPD_MASK 0x0400
|
||||
#define MII_DM9161_INTR_LINK_MASK 0x0200
|
||||
#define MII_DM9161_INTR_MASK 0x0100
|
||||
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
|
||||
#define MII_DM9161_INTR_SPD_CHANGE 0x0008
|
||||
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
|
||||
#define MII_DM9161_INTR_INIT 0x0000
|
||||
#define MII_DM9161_INTR_STOP \
|
||||
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
|
||||
MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
|
||||
|
||||
/* DM9161 10BT Configuration/Status */
|
||||
#define MII_DM9161_10BTCSR 0x12
|
||||
#define MII_DM9161_10BTCSR_INIT 0x7800
|
||||
|
||||
#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
|
||||
SUPPORTED_10baseT_Full | \
|
||||
SUPPORTED_100baseT_Half | \
|
||||
SUPPORTED_100baseT_Full | \
|
||||
SUPPORTED_Autoneg | \
|
||||
SUPPORTED_TP | \
|
||||
SUPPORTED_MII)
|
||||
|
||||
#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
|
||||
SUPPORTED_1000baseT_Half | \
|
||||
SUPPORTED_1000baseT_Full)
|
||||
|
||||
#define MII_READ_COMMAND 0x00000001
|
||||
|
||||
#define MII_INTERRUPT_DISABLED 0x0
|
||||
#define MII_INTERRUPT_ENABLED 0x1
|
||||
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
|
||||
/* Duplex, half or full. */
|
||||
#define DUPLEX_HALF 0x00
|
||||
#define DUPLEX_FULL 0x01
|
||||
|
||||
/* Taken from mii_if_info and sungem_phy.h */
|
||||
struct uec_mii_info {
|
||||
/* Information about the PHY type */
|
||||
/* And management functions */
|
||||
struct phy_info *phyinfo;
|
||||
|
||||
struct eth_device *dev;
|
||||
|
||||
/* forced speed & duplex (no autoneg)
|
||||
* partner speed & duplex & pause (autoneg)
|
||||
*/
|
||||
int speed;
|
||||
int duplex;
|
||||
int pause;
|
||||
|
||||
/* The most recently read link state */
|
||||
int link;
|
||||
|
||||
/* Enabled Interrupts */
|
||||
u32 interrupts;
|
||||
|
||||
u32 advertising;
|
||||
int autoneg;
|
||||
int mii_id;
|
||||
|
||||
/* private data pointer */
|
||||
/* For use by PHYs to maintain extra state */
|
||||
void *priv;
|
||||
|
||||
/* Provided by ethernet driver */
|
||||
int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
|
||||
void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
|
||||
int val);
|
||||
};
|
||||
|
||||
/* struct phy_info: a structure which defines attributes for a PHY
|
||||
*
|
||||
* id will contain a number which represents the PHY. During
|
||||
* startup, the driver will poll the PHY to find out what its
|
||||
* UID--as defined by registers 2 and 3--is. The 32-bit result
|
||||
* gotten from the PHY will be ANDed with phy_id_mask to
|
||||
* discard any bits which may change based on revision numbers
|
||||
* unimportant to functionality
|
||||
*
|
||||
* There are 6 commands which take a ugeth_mii_info structure.
|
||||
* Each PHY must declare config_aneg, and read_status.
|
||||
*/
|
||||
struct phy_info {
|
||||
u32 phy_id;
|
||||
char *name;
|
||||
unsigned int phy_id_mask;
|
||||
u32 features;
|
||||
|
||||
/* Called to initialize the PHY */
|
||||
int (*init)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Called to suspend the PHY for power */
|
||||
int (*suspend)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Reconfigures autonegotiation (or disables it) */
|
||||
int (*config_aneg)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Determines the negotiated speed and duplex */
|
||||
int (*read_status)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Clears any pending interrupts */
|
||||
int (*ack_interrupt)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Enables or disables interrupts */
|
||||
int (*config_intr)(struct uec_mii_info *mii_info);
|
||||
|
||||
/* Clears up any memory if needed */
|
||||
void (*close)(struct uec_mii_info *mii_info);
|
||||
};
|
||||
|
||||
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
|
||||
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
|
||||
int value);
|
||||
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
|
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
|
||||
u32 interrupts);
|
||||
void change_phy_interface_mode(struct eth_device *dev,
|
||||
phy_interface_t type, int speed);
|
||||
#endif /* __UEC_PHY_H__ */
|
||||
Loading…
Reference in New Issue
Block a user