spi: zynq_[q]spi: Use GENMASK macro
GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
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#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
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#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
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#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */
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#define ZYNQ_QSPI_CR_SS_MASK (0xF << 10) /* Slave Select */
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#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */
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#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
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#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
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#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
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#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
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#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
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#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
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#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
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#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
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#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */
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#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
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#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
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/* zynq qspi Transmit Data Register */
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@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
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/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
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#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
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#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
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#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */
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#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */
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#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
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#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
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#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
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#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
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#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
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#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
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#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
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#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */
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#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
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#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
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#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
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