leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

86xx: Remove old-style law setup code

Browse Source 
This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This commit is contained in:
Becky Bruce
2008-01-23 16:31:04 -06:00
committed by Jon Loeliger
parent 713d818664
commit 9cd32426f2
11 changed files with 0 additions and 558 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
cpu/mpc86xx/spd_sdram.c
View File

@@ -1123,7 +1123,6 @@ spd_sdram(void)
int memsize_ddr1 = 0;
unsigned int law_size_ddr1;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
#ifdef CONFIG_DDR_INTERLEAVE
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
#endif
@@ -1181,13 +1180,6 @@ spd_sdram(void)
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
#else
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
mcm->lawar1 = (LAWAR_EN
| LAWAR_TRGT_IF_DDR_INTERLEAVED
| (LAWAR_SIZE & law_size_interleaved));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
@@ -1245,13 +1237,6 @@ spd_sdram(void)
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
#else
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
mcm->lawar1 = (LAWAR_EN
| LAWAR_TRGT_IF_DDR1
| (LAWAR_SIZE & law_size_ddr1));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
#endif
}
@@ -1281,18 +1266,6 @@ spd_sdram(void)
set_law(8,
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
law_size_ddr2, LAW_TRGT_IF_DDR_2);
#else
if (ddr1_enabled)
mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
& 0xfffff);
else
mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
mcm->lawar8 = (LAWAR_EN
| LAWAR_TRGT_IF_DDR2
| (LAWAR_SIZE & law_size_ddr2));
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
#endif
}

5
cpu/mpc86xx/start.S
View File

@@ -283,11 +283,6 @@ in_flash:
bl setup_ccsrbar
#endif
#ifndef CONFIG_FSL_LAW
bl law_entry
sync
#endif
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync