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Merge branch '2019-08-11-ti-imports'

Browse Source 
- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
This commit is contained in:
Tom Rini
2019-08-12 18:47:53 -04:00
parent 5939afc961 0805fe151d
commit 9c6115822e
47 changed files with 2850 additions and 59 deletions
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15
board/BuR/brsmarc1/Kconfig Normal file
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if TARGET_BRSMARC1
config SYS_BOARD
default "brsmarc1"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "brsmarc1"
endif

6
board/BuR/brsmarc1/MAINTAINERS Normal file
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BRSMARC1 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brsmarc1/
F: include/configs/brsmarc1.h
F: configs/brsmarc1_defconfig

10
board/BuR/brsmarc1/Makefile Normal file
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@@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com/
#
obj-$(CONFIG_SPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o

168
board/BuR/brsmarc1/board.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for B&R BRSMARC1 Board
*
* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include "../common/br_resetc.h"
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
#define PER_RESET (2 * 32 + 0)
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
int rc;
/*
* enable additional clocks of modules which are accessed later from
* VxWorks OS
*/
u32 *const clk_domains[] = { 0 };
u32 *const clk_modules_specific[] = {
&cmwkup->wkup_adctscctrl,
&cmper->spi1clkctrl,
&cmper->dcan0clkctrl,
&cmper->dcan1clkctrl,
&cmper->timer4clkctrl,
&cmper->timer5clkctrl,
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_specific, 1);
/* setup I2C */
enable_i2c_pin_mux();
/* peripheral reset */
rc = gpio_request(PER_RESET, "PER_RESET");
if (rc != 0)
printf("cannot request PER_RESET GPIO!\n");
rc = gpio_direction_output(PER_RESET, 0);
if (rc != 0)
printf("cannot set PER_RESET GPIO!\n");
/* setup pmic */
pmicsetup(0, 0);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr3;
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
#if !defined(CONFIG_SPL_BUILD)
/* decision if backlight is switched on or not on powerup */
int board_backlightstate(void)
{
u8 bklmask, rstcause;
int rc = 0;
rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
if (rc != 0) {
printf("%s: read rstctrl failed!\n", __func__);
return 1;
}
if ((rstcause & bklmask) != 0)
return 0;
return 1;
}
/* Basic board specific setup. run quite after relocation */
int board_init(void)
{
if (power_tps65217_init(0))
printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
return 0;
}
#if defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
br_resetc_bmode();
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#endif /* !CONFIG_SPL_BUILD */

33
board/BuR/brsmarc1/config.mk Normal file
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@@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
cmd_prodbin = \
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
quiet_cmd_prodzip = SAPZIP $@
cmd_prodzip = \
test -d misc && rm -r misc; \
mkdir misc && \
cp MLO.byteswap misc/ && \
cp spl/u-boot-spl.bin misc/ && \
cp u-boot-dtb.img misc/ && \
zip -9 -r $@ misc/* >/dev/null $<
ALL-y += $(hw-platform-y)_prog.bin
ALL-y += $(hw-platform-y)_prod.zip
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
$(call if_changed,prodbin)
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
$(call if_changed,prodzip)

266
board/BuR/brsmarc1/mux.c Normal file
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@@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
*
* Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux spi0_pin_mux[] = {
/* SPI0_SCLK */
{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D0 */
{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D1 */
{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_CS0 */
{OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI0_CS1 */
{OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux spi1_pin_mux[] = {
/* SPI1_SCLK */
{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
{OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI1_CS1 */
{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan0_pin_mux[] = {
/* DCAN0 TX */
{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN0 RX */
{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan1_pin_mux[] = {
/* DCAN1 TX */
{OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN1 RX */
{OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux gpios[] = {
/* GPIO0_7 - LVDS_EN */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO0_20 - BKLT_PWM (timer7) */
{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_4 - DISON */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_24 - RGB_EN */
{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_28 - nPD */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_5 - Watchdog */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_0 - ResetOut */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_2 - BKLT_EN */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_17 - GPIO0 */
{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_18 - GPIO1 */
{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_19 - GPIO2 */
{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_22 - GPIO3 */
{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_23 - GPIO4 */
{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_25 - GPIO5 */
{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_7 - GPIO6 */
{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_8 - GPIO7 */
{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 - GPIO8 */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 - GPIO9 */
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_20 - GPIO10 */
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_21 - GPIO11 */
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_28 - DRAM-strapping */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_4 - not routed (Pin U6) */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_5 - not routed (Pin T6) */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_28 - not routed (Pin G15) */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_18 - not routed (Pin B12) */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux uart0_pin_mux[] = {
/* UART0_RXD */
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_TXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart234_pin_mux[] = {
/* UART2_RXD */
{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART2_TXD */
{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
/* UART3_RXD */
{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART3_TXD */
{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
/* UART3_RTS */
{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
/* UART3_CTS */
{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_RXD */
{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_TXD */
{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
/* UART4_RTS */
{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
/* UART4_CTS */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux i2c_pin_mux[] = {
/* I2C0_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C0_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_DATA */
{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_SCLK */
{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux eth_pin_mux[] = {
/* ETH1 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
/* ETH2 */
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
/* gpio2_19, gpio 3_4, not connected on board */
{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* ETH Management */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c_pin_mux(void)
{
configure_module_pin_mux(i2c_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(eth_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(spi1_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(uart234_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(gpios);
}

3
board/davinci/da8xxevm/da850evm.c
View File

@@ -234,7 +234,8 @@ const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
PINMUX_ITEM(emifa_pins_nand),
#elif defined(CONFIG_USE_NOR)
#endif
#ifdef CONFIG_USE_NOR
PINMUX_ITEM(emifa_pins_cs2),
PINMUX_ITEM(emifa_pins_nor),
#endif

26
board/overo/common.c
View File

@@ -17,6 +17,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/omap_mmc.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,31 @@ int board_init(void)
return 0;
}
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
#define MUX_OVERO() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\

14
board/overo/overo.c
View File

@@ -377,20 +377,6 @@ int board_eth_init(bd_t *bis)
}
#endif
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#if defined(CONFIG_USB_EHCI_HCD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,

124
board/siemens/common/factoryset.c
View File

@@ -9,6 +9,8 @@
#include <common.h>
#include <env.h>
#include <dm.h>
#include <env_internal.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@@ -143,16 +145,39 @@ int factoryset_read_eeprom(int i2c_addr)
int i, pages = 0, size = 0;
unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
unsigned char *cp, *cp1;
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *bus, *dev;
int ret;
#endif
#if defined(CONFIG_DFU_OVER_USB)
factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM;
factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM;
#endif
#if CONFIG_IS_ENABLED(DM_I2C)
ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, &bus);
if (ret)
goto err;
ret = dm_i2c_probe(bus, i2c_addr, 0, &dev);
if (ret)
goto err;
ret = i2c_set_chip_offset_len(dev, 2);
if (ret)
goto err;
ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr));
if (ret)
goto err;
#else
if (i2c_probe(i2c_addr))
goto err;
if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
goto err;
#endif
if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
printf("FactorySet is not right in eeprom.\n");
@@ -173,16 +198,33 @@ int factoryset_read_eeprom(int i2c_addr)
* data after every time we got a record from eeprom
*/
debug("Read eeprom page :\n");
for (i = 0; i < pages; i++)
for (i = 0; i < pages; i++) {
#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ,
eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ);
if (ret)
goto err;
#else
if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
goto err;
#endif
}
if (size % EEPR_PG_SZ)
if (size % EEPR_PG_SZ) {
#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, (OFF_PG + pages) * EEPR_PG_SZ,
eeprom_buf + (pages * EEPR_PG_SZ),
size % EEPR_PG_SZ);
if (ret)
goto err;
#else
if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
eeprom_buf + (pages * EEPR_PG_SZ),
(size % EEPR_PG_SZ)))
goto err;
#endif
}
/* we do below just for eeprom align */
for (i = 0; i < size; i++)
@@ -202,6 +244,20 @@ int factoryset_read_eeprom(int i2c_addr)
cp1 += 3;
}
#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
/* get mac address for WLAN */
ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac",
buf, MAX_STRING_LENGTH);
if (ret > 0) {
cp1 = buf;
for (i = 0; i < 6; i++) {
factory_dat.mac_wlan[i] = simple_strtoul((char *)cp1,
NULL, 16);
cp1 += 3;
}
}
#endif
#if defined(CONFIG_DFU_OVER_USB)
/* read vid and pid for dfu mode */
if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
@@ -264,42 +320,76 @@ err:
return 1;
}
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static int get_mac_from_efuse(uint8_t mac[6])
{
#ifdef CONFIG_AM33XX
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
uint32_t mac_hi, mac_lo;
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac[0] = mac_hi & 0xFF;
mac[1] = (mac_hi & 0xFF00) >> 8;
mac[2] = (mac_hi & 0xFF0000) >> 16;
mac[3] = (mac_hi & 0xFF000000) >> 24;
mac[4] = mac_lo & 0xFF;
mac[5] = (mac_lo & 0xFF00) >> 8;
#else
/* unhandled */
memset(mac, 0, 6);
#endif
if (!is_valid_ethaddr(mac)) {
puts("Warning: ethaddr not set by FactorySet or E-fuse. ");
puts("Set <ethaddr> variable to overcome this.\n");
return -1;
}
return 0;
}
static int factoryset_mac_env_set(void)
{
uint8_t mac_addr[6];
/* Set mac from factoryset or try reading E-fuse */
debug("FactorySet: Set mac address\n");
if (is_valid_ethaddr(factory_dat.mac)) {
memcpy(mac_addr, factory_dat.mac, 6);
} else {
uint32_t mac_hi, mac_lo;
debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!is_valid_ethaddr(mac_addr)) {
printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n");
if (get_mac_from_efuse(mac_addr) < 0)
return -1;
}
}
eth_env_set_enetaddr("ethaddr", mac_addr);
#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
eth_env_set_enetaddr("eth1addr", mac_addr);
/* wlan mac */
if (is_valid_ethaddr(factory_dat.mac_wlan))
eth_env_set_enetaddr("eth2addr", factory_dat.mac_wlan);
#endif
return 0;
}
static void factoryset_dtb_env_set(void)
{
/* Set ASN in environment*/
if (factory_dat.asn[0] != 0) {
env_set("dtb_name", (char *)factory_dat.asn);
} else {
/* dtb suffix gets added in load script */
env_set("dtb_name", "default");
}
}
int factoryset_env_set(void)
{
int ret = 0;
factoryset_dtb_env_set();
if (factoryset_mac_env_set() < 0)
ret = -1;

3
board/siemens/common/factoryset.h
View File

@@ -11,6 +11,9 @@
struct factorysetcontainer {
uchar mac[6];
#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
uchar mac_wlan[6];
#endif
int usb_vendor_id;
int usb_product_id;
int pxm50;