Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh
This commit is contained in:
Tom Rini
10
arch/arm/dts/r8a7790-lager-u-boot.dts
Normal file
10
arch/arm/dts/r8a7790-lager-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Lager board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7790-lager.dts"
|
||||
#include "r8a7790-u-boot.dtsi"
|
||||
856
arch/arm/dts/r8a7790-lager.dts
Normal file
856
arch/arm/dts/r8a7790-lager.dts
Normal file
@@ -0,0 +1,856 @@
|
||||
/*
|
||||
* Device Tree Source for the Lager board
|
||||
*
|
||||
* Copyright (C) 2013-2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Cogent Embedded, Inc.
|
||||
* Copyright (C) 2015-2016 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7790.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Lager";
|
||||
compatible = "renesas,lager", "renesas,r8a7790";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scifa1;
|
||||
i2c8 = &gpioi2c1;
|
||||
i2c10 = &i2cexio0;
|
||||
i2c11 = &i2cexio1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@140000000 {
|
||||
device_type = "memory";
|
||||
reg = <1 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
one {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
two {
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
three {
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
four {
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
fixedregulator3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c1: i2c-8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
|
||||
* We use the I2C demuxer, so the desired IP core can be selected at runtime
|
||||
* depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
|
||||
* Note: For testing the I2C slave feature, it is convenient to connect this
|
||||
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
|
||||
* instantiate the slave device at runtime according to the documentation.
|
||||
* You can then communicate with the slave via IIC3.
|
||||
*
|
||||
* IIC0/I2C0 does not appear to support fallback to GPIO.
|
||||
*/
|
||||
i2cexio0: i2c-10 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&iic0>, <&i2c0>;
|
||||
i2c-bus-name = "i2c-exio0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
/*
|
||||
* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
|
||||
* This is similar to the arangement described for i2cexio0 (above)
|
||||
* with a fallback to GPIO also provided.
|
||||
*/
|
||||
i2cexio1: i2c-11 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
|
||||
i2c-bus-name = "i2c-exio1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
scifa1_pins: scifa1 {
|
||||
groups = "scifa1_data";
|
||||
function = "scifa1";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1 {
|
||||
groups = "mmc1_data8", "mmc1_ctrl";
|
||||
function = "mmc1";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof1_pins: msiof1 {
|
||||
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
|
||||
"msiof1_tx";
|
||||
function = "msiof1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
iic0_pins: iic0 {
|
||||
groups = "iic0";
|
||||
function = "iic0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
iic1_pins: iic1 {
|
||||
groups = "iic1";
|
||||
function = "iic1";
|
||||
};
|
||||
|
||||
iic2_pins: iic2 {
|
||||
groups = "iic2";
|
||||
function = "iic2";
|
||||
};
|
||||
|
||||
iic3_pins: iic3 {
|
||||
groups = "iic3";
|
||||
function = "iic3";
|
||||
};
|
||||
|
||||
hsusb_pins: hsusb {
|
||||
groups = "usb0_ovc_vbus";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
function = "usb2";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmcif1 {
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&fixedregulator3v3>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scifa1 {
|
||||
pinctrl-0 = <&scifa1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&msiof1 {
|
||||
pinctrl-0 = <&msiof1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@0 {
|
||||
compatible = "renesas,r2a11302ft";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&iic0 {
|
||||
pinctrl-0 = <&iic0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic1 {
|
||||
pinctrl-0 = <&iic1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&iic2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iic3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&iic3_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "dlg,da9210";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&xhci {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hsusb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep0: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
10
arch/arm/dts/r8a7790-stout-u-boot.dts
Normal file
10
arch/arm/dts/r8a7790-stout-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Stout board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7790-stout.dts"
|
||||
#include "r8a7790-u-boot.dtsi"
|
||||
54
arch/arm/dts/r8a7790-stout.dts
Normal file
54
arch/arm/dts/r8a7790-stout.dts
Normal file
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Device Tree Source for the Stout board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7790.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Stout";
|
||||
compatible = "renesas,stout", "renesas,r8a7790";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
13
arch/arm/dts/r8a7790-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7790-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7790 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1665
arch/arm/dts/r8a7790.dtsi
Normal file
1665
arch/arm/dts/r8a7790.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
10
arch/arm/dts/r8a7791-koelsch-u-boot.dts
Normal file
10
arch/arm/dts/r8a7791-koelsch-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Koelsch board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7791-koelsch.dts"
|
||||
#include "r8a7791-u-boot.dtsi"
|
||||
840
arch/arm/dts/r8a7791-koelsch.dts
Normal file
840
arch/arm/dts/r8a7791-koelsch.dts
Normal file
@@ -0,0 +1,840 @@
|
||||
/*
|
||||
* Device Tree Source for the Koelsch board
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
* Copyright (C) 2013-2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7791.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Koelsch";
|
||||
compatible = "renesas,koelsch", "renesas,r8a7791";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
i2c9 = &gpioi2c1;
|
||||
i2c12 = &i2cexio1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@200000000 {
|
||||
device_type = "memory";
|
||||
reg = <2 0x00000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-a {
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW30";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-b {
|
||||
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW31";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-c {
|
||||
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_C>;
|
||||
label = "SW32";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-d {
|
||||
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_D>;
|
||||
label = "SW33";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-e {
|
||||
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_E>;
|
||||
label = "SW34";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-f {
|
||||
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_F>;
|
||||
label = "SW35";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-g {
|
||||
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_G>;
|
||||
label = "SW36";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED6";
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED7";
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED8";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c1: i2c-9 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
|
||||
* A fallback to GPIO is provided.
|
||||
*/
|
||||
i2cexio1: i2c-12 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&i2c1>, <&gpioi2c1>;
|
||||
i2c-bus-name = "i2c-exio1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: scif1 {
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof0_pins: msiof0 {
|
||||
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
|
||||
"msiof0_tx";
|
||||
function = "msiof0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
pinctrl-0 = <&scif1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "user";
|
||||
reg = <0x00080000 0x00580000>;
|
||||
read-only;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "flash";
|
||||
reg = <0x00600000 0x03a00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&msiof0 {
|
||||
pinctrl-0 = <&msiof0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@0 {
|
||||
compatible = "renesas,r2a11302ft";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cec_clock: cec-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cec_clock>;
|
||||
clock-names = "cec";
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,24c02", "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "dlg,da9210";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
10
arch/arm/dts/r8a7791-porter-u-boot.dts
Normal file
10
arch/arm/dts/r8a7791-porter-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Porter board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7791-porter.dts"
|
||||
#include "r8a7791-u-boot.dtsi"
|
||||
452
arch/arm/dts/r8a7791-porter.dts
Normal file
452
arch/arm/dts/r8a7791-porter.dts
Normal file
@@ -0,0 +1,452 @@
|
||||
/*
|
||||
* Device Tree Source for the Porter board
|
||||
*
|
||||
* Copyright (C) 2015 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4642
|
||||
*
|
||||
* JP3: 2-1: AK4642
|
||||
* 2-3: ADV7511
|
||||
*
|
||||
* This command is required before playback/capture:
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7791.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Porter";
|
||||
compatible = "renesas,porter", "renesas,r8a7791";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@200000000 {
|
||||
device_type = "memory";
|
||||
reg = <2 0x00000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x3_clk: x3-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x16_clk: x16-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x14_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&soundcodec>;
|
||||
simple-audio-card,frame-master = <&soundcodec>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
soundcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4642>;
|
||||
clocks = <&x14_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader_prg";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user_prg";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash_fs";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak4642: codec@12 {
|
||||
compatible = "asahi-kasei,ak4642";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x3_clk>, <&x16_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>;
|
||||
capture = <&ssi1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
13
arch/arm/dts/r8a7791-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7791-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7791 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1665
arch/arm/dts/r8a7791.dtsi
Normal file
1665
arch/arm/dts/r8a7791.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
10
arch/arm/dts/r8a7792-blanche-u-boot.dts
Normal file
10
arch/arm/dts/r8a7792-blanche-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Blanche board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7792-blanche.dts"
|
||||
#include "r8a7792-u-boot.dtsi"
|
||||
327
arch/arm/dts/r8a7792-blanche.dts
Normal file
327
arch/arm/dts/r8a7792-blanche.dts
Normal file
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
* Device Tree Source for the Blanche board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7792.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Blanche";
|
||||
compatible = "renesas,blanche", "renesas,r8a7792";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ethernet@18000000 {
|
||||
compatible = "smsc,lan89218", "smsc,lan9115";
|
||||
reg = <0 0x18000000 0 0x100>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||
smsc,irq-push-pull;
|
||||
reg-io-width = <4>;
|
||||
vddvario-supply = <&d3_3v>;
|
||||
vdd33a-supply = <&d3_3v>;
|
||||
|
||||
pinctrl-0 = <&lan89218_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x1_clk: x1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x2_clk: x2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <65000000>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-2 {
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-3 {
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-4 {
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-a {
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW24";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-b {
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW25";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led17 {
|
||||
gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led18 {
|
||||
gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led19 {
|
||||
gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led20 {
|
||||
gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&can_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif3_pins: scif3 {
|
||||
groups = "scif3_data";
|
||||
function = "scif3";
|
||||
};
|
||||
|
||||
lan89218_pins: lan89218 {
|
||||
intc {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
lbsc {
|
||||
groups = "lbsc_ex_cs0";
|
||||
function = "lbsc";
|
||||
};
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data", "can_clk";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
sdhi0_pins: sdhi0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
du0_pins: du0 {
|
||||
groups = "du0_rgb888", "du0_sync", "du0_disp";
|
||||
function = "du0";
|
||||
};
|
||||
|
||||
du1_pins: du1 {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp";
|
||||
function = "du1";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif3 {
|
||||
pinctrl-0 = <&scif3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
9
arch/arm/dts/r8a7792-u-boot.dtsi
Normal file
9
arch/arm/dts/r8a7792-u-boot.dtsi
Normal file
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7792 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
857
arch/arm/dts/r8a7792.dtsi
Normal file
857
arch/arm/dts/r8a7792.dtsi
Normal file
@@ -0,0 +1,857 @@
|
||||
/*
|
||||
* Device Tree Source for the r8a7792 SoC
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7792-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7792";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
spi0 = &qspi;
|
||||
spi1 = &msiof0;
|
||||
spi2 = &msiof1;
|
||||
vin0 = &vin0;
|
||||
vin1 = &vin1;
|
||||
vin2 = &vin2;
|
||||
vin3 = &vin3;
|
||||
vin4 = &vin4;
|
||||
vin5 = &vin5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
L2_CA15: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_SCU>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1001000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1001000 0 0x1000>,
|
||||
<0 0xf1002000 0 0x2000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
irqc: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7792", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a7792-rst";
|
||||
reg = <0 0xe6160000 0 0x0100>;
|
||||
};
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7792-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7792";
|
||||
reg = <0 0xe6060000 0 0x144>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 29>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 912>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 23>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 911>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 910>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 28>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 909>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 908>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055100 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055100 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 905>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055200 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055200 0 0x50>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 904>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 904>;
|
||||
};
|
||||
|
||||
gpio8: gpio@e6055300 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055300 0 0x50>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 256 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 921>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 921>;
|
||||
};
|
||||
|
||||
gpio9: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 288 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 919>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 919>;
|
||||
};
|
||||
|
||||
gpio10: gpio@e6055500 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055500 0 0x50>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 320 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 914>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
};
|
||||
|
||||
gpio11: gpio@e6055600 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055600 0 0x50>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 352 30>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 913>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 913>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e60000 0 64>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
||||
<&dmac1 0x29>, <&dmac1 0x2a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 721>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif1: serial@e6e68000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e68000 0 64>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 720>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
||||
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 720>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@e6e58000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e58000 0 64>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 719>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
||||
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 719>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif3: serial@e6ea8000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6ea8000 0 64>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 718>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
||||
<&dmac1 0x2f>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 718>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e62c0000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c0000 0 96>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 717>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
||||
<&dmac1 0x39>, <&dmac1 0x3a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 717>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif1: serial@e62c8000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c8000 0 96>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 716>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
||||
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 716>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
icram0: sram@e63a0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63a0000 0 0x12000>;
|
||||
};
|
||||
|
||||
icram1: sram@e63c0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63c0000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xe63c0000 0x1000>;
|
||||
|
||||
smp-sram@0 {
|
||||
compatible = "renesas,smp-sram";
|
||||
reg = <0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7792";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
<&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7792",
|
||||
"renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 106>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 106>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7792",
|
||||
"renesas,etheravb-rcar-gen2";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C doesn't need pinmux */
|
||||
i2c0: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6518000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6530000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e6540000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 928>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@e6520000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 927>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 927>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@e6528000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 925>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 925>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
||||
<&dmac1 0x17>, <&dmac1 0x18>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e20000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e20000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 000>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
|
||||
<&dmac1 0x51>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6e10000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
|
||||
<&dmac1 0x55>, <&dmac1 0x56>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 811>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 810>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 809>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 805>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 804>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vsp@fe928000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 131>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 131>;
|
||||
};
|
||||
|
||||
vsp@fe930000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 128>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 128>;
|
||||
};
|
||||
|
||||
vsp@fe938000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 127>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 127>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7792-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
10
arch/arm/dts/r8a7793-gose-u-boot.dts
Normal file
10
arch/arm/dts/r8a7793-gose-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Gose board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7793-gose.dts"
|
||||
#include "r8a7793-u-boot.dtsi"
|
||||
727
arch/arm/dts/r8a7793-gose.dts
Normal file
727
arch/arm/dts/r8a7793-gose.dts
Normal file
@@ -0,0 +1,727 @@
|
||||
/*
|
||||
* Device Tree Source for the Gose board
|
||||
*
|
||||
* Copyright (C) 2014-2015 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7793.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Gose";
|
||||
compatible = "renesas,gose", "renesas,r8a7793";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-a {
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW30";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-b {
|
||||
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW31";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-c {
|
||||
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_C>;
|
||||
label = "SW32";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-d {
|
||||
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_D>;
|
||||
label = "SW33";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-e {
|
||||
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_E>;
|
||||
label = "SW34";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-f {
|
||||
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_F>;
|
||||
label = "SW35";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-g {
|
||||
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_G>;
|
||||
label = "SW36";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED6";
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED7";
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED8";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: scif1 {
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
pinctrl-0 = <&scif1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
adv7180_out: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,r1ex24002", "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep: endpoint {
|
||||
remote-endpoint = <&adv7180_out>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
13
arch/arm/dts/r8a7793-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7793-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7793 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1332
arch/arm/dts/r8a7793.dtsi
Normal file
1332
arch/arm/dts/r8a7793.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
10
arch/arm/dts/r8a7794-alt-u-boot.dts
Normal file
10
arch/arm/dts/r8a7794-alt-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Alt board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7794-alt.dts"
|
||||
#include "r8a7794-u-boot.dtsi"
|
||||
414
arch/arm/dts/r8a7794-alt.dts
Normal file
414
arch/arm/dts/r8a7794-alt.dts
Normal file
@@ -0,0 +1,414 @@
|
||||
/*
|
||||
* Device Tree Source for the Alt board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Alt";
|
||||
compatible = "renesas,alt", "renesas,r8a7794";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
i2c10 = &gpioi2c4;
|
||||
i2c12 = &i2cexio4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-d3-3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c4: i2c-10 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
|
||||
* A fallback to GPIO is provided.
|
||||
*/
|
||||
i2cexio4: i2c-14 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&i2c4>, <&gpioi2c4>;
|
||||
i2c-bus-name = "i2c-exio4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||
function = "du1";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4 {
|
||||
groups = "i2c4";
|
||||
function = "i2c4";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
mmcif0_pins: mmcif0 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmcif0 {
|
||||
pinctrl-0 = <&mmcif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&d3_3v>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "i2c-exio4";
|
||||
};
|
||||
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "system";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "user";
|
||||
reg = <0x00080000 0x03f80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
10
arch/arm/dts/r8a7794-silk-u-boot.dts
Normal file
10
arch/arm/dts/r8a7794-silk-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Silk board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7794-silk.dts"
|
||||
#include "r8a7794-u-boot.dtsi"
|
||||
460
arch/arm/dts/r8a7794-silk.dts
Normal file
460
arch/arm/dts/r8a7794-silk.dts
Normal file
@@ -0,0 +1,460 @@
|
||||
/*
|
||||
* Device Tree Source for the SILK board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2014-2015 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014-2015 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 2-1: AK4643
|
||||
* 2-3: ADV7511
|
||||
*
|
||||
* This command is required before playback/capture:
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "SILK";
|
||||
compatible = "renesas,silk", "renesas,r8a7794";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-d3-3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x3_clk: x3-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x9_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&soundcodec>;
|
||||
simple-audio-card,frame-master = <&soundcodec>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
soundcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&x9_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
mmcif0_pins: mmcif0 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
du0_pins: du0 {
|
||||
groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
|
||||
function = "du0";
|
||||
};
|
||||
|
||||
du1_pins: du1 {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||
function = "du1";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
groups = "audio_clkc";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmcif0 {
|
||||
pinctrl-0 = <&mmcif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&d3_3v>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x2_clk>, <&x3_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>;
|
||||
capture = <&ssi1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
13
arch/arm/dts/r8a7794-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7794-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7794 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1347
arch/arm/dts/r8a7794.dtsi
Normal file
1347
arch/arm/dts/r8a7794.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
10
arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
Normal file
10
arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the ULCB board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7795-h3ulcb.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
@@ -4,13 +4,9 @@
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include "ulcb.dtsi"
|
||||
@@ -40,3 +36,17 @@
|
||||
reg = <0x7 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
|
||||
};
|
||||
|
||||
10
arch/arm/dts/r8a7795-salvator-x-u-boot.dts
Normal file
10
arch/arm/dts/r8a7795-salvator-x-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Salvator-X board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7795-salvator-x.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
@@ -3,13 +3,9 @@
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include "salvator-x.dtsi"
|
||||
|
||||
13
arch/arm/dts/r8a7795-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7795-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7795 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
@@ -3,15 +3,15 @@
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7795";
|
||||
#address-cells = <2>;
|
||||
@@ -129,7 +129,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
@@ -137,7 +136,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -191,7 +189,6 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
@@ -383,7 +380,6 @@
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
@@ -394,7 +390,6 @@
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
@@ -696,6 +691,126 @@
|
||||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x64>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x64>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x64>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x64>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x64>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x64>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
@@ -781,6 +896,68 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e90000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6e90000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
||||
<&dmac2 0x41>, <&dmac2 0x40>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 211>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6ea0000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6ea0000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof2: spi@e6c00000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c00000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 209>;
|
||||
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 209>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof3: spi@e6c10000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
@@ -1272,7 +1449,8 @@
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7795";
|
||||
compatible = "renesas,sata-r8a7795",
|
||||
"renesas,rcar-gen3-sata";
|
||||
reg = <0 0xee300000 0 0x200000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
@@ -1319,6 +1497,34 @@
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac2: dma-controller@e6460000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe6460000 0 0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 326>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 326>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac3: dma-controller@e6470000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe6470000 0 0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 329>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 329>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
@@ -1397,6 +1603,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy3: usb-phy@ee0e0200 {
|
||||
compatible = "renesas,usb2-phy-r8a7795",
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee0e0200 0 0x700>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
@@ -1404,6 +1622,7 @@
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
@@ -1416,6 +1635,7 @@
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
@@ -1428,11 +1648,25 @@
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci2>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 701>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci3: usb@ee0e0100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee0e0100 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci3>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
@@ -1469,6 +1703,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci3: usb@ee0e0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0e0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
@@ -1486,6 +1732,23 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb3: usb@e659c000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe659c000 0 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 705>;
|
||||
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
|
||||
<&usb_dmac3 0>, <&usb_dmac3 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 705>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7795",
|
||||
"renesas,pcie-rcar-gen3";
|
||||
@@ -1540,6 +1803,46 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
imr-lx4@fe860000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe860000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 823>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 823>;
|
||||
};
|
||||
|
||||
imr-lx4@fe870000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe870000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 822>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 822>;
|
||||
};
|
||||
|
||||
imr-lx4@fe880000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe880000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 821>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 821>;
|
||||
};
|
||||
|
||||
imr-lx4@fe890000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe890000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 820>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 820>;
|
||||
};
|
||||
|
||||
vspbc: vsp@fe920000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe920000 0 0x8000>;
|
||||
@@ -1760,6 +2063,7 @@
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
@@ -1773,6 +2077,7 @@
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
|
||||
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
||||
10
arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
Normal file
10
arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the ULCB board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7796-m3ulcb.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
@@ -4,13 +4,9 @@
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7796.dtsi"
|
||||
#include "ulcb.dtsi"
|
||||
@@ -30,3 +26,15 @@
|
||||
reg = <0x6 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
10
arch/arm/dts/r8a7796-salvator-x-u-boot.dts
Normal file
10
arch/arm/dts/r8a7796-salvator-x-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Salvator-X board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7796-salvator-x.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
@@ -3,13 +3,9 @@
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7796.dtsi"
|
||||
#include "salvator-x.dtsi"
|
||||
@@ -29,3 +25,32 @@
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&x21_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
13
arch/arm/dts/r8a7796-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7796-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7796 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
@@ -3,15 +3,15 @@
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7796-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7796";
|
||||
#address-cells = <2>;
|
||||
@@ -111,7 +111,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
@@ -119,7 +118,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -172,7 +170,6 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
@@ -366,7 +363,6 @@
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
@@ -377,7 +373,6 @@
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
@@ -644,6 +639,126 @@
|
||||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x64>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x64>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x64>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x64>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x64>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x64>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7796",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
@@ -882,7 +997,7 @@
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
||||
<&dmac2 0x41>, <&dmac2 0x40>;
|
||||
dma-names = "tx", "rx";
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 211>;
|
||||
#address-cells = <1>;
|
||||
@@ -898,7 +1013,7 @@
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
@@ -1106,12 +1221,43 @@
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7796-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 330>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,r8a7796-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 331>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 331>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7796",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
@@ -1121,7 +1267,8 @@
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci";
|
||||
compatible = "renesas,xhci-r8a7796",
|
||||
"renesas,rcar-gen3-xhci";
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
@@ -1131,7 +1278,15 @@
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
/* placeholder */
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
@@ -1141,6 +1296,7 @@
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci0>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
@@ -1159,7 +1315,15 @@
|
||||
};
|
||||
|
||||
ohci1: usb@ee0a0000 {
|
||||
/* placeholder */
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@ee0a0100 {
|
||||
@@ -1169,6 +1333,7 @@
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci1>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
@@ -1492,8 +1657,150 @@
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
compatible = "renesas,fcpf";
|
||||
reg = <0 0xfe950000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 615>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 615>;
|
||||
};
|
||||
|
||||
vspb: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 626>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 626>;
|
||||
|
||||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 607>;
|
||||
};
|
||||
|
||||
vspi0: vsp@fe9a0000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe9a0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 631>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 631>;
|
||||
|
||||
renesas,fcp = <&fcpvi0>;
|
||||
};
|
||||
|
||||
fcpvi0: fcp@fe9af000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe9af000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 611>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 611>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 623>;
|
||||
|
||||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 622>;
|
||||
|
||||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 602>;
|
||||
};
|
||||
|
||||
vspd2: vsp@fea30000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea30000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 621>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 621>;
|
||||
|
||||
renesas,fcp = <&fcpvd2>;
|
||||
};
|
||||
|
||||
fcpvd2: fcp@fea37000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea37000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 601>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 601>;
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 729>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dw_hdmi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
/* placeholder */
|
||||
compatible = "renesas,du-r8a7796";
|
||||
reg = <0 0xfeb00000 0 0x70000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0";
|
||||
status = "disabled";
|
||||
|
||||
vsps = <&vspd0 &vspd1 &vspd2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@@ -1504,7 +1811,38 @@
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_hdmi0: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
imr-lx4@fe860000 {
|
||||
compatible = "renesas,r8a7796-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe860000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 823>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 823>;
|
||||
};
|
||||
|
||||
imr-lx4@fe870000 {
|
||||
compatible = "renesas,r8a7796-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe870000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 822>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 822>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
10
arch/arm/dts/r8a77970-eagle-u-boot.dts
Normal file
10
arch/arm/dts/r8a77970-eagle-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Eagle board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a77970-eagle.dts"
|
||||
#include "r8a77970-u-boot.dtsi"
|
||||
@@ -4,9 +4,7 @@
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
13
arch/arm/dts/r8a77970-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a77970-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A77970 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
@@ -4,9 +4,7 @@
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
@@ -50,7 +48,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
@@ -58,7 +55,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
@@ -75,7 +71,6 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
@@ -114,7 +109,6 @@
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
@@ -152,7 +146,6 @@
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
|
||||
10
arch/arm/dts/r8a77995-draak-u-boot.dts
Normal file
10
arch/arm/dts/r8a77995-draak-u-boot.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Draak board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a77995-draak.dts"
|
||||
#include "r8a77995-u-boot.dtsi"
|
||||
@@ -4,9 +4,7 @@
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
9
arch/arm/dts/r8a77995-u-boot.dtsi
Normal file
9
arch/arm/dts/r8a77995-u-boot.dtsi
Normal file
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A77995 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
@@ -4,9 +4,7 @@
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
|
||||
@@ -49,7 +47,6 @@
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
scif_clk: scif {
|
||||
@@ -64,7 +61,6 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
@@ -118,7 +114,6 @@
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
@@ -134,7 +129,6 @@
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
|
||||
25
arch/arm/dts/r8a779x-u-boot.dtsi
Normal file
25
arch/arm/dts/r8a779x-u-boot.dtsi
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar Gen3
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&prr {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
@@ -62,6 +62,7 @@
|
||||
brightness-levels = <256 128 64 16 8 4 0>;
|
||||
default-brightness-level = <6>;
|
||||
|
||||
power-supply = <®_12v>;
|
||||
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
@@ -83,6 +84,15 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12v: regulator2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-12V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
@@ -247,7 +257,6 @@
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
@@ -269,10 +278,6 @@
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -43,6 +43,16 @@
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
@@ -129,6 +139,12 @@
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
x23_clk: x23-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
@@ -140,7 +156,6 @@
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
@@ -163,6 +178,23 @@
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
@@ -199,6 +231,20 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
versaclock5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5925";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&x23_clk>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -1,5 +1,31 @@
|
||||
if RCAR_32
|
||||
|
||||
config RCAR_GEN2
|
||||
bool "Renesas RCar Gen2"
|
||||
|
||||
config R8A7740
|
||||
bool "Renesas SoC R8A7740"
|
||||
|
||||
config R8A7790
|
||||
bool "Renesas SoC R8A7790"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7791
|
||||
bool "Renesas SoC R8A7791"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7792
|
||||
bool "Renesas SoC R8A7792"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7793
|
||||
bool "Renesas SoC R8A7793"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7794
|
||||
bool "Renesas SoC R8A7794"
|
||||
select RCAR_GEN2
|
||||
|
||||
choice
|
||||
prompt "Renesas ARM SoCs board select"
|
||||
optional
|
||||
|
||||
Reference in New Issue
Block a user