Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig
This converts the following to Kconfig: CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DM9000_DEBUG CONFIG_MXC_GPT_HCLK CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
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6bd2372094
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9b0240f8c6
@ -915,6 +915,7 @@ config ARCH_MX7
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select CPU_V7A
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select CPU_V7A
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select GPIO_EXTRA_HEADER
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select GPIO_EXTRA_HEADER
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select MACH_IMX
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select MACH_IMX
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select MXC_GPT_HCLK
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_4
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select SYS_FSL_SEC_COMPAT_4
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select SYS_FSL_SEC_LE
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select SYS_FSL_SEC_LE
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@ -928,6 +929,7 @@ config ARCH_MX6
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select CPU_V7A
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select CPU_V7A
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select GPIO_EXTRA_HEADER
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select GPIO_EXTRA_HEADER
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select MACH_IMX
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select MACH_IMX
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select MXC_GPT_HCLK
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_4
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select SYS_FSL_SEC_COMPAT_4
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select SYS_FSL_SEC_LE
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select SYS_FSL_SEC_LE
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@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER
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config GPT_TIMER
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config GPT_TIMER
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bool
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bool
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config MXC_GPT_HCLK
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bool
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config IMX_RDC
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config IMX_RDC
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bool "i.MX Resource domain controller driver"
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bool "i.MX Resource domain controller driver"
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depends on ARCH_MX6 || ARCH_MX7
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depends on ARCH_MX6 || ARCH_MX7
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@ -37,6 +37,9 @@ config SYS_VENDOR
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config SYS_CONFIG_NAME
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config SYS_CONFIG_NAME
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default "omapl138_lcdk"
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default "omapl138_lcdk"
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config NAND_6BYTES_OOB_FREE_10BYTES_ECC
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def_bool y
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endif
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endif
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source "board/ti/common/Kconfig"
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source "board/ti/common/Kconfig"
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@ -76,10 +76,11 @@ int board_init(void)
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}
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}
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/* Configure GPMC registers for DM9000 */
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/* Configure GPMC registers for DM9000 */
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#define DM9000_BASE 0x2c000000
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static void gpmc_dm9000_config(void)
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static void gpmc_dm9000_config(void)
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{
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{
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
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CONFIG_DM9000_BASE, GPMC_SIZE_16M);
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DM9000_BASE, GPMC_SIZE_16M);
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}
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}
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/*
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/*
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@ -100,9 +101,7 @@ int misc_init_r(void)
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#endif
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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#ifdef CONFIG_DRIVER_DM9000
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/* Configure GPMC registers for DM9000 */
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gpmc_dm9000_config();
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
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CONFIG_DM9000_BASE, GPMC_SIZE_16M);
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/* Use OMAP DIE_ID as MAC address */
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/* Use OMAP DIE_ID as MAC address */
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if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
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if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
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@ -44,4 +44,5 @@ CONFIG_MTD_NOR_FLASH=y
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CONFIG_SYS_MAX_FLASH_SECT=2048
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CONFIG_SYS_MAX_FLASH_SECT=2048
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CONFIG_USE_SYS_MAX_FLASH_BANKS=y
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CONFIG_USE_SYS_MAX_FLASH_BANKS=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DM9000_BYTE_SWAPPED=y
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CONFIG_MCFUART=y
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CONFIG_MCFUART=y
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@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DM9000_NO_SROM=y
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CONFIG_DM9000_USE_16BIT=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SERIAL=y
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@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DM9000_NO_SROM=y
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CONFIG_DM9000_USE_16BIT=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SERIAL=y
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@ -52,6 +52,8 @@ CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DM9000_NO_SROM=y
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CONFIG_DM9000_USE_16BIT=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SERIAL=y
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@ -84,4 +84,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_DRIVER_DM9000=y
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CONFIG_DRIVER_DM9000=y
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CONFIG_DM9000_NO_SROM=y
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CONFIG_DM9000_USE_16BIT=y
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CONFIG_JFFS2_NAND=y
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CONFIG_JFFS2_NAND=y
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@ -198,6 +198,18 @@ config DRIVER_DM9000
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help
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help
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The Davicom DM9000 parallel bus external ethernet interface chip.
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The Davicom DM9000 parallel bus external ethernet interface chip.
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config DM9000_BYTE_SWAPPED
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bool "Byte swapped access for DM9000"
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depends on DRIVER_DM9000
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config DM9000_NO_SROM
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bool "No SROM on DM9000"
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depends on DRIVER_DM9000
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config DM9000_USE_16BIT
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bool "Use 16bit access in DM9000"
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depends on DRIVER_DM9000
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config DWC_ETH_QOS
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config DWC_ETH_QOS
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bool "Synopsys DWC Ethernet QOS device support"
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bool "Synopsys DWC Ethernet QOS device support"
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select PHYLIB
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select PHYLIB
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@ -20,12 +20,6 @@
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env/embedded.o(.text*);
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env/embedded.o(.text*);
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#ifdef CONFIG_DRIVER_DM9000
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#ifdef CONFIG_DRIVER_DM9000
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# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300)
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# define DM9000_IO CONFIG_DM9000_BASE
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# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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# undef CONFIG_DM9000_DEBUG
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# define CONFIG_DM9000_BYTE_SWAPPED
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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# define CONFIG_EXTRA_ENV_SETTINGS \
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# define CONFIG_EXTRA_ENV_SETTINGS \
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@ -34,13 +34,6 @@
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#endif
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#endif
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/* Ethernet */
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#define CONFIG_DM9000_BASE 0x30000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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#define CONFIG_DM9000_USE_16BIT
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#define CONFIG_DM9000_NO_SROM
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/* USB */
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/* USB */
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#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
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#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
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@ -16,8 +16,6 @@
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#define CFG_SYS_PL310_BASE L2_PL310_BASE
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#define CFG_SYS_PL310_BASE L2_PL310_BASE
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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#define CONFIG_MXC_GPT_HCLK
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/* MMC */
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/* MMC */
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/* Boot */
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/* Boot */
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@ -17,11 +17,4 @@
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/* NS16550-ish UARTs */
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/* NS16550-ish UARTs */
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#define CFG_SYS_NS16550_CLK 48000000
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#define CFG_SYS_NS16550_CLK 48000000
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/* Ethernet: davicom DM9000 */
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#define CONFIG_DM9000_BASE 0xb6000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
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/* Miscellaneous configuration options */
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#endif /* __CONFIG_CI20_H__ */
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#endif /* __CONFIG_CI20_H__ */
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@ -16,17 +16,6 @@
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#include <configs/ti_omap3_common.h>
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#include <configs/ti_omap3_common.h>
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/* Hardware drivers */
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/* DM9000 */
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#define CONFIG_DM9000_BASE 0x2c000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
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#define CONFIG_DM9000_USE_16BIT 1
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#define CONFIG_DM9000_NO_SROM 1
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#undef CONFIG_DM9000_DEBUG
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/* TWL4030 */
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/* BOOTP/DHCP options */
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/* BOOTP/DHCP options */
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#define MEM_LAYOUT_ENV_SETTINGS \
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#define MEM_LAYOUT_ENV_SETTINGS \
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@ -16,7 +16,6 @@
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#endif
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#endif
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#endif
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#endif
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#define CONFIG_MXC_GPT_HCLK
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#include <linux/sizes.h>
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx-regs.h>
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@ -14,7 +14,6 @@
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/gpio.h>
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/* Timer settings */
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/* Timer settings */
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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/* Miscellaneous configurable options */
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/* Miscellaneous configurable options */
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@ -109,7 +109,6 @@
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#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CFG_SYS_NAND_MASK_CLE 0x10
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#define CFG_SYS_NAND_MASK_CLE 0x10
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#define CFG_SYS_NAND_MASK_ALE 0x8
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#define CFG_SYS_NAND_MASK_ALE 0x8
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#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
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#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
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#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
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