From e104a9f8eb9f105c784e4b8addb5147001de0df6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 May 2022 16:03:04 -0300 Subject: [PATCH 01/14] imx8mn_evk: Add the missing spl.bin entry The generated flash.bin does not boot the imx8mn evk LPDDR4 variant as it misses the spl.bin description in binman. Add its entry to fix the boot on the imx8mn evk LPDDR4 variant. Signed-off-by: Fabio Estevam Tested-by: Arti Zirk Reviewed-by: Alper Nebi Yasak --- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi index 3db46d4cbc..593cf06eb9 100644 --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -58,7 +58,9 @@ }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; From 4941035143a467bb356af7bfe6bfe3f04b2186f1 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Mon, 9 May 2022 18:58:15 +0200 Subject: [PATCH 02/14] toradex: tdx-cfg-block: add new 8gb apalis-imx8 0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT This module is identical to its 4GB counterpart 0037: Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT except for the RAM size. Signed-off-by: Philippe Schenker Reviewed-by: Francesco Dolcini Acked-by: Marcel Ziswiler --- board/toradex/common/tdx-cfg-block.c | 18 ++++++++++++++++-- board/toradex/common/tdx-cfg-block.h | 1 + 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 9c87289ae9..6c8cf4592d 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -144,6 +144,7 @@ const char * const toradex_modules[] = { [64] = "Verdin iMX8M Plus Quad 2GB Wi-Fi / BT IT", [65] = "Verdin iMX8M Plus QuadLite 1GB IT", [66] = "Verdin iMX8M Plus Quad 8GB Wi-Fi / BT", + [67] = "Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT", }; const char * const toradex_carrier_boards[] = { @@ -359,6 +360,7 @@ static int get_cfgblock_interactive(void) char *soc; char it = 'n'; char wb = 'n'; + char mem8g = 'n'; int len = 0; /* Unknown module by default */ @@ -377,6 +379,14 @@ static int get_cfgblock_interactive(void) sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] "); len = cli_readline(message); wb = console_buffer[0]; + +#if defined(CONFIG_TARGET_APALIS_IMX8) + if ((wb == 'y' || wb == 'Y') && (it == 'y' || it == 'Y')) { + sprintf(message, "Does your module have 8GB of RAM? [y/N] "); + len = cli_readline(message); + mem8g = console_buffer[0]; + } +#endif #endif soc = env_get("soc"); @@ -430,8 +440,12 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7S; else if (is_cpu_type(MXC_CPU_IMX8QM)) { if (it == 'y' || it == 'Y') { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT; + if (wb == 'y' || wb == 'Y') { + if (mem8g == 'y' || mem8g == 'Y') + tdx_hw_tag.prodid = APALIS_IMX8QM_8GB_WIFI_BT_IT; + else + tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT; + } else tdx_hw_tag.prodid = APALIS_IMX8QM_IT; } else { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index ddcf699748..43e662e41d 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -87,6 +87,7 @@ enum { VERDIN_IMX8MPQ_2GB_WIFI_BT_IT, VERDIN_IMX8MPQL_IT, /* 65 */ VERDIN_IMX8MPQ_8GB_WIFI_BT, + APALIS_IMX8QM_8GB_WIFI_BT_IT, }; enum { From 0da8dde6343fb91628794f9772b119bc7241c8a1 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Mon, 9 May 2022 18:58:16 +0200 Subject: [PATCH 03/14] board: apalis-imx8: add new 8gb product variant Add the new Apalis iMX8 product variant 0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT the only difference to the product 0037 Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT is the 8gb of RAM. Toradex strategy to choose the correct RAM timing in SCFW is by fuses in the user area telling which RAM timing to load. This commit makes use of this information to set the correct size of the RAM and therefore distinguish between the new 0067 and 0037 product Signed-off-by: Philippe Schenker Reviewed-by: Francesco Dolcini Acked-by: Marcel Ziswiler --- board/toradex/apalis-imx8/apalis-imx8.c | 81 +++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 04877fcd94..408198843f 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/tdx-cfg-block.h" @@ -28,22 +29,75 @@ DECLARE_GLOBAL_DATA_PTR; (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define TDX_USER_FUSE_BLOCK1_A 276 +#define TDX_USER_FUSE_BLOCK1_B 277 +#define TDX_USER_FUSE_BLOCK2_A 278 +#define TDX_USER_FUSE_BLOCK2_B 279 + static iomux_cfg_t uart1_pads[] = { SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +struct tdx_user_fuses { + u16 pid4; + u16 vers; + u8 ramid; +}; + static void setup_iomux_uart(void) { imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +static uint32_t do_get_tdx_user_fuse(int a, int b) +{ + sc_err_t sciErr; + u32 val_a = 0; + u32 val_b = 0; + + sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", a); + return 0; + } + + sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", b); + return 0; + } + + return ((val_a & 0xffff) << 16) | (val_b & 0xffff); +} + +static void get_tdx_user_fuse(struct tdx_user_fuses *tdxuserfuse) +{ + u32 fuse_block; + + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK2_A, + TDX_USER_FUSE_BLOCK2_B); + + /* + * Fuse block 2 acts as a backup area, if this reads 0 we want to + * use fuse block 1 + */ + if (fuse_block == 0) + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK1_A, + TDX_USER_FUSE_BLOCK1_B); + + tdxuserfuse->pid4 = (fuse_block >> 18) & GENMASK(13, 0); + tdxuserfuse->vers = (fuse_block >> 4) & GENMASK(13, 0); + tdxuserfuse->ramid = fuse_block & GENMASK(3, 0); +} + void board_mem_get_layout(u64 *phys_sdram_1_start, u64 *phys_sdram_1_size, u64 *phys_sdram_2_start, u64 *phys_sdram_2_size) { u32 is_quadplus = 0, val = 0; + struct tdx_user_fuses tdxramfuses; sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); if (scierr == SC_ERR_NONE) { @@ -51,14 +105,33 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, is_quadplus = ((val >> 4) & 0x3) != 0x0; } + get_tdx_user_fuse(&tdxramfuses); + *phys_sdram_1_start = PHYS_SDRAM_1; *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; *phys_sdram_2_start = PHYS_SDRAM_2; - if (is_quadplus) - /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + + switch (tdxramfuses.ramid) { + case 1: + *phys_sdram_2_size = SZ_2G; + break; + case 2: *phys_sdram_2_size = 0x0UL; - else - *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + case 3: + *phys_sdram_2_size = SZ_2G; + break; + case 4: + *phys_sdram_2_size = SZ_4G + SZ_2G; + break; + default: + if (is_quadplus) + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + *phys_sdram_2_size = 0x0UL; + else + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + } } int board_early_init_f(void) From 827ded0e82e5a000cfb4e7bd2697a320c65d835a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 May 2022 13:23:09 -0300 Subject: [PATCH 04/14] imx8mn_evk: Add Ethernet support to the LPDDR4 variant The imx8mn-ddr4-evk board has Ethernet support already, but the lpddr4 board does not. Add Ethernet support for the LPDDR4 variant too. Signed-off-by: Fabio Estevam --- configs/imx8mn_evk_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index c18c19fa14..52954b0463 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -70,7 +73,12 @@ CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y From 4cc25cd5ce6923ccd0a6164703bcbde0216fd77d Mon Sep 17 00:00:00 2001 From: Nate Drude Date: Thu, 19 May 2022 12:31:56 +0300 Subject: [PATCH 05/14] phy: adin: fix broken support for adi, phy-mode-override Currently, the adin driver fails to compile. The original patch introducing the adin driver used the function phy_get_interface_by_name to support the adi,phy-mode-override property. Unfortunately, a few days before the adin patch was accepted, another patch removed support for phy_get_interface_by_name: https://github.com/u-boot/u-boot/commit/123ca114e07ecf28aa2538748d733e2b22d8b8b5 This patch refactors adin_get_phy_mode_override, implementing the logic in the new function, ofnode_read_phy_mode, from the patch above. Signed-off-by: Nate Drude Tested-by: Josua Mayer Signed-off-by: Josua Mayer --- drivers/net/phy/adin.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index cff841ab3d..e60f288b9b 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -100,27 +100,27 @@ static u32 adin_get_reg_value(struct phy_device *phydev, * The function gets phy-mode string from property 'adi,phy-mode-override' * and return its index in phy_interface_strings table, or -1 in error case. */ -int adin_get_phy_mode_override(struct phy_device *phydev) +phy_interface_t adin_get_phy_mode_override(struct phy_device *phydev) { ofnode node = phy_get_ofnode(phydev); const char *phy_mode_override; const char *prop_phy_mode_override = "adi,phy-mode-override"; - int override_interface; + int i; phy_mode_override = ofnode_read_string(node, prop_phy_mode_override); if (!phy_mode_override) - return -ENODEV; + return PHY_INTERFACE_MODE_NA; debug("%s: %s = '%s'\n", __func__, prop_phy_mode_override, phy_mode_override); - override_interface = phy_get_interface_by_name(phy_mode_override); + for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) + if (!strcmp(phy_mode_override, phy_interface_strings[i])) + return (phy_interface_t) i; - if (override_interface < 0) - printf("%s: %s = '%s' is not valid\n", - __func__, prop_phy_mode_override, phy_mode_override); + printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode_override); - return override_interface; + return PHY_INTERFACE_MODE_NA; } static u16 adin_ext_read(struct phy_device *phydev, const u32 regnum) @@ -148,10 +148,10 @@ static int adin_config_rgmii_mode(struct phy_device *phydev) { u16 reg_val; u32 val; - int phy_mode_override = adin_get_phy_mode_override(phydev); + phy_interface_t phy_mode_override = adin_get_phy_mode_override(phydev); - if (phy_mode_override >= 0) { - phydev->interface = (phy_interface_t) phy_mode_override; + if (phy_mode_override != PHY_INTERFACE_MODE_NA) { + phydev->interface = phy_mode_override; } reg_val = adin_ext_read(phydev, ADIN1300_GE_RGMII_CFG); From 54337abb141d898ae114f51619531cf905d5b0b5 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 19 May 2022 12:31:57 +0300 Subject: [PATCH 06/14] phy: adin: add support for clock output The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. This patch is based on the Linux implementation for this feature, which has been added to netdev/net-next.git [1]. [2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/ Signed-off-by: Josua Mayer --- drivers/net/phy/adin.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index e60f288b9b..a5bfd960d9 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -4,6 +4,7 @@ * * Copyright 2019 Analog Devices Inc. * Copyright 2022 Variscite Ltd. + * Copyright 2022 Josua Mayer */ #include #include @@ -13,6 +14,16 @@ #define PHY_ID_ADIN1300 0x0283bc30 #define ADIN1300_EXT_REG_PTR 0x10 #define ADIN1300_EXT_REG_DATA 0x11 + +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) +#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) +#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) +#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) +#define ADIN1300_GE_CLK_CFG_25 BIT(0) + #define ADIN1300_GE_RGMII_CFG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -144,6 +155,33 @@ static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val); } +static int adin_config_clk_out(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + const char *val = NULL; + u8 sel = 0; + + val = ofnode_read_string(node, "adi,phy-output-clock"); + if (!val) { + /* property not present, do not enable GP_CLK pin */ + } else if (strcmp(val, "25mhz-reference") == 0) { + sel |= ADIN1300_GE_CLK_CFG_25; + } else if (strcmp(val, "125mhz-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if (strcmp(val, "adaptive-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; + } else { + pr_err("%s: invalid adi,phy-output-clock\n", __func__); + return -EINVAL; + } + + if (ofnode_read_bool(node, "adi,phy-output-reference-clock")) + sel |= ADIN1300_GE_CLK_CFG_REF_EN; + + return adin_ext_write(phydev, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK & sel); +} + static int adin_config_rgmii_mode(struct phy_device *phydev) { u16 reg_val; @@ -202,6 +240,10 @@ static int adin1300_config(struct phy_device *phydev) printf("ADIN1300 PHY detected at addr %d\n", phydev->addr); + ret = adin_config_clk_out(phydev); + if (ret < 0) + return ret; + ret = adin_config_rgmii_mode(phydev); if (ret < 0) From 17baba4682001cc11446ff8406c63850b46edf72 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 19 May 2022 12:31:58 +0300 Subject: [PATCH 07/14] ARM: dts: imx6qdl-sr-som: add support for alternate phy addresses The Cubox has an unstable phy address - which can appear at either address 0 (intended) or 4 (unintended). SoM revision 1.9 has replaced the ar8035 phy with an adin1300, which will always appear at address 1. Change the reg property of the phy node to the magic value 0xffffffff, which indicates to the generic phy driver that all addresses should be probed. That allows the same node (which is pinned by phy-handle) to match either the AR8035 PHY at both possible addresses, as well as the new one at address 1. Also add the new adi,phy-output-clock property for enabling the 125MHz clock used by the fec ethernet controller, as submitted to Linux [1]. Linux solves this problem differently: For the ar8035 phy it will probe both phy nodes in device-tree in order, and use the one that succeeds. For the new adin1300 it expects U-Boot to patch the status field in the DTB before booting While at it also sync the reset-delay with the upstream Linux dtb. [1] https://patchwork.kernel.org/project/netdevbpf/patch/20220428082848.12191-4-josua@solid-run.com/ Signed-off-by: Josua Mayer --- arch/arm/dts/imx6qdl-sr-som.dtsi | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi index b06577808f..c20bed2721 100644 --- a/arch/arm/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/dts/imx6qdl-sr-som.dtsi @@ -55,7 +55,13 @@ pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-handle = <&phy>; phy-mode = "rgmii-id"; - phy-reset-duration = <2>; + + /* + * The PHY seems to require a long-enough reset duration to avoid + * some rare issues where the PHY gets stuck in an inconsistent and + * non-functional state at boot-up. 10ms proved to be fine . + */ + phy-reset-duration = <10>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; @@ -64,8 +70,15 @@ #size-cells = <0>; phy: ethernet-phy@0 { - reg = <0>; + /* + * The PHY can appear either: + * - AR8035: at address 0 or 4 + * - ADIN1300: at address 1 + * Actual address being detected at runtime. + */ + reg = <0xffffffff>; qca,clk-out-frequency = <125000000>; + adi,phy-output-clock = "125mhz-free-running"; }; }; }; From 741ce3084efffee6b43b88a389caf0f64eaf80e8 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 19 May 2022 12:31:59 +0300 Subject: [PATCH 08/14] mx6cuboxi: fixup dtb ethernet phy nodes before booting an OS SoM revision 1.9 has replaced the ar8035 phy address 0 with an adin1300 at address 1. Because early SoMs had a hardware flaw, the ar8035 can also appear at address 4 - making it a total of 3 phy nodes in the DTB. To avoid confusing Linux with probe errors, fixup the dtb to only enable the phy node that is detected at runtime. Signed-off-by: Josua Mayer --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 78 ++++++++++++++++++++++++++++ configs/mx6cuboxi_defconfig | 1 + 2 files changed, 79 insertions(+) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 6207bf8253..42aa5cb63c 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2022 Josua Mayer + * * Copyright (C) 2015 Freescale Semiconductor, Inc. * * Author: Fabio Estevam @@ -39,6 +41,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -407,6 +411,80 @@ out: return 0; } +static int find_ethernet_phy(void) +{ + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int phy_addr = -ENOENT; + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(ENET_BASE_ADDR, -1); + if (!bus) + return -ENOENT; + + // scan address 0, 1, 4 + phydev = phy_find_by_mask(bus, 0b00010011); + if (!phydev) { + free(bus); + return -ENOENT; + } + pr_debug("%s: detected ethernet phy at address %d\n", __func__, phydev->addr); + phy_addr = phydev->addr; + + free(phydev); +#endif + + return phy_addr; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +/* + * Configure the correct ethernet PHYs nodes in device-tree: + * - AR8035 at addresses 0 or 4: Cubox + * - AR8035 at address 0: HummingBoard, HummingBoard 2 + * - ADIN1300 at address 1: since SoM rev 1.9 + */ +int ft_board_setup(void *fdt, struct bd_info *bd) +{ + int node_phy0, node_phy1, node_phy4; + int ret, phy; + bool enable_phy0 = false, enable_phy1 = false, enable_phy4 = false; + + // detect phy + phy = find_ethernet_phy(); + if (phy == 0 || phy == 4) { + enable_phy0 = true; + switch (board_type()) { + case CUBOXI: + case UNKNOWN: + default: + enable_phy4 = true; + } + } else if (phy == 1) { + enable_phy1 = true; + } else { + pr_err("%s: couldn't detect ethernet phy, not patching dtb!\n", __func__); + return 0; + } + + // update all phy nodes status + node_phy0 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0"); + ret = fdt_setprop_string(fdt, node_phy0, "status", enable_phy0 ? "okay" : "disabled"); + if (ret < 0 && enable_phy0) + pr_err("%s: failed to enable ethernet phy at address 0 in dtb!\n", __func__); + node_phy1 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@1"); + ret = fdt_setprop_string(fdt, node_phy1, "status", enable_phy1 ? "okay" : "disabled"); + if (ret < 0 && enable_phy1) + pr_err("%s: failed to enable ethernet phy at address 1 in dtb!\n", __func__); + node_phy4 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@4"); + ret = fdt_setprop_string(fdt, node_phy4, "status", enable_phy4 ? "okay" : "disabled"); + if (ret < 0 && enable_phy4) + pr_err("%s: failed to enable ethernet phy at address 4 in dtb!\n", __func__); + + return 0; +} +#endif + /* Override the default implementation, DT model is not accurate */ int show_board_info(void) { diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 1e2e332af9..d3ac8eeeba 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" From 815216187e9c93dddb6c65ea2b114c19ca083654 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 19 May 2022 12:32:00 +0300 Subject: [PATCH 09/14] mx6cuboxi: enable driver for adin1300 phy Since SoMs revision 1.9 the ar8035 phy has been replaced by adin1300. Enable the driver so that the new SoMs have functional networking. Signed-off-by: Josua Mayer --- configs/mx6cuboxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index d3ac8eeeba..46634a1727 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -55,6 +55,7 @@ CONFIG_DWC_AHSATA=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_ADIN=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_FEC_MXC=y From a3f2dcf8f44445703a1919a5fa83b4328b244f92 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Wed, 25 May 2022 09:55:02 +0200 Subject: [PATCH 10/14] verdin-imx8mm, verdin-imx8mp: Fix default systemd console output systemd prints its messages on the last console= statement that it finds in the kernel arguments. The current ordering sends the systemd messages to tty1, by default this is the display. Ensure that systemd sends its messages to the default UART, reorder the console= statements accordingly. Signed-off-by: Philippe Schenker Reviewed-by: Stefano Babic Acked-by: Marcel Ziswiler Signed-off-by: Marcel Ziswiler --- include/configs/verdin-imx8mm.h | 4 ++-- include/configs/verdin-imx8mp.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index cd950ad055..558b78115d 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -58,8 +58,8 @@ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=${console},${baudrate} " \ - "console=tty1 consoleblank=0 earlycon\0" \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 470f64d5a7..52fa2be3ab 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -75,7 +75,7 @@ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ From 698c0411cfabcd245027400961d184d0e072a22c Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Fri, 3 Jun 2022 17:15:21 +0200 Subject: [PATCH 11/14] clk: imx8mp: fix root clock names for ecspi Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: uboot-imx Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ac727b7e40..cbed86a684 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -122,15 +122,15 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_p "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; -static const char *imx8mp_ecspi1_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi2_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi3_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; From 65d5931d02d47eacdb26b879a252064bf728ae12 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Fri, 3 Jun 2022 17:15:22 +0200 Subject: [PATCH 12/14] clk: imx8mp: use usb_core_ref for usb_root_clk Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index cbed86a684..ffbc1d1ba9 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -300,7 +300,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); From 66e54716cfd1be2ca3a2a17749b45b7e3980f050 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Thu, 9 Jun 2022 16:32:15 +0530 Subject: [PATCH 13/14] secure boot: enable ARCH_MISC_INIT config. add ARCH_MISC_INIT to initilaize caam jr driver. Signed-off-by: Gaurav Jain Reviewed-by: Fabio Estevam --- board/freescale/common/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 6553bf63bf..b0e6e43f4f 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -3,6 +3,7 @@ config CHAIN_OF_TRUST imply CMD_BLOB imply CMD_HASH if ARM select FSL_CAAM + select ARCH_MISC_INIT select SPL_BOARD_INIT if (ARM && SPL) select SPL_HASH if (ARM && SPL) select SHA_HW_ACCEL From 1a558fafbbdff80cb6a7c8e883addec7f02fe8e5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 Jun 2022 14:35:25 +0200 Subject: [PATCH 14/14] spi: nxp_fspi: Fix clock imbalance The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(), where the IP clock are initially disabled. Drop the second disabling of clock to prevent clock enable/disable imbalance reported by clock core: " clk qspi_root_clk already disabled " Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Peng Fan --- drivers/spi/nxp_fspi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 607c953987..579d6bac9b 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -866,9 +866,6 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) u32 reg; #if CONFIG_IS_ENABLED(CLK) - /* disable and unprepare clock to avoid glitch pass to controller */ - nxp_fspi_clk_disable_unprep(f); - /* the default frequency, we will change it later if necessary. */ ret = clk_set_rate(&f->clk, 20000000); if (ret < 0)