net: zynq_gem: Added 64-bit addressing support
This patch adds 64-bit addressing support for zynq gem. This means it can perform send and receive operations on 64-bit address buffers. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Vipul Kumar
Michal Simek
parent
332d185c37
commit
9a7799f4f4
@ -86,10 +86,17 @@ DECLARE_GLOBAL_DATA_PTR;
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/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
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#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
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#if defined(CONFIG_PHYS_64BIT)
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# define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
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#else
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# define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
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#endif
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#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
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ZYNQ_GEM_DMACR_RXSIZE | \
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ZYNQ_GEM_DMACR_TXSIZE | \
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ZYNQ_GEM_DMACR_RXBUF)
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ZYNQ_GEM_DMACR_RXBUF | \
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ZYNQ_GEM_DMA_BUS_WIDTH)
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#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
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@ -147,12 +154,20 @@ struct zynq_gem_regs {
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u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
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u32 reserved8[15];
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u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
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u32 reserved10[17];
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u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
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u32 reserved11[2];
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u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
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};
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/* BD descriptors */
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struct emac_bd {
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u32 addr; /* Next descriptor pointer */
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u32 status;
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#if defined(CONFIG_PHYS_64BIT)
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u32 addr_hi;
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u32 reserved;
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#endif
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};
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#define RX_BUF 32
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@ -390,13 +405,21 @@ static int zynq_gem_init(struct udevice *dev)
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for (i = 0; i < RX_BUF; i++) {
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priv->rx_bd[i].status = 0xF0000000;
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priv->rx_bd[i].addr =
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((ulong)(priv->rxbuffers) +
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(i * PKTSIZE_ALIGN));
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}
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(lower_32_bits((ulong)(priv->rxbuffers)
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+ (i * PKTSIZE_ALIGN)));
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#if defined(CONFIG_PHYS_64BIT)
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priv->rx_bd[i].addr_hi =
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(upper_32_bits((ulong)(priv->rxbuffers)
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+ (i * PKTSIZE_ALIGN)));
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#endif
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}
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/* WRAP bit to last BD */
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priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
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/* Write RxBDs to IP */
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writel((ulong)priv->rx_bd, ®s->rxqbase);
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writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
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#if defined(CONFIG_PHYS_64BIT)
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writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
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#endif
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/* Setup for DMA Configuration register */
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writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
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@ -406,12 +429,18 @@ static int zynq_gem_init(struct udevice *dev)
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/* Disable the second priority queue */
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dummy_tx_bd->addr = 0;
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#if defined(CONFIG_PHYS_64BIT)
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dummy_tx_bd->addr_hi = 0;
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#endif
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dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
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ZYNQ_GEM_TXBUF_LAST_MASK|
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ZYNQ_GEM_TXBUF_USED_MASK;
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dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
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ZYNQ_GEM_RXBUF_NEW_MASK;
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#if defined(CONFIG_PHYS_64BIT)
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dummy_rx_bd->addr_hi = 0;
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#endif
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dummy_rx_bd->status = 0;
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writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
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@ -485,7 +514,8 @@ static int zynq_gem_init(struct udevice *dev)
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static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
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{
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u32 addr, size;
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dma_addr_t addr;
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u32 size;
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struct zynq_gem_priv *priv = dev_get_priv(dev);
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struct zynq_gem_regs *regs = priv->iobase;
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struct emac_bd *current_bd = &priv->tx_bd[1];
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@ -493,17 +523,26 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
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/* Setup Tx BD */
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memset(priv->tx_bd, 0, sizeof(struct emac_bd));
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priv->tx_bd->addr = (ulong)ptr;
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priv->tx_bd->addr = lower_32_bits((ulong)ptr);
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#if defined(CONFIG_PHYS_64BIT)
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priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
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#endif
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priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
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ZYNQ_GEM_TXBUF_LAST_MASK;
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/* Dummy descriptor to mark it as the last in descriptor chain */
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current_bd->addr = 0x0;
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#if defined(CONFIG_PHYS_64BIT)
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current_bd->addr_hi = 0x0;
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#endif
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current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
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ZYNQ_GEM_TXBUF_LAST_MASK|
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ZYNQ_GEM_TXBUF_USED_MASK;
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/* setup BD */
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writel((ulong)priv->tx_bd, ®s->txqbase);
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writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
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#if defined(CONFIG_PHYS_64BIT)
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writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
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#endif
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addr = (ulong) ptr;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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@ -531,7 +570,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
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static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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int frame_len;
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u32 addr;
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dma_addr_t addr;
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struct zynq_gem_priv *priv = dev_get_priv(dev);
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struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
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@ -550,8 +589,14 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
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return -1;
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}
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#if defined(CONFIG_PHYS_64BIT)
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addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
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| ((dma_addr_t)current_bd->addr_hi << 32));
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#else
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addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
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#endif
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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*packetp = (uchar *)(uintptr_t)addr;
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return frame_len;
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