From cba6edd68b15f8a82f5a28c7db4d0b17866bb5cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Feb 2021 15:32:28 +0100 Subject: [PATCH 01/28] arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 8713b88461..b4e1b60240 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -42,6 +42,10 @@ #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 #define PCIE_CORE_LINK_TRAINING BIT(5) #define PCIE_CORE_ERR_CAPCTL_REG 0x118 @@ -534,6 +538,10 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) /* Set PCIe Device Control and Status 1 PF0 register */ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | + (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE << + PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) | + (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE << + PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE; advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); From b1d58437ef9e4202a0edd23fa5cd241ea2352f47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Feb 2021 15:32:29 +0100 Subject: [PATCH 02/28] arm: mvebu: turris_mox: Enable CONFIG_PCI_PNP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCIe devices do not work in U-Boot without proper initialization and configuration of PCI config space like the PCI_BASE_ADDRESS_0 register. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_mox_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index dde7437f24..329c596cea 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -64,7 +64,6 @@ CONFIG_MVNETA=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y -# CONFIG_PCI_PNP is not set CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y From 3abcc76ef592027f9a745d0ae9dea049809d5715 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Feb 2021 15:32:30 +0100 Subject: [PATCH 03/28] arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit USB devices can be connected to Turris MOX also via MOX F extension which contains VL805 PCIe based USB 3.0 controller. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 329c596cea..27a5179fe5 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -77,6 +77,7 @@ CONFIG_MVEBU_A3700_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y From 579e656f4fef3538c88ee2429ce80e65f4124013 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 5 Feb 2021 15:32:31 +0100 Subject: [PATCH 04/28] arm: mvebu: turris_mox: Enable NVMe support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit NVMe drives can be connected to Turris MOX via MOX B and MOX G extensions. Signed-off-by: Marek Behún Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 27a5179fe5..f938fbb475 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y From 201958af103a4ae8679e0d4d36353b8fb38486ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 8 Feb 2021 23:01:37 +0100 Subject: [PATCH 05/28] pci: pci_mvebu: use dev_seq instead of static variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 235d9bb90c..bea8dcfc91 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -273,7 +273,7 @@ static int mvebu_pcie_probe(struct udevice *dev) struct mvebu_pcie *pcie = dev_get_plat(dev); struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); - static int bus; + int bus = dev_seq(dev); u32 reg; debug("%s: PCIe %d.%d - up, base %08x\n", __func__, @@ -336,8 +336,6 @@ static int mvebu_pcie_probe(struct udevice *dev) writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); - bus++; - return 0; } From 241d763618fda78913e05b929fb1de3e27fa8dde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 8 Feb 2021 23:01:38 +0100 Subject: [PATCH 06/28] pci: pci_mvebu: cosmetic fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index bea8dcfc91..0cd05ead44 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -151,7 +151,6 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, struct mvebu_pcie *pcie = dev_get_plat(bus); int local_bus = PCI_BUS(pcie->dev); int local_dev = PCI_DEV(pcie->dev); - u32 reg; u32 data; debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", @@ -172,8 +171,9 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, } /* write address */ - reg = PCIE_CONF_ADDR(bdf, offset); - writel(reg, pcie->base + PCIE_CONF_ADDR_OFF); + writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF); + + /* read data */ data = readl(pcie->base + PCIE_CONF_DATA_OFF); debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data); *valuep = pci_conv_32_to_size(data, offset, size); @@ -206,7 +206,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, return 0; } + /* write address */ writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF); + + /* write data */ data = pci_conv_size_to_32(0, value, offset, size); writel(data, pcie->base + PCIE_CONF_DATA_OFF); From 26f7a76ef9139544ea053a7d806cddda330a57d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 8 Feb 2021 23:01:39 +0100 Subject: [PATCH 07/28] pci: pci_mvebu: debug rd/wr config as other drivers do MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 0cd05ead44..8e674bbef2 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -175,7 +175,7 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, /* read data */ data = readl(pcie->base + PCIE_CONF_DATA_OFF); - debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data); + debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data); *valuep = pci_conv_32_to_size(data, offset, size); return 0; @@ -192,7 +192,7 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); - debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); + debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); /* Don't access the local host controller via this API */ if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) { From 10eb2cc3442aa9a91c98f2fdda2a5b48de9bbc88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 8 Feb 2021 23:01:40 +0100 Subject: [PATCH 08/28] pci: pci_mvebu: refactor validation of addresses for config access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 59 ++++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 8e674bbef2..54f8e8b9ec 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -79,7 +79,8 @@ struct mvebu_pcie { u32 lane; int devfn; u32 lane_mask; - pci_dev_t dev; + int first_busno; + int local_dev; char name[16]; unsigned int mem_target; unsigned int mem_attr; @@ -144,27 +145,36 @@ static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) return container_of(hose, struct mvebu_pcie, hose); } +static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf) +{ + /* + * There are two devices visible on local bus: + * * on slot configured by function mvebu_pcie_set_local_dev_nr() + * (by default this register is set to 0) there is a + * "Marvell Memory controller", which isn't useful in root complex + * mode, + * * on all other slots the real PCIe card connected to the PCIe slot. + * + * We therefore allow access only to the real PCIe card. + */ + if (PCI_BUS(bdf) == pcie->first_busno && + PCI_DEV(bdf) != !pcie->local_dev) + return 0; + + return 1; +} + static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { struct mvebu_pcie *pcie = dev_get_plat(bus); - int local_bus = PCI_BUS(pcie->dev); - int local_dev = PCI_DEV(pcie->dev); u32 data; - debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", - local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); - /* Don't access the local host controller via this API */ - if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) { - debug("- skipping host controller\n"); - *valuep = pci_get_ff(size); - return 0; - } - - /* If local dev is 0, the first other dev can only be 1 */ - if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) { + if (!mvebu_pcie_valid_addr(pcie, bdf)) { debug("- out of range\n"); *valuep = pci_get_ff(size); return 0; @@ -186,22 +196,13 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct mvebu_pcie *pcie = dev_get_plat(bus); - int local_bus = PCI_BUS(pcie->dev); - int local_dev = PCI_DEV(pcie->dev); u32 data; - debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", - local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); - /* Don't access the local host controller via this API */ - if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) { - debug("- skipping host controller\n"); - return 0; - } - - /* If local dev is 0, the first other dev can only be 1 */ - if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) { + if (!mvebu_pcie_valid_addr(pcie, bdf)) { debug("- out of range\n"); return 0; } @@ -287,9 +288,11 @@ static int mvebu_pcie_probe(struct udevice *dev) readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie), mvebu_pcie_get_local_dev_nr(pcie)); + pcie->first_busno = bus; + pcie->local_dev = 0; + mvebu_pcie_set_local_bus_nr(pcie, bus); - mvebu_pcie_set_local_dev_nr(pcie, 0); - pcie->dev = PCI_BDF(bus, 0, 0); + mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev); pcie->mem.start = (u32)mvebu_pcie_membase; pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1; From 5ddfd3f4412750fa0c035d08d747b38b0aefb3fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 8 Feb 2021 23:01:41 +0100 Subject: [PATCH 09/28] pci: pci_mvebu: set local dev to number 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 54f8e8b9ec..0c1d7cd770 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -289,7 +289,7 @@ static int mvebu_pcie_probe(struct udevice *dev) mvebu_pcie_get_local_dev_nr(pcie)); pcie->first_busno = bus; - pcie->local_dev = 0; + pcie->local_dev = 1; mvebu_pcie_set_local_bus_nr(pcie, bus); mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev); From 2ca5b190c34cda1e2d8ef1733a497839c5341db9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 9 Feb 2021 03:43:03 +0100 Subject: [PATCH 10/28] ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SPI NOR flash node name in main device tree for Turris Omnia is called `spi-nor@0`. Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0 so that U-Boot does not try to probe the same SPI NOR device multiple times. Signed-off-by: Marek Behún Cc: Stefan Roese Reviewed-by: Stefan Roese Reviewed-by: Pali Rohár --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 1b46797583..af0655daaa 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -41,10 +41,7 @@ &spi0 { u-boot,dm-pre-reloc; - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; + spi-nor@0 { u-boot,dm-pre-reloc; }; }; From 69f084f5c613942ff100fe2cc6db82337a87cc49 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:09 +0100 Subject: [PATCH 11/28] ddr: marvell: a38x: fix write leveling suplementary algo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit ce62bef8fac559e27245259882e45f19cdc293ad upstream. - fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct Signed-off-by: Moti Buskila Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 979f3530b7..5fd9a052fa 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num) DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); } - for (pattern = 0; pattern < PATTERN_LAST; pattern++) + for (pattern = 0; pattern < PATTERN_LAST; pattern++) { + if (pattern == PATTERN_TEST) + continue; ddr3_tip_load_pattern_to_mem(dev_num, pattern); + } return MV_OK; } From ab7dda724f4a646ab68f928570496d2bef032793 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:10 +0100 Subject: [PATCH 12/28] ddr: marvell: a38x: import header change from upstream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit a165037ec26f301be75e1fabc263643683e85255 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 34196b1662..c55e3b57e4 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -148,7 +148,8 @@ enum mv_ddr_validation { MV_DDR_VAL_DIS, MV_DDR_VAL_RX, MV_DDR_VAL_TX, - MV_DDR_VAL_RX_TX + MV_DDR_VAL_RX_TX, + MV_DDR_MEMORY_CHECK }; struct mv_ddr_iface { From 5d88723ca4de4c71ad4f18c98241431ff158c479 Mon Sep 17 00:00:00 2001 From: Alex Leibovich Date: Fri, 19 Feb 2021 17:11:11 +0100 Subject: [PATCH 13/28] ddr: marvell: a38x: add ddr32 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich Reviewed-by: Nadav Haklai Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 09840b1e70..f2cd7c0ef3 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); if (tm->cfg_src == MV_DDR_CFG_SPD) { + if (tm->bus_act_mask == BUS_MASK_32BIT) + tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; + enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data); @@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) case MV_DDR_PRI_BUS_WIDTH_16: pri_and_ext_bus_width = BUS_MASK_16BIT; break; - case MV_DDR_PRI_BUS_WIDTH_32: + case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/ pri_and_ext_bus_width = BUS_MASK_32BIT; break; case MV_DDR_PRI_BUS_WIDTH_64: From 1dbd0bd599de8cb105c2dbd8aa2361fe2f353702 Mon Sep 17 00:00:00 2001 From: Alex Leibovich Date: Fri, 19 Feb 2021 17:11:12 +0100 Subject: [PATCH 14/28] ddr: marvell: a38x: add ddr 32bit ECC support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_spd.c | 5 +++++ drivers/ddr/marvell/a38x/mv_ddr_spd.h | 1 + drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index 04dbfe94d6..cb90d30a6a 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -217,6 +217,11 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_ return ret_val; } +void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity) +{ + spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity; +} + unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data) { unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index b4bfef3103..ee35377af5 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -277,6 +277,7 @@ union mv_ddr_spd_data { int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]); enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data); enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data); +void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity); unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index f2cd7c0ef3..0cbe8d3d1e 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void) /* update device width in topology map */ iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); + /* overwrite SPD configuration, with what the user set */ + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) + mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size); + /* update die capacity in topology map */ iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); @@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); if (tm->cfg_src == MV_DDR_CFG_SPD) { - if (tm->bus_act_mask == BUS_MASK_32BIT) + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); From 4d676739b960f383428445ef012e6f465ed52798 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:13 +0100 Subject: [PATCH 15/28] ddr: marvell: a38x: import header change from upstream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header mv_ddr_topology.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h index 4fca47689f..1cb69ad085 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h @@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue { /* phy electrical configuration values */ enum mv_ddr_ohm_evalue { + MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/ MV_DDR_OHM_30 = 30, + MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/ MV_DDR_OHM_48 = 48, MV_DDR_OHM_60 = 60, MV_DDR_OHM_80 = 80, From 6373a92d42b165872c43b5b7424a331260cb6212 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:14 +0100 Subject: [PATCH 16/28] ddr: marvell: a38x: fix 32bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream. Signed-off-by: Moti Buskila Reviewed-by: Alex Leibovich Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 0cbe8d3d1e..3feb65ea46 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -149,7 +149,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) if (tm->cfg_src == MV_DDR_CFG_SPD) { if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) - tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; + tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32; enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data); From 9c4e06af0bfad86ff66df6fbd6be6c4a75ffd303 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:15 +0100 Subject: [PATCH 17/28] ddr: marvell: a38x: fix memory size calculation using 32bit bus width MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit ab9240402a70cc02496683971779e75eff410ab4 upstream. - function mv_ddr_spd_die_capacity_user_get() has a bug, since it insert a user memory enum to it, instead of SPD memory enum (which are different) - fix: remove mv_ddr_spd_die_capacity_user_get() function. - memory size with 64 and 32 bit already calculated correctly at mv_ddr_mem_sz_per_cs_get() function Signed-off-by: Moti Buskila Reviewed-by: Stefan Chulski Reviewed-by: Alex Leibovich Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_spd.c | 5 ----- drivers/ddr/marvell/a38x/mv_ddr_spd.h | 1 - drivers/ddr/marvell/a38x/mv_ddr_topology.c | 4 ---- 3 files changed, 10 deletions(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index cb90d30a6a..04dbfe94d6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -217,11 +217,6 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_ return ret_val; } -void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity) -{ - spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity; -} - unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data) { unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index ee35377af5..b4bfef3103 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -277,7 +277,6 @@ union mv_ddr_spd_data { int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]); enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data); enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data); -void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity); unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 3feb65ea46..31711fdd49 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -74,10 +74,6 @@ int mv_ddr_topology_map_update(void) /* update device width in topology map */ iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); - /* overwrite SPD configuration, with what the user set */ - if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) - mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size); - /* update die capacity in topology map */ iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); From 6e0532401bd4b8f368bd813048b8f3cfdda227c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:16 +0100 Subject: [PATCH 18/28] ddr: marvell: a38x: import header change from upstream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index c55e3b57e4..342c2cf451 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -152,6 +152,11 @@ enum mv_ddr_validation { MV_DDR_MEMORY_CHECK }; +enum mv_ddr_sscg { + SSCG_EN, + SSCG_DIS, +}; + struct mv_ddr_iface { /* base addr of ap ddr interface belongs to */ unsigned int ap_base; @@ -180,6 +185,9 @@ struct mv_ddr_iface { /* ddr interface validation mode */ enum mv_ddr_validation validation; + /* ddr interface validation mode */ + enum mv_ddr_sscg sscg; + /* ddr interface topology map */ struct mv_ddr_topology_map tm; }; From 369e532691e0df4bce5ea8d0963ec3dc061d15a6 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Fri, 19 Feb 2021 17:11:17 +0100 Subject: [PATCH 19/28] ddr: marvell: a38x: allow board specific ODT configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream. The ODT enable heuristic based on active chip-selects is not always correct. Some board might use two chip-selects, but have only one ODT line connected. Allow board specific mv_ddr_topology_map to directly set the ODT configuration register value. Signed-off-by: Baruch Siach Reviewed-by: Moti Buskila Reviewed-by: Nadav Haklai Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_init.c | 5 +++++ drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index a971cc155a..7488770268 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -104,6 +104,7 @@ int ddr3_init(void) static int mv_ddr_training_params_set(u8 dev_num) { struct tune_train_params params; + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); int status; u32 cs_num; int ck_delay; @@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num) if (ck_delay > 0) params.ck_delay = ck_delay; + /* Use platform specific override ODT value */ + if (tm->odt_config) + params.g_odt_config = tm->odt_config; + status = ddr3_tip_tune_training_params(dev_num, ¶ms); if (MV_OK != status) { printf("%s Training Sequence - FAILED\n", ddr_type); diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 342c2cf451..3991fec272 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -125,6 +125,9 @@ struct mv_ddr_topology_map { /* electrical parameters */ unsigned int electrical_data[MV_DDR_EDATA_LAST]; + /* ODT configuration */ + u32 odt_config; + /* Clock enable mask */ u32 clk_enable; From 52dd9b96fcacb42a14caa126b18afe52cf42b556 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:18 +0100 Subject: [PATCH 20/28] ddr: marvell: a38x: add 16Gbit memory devices support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream. Signed-off-by: Moti Buskila Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++ drivers/ddr/marvell/a38x/mv_ddr_topology.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h index 2a68669f36..8765df7cfb 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h @@ -80,6 +80,8 @@ #define ADDR_SIZE_2GB 0x10000000 #define ADDR_SIZE_4GB 0x20000000 #define ADDR_SIZE_8GB 0x40000000 +#define ADDR_SIZE_16GB 0x80000000 + enum hws_edge_compare { EDGE_PF, diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 31711fdd49..c4c3ab72b2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -248,7 +248,8 @@ static unsigned int mem_size[] = { ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB, - ADDR_SIZE_8GB + ADDR_SIZE_8GB, + ADDR_SIZE_16GB /* TODO: add capacity up to 256GB */ }; From 32e7a6baef2bcaacd5e2ca2d788072a487c5e311 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:19 +0100 Subject: [PATCH 21/28] ddr: marvell: a38x: add support for twin-die combined memory device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream. the twin-die combined memory device should be treatened as X8 device and not as X16 one Signed-off-by: Moti Buskila Reviewed-by: Kostya Porotchkin [ - the default value for twin_die_combined is set to NOT_COMBINED for all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún Tested-by: Chris Packham --- board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++ board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 + board/alliedtelesis/x530/x530.c | 1 + board/gdsys/a38x/controlcenterdc.c | 1 + board/kobol/helios4/helios4.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + drivers/ddr/marvell/a38x/ddr_topology_def.h | 12 ++++++++++++ drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++- 9 files changed, 25 insertions(+), 1 deletion(-) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 0353d58a36..1d3cefe703 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -286,6 +286,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; @@ -308,6 +309,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index 163a1b3de9..122c63d11f 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 06307e582c..1edc1cb651 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -94,6 +94,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index d602092d73..7bcfa828d7 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -68,6 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT_ECC, /* subphys mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ { {0} }, /* electrical configuration */ diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index ba57a27218..4f1dc3b431 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -71,6 +71,7 @@ static struct mv_ddr_topology_map ddr_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index adb091ce4f..9c5b687b3e 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -71,6 +71,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT_ECC, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 7b2accf01d..c920cf8d6b 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -142,6 +142,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ { {0} }, /* electrical configuration */ diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 3991fec272..461f091472 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -14,6 +14,11 @@ #define MV_DDR_MAX_BUS_NUM 9 #define MV_DDR_MAX_IFACE_NUM 1 +enum mv_ddr_twin_die { + COMBINED, + NOT_COMBINED, +}; + struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -47,6 +52,9 @@ struct if_params { /* The DDR frequency for each interfaces */ enum mv_ddr_freq memory_freq; + /* ddr twin-die */ + enum mv_ddr_twin_die twin_die_combined; + /* * delay CAS Write Latency * - 0 for using default value (jedec suggested) @@ -113,6 +121,9 @@ struct mv_ddr_topology_map { /* source of ddr configuration data */ enum mv_ddr_cfg_src cfg_src; + /* ddr twin-die */ + enum mv_ddr_twin_die twin_die_combined; + /* raw spd data */ union mv_ddr_spd_data spd_data; @@ -193,6 +204,7 @@ struct mv_ddr_iface { /* ddr interface topology map */ struct mv_ddr_topology_map tm; + }; struct mv_ddr_iface *mv_ddr_iface_get(void); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index c4c3ab72b2..2db6283c23 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void) speed_bin_index = iface_params->speed_bin_index; freq = iface_params->memory_freq; + if (tm->twin_die_combined == COMBINED) { + iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT; + iface_params->memory_size -= 1; + } + if (iface_params->cas_l == 0) iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq); @@ -281,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void) mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] * (unsigned long long)sphys / (unsigned long long)sphys_per_dunit; - return mem_sz_per_cs; } From 44aeb28c9b4475526d2b87172b4ed1867072b030 Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:20 +0100 Subject: [PATCH 22/28] ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream. WL phase correcion stage is failing while using bus_width of 16bit, not to be fix this stage is un-necessary when working with bus_width of 16 bit. Signed-off-by: Moti Buskila Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index b2f11a8399..6aa7b6069e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) pattern = pattern_table_get_isi_word16(index); break; default: + if (((int)type == 29) || ((int)type == 30)) + break; + printf("error: %s: unsupported pattern type [%d] found\n", __func__, (int)type); pattern = 0; From b85c6fb065f2eea0d08402bda9394c4b3db6f753 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:21 +0100 Subject: [PATCH 23/28] ddr: marvell: a38x: import header change from upstream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 461f091472..2cca5676a0 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -52,9 +52,6 @@ struct if_params { /* The DDR frequency for each interfaces */ enum mv_ddr_freq memory_freq; - /* ddr twin-die */ - enum mv_ddr_twin_die twin_die_combined; - /* * delay CAS Write Latency * - 0 for using default value (jedec suggested) From 2ab7bbf71ef63ffb621312730232d6d1b9b9f92f Mon Sep 17 00:00:00 2001 From: Moti Buskila Date: Fri, 19 Feb 2021 17:11:22 +0100 Subject: [PATCH 24/28] ddr: marvell: a38x: fix memory cs size function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream. The funtion returnd cs size in byte instead of MB, that cause calculation error since the caller was expected to get u32 and when he got above 4G it refers it as 0. The fix was to get the cs memory size from function as in MB and then multiply it by 1MB. Signed-off-by: Moti Buskila Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 +++++++-- drivers/ddr/marvell/a38x/xor.c | 6 +++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 72f0dfbbbb..0d1df189e8 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_common.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" @@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size) return MV_BAD_VALUE; } - *cs_size = cs_mem_size << 20; /* write cs size in bytes */ + *cs_size = cs_mem_size; return MV_OK; } @@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) { u32 reg, cs; uint64_t mem_total_size = 0; + uint64_t cs_mem_size_mb = 0; uint64_t cs_mem_size = 0; uint64_t mem_total_size_c, cs_mem_size_c; + #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE u32 physical_mem_size; u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE; @@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) for (cs = 0; cs < MAX_CS_NUM; cs++) { if (cs_ena & (1 << cs)) { /* get CS size */ - if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) + if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK) return MV_FAIL; + cs_mem_size = cs_mem_size_mb * _1M; #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE /* @@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) */ mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff; cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff; + /* if the sum less than 2 G - calculate the value */ if (mem_total_size_c + cs_mem_size_c < 0x10000) mem_total_size += cs_mem_size; diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 5fb9e216d3..98fb39eaf0 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void) { u32 cs_c, max_cs; u32 cs_ena = 0; - uint64_t total_mem_size, cs_mem_size = 0; + uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0; printf("DDR Training Sequence - Start scrubbing\n"); max_cs = mv_ddr_cs_num_get(); @@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void) #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* all chip-selects are of same size */ - ddr3_calc_mem_cs_size(0, &cs_mem_size); + ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); #endif - + cs_mem_size = cs_mem_size_mb * _1M; mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef); From a267943fd95bc5b077e02b3d266ee538a1973946 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:23 +0100 Subject: [PATCH 25/28] ddr: marvell: a38x: import code change from upstream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes code in ddr3_training.c. Import this change to remain consistent with upstream. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_training.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 34cc170910..0358f6287a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = { {0x15a4, 0x0, MASK_ALL_BITS}, {0x15a8, 0x0, MASK_ALL_BITS}, {0x15ac, 0x0, MASK_ALL_BITS}, + {0x1600, 0x0, MASK_ALL_BITS}, {0x1604, 0x0, MASK_ALL_BITS}, {0x1608, 0x0, MASK_ALL_BITS}, {0x160c, 0x0, MASK_ALL_BITS}, @@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, val = ((cl_mask_table[cl_value] & 0x1) << 2) | ((cl_mask_table[cl_value] & 0xe) << 3); + cs_mask[0] = 0xc; + CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0, val, (0x7 << 4) | (0x1 << 2))); From 420e106ef17b78d3099d488b0c87cd821b93ff3a Mon Sep 17 00:00:00 2001 From: heaterC Date: Fri, 19 Feb 2021 17:11:24 +0100 Subject: [PATCH 26/28] ddr: marvell: a38x: enum mv_ddr_twin_die: change order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream. @pali suggested this change In commit 6285efb ("mv_ddr: add support for twin-die combined memory device") was added support for twin-die combined memory device and default value for explicitly uninitialized structure members is zero, s also twin_die_combined is initialized to zero. Which means COMBINED value. As prior this commit there was no support for twin-die combined memory device, default value for twin_die_combined should be NOT_COMBINED. This change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED has value zero. Signed-off-by: heaterC Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 2cca5676a0..7f2317edfa 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -15,8 +15,8 @@ #define MV_DDR_MAX_IFACE_NUM 1 enum mv_ddr_twin_die { - COMBINED, NOT_COMBINED, + COMBINED, }; struct bus_params { From b1b17f89674bb3e4366eece4f037fb32544d9757 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:25 +0100 Subject: [PATCH 27/28] ddr: marvell: a38x: bump version to 14.0.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the version in the mv-ddr-devel branch of upstream repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. There is a new version numbering system, where after 18.12.0 came 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_build_message.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c index cc6234fd40..a2bb8a96a6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c @@ -1,3 +1,3 @@ // SPDX-License-Identifier: GPL-2.0 const char mv_ddr_build_message[] = ""; -const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2"; +const char mv_ddr_version_string[] = "mv_ddr: 14.0.0"; From 2f0c18b1584129d8386f5a18390996f6bea78065 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 19 Feb 2021 17:11:26 +0100 Subject: [PATCH 28/28] ddr: marvell: a38x: fix comment in conditional macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code was processed with unifdef utility to omit portions not relevant to A38x and DDR3. This removes usage of many macros, including A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove the macros from #else comment. Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/ddr3_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 0358f6287a..2b3af23202 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -219,7 +219,7 @@ static int ddr3_tip_pad_inv(void) DDR_PHY_CONTROL, PHY_CTRL_PHY_REG, data, data); -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */ +#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ #pragma message "unknown platform to configure ddr clock swap" #endif }