arm: dts: imx7: sync with Linux
Sync with Linux commit 308ac756("Merge tag 'gpio-v4.11-3'").
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
9f0a3ac1b2
commit
993274f485
arch/arm/dts
include/dt-bindings/clock
@ -6,7 +6,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx7.dtsi"
|
||||
#include "imx7d.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7S/D";
|
||||
@ -83,15 +83,15 @@
|
||||
&iomuxc_lpsr {
|
||||
pinctrl_i2c1: i2c1-grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
|
||||
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
|
||||
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
|
||||
MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
|
||||
MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
|
||||
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
|
||||
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,194 +0,0 @@
|
||||
/*
|
||||
* Copyright 2016 Toradex AG
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ or X11
|
||||
*/
|
||||
#include "imx7d-pinfunc.h"
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
gpio6 = &gpio7;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
serial6 = &uart7;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
aips1: aips-bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
ranges;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@30250000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30250000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@30260000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30260000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx7d-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
aips3: aips-bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
ranges;
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a20000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a30000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a50000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@30a70000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a70000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@30a80000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a80000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@30a90000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a90000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,7 +1,10 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX7D_PINFUNC_H
|
||||
@ -12,57 +15,61 @@
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
|
||||
#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
|
||||
#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
|
||||
#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
|
||||
#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
|
||||
#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
|
||||
#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
|
||||
#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
|
||||
#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
|
||||
#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
|
||||
#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
|
||||
#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
|
||||
#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
|
||||
|
||||
140
arch/arm/dts/imx7d.dtsi
Normal file
140
arch/arm/dts/imx7d.dtsi
Normal file
@ -0,0 +1,140 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 Toradex AG
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "imx7s.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu0: cpu@0 {
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
996000 1075000
|
||||
792000 975000
|
||||
>;
|
||||
clock-frequency = <996000000>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clock-frequency = <996000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
etm@3007d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0x3007d000 0x1000>;
|
||||
|
||||
/*
|
||||
* System will hang if added nosmp in kernel command line
|
||||
* without arm,primecell-periphid because amba bus try to
|
||||
* read id and core1 power off at this time.
|
||||
*/
|
||||
arm,primecell-periphid = <0xbb956>;
|
||||
cpu = <&cpu1>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm1_out_port: endpoint {
|
||||
remote-endpoint = <&ca_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&aips3 {
|
||||
usbotg2: usb@30b20000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b20000 0x200>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@30b20200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b20200 0x200>;
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_PHY2_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
fec2: ethernet@30bf0000 {
|
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30bf0000 0x10000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
|
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
|
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&ca_funnel_ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
ca_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm1_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
999
arch/arm/dts/imx7s.dtsi
Normal file
999
arch/arm/dts/imx7s.dtsi
Normal file
@ -0,0 +1,999 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 Toradex AG
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx7d-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "imx7d-pinfunc.h"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
* Also for U-Boot there must be a pre-existing /memory node.
|
||||
*/
|
||||
chosen {};
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
gpio6 = &gpio7;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
serial6 = &uart7;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
spi3 = &ecspi4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clock-frequency = <792000000>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX7D_CLK_ARM>;
|
||||
};
|
||||
};
|
||||
|
||||
ckil: clock-cki {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ckil";
|
||||
};
|
||||
|
||||
osc: clock-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
funnel@30041000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0x30041000 0x1000>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ca_funnel_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* funnel input ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
ca_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* funnel output port */
|
||||
port@2 {
|
||||
reg = <0>;
|
||||
ca_funnel_out_port0: endpoint {
|
||||
remote-endpoint = <&hugo_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* the other input ports are not connect to anything */
|
||||
};
|
||||
};
|
||||
|
||||
etm@3007c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0x3007c000 0x1000>;
|
||||
cpu = <&cpu0>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm0_out_port: endpoint {
|
||||
remote-endpoint = <&ca_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@30083000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0x30083000 0x1000>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* funnel input ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hugo_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&ca_funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hugo_funnel_in_port1: endpoint {
|
||||
slave-mode; /* M4 input */
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0>;
|
||||
hugo_funnel_out_port0: endpoint {
|
||||
remote-endpoint = <&etf_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* the other input ports are not connect to anything */
|
||||
};
|
||||
};
|
||||
|
||||
etf@30084000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0x30084000 0x1000>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
etf_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&hugo_funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
etf_out_port: endpoint {
|
||||
remote-endpoint = <&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@30086000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0x30086000 0x1000>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etr_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@30087000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0x30087000 0x1000>;
|
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator {
|
||||
/*
|
||||
* non-configurable replicators don't show up on the
|
||||
* AMBA bus. As such no need to add "arm,primecell"
|
||||
*/
|
||||
compatible = "arm,coresight-replicator";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etr_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* replicator input port */
|
||||
port@2 {
|
||||
reg = <0>;
|
||||
replicator_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@31001000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x31001000 0x1000>,
|
||||
<0x31002000 0x2000>,
|
||||
<0x31004000 0x2000>,
|
||||
<0x31006000 0x2000>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
ranges;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 13 32>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 45 29>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 74 24>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 98 18>;
|
||||
};
|
||||
|
||||
gpio6: gpio@30250000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30250000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 116 23>;
|
||||
};
|
||||
|
||||
gpio7: gpio@30260000 {
|
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30260000 0x10000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 139 16>;
|
||||
};
|
||||
|
||||
wdog1: wdog@30280000 {
|
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
|
||||
};
|
||||
|
||||
wdog2: wdog@30290000 {
|
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30290000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: wdog@302a0000 {
|
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog4: wdog@302b0000 {
|
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
};
|
||||
|
||||
gpt1: gpt@302d0000 {
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_GPT1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt2: gpt@302e0000 {
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302e0000 0x10000>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_GPT2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt3: gpt@302f0000 {
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302f0000 0x10000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_GPT3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt4: gpt@30300000 {
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x30300000 0x10000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_GPT4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx7d-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx7d-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clks IMX7D_OCOTP_CLK>;
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x30360000 0x10000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
reg_1p0d: regulator-vdd1p0d {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd1p0d";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
anatop-reg-offset = <0x210>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <8>;
|
||||
anatop-min-voltage = <800000>;
|
||||
anatop-max-voltage = <1200000>;
|
||||
};
|
||||
};
|
||||
|
||||
snvs: snvs@30370000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
||||
reg = <0x30370000 0x10000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
snvs_poweroff: snvs-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x38>;
|
||||
mask = <0x60>;
|
||||
};
|
||||
|
||||
snvs_pwrkey: snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
clks: ccm@30380000 {
|
||||
compatible = "fsl,imx7d-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>;
|
||||
clock-names = "ckil", "osc";
|
||||
};
|
||||
|
||||
src: src@30390000 {
|
||||
compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
|
||||
reg = <0x30390000 0x10000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: aips-bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
ranges;
|
||||
|
||||
adc1: adc@30610000 {
|
||||
compatible = "fsl,imx7d-adc";
|
||||
reg = <0x30610000 0x10000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
|
||||
clock-names = "adc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc2: adc@30620000 {
|
||||
compatible = "fsl,imx7d-adc";
|
||||
reg = <0x30620000 0x10000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
|
||||
clock-names = "adc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi4: ecspi@30630000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30630000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@30660000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30660000 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30670000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@30680000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30680000 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@30690000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30690000 0x10000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdif: lcdif@30730000 {
|
||||
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x30730000 0x10000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
|
||||
<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
|
||||
clock-names = "pix", "axi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: aips-bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
ranges;
|
||||
|
||||
ecspi1: ecspi@30820000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: ecspi@30830000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: ecspi@30840000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART1_ROOT_CLK>,
|
||||
<&clks IMX7D_UART1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART2_ROOT_CLK>,
|
||||
<&clks IMX7D_UART2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART3_ROOT_CLK>,
|
||||
<&clks IMX7D_UART3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai1: sai@308a0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI1_IPG_CLK>,
|
||||
<&clks IMX7D_SAI1_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@308b0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI2_IPG_CLK>,
|
||||
<&clks IMX7D_SAI2_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai3: sai@308c0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI3_IPG_CLK>,
|
||||
<&clks IMX7D_SAI3_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan1: can@30a00000 {
|
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
||||
reg = <0x30a00000 0x10000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CAN1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan2: can@30a10000 {
|
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
||||
reg = <0x30a10000 0x10000>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CAN2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART4_ROOT_CLK>,
|
||||
<&clks IMX7D_UART4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@30a70000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a70000 0x10000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART5_ROOT_CLK>,
|
||||
<&clks IMX7D_UART5_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@30a80000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a80000 0x10000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART6_ROOT_CLK>,
|
||||
<&clks IMX7D_UART6_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@30a90000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a90000 0x10000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART7_ROOT_CLK>,
|
||||
<&clks IMX7D_UART7_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg1: usb@30b10000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b10000 0x200>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb@30b30000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b30000 0x200>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop3>;
|
||||
fsl,usbmisc = <&usbmisc3 0>;
|
||||
phy_type = "hsic";
|
||||
dr_mode = "host";
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@30b10200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b10200 0x200>;
|
||||
};
|
||||
|
||||
usbmisc3: usbmisc@30b30200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b30200 0x200>;
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_PHY1_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop3: usbphynop3 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@30b40000 {
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_USDHC1_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: usdhc@30b50000 {
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_USDHC2_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: usdhc@30b60000 {
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma: sdma@30bd0000 {
|
||||
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SDMA_CORE_CLK>,
|
||||
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
|
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
|
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
454
include/dt-bindings/clock/imx7d-clock.h
Normal file
454
include/dt-bindings/clock/imx7d-clock.h
Normal file
@ -0,0 +1,454 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX7D_H
|
||||
|
||||
#define IMX7D_OSC_24M_CLK 0
|
||||
#define IMX7D_PLL_ARM_MAIN 1
|
||||
#define IMX7D_PLL_ARM_MAIN_CLK 2
|
||||
#define IMX7D_PLL_ARM_MAIN_SRC 3
|
||||
#define IMX7D_PLL_ARM_MAIN_BYPASS 4
|
||||
#define IMX7D_PLL_SYS_MAIN 5
|
||||
#define IMX7D_PLL_SYS_MAIN_CLK 6
|
||||
#define IMX7D_PLL_SYS_MAIN_SRC 7
|
||||
#define IMX7D_PLL_SYS_MAIN_BYPASS 8
|
||||
#define IMX7D_PLL_SYS_MAIN_480M 9
|
||||
#define IMX7D_PLL_SYS_MAIN_240M 10
|
||||
#define IMX7D_PLL_SYS_MAIN_120M 11
|
||||
#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
|
||||
#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
|
||||
#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
|
||||
#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
|
||||
#define IMX7D_PLL_SYS_PFD0_196M 16
|
||||
#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
|
||||
#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
|
||||
#define IMX7D_PLL_SYS_PFD1_166M 19
|
||||
#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
|
||||
#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
|
||||
#define IMX7D_PLL_SYS_PFD2_135M 22
|
||||
#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
|
||||
#define IMX7D_PLL_SYS_PFD3_CLK 24
|
||||
#define IMX7D_PLL_SYS_PFD4_CLK 25
|
||||
#define IMX7D_PLL_SYS_PFD5_CLK 26
|
||||
#define IMX7D_PLL_SYS_PFD6_CLK 27
|
||||
#define IMX7D_PLL_SYS_PFD7_CLK 28
|
||||
#define IMX7D_PLL_ENET_MAIN 29
|
||||
#define IMX7D_PLL_ENET_MAIN_CLK 30
|
||||
#define IMX7D_PLL_ENET_MAIN_SRC 31
|
||||
#define IMX7D_PLL_ENET_MAIN_BYPASS 32
|
||||
#define IMX7D_PLL_ENET_MAIN_500M 33
|
||||
#define IMX7D_PLL_ENET_MAIN_250M 34
|
||||
#define IMX7D_PLL_ENET_MAIN_125M 35
|
||||
#define IMX7D_PLL_ENET_MAIN_100M 36
|
||||
#define IMX7D_PLL_ENET_MAIN_50M 37
|
||||
#define IMX7D_PLL_ENET_MAIN_40M 38
|
||||
#define IMX7D_PLL_ENET_MAIN_25M 39
|
||||
#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
|
||||
#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
|
||||
#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
|
||||
#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
|
||||
#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
|
||||
#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
|
||||
#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
|
||||
#define IMX7D_PLL_DRAM_MAIN 47
|
||||
#define IMX7D_PLL_DRAM_MAIN_CLK 48
|
||||
#define IMX7D_PLL_DRAM_MAIN_SRC 49
|
||||
#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
|
||||
#define IMX7D_PLL_DRAM_MAIN_533M 51
|
||||
#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
|
||||
#define IMX7D_PLL_AUDIO_MAIN 53
|
||||
#define IMX7D_PLL_AUDIO_MAIN_CLK 54
|
||||
#define IMX7D_PLL_AUDIO_MAIN_SRC 55
|
||||
#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
|
||||
#define IMX7D_PLL_VIDEO_MAIN_CLK 57
|
||||
#define IMX7D_PLL_VIDEO_MAIN 58
|
||||
#define IMX7D_PLL_VIDEO_MAIN_SRC 59
|
||||
#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
|
||||
#define IMX7D_USB_MAIN_480M_CLK 61
|
||||
#define IMX7D_ARM_A7_ROOT_CLK 62
|
||||
#define IMX7D_ARM_A7_ROOT_SRC 63
|
||||
#define IMX7D_ARM_A7_ROOT_CG 64
|
||||
#define IMX7D_ARM_A7_ROOT_DIV 65
|
||||
#define IMX7D_ARM_M4_ROOT_CLK 66
|
||||
#define IMX7D_ARM_M4_ROOT_SRC 67
|
||||
#define IMX7D_ARM_M4_ROOT_CG 68
|
||||
#define IMX7D_ARM_M4_ROOT_DIV 69
|
||||
#define IMX7D_ARM_M0_ROOT_CLK 70
|
||||
#define IMX7D_ARM_M0_ROOT_SRC 71
|
||||
#define IMX7D_ARM_M0_ROOT_CG 72
|
||||
#define IMX7D_ARM_M0_ROOT_DIV 73
|
||||
#define IMX7D_MAIN_AXI_ROOT_CLK 74
|
||||
#define IMX7D_MAIN_AXI_ROOT_SRC 75
|
||||
#define IMX7D_MAIN_AXI_ROOT_CG 76
|
||||
#define IMX7D_MAIN_AXI_ROOT_DIV 77
|
||||
#define IMX7D_DISP_AXI_ROOT_CLK 78
|
||||
#define IMX7D_DISP_AXI_ROOT_SRC 79
|
||||
#define IMX7D_DISP_AXI_ROOT_CG 80
|
||||
#define IMX7D_DISP_AXI_ROOT_DIV 81
|
||||
#define IMX7D_ENET_AXI_ROOT_CLK 82
|
||||
#define IMX7D_ENET_AXI_ROOT_SRC 83
|
||||
#define IMX7D_ENET_AXI_ROOT_CG 84
|
||||
#define IMX7D_ENET_AXI_ROOT_DIV 85
|
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
|
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
|
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
|
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
|
||||
#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
|
||||
#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
|
||||
#define IMX7D_AHB_CHANNEL_ROOT_CG 92
|
||||
#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
|
||||
#define IMX7D_DRAM_PHYM_ROOT_CLK 94
|
||||
#define IMX7D_DRAM_PHYM_ROOT_SRC 95
|
||||
#define IMX7D_DRAM_PHYM_ROOT_CG 96
|
||||
#define IMX7D_DRAM_PHYM_ROOT_DIV 97
|
||||
#define IMX7D_DRAM_ROOT_CLK 98
|
||||
#define IMX7D_DRAM_ROOT_SRC 99
|
||||
#define IMX7D_DRAM_ROOT_CG 100
|
||||
#define IMX7D_DRAM_ROOT_DIV 101
|
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
|
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
|
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
|
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
|
||||
#define IMX7D_DRAM_ALT_ROOT_CLK 106
|
||||
#define IMX7D_DRAM_ALT_ROOT_SRC 107
|
||||
#define IMX7D_DRAM_ALT_ROOT_CG 108
|
||||
#define IMX7D_DRAM_ALT_ROOT_DIV 109
|
||||
#define IMX7D_USB_HSIC_ROOT_CLK 110
|
||||
#define IMX7D_USB_HSIC_ROOT_SRC 111
|
||||
#define IMX7D_USB_HSIC_ROOT_CG 112
|
||||
#define IMX7D_USB_HSIC_ROOT_DIV 113
|
||||
#define IMX7D_PCIE_CTRL_ROOT_CLK 114
|
||||
#define IMX7D_PCIE_CTRL_ROOT_SRC 115
|
||||
#define IMX7D_PCIE_CTRL_ROOT_CG 116
|
||||
#define IMX7D_PCIE_CTRL_ROOT_DIV 117
|
||||
#define IMX7D_PCIE_PHY_ROOT_CLK 118
|
||||
#define IMX7D_PCIE_PHY_ROOT_SRC 119
|
||||
#define IMX7D_PCIE_PHY_ROOT_CG 120
|
||||
#define IMX7D_PCIE_PHY_ROOT_DIV 121
|
||||
#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
|
||||
#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
|
||||
#define IMX7D_EPDC_PIXEL_ROOT_CG 124
|
||||
#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
|
||||
#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
|
||||
#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
|
||||
#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
|
||||
#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
|
||||
#define IMX7D_MIPI_DSI_ROOT_CLK 130
|
||||
#define IMX7D_MIPI_DSI_ROOT_SRC 131
|
||||
#define IMX7D_MIPI_DSI_ROOT_CG 132
|
||||
#define IMX7D_MIPI_DSI_ROOT_DIV 133
|
||||
#define IMX7D_MIPI_CSI_ROOT_CLK 134
|
||||
#define IMX7D_MIPI_CSI_ROOT_SRC 135
|
||||
#define IMX7D_MIPI_CSI_ROOT_CG 136
|
||||
#define IMX7D_MIPI_CSI_ROOT_DIV 137
|
||||
#define IMX7D_MIPI_DPHY_ROOT_CLK 138
|
||||
#define IMX7D_MIPI_DPHY_ROOT_SRC 139
|
||||
#define IMX7D_MIPI_DPHY_ROOT_CG 140
|
||||
#define IMX7D_MIPI_DPHY_ROOT_DIV 141
|
||||
#define IMX7D_SAI1_ROOT_CLK 142
|
||||
#define IMX7D_SAI1_ROOT_SRC 143
|
||||
#define IMX7D_SAI1_ROOT_CG 144
|
||||
#define IMX7D_SAI1_ROOT_DIV 145
|
||||
#define IMX7D_SAI2_ROOT_CLK 146
|
||||
#define IMX7D_SAI2_ROOT_SRC 147
|
||||
#define IMX7D_SAI2_ROOT_CG 148
|
||||
#define IMX7D_SAI2_ROOT_DIV 149
|
||||
#define IMX7D_SAI3_ROOT_CLK 150
|
||||
#define IMX7D_SAI3_ROOT_SRC 151
|
||||
#define IMX7D_SAI3_ROOT_CG 152
|
||||
#define IMX7D_SAI3_ROOT_DIV 153
|
||||
#define IMX7D_SPDIF_ROOT_CLK 154
|
||||
#define IMX7D_SPDIF_ROOT_SRC 155
|
||||
#define IMX7D_SPDIF_ROOT_CG 156
|
||||
#define IMX7D_SPDIF_ROOT_DIV 157
|
||||
#define IMX7D_ENET1_REF_ROOT_CLK 158
|
||||
#define IMX7D_ENET1_REF_ROOT_SRC 159
|
||||
#define IMX7D_ENET1_REF_ROOT_CG 160
|
||||
#define IMX7D_ENET1_REF_ROOT_DIV 161
|
||||
#define IMX7D_ENET1_TIME_ROOT_CLK 162
|
||||
#define IMX7D_ENET1_TIME_ROOT_SRC 163
|
||||
#define IMX7D_ENET1_TIME_ROOT_CG 164
|
||||
#define IMX7D_ENET1_TIME_ROOT_DIV 165
|
||||
#define IMX7D_ENET2_REF_ROOT_CLK 166
|
||||
#define IMX7D_ENET2_REF_ROOT_SRC 167
|
||||
#define IMX7D_ENET2_REF_ROOT_CG 168
|
||||
#define IMX7D_ENET2_REF_ROOT_DIV 169
|
||||
#define IMX7D_ENET2_TIME_ROOT_CLK 170
|
||||
#define IMX7D_ENET2_TIME_ROOT_SRC 171
|
||||
#define IMX7D_ENET2_TIME_ROOT_CG 172
|
||||
#define IMX7D_ENET2_TIME_ROOT_DIV 173
|
||||
#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
|
||||
#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
|
||||
#define IMX7D_ENET_PHY_REF_ROOT_CG 176
|
||||
#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
|
||||
#define IMX7D_EIM_ROOT_CLK 178
|
||||
#define IMX7D_EIM_ROOT_SRC 179
|
||||
#define IMX7D_EIM_ROOT_CG 180
|
||||
#define IMX7D_EIM_ROOT_DIV 181
|
||||
#define IMX7D_NAND_ROOT_CLK 182
|
||||
#define IMX7D_NAND_ROOT_SRC 183
|
||||
#define IMX7D_NAND_ROOT_CG 184
|
||||
#define IMX7D_NAND_ROOT_DIV 185
|
||||
#define IMX7D_QSPI_ROOT_CLK 186
|
||||
#define IMX7D_QSPI_ROOT_SRC 187
|
||||
#define IMX7D_QSPI_ROOT_CG 188
|
||||
#define IMX7D_QSPI_ROOT_DIV 189
|
||||
#define IMX7D_USDHC1_ROOT_CLK 190
|
||||
#define IMX7D_USDHC1_ROOT_SRC 191
|
||||
#define IMX7D_USDHC1_ROOT_CG 192
|
||||
#define IMX7D_USDHC1_ROOT_DIV 193
|
||||
#define IMX7D_USDHC2_ROOT_CLK 194
|
||||
#define IMX7D_USDHC2_ROOT_SRC 195
|
||||
#define IMX7D_USDHC2_ROOT_CG 196
|
||||
#define IMX7D_USDHC2_ROOT_DIV 197
|
||||
#define IMX7D_USDHC3_ROOT_CLK 198
|
||||
#define IMX7D_USDHC3_ROOT_SRC 199
|
||||
#define IMX7D_USDHC3_ROOT_CG 200
|
||||
#define IMX7D_USDHC3_ROOT_DIV 201
|
||||
#define IMX7D_CAN1_ROOT_CLK 202
|
||||
#define IMX7D_CAN1_ROOT_SRC 203
|
||||
#define IMX7D_CAN1_ROOT_CG 204
|
||||
#define IMX7D_CAN1_ROOT_DIV 205
|
||||
#define IMX7D_CAN2_ROOT_CLK 206
|
||||
#define IMX7D_CAN2_ROOT_SRC 207
|
||||
#define IMX7D_CAN2_ROOT_CG 208
|
||||
#define IMX7D_CAN2_ROOT_DIV 209
|
||||
#define IMX7D_I2C1_ROOT_CLK 210
|
||||
#define IMX7D_I2C1_ROOT_SRC 211
|
||||
#define IMX7D_I2C1_ROOT_CG 212
|
||||
#define IMX7D_I2C1_ROOT_DIV 213
|
||||
#define IMX7D_I2C2_ROOT_CLK 214
|
||||
#define IMX7D_I2C2_ROOT_SRC 215
|
||||
#define IMX7D_I2C2_ROOT_CG 216
|
||||
#define IMX7D_I2C2_ROOT_DIV 217
|
||||
#define IMX7D_I2C3_ROOT_CLK 218
|
||||
#define IMX7D_I2C3_ROOT_SRC 219
|
||||
#define IMX7D_I2C3_ROOT_CG 220
|
||||
#define IMX7D_I2C3_ROOT_DIV 221
|
||||
#define IMX7D_I2C4_ROOT_CLK 222
|
||||
#define IMX7D_I2C4_ROOT_SRC 223
|
||||
#define IMX7D_I2C4_ROOT_CG 224
|
||||
#define IMX7D_I2C4_ROOT_DIV 225
|
||||
#define IMX7D_UART1_ROOT_CLK 226
|
||||
#define IMX7D_UART1_ROOT_SRC 227
|
||||
#define IMX7D_UART1_ROOT_CG 228
|
||||
#define IMX7D_UART1_ROOT_DIV 229
|
||||
#define IMX7D_UART2_ROOT_CLK 230
|
||||
#define IMX7D_UART2_ROOT_SRC 231
|
||||
#define IMX7D_UART2_ROOT_CG 232
|
||||
#define IMX7D_UART2_ROOT_DIV 233
|
||||
#define IMX7D_UART3_ROOT_CLK 234
|
||||
#define IMX7D_UART3_ROOT_SRC 235
|
||||
#define IMX7D_UART3_ROOT_CG 236
|
||||
#define IMX7D_UART3_ROOT_DIV 237
|
||||
#define IMX7D_UART4_ROOT_CLK 238
|
||||
#define IMX7D_UART4_ROOT_SRC 239
|
||||
#define IMX7D_UART4_ROOT_CG 240
|
||||
#define IMX7D_UART4_ROOT_DIV 241
|
||||
#define IMX7D_UART5_ROOT_CLK 242
|
||||
#define IMX7D_UART5_ROOT_SRC 243
|
||||
#define IMX7D_UART5_ROOT_CG 244
|
||||
#define IMX7D_UART5_ROOT_DIV 245
|
||||
#define IMX7D_UART6_ROOT_CLK 246
|
||||
#define IMX7D_UART6_ROOT_SRC 247
|
||||
#define IMX7D_UART6_ROOT_CG 248
|
||||
#define IMX7D_UART6_ROOT_DIV 249
|
||||
#define IMX7D_UART7_ROOT_CLK 250
|
||||
#define IMX7D_UART7_ROOT_SRC 251
|
||||
#define IMX7D_UART7_ROOT_CG 252
|
||||
#define IMX7D_UART7_ROOT_DIV 253
|
||||
#define IMX7D_ECSPI1_ROOT_CLK 254
|
||||
#define IMX7D_ECSPI1_ROOT_SRC 255
|
||||
#define IMX7D_ECSPI1_ROOT_CG 256
|
||||
#define IMX7D_ECSPI1_ROOT_DIV 257
|
||||
#define IMX7D_ECSPI2_ROOT_CLK 258
|
||||
#define IMX7D_ECSPI2_ROOT_SRC 259
|
||||
#define IMX7D_ECSPI2_ROOT_CG 260
|
||||
#define IMX7D_ECSPI2_ROOT_DIV 261
|
||||
#define IMX7D_ECSPI3_ROOT_CLK 262
|
||||
#define IMX7D_ECSPI3_ROOT_SRC 263
|
||||
#define IMX7D_ECSPI3_ROOT_CG 264
|
||||
#define IMX7D_ECSPI3_ROOT_DIV 265
|
||||
#define IMX7D_ECSPI4_ROOT_CLK 266
|
||||
#define IMX7D_ECSPI4_ROOT_SRC 267
|
||||
#define IMX7D_ECSPI4_ROOT_CG 268
|
||||
#define IMX7D_ECSPI4_ROOT_DIV 269
|
||||
#define IMX7D_PWM1_ROOT_CLK 270
|
||||
#define IMX7D_PWM1_ROOT_SRC 271
|
||||
#define IMX7D_PWM1_ROOT_CG 272
|
||||
#define IMX7D_PWM1_ROOT_DIV 273
|
||||
#define IMX7D_PWM2_ROOT_CLK 274
|
||||
#define IMX7D_PWM2_ROOT_SRC 275
|
||||
#define IMX7D_PWM2_ROOT_CG 276
|
||||
#define IMX7D_PWM2_ROOT_DIV 277
|
||||
#define IMX7D_PWM3_ROOT_CLK 278
|
||||
#define IMX7D_PWM3_ROOT_SRC 279
|
||||
#define IMX7D_PWM3_ROOT_CG 280
|
||||
#define IMX7D_PWM3_ROOT_DIV 281
|
||||
#define IMX7D_PWM4_ROOT_CLK 282
|
||||
#define IMX7D_PWM4_ROOT_SRC 283
|
||||
#define IMX7D_PWM4_ROOT_CG 284
|
||||
#define IMX7D_PWM4_ROOT_DIV 285
|
||||
#define IMX7D_FLEXTIMER1_ROOT_CLK 286
|
||||
#define IMX7D_FLEXTIMER1_ROOT_SRC 287
|
||||
#define IMX7D_FLEXTIMER1_ROOT_CG 288
|
||||
#define IMX7D_FLEXTIMER1_ROOT_DIV 289
|
||||
#define IMX7D_FLEXTIMER2_ROOT_CLK 290
|
||||
#define IMX7D_FLEXTIMER2_ROOT_SRC 291
|
||||
#define IMX7D_FLEXTIMER2_ROOT_CG 292
|
||||
#define IMX7D_FLEXTIMER2_ROOT_DIV 293
|
||||
#define IMX7D_SIM1_ROOT_CLK 294
|
||||
#define IMX7D_SIM1_ROOT_SRC 295
|
||||
#define IMX7D_SIM1_ROOT_CG 296
|
||||
#define IMX7D_SIM1_ROOT_DIV 297
|
||||
#define IMX7D_SIM2_ROOT_CLK 298
|
||||
#define IMX7D_SIM2_ROOT_SRC 299
|
||||
#define IMX7D_SIM2_ROOT_CG 300
|
||||
#define IMX7D_SIM2_ROOT_DIV 301
|
||||
#define IMX7D_GPT1_ROOT_CLK 302
|
||||
#define IMX7D_GPT1_ROOT_SRC 303
|
||||
#define IMX7D_GPT1_ROOT_CG 304
|
||||
#define IMX7D_GPT1_ROOT_DIV 305
|
||||
#define IMX7D_GPT2_ROOT_CLK 306
|
||||
#define IMX7D_GPT2_ROOT_SRC 307
|
||||
#define IMX7D_GPT2_ROOT_CG 308
|
||||
#define IMX7D_GPT2_ROOT_DIV 309
|
||||
#define IMX7D_GPT3_ROOT_CLK 310
|
||||
#define IMX7D_GPT3_ROOT_SRC 311
|
||||
#define IMX7D_GPT3_ROOT_CG 312
|
||||
#define IMX7D_GPT3_ROOT_DIV 313
|
||||
#define IMX7D_GPT4_ROOT_CLK 314
|
||||
#define IMX7D_GPT4_ROOT_SRC 315
|
||||
#define IMX7D_GPT4_ROOT_CG 316
|
||||
#define IMX7D_GPT4_ROOT_DIV 317
|
||||
#define IMX7D_TRACE_ROOT_CLK 318
|
||||
#define IMX7D_TRACE_ROOT_SRC 319
|
||||
#define IMX7D_TRACE_ROOT_CG 320
|
||||
#define IMX7D_TRACE_ROOT_DIV 321
|
||||
#define IMX7D_WDOG1_ROOT_CLK 322
|
||||
#define IMX7D_WDOG_ROOT_SRC 323
|
||||
#define IMX7D_WDOG_ROOT_CG 324
|
||||
#define IMX7D_WDOG_ROOT_DIV 325
|
||||
#define IMX7D_CSI_MCLK_ROOT_CLK 326
|
||||
#define IMX7D_CSI_MCLK_ROOT_SRC 327
|
||||
#define IMX7D_CSI_MCLK_ROOT_CG 328
|
||||
#define IMX7D_CSI_MCLK_ROOT_DIV 329
|
||||
#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
|
||||
#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
|
||||
#define IMX7D_AUDIO_MCLK_ROOT_CG 332
|
||||
#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
|
||||
#define IMX7D_WRCLK_ROOT_CLK 334
|
||||
#define IMX7D_WRCLK_ROOT_SRC 335
|
||||
#define IMX7D_WRCLK_ROOT_CG 336
|
||||
#define IMX7D_WRCLK_ROOT_DIV 337
|
||||
#define IMX7D_CLKO1_ROOT_SRC 338
|
||||
#define IMX7D_CLKO1_ROOT_CG 339
|
||||
#define IMX7D_CLKO1_ROOT_DIV 340
|
||||
#define IMX7D_CLKO2_ROOT_SRC 341
|
||||
#define IMX7D_CLKO2_ROOT_CG 342
|
||||
#define IMX7D_CLKO2_ROOT_DIV 343
|
||||
#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
|
||||
#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
|
||||
#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
|
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
|
||||
#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
|
||||
#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
|
||||
#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
|
||||
#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
|
||||
#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
|
||||
#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
|
||||
#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
|
||||
#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
|
||||
#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
|
||||
#define IMX7D_SAI1_ROOT_PRE_DIV 357
|
||||
#define IMX7D_SAI2_ROOT_PRE_DIV 358
|
||||
#define IMX7D_SAI3_ROOT_PRE_DIV 359
|
||||
#define IMX7D_SPDIF_ROOT_PRE_DIV 360
|
||||
#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
|
||||
#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
|
||||
#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
|
||||
#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
|
||||
#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
|
||||
#define IMX7D_EIM_ROOT_PRE_DIV 366
|
||||
#define IMX7D_NAND_ROOT_PRE_DIV 367
|
||||
#define IMX7D_QSPI_ROOT_PRE_DIV 368
|
||||
#define IMX7D_USDHC1_ROOT_PRE_DIV 369
|
||||
#define IMX7D_USDHC2_ROOT_PRE_DIV 370
|
||||
#define IMX7D_USDHC3_ROOT_PRE_DIV 371
|
||||
#define IMX7D_CAN1_ROOT_PRE_DIV 372
|
||||
#define IMX7D_CAN2_ROOT_PRE_DIV 373
|
||||
#define IMX7D_I2C1_ROOT_PRE_DIV 374
|
||||
#define IMX7D_I2C2_ROOT_PRE_DIV 375
|
||||
#define IMX7D_I2C3_ROOT_PRE_DIV 376
|
||||
#define IMX7D_I2C4_ROOT_PRE_DIV 377
|
||||
#define IMX7D_UART1_ROOT_PRE_DIV 378
|
||||
#define IMX7D_UART2_ROOT_PRE_DIV 379
|
||||
#define IMX7D_UART3_ROOT_PRE_DIV 380
|
||||
#define IMX7D_UART4_ROOT_PRE_DIV 381
|
||||
#define IMX7D_UART5_ROOT_PRE_DIV 382
|
||||
#define IMX7D_UART6_ROOT_PRE_DIV 383
|
||||
#define IMX7D_UART7_ROOT_PRE_DIV 384
|
||||
#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
|
||||
#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
|
||||
#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
|
||||
#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
|
||||
#define IMX7D_PWM1_ROOT_PRE_DIV 389
|
||||
#define IMX7D_PWM2_ROOT_PRE_DIV 390
|
||||
#define IMX7D_PWM3_ROOT_PRE_DIV 391
|
||||
#define IMX7D_PWM4_ROOT_PRE_DIV 392
|
||||
#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
|
||||
#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
|
||||
#define IMX7D_SIM1_ROOT_PRE_DIV 395
|
||||
#define IMX7D_SIM2_ROOT_PRE_DIV 396
|
||||
#define IMX7D_GPT1_ROOT_PRE_DIV 397
|
||||
#define IMX7D_GPT2_ROOT_PRE_DIV 398
|
||||
#define IMX7D_GPT3_ROOT_PRE_DIV 399
|
||||
#define IMX7D_GPT4_ROOT_PRE_DIV 400
|
||||
#define IMX7D_TRACE_ROOT_PRE_DIV 401
|
||||
#define IMX7D_WDOG_ROOT_PRE_DIV 402
|
||||
#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
|
||||
#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
|
||||
#define IMX7D_WRCLK_ROOT_PRE_DIV 405
|
||||
#define IMX7D_CLKO1_ROOT_PRE_DIV 406
|
||||
#define IMX7D_CLKO2_ROOT_PRE_DIV 407
|
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
|
||||
#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
|
||||
#define IMX7D_LVDS1_IN_CLK 410
|
||||
#define IMX7D_LVDS1_OUT_SEL 411
|
||||
#define IMX7D_LVDS1_OUT_CLK 412
|
||||
#define IMX7D_CLK_DUMMY 413
|
||||
#define IMX7D_GPT_3M_CLK 414
|
||||
#define IMX7D_OCRAM_CLK 415
|
||||
#define IMX7D_OCRAM_S_CLK 416
|
||||
#define IMX7D_WDOG2_ROOT_CLK 417
|
||||
#define IMX7D_WDOG3_ROOT_CLK 418
|
||||
#define IMX7D_WDOG4_ROOT_CLK 419
|
||||
#define IMX7D_SDMA_CORE_CLK 420
|
||||
#define IMX7D_USB1_MAIN_480M_CLK 421
|
||||
#define IMX7D_USB_CTRL_CLK 422
|
||||
#define IMX7D_USB_PHY1_CLK 423
|
||||
#define IMX7D_USB_PHY2_CLK 424
|
||||
#define IMX7D_IPG_ROOT_CLK 425
|
||||
#define IMX7D_SAI1_IPG_CLK 426
|
||||
#define IMX7D_SAI2_IPG_CLK 427
|
||||
#define IMX7D_SAI3_IPG_CLK 428
|
||||
#define IMX7D_PLL_AUDIO_TEST_DIV 429
|
||||
#define IMX7D_PLL_AUDIO_POST_DIV 430
|
||||
#define IMX7D_PLL_VIDEO_TEST_DIV 431
|
||||
#define IMX7D_PLL_VIDEO_POST_DIV 432
|
||||
#define IMX7D_MU_ROOT_CLK 433
|
||||
#define IMX7D_SEMA4_HS_ROOT_CLK 434
|
||||
#define IMX7D_PLL_DRAM_TEST_DIV 435
|
||||
#define IMX7D_ADC_ROOT_CLK 436
|
||||
#define IMX7D_CLK_ARM 437
|
||||
#define IMX7D_CKIL 438
|
||||
#define IMX7D_OCOTP_CLK 439
|
||||
#define IMX7D_CLK_END 440
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
Loading…
Reference in New Issue
Block a user