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Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

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This commit is contained in:
Tom Rini 2022-06-16 09:27:43 -04:00
commit 98c4828740
62 changed files with 57 additions and 316 deletions
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4
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
View File

@ -73,6 +73,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
View File

@ -84,6 +84,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
View File

@ -126,3 +126,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-venice-u-boot.dtsi
View File

@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
View File

@ -132,6 +132,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";

4
arch/arm/dts/imx8mn-venice-u-boot.dtsi
View File

@ -110,6 +110,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;

8
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
View File

@ -89,6 +89,14 @@
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mp-venice-u-boot.dtsi
View File

@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

12
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
View File

@ -28,12 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#ifdef CONFIG_NAND_MXS
static void setup_gpmi_nand(void)
{
@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
init_uart_clk(2);
return 0;

31
board/beacon/imx8mm/spl.c
View File

@ -59,31 +59,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
static int power_init_board(void)
{
struct udevice *dev;
@ -124,12 +99,8 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -139,6 +110,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);

21
board/beacon/imx8mn/spl.c
View File

@ -68,34 +68,17 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(1);
return 0;
@ -114,14 +97,14 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
/* DDR initialization */

31
board/compulab/imx8mm-cl-iot-gate/spl.c
View File

@ -83,31 +83,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
static int power_init_board(void)
{
struct udevice *dev;
@ -149,14 +124,10 @@ void board_init_f(ulong dummy)
arch_cpu_init();
board_early_init_f();
init_uart_clk(2);
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -166,6 +137,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);

16
board/engicam/imx8mm/spl.c
View File

@ -54,19 +54,9 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
return 0;
}
void board_init_f(ulong dummy)
@ -81,8 +71,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -92,6 +80,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
enable_tzc380();
/* DDR initialization */

29
board/gateworks/venice/spl.c
View File

@ -87,33 +87,6 @@ static void spl_dram_init(int size)
ddr_init(dram_timing);
}
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MN
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MP
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#endif
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
return 0;
}
/*
* Model specific PMIC adjustments necessary prior to DRAM init
*
@ -253,8 +226,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
board_early_init_f();
timer_init();
/* Clear the BSS. */

30
board/kontron/sl-mx8mm/spl.c
View File

@ -32,8 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
@ -51,15 +49,6 @@ static iomux_v3_cfg_t const touch_gpio[] = {
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@ -222,19 +211,6 @@ void spl_board_init(void)
printf("Failed to find clock node. Check device tree\n");
}
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
static int power_init_board(void)
{
struct udevice *dev;
@ -269,12 +245,8 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -284,6 +256,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
enable_tzc380();
/* PMIC initialization */

31
board/phytec/phycore_imx8mm/spl.c
View File

@ -57,31 +57,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
@ -90,10 +65,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
board_early_init_f();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -103,6 +74,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
enable_tzc380();
/* DDR initialization */

27
board/phytec/phycore_imx8mp/spl.c
View File

@ -89,31 +89,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
@ -122,8 +97,6 @@ void board_init_f(ulong dummy)
init_uart_clk(0);
board_early_init_f();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);

22
board/variscite/imx8mn_var_som/spl.c
View File

@ -40,26 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t uart_pads[] = {
IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
return 0;
@ -78,14 +60,14 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
/* DDR initialization */
spl_dram_init();

1
configs/imx8mm-cl-iot-gate-optee_defconfig
View File

@ -121,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mm-cl-iot-gate_defconfig
View File

@ -124,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mm-icore-mx8mm-ctouch2_defconfig
View File

@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

1
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
View File

@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

1
configs/imx8mm_beacon_defconfig
View File

@ -125,7 +125,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mn_beacon_2g_defconfig
View File

@ -127,7 +127,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mn_beacon_defconfig
View File

@ -131,7 +131,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/imx8mn_var_som_defconfig
View File

@ -96,6 +96,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y

1
configs/kontron-sl-mx8mm_defconfig
View File

@ -114,6 +114,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/phycore-imx8mm_defconfig
View File

@ -120,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/phycore-imx8mp_defconfig
View File

@ -111,6 +111,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

2
include/configs/aristainetos2.h
View File

@ -14,10 +14,8 @@
#define CONFIG_HOSTNAME "aristainetos2"
#if (CONFIG_SYS_BOARD_VERSION == 5)
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
#elif (CONFIG_SYS_BOARD_VERSION == 6)
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
#endif

1
include/configs/capricorn-common.h
View File

@ -20,7 +20,6 @@
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif /* CONFIG_SPL_BUILD */

1
include/configs/cgtqmx8.h
View File

@ -19,7 +19,6 @@
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
/* Flat Device Tree Definitions */

3
include/configs/imx8mm-cl-iot-gate.h
View File

@ -20,7 +20,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x912000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
@ -134,8 +133,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2

3
include/configs/imx8mm_beacon.h
View File

@ -17,7 +17,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
@ -80,6 +79,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
#endif

1
include/configs/imx8mm_data_modul_edm_sbc.h
View File

@ -18,7 +18,6 @@
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif

3
include/configs/imx8mm_evk.h
View File

@ -19,7 +19,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
@ -57,8 +56,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
#define CONFIG_FEC_MXC_PHYADDR 0
#endif

4
include/configs/imx8mm_icore_mx8mm.h
View File

@ -18,7 +18,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
# define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif /* CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
@ -54,9 +53,6 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

4
include/configs/imx8mm_venice.h
View File

@ -17,7 +17,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
@ -90,9 +89,6 @@
#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* FEC */
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC

3
include/configs/imx8mn_beacon.h
View File

@ -18,7 +18,6 @@
#define CONFIG_MALLOC_F_ADDR 0x184000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif /* CONFIG_SPL_BUILD */
@ -96,6 +95,4 @@
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#endif
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
#endif

4
include/configs/imx8mn_bsh_smm_s2_common.h
View File

@ -32,8 +32,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
/* I2C */
#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */

3
include/configs/imx8mn_evk.h
View File

@ -18,7 +18,6 @@
#ifdef CONFIG_SPL_BUILD
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
@ -64,6 +63,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
#endif

2
include/configs/imx8mn_var_som.h
View File

@ -53,8 +53,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4)
/* USDHC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

4
include/configs/imx8mn_venice.h
View File

@ -15,7 +15,6 @@
#ifdef CONFIG_SPL_BUILD
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
@ -86,9 +85,6 @@
#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* FEC */
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC

3
include/configs/imx8mp_evk.h
View File

@ -18,7 +18,6 @@
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PCA9450
@ -69,6 +68,4 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
#endif

1
include/configs/imx8mp_rsb3720.h
View File

@ -32,7 +32,6 @@
* set \
*/
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SPL_NAND_MXS

4
include/configs/imx8mp_venice.h
View File

@ -15,7 +15,6 @@
#ifdef CONFIG_SPL_BUILD
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
@ -86,9 +85,6 @@
#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* FEC */
#define FEC_QUIRK_ENET_MAC

1
include/configs/imx8mq_cm.h
View File

@ -20,7 +20,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif

1
include/configs/imx8mq_evk.h
View File

@ -21,7 +21,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08

1
include/configs/imx8mq_phanbell.h
View File

@ -18,7 +18,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
/* ENET Config */

1
include/configs/imx8qm_mek.h
View File

@ -20,7 +20,6 @@
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#ifdef CONFIG_AHAB_BOOT

1
include/configs/imx8qxp_mek.h
View File

@ -18,7 +18,6 @@
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#ifdef CONFIG_AHAB_BOOT

1
include/configs/imx8ulp_evk.h
View File

@ -16,7 +16,6 @@
#ifdef CONFIG_SPL_BUILD
#define CONFIG_MALLOC_F_ADDR 0x22040000
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#endif

1
include/configs/kontron-sl-mx8mm.h
View File

@ -23,7 +23,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
/* Board and environment settings */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_HOSTNAME "kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD

1
include/configs/kontron_pitx_imx8m.h
View File

@ -22,7 +22,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PFUZE100

1
include/configs/mx7dsabresd.h
View File

@ -12,7 +12,6 @@
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
#ifdef CONFIG_IMX_BOOTAUX
/* Set to QSPI1 A flash at default */

4
include/configs/phycore_imx8mm.h
View File

@ -20,7 +20,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -72,7 +71,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#endif /* __PHYCORE_IMX8MM_H */

4
include/configs/phycore_imx8mp.h
View File

@ -17,7 +17,6 @@
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PCA9450
@ -72,7 +71,4 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
#endif /* __PHYCORE_IMX8MP_H */

1
include/configs/pico-imx8mq.h
View File

@ -18,7 +18,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
/* ENET Config */

1
include/configs/somlabs_visionsom_6ull.h
View File

@ -16,7 +16,6 @@
/* SPL options */
#include "imx6_spl.h"
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC

3
include/configs/tbs2910.h
View File

@ -20,9 +20,6 @@
#define CONFIG_SYS_BOOTMAPSZ 0x10000000
/* Serial console */
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
/* Framebuffer */
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

4
include/configs/verdin-imx8mm.h
View File

@ -19,7 +19,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
@ -72,9 +71,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* ENET */
#define CONFIG_FEC_MXC_PHYADDR 7

4
include/configs/verdin-imx8mp.h
View File

@ -19,7 +19,6 @@
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x184000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_POWER_PCA9450
@ -89,7 +88,4 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#endif /* __VERDIN_IMX8MP_H */