ns16550: unify serial_rockchip
Unify serial_rockchip, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
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@ -324,6 +324,7 @@
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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@ -337,6 +338,7 @@
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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@ -350,6 +352,7 @@
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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@ -362,6 +365,7 @@
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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@ -375,6 +379,7 @@
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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@ -33,9 +33,6 @@ config DM_I2C
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config DM_GPIO
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default y
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config ROCKCHIP_SERIAL
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default y
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source "arch/arm/mach-rockchip/rk3288/Kconfig"
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endif
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@ -186,19 +186,10 @@ config ALTERA_UART
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Select this to enable an UART for Altera devices. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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config ROCKCHIP_SERIAL
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bool "Rockchip on-chip UART support"
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depends on ARCH_ROCKCHIP && DM_SERIAL
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help
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Select this to enable a debug UART for Rockchip devices. This uses
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the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
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your board config header. The clock input is automatically set to
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use the oscillator (24MHz).
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config NS16550_SERIAL
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bool "NS16550 UART or compatible"
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depends on DM_SERIAL
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default y if X86 || PPC
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default y if X86 || PPC || ARCH_ROCKCHIP
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help
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Support NS16550 UART or compatible with driver model. This can be
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enabled in the device tree with the correct input clock frequency.
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@ -40,7 +40,6 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
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obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
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obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
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obj-$(CONFIG_MXS_AUART) += mxs_auart.o
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obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
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obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
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obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
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obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
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@ -1,43 +0,0 @@
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/*
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* Copyright (c) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <serial.h>
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#include <asm/arch/clock.h>
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static const struct udevice_id rockchip_serial_ids[] = {
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{ .compatible = "rockchip,rk3288-uart" },
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{ }
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};
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static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct ns16550_platdata *plat = dev_get_platdata(dev);
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int ret;
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ret = ns16550_serial_ofdata_to_platdata(dev);
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if (ret)
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return ret;
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/* Do all Rockchip parts use 24MHz? */
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plat->clock = 24 * 1000000;
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return 0;
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}
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U_BOOT_DRIVER(serial_ns16550) = {
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.name = "serial_rockchip",
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.id = UCLASS_SERIAL,
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.of_match = rockchip_serial_ids,
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.ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
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.priv_auto_alloc_size = sizeof(struct NS16550),
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.probe = ns16550_serial_probe,
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.ops = &ns16550_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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