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tegra: mmc: Support operation with dcache enabled

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When the data cache is enabled we must flush on write and invalidate
on read. We also check that buffers are aligned to data cache lines
boundaries. With recent work in U-Boot this should generally be the case
but the warnings will catch problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass 2012-01-09 13:20:40 +00:00 committed by Albert ARIBAUD
parent ca28090d21
commit 98450d0220
1 changed files with 16 additions and 0 deletions
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16
drivers/mmc/tegra2_mmc.c
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@ -114,6 +114,14 @@ static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
if (data->flags & MMC_DATA_READ)
mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
if (data->flags & MMC_DATA_WRITE) {
if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1))
printf("Warning: unaligned write to %p may fail\n",
data->src);
flush_dcache_range((ulong)data->src, (ulong)data->src +
data->blocks * data->blocksize);
}
writew(mode, &host->reg->trnmod);
}
@ -310,6 +318,14 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
}
}
writel(mask, &host->reg->norintsts);
if (data->flags & MMC_DATA_READ) {
if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
printf("Warning: unaligned read from %p "
"may fail\n", data->dest);
invalidate_dcache_range((ulong)data->dest,
(ulong)data->dest +
data->blocks * data->blocksize);
}
}
udelay(1000);