From 9db60e257be0d928726c7ffe273039860e968d46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Oct 2017 14:51:55 +0200 Subject: [PATCH 01/34] MAINTAINERS: Add myself as RCar/RMobile comaintainer To help out with the RCar/RMobile upstreaming, I'm adding myself as the RCar/RMobile maintainer. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 41c881f40f..a3069e65a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,6 +133,7 @@ F: arch/arm/include/asm/arch-pxa/ ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu +M: Marek Vasut S: Maintained T: git git://git.denx.de/u-boot-sh.git F: arch/arm/mach-rmobile/ From 942ee0933e881ff500aae7e42309bf6abbc495d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 05:32:42 +0100 Subject: [PATCH 02/34] fdtdec: Support parsing multiple /memory nodes It is legal to have multiple /memory nodes in a device tree . Currently, fdtdec_setup_memory_size() only supports parsing the first node . This patch extends the function such that if a particular /memory node does no longer have further "reg" entries and CONFIG_NR_DRAM_BANKS still allows for more DRAM banks, the code moves on to the next memory node and checks it's "reg"s. This makes it possible to handle both systems with single memory node with multiple entries and systems with multiple memory nodes with single entry. Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Simon Glass --- lib/fdtdec.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c4582eacca..46df0f15f9 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1176,21 +1176,33 @@ int fdtdec_setup_memory_size(void) #if defined(CONFIG_NR_DRAM_BANKS) int fdtdec_setup_memory_banksize(void) { - int bank, ret, mem; + int bank, ret, mem, reg = 0; struct fdt_resource res; - mem = fdt_path_offset(gd->fdt_blob, "/memory"); + mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type", + "memory", 7); if (mem < 0) { debug("%s: Missing /memory node\n", __func__); return -EINVAL; } for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res); - if (ret == -FDT_ERR_NOTFOUND) - break; - if (ret != 0) + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res); + if (ret == -FDT_ERR_NOTFOUND) { + reg = 0; + mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem, + "device_type", + "memory", 7); + if (mem == -FDT_ERR_NOTFOUND) + break; + + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res); + if (ret == -FDT_ERR_NOTFOUND) + break; + } + if (ret != 0) { return -EINVAL; + } gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; gd->bd->bi_dram[bank].size = From 18cac5afc288fa30eb72421276b0bfd5d2e83ba6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 22:08:55 +0100 Subject: [PATCH 03/34] clk: rmobile: Move preboot clock shutdown to the driver The MSTP registers were poked in boards/renesas/rcar-common/common.c in arch_preboot_os hook thus far to shut down the clock before Linux takes over. With DM, this is no longer needed and we can do the same in the clock driver .remove callback. This patch adds such a .remove callback for R8A7795 and R8A7796. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/clk-rcar-gen3.c | 59 +++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c821bddc25..a3fb58b53b 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1074,6 +1074,64 @@ static int gen3_clk_probe(struct udevice *dev) return 0; } +struct mstp_stop_table { + u32 dis; + u32 en; +}; + +static struct mstp_stop_table r8a7795_mstp_table[] = { + { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 }, + { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 }, + { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 }, + { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 }, + { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 }, + { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 }, +}; + +static struct mstp_stop_table r8a7796_mstp_table[] = { + { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, + { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 }, + { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 }, + { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, +}; + +#define TSTR0 0x04 +#define TSTR0_STR0 BIT(0) + +static int gen3_clk_remove(struct udevice *dev) +{ + struct gen3_clk_priv *priv = dev_get_priv(dev); + enum gen3_clk_model model = dev_get_driver_data(dev); + struct mstp_stop_table *tbl; + unsigned int i, tbl_size; + + switch (model) { + case CLK_R8A7795: + tbl = r8a7795_mstp_table; + tbl_size = ARRAY_SIZE(r8a7795_mstp_table); + break; + case CLK_R8A7796: + tbl = r8a7796_mstp_table; + tbl_size = ARRAY_SIZE(r8a7796_mstp_table); + break; + default: + return -EINVAL; + } + + /* Stop TMU0 */ + clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0); + + /* Stop module clock */ + for (i = 0; i < tbl_size; i++) { + clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en); + clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0); + } + + return 0; +} + static const struct udevice_id gen3_clk_ids[] = { { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, @@ -1087,4 +1145,5 @@ U_BOOT_DRIVER(clk_gen3) = { .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), .ops = &gen3_clk_ops, .probe = gen3_clk_probe, + .remove = gen3_clk_remove, }; From 033b61198997c54c4cc962ed17a755029de7ad56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 10 Nov 2017 23:17:51 +0100 Subject: [PATCH 04/34] clk: rmobile: Add R8A7796 xHCI clock Add xHCI entry into the clock tables, so that the xHCI USB driver can enable the clock for the xHCI block via clock framework. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/clk-rcar-gen3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index a3fb58b53b..5abb171827 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -490,6 +490,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), DEF_MOD("rwdt", 402, R8A7796_CLK_R), From 167ee838dfec0a1d0574add00b9864808b93285f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 23:08:34 +0100 Subject: [PATCH 05/34] serial: sh: Unify R8A7795 and R8A7796 as Gen3 Unify the CONFIG_R8A7795 and CONFIG_R8A7796 as CONFIG_RCAR_GEN3 so that every time we add a new SoC, we won't have to add more stuff to this list. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 4d27122243..1b8d742f1c 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,8 +226,7 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \ - defined(CONFIG_R8A7796) + defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3) # if defined(CONFIG_SCIF_A) # define SCIF_ORER 0x0200 # else From 9e75ea46d50886187cd418168330745c1e1faf3f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Nov 2017 08:02:27 +0100 Subject: [PATCH 06/34] i2c: rcar_iic: Add RCar IIC driver Add driver for the RCar IIC or DVFS I2C controller. This driver is based on the SH I2C driver, but supports DM and DT probing as well as modern I2C framework API. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/rcar_iic.c | 271 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 drivers/i2c/rcar_iic.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1989f8eb57..cc370b9c57 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -157,6 +157,12 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. +config SYS_I2C_RCAR_IIC + bool "Renesas RCar Gen3 IIC driver" + depends on RCAR_GEN3 && DM_I2C + help + Support for Renesas RCar Gen3 IIC controller. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 733cd3e92f..169a2f1d7a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c new file mode 100644 index 0000000000..57ae2f51fc --- /dev/null +++ b/drivers/i2c/rcar_iic.c @@ -0,0 +1,271 @@ +/* + * Renesas RCar IIC driver + * + * Copyright (C) 2017 Marek Vasut + * + * Based on + * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +struct rcar_iic_priv { + void __iomem *base; + struct clk clk; + u8 iccl; + u8 icch; +}; + +#define RCAR_IIC_ICDR 0x00 +#define RCAR_IIC_ICCR 0x04 +#define RCAR_IIC_ICSR 0x08 +#define RCAR_IIC_ICIC 0x0c +#define RCAR_IIC_ICCL 0x10 +#define RCAR_IIC_ICCH 0x14 + +/* ICCR */ +#define RCAR_IIC_ICCR_ICE BIT(7) +#define RCAR_IIC_ICCR_RACK BIT(6) +#define RCAR_IIC_ICCR_RTS BIT(4) +#define RCAR_IIC_ICCR_BUSY BIT(2) +#define RCAR_IIC_ICCR_SCP BIT(0) + +/* ICSR / ICIC */ +#define RCAR_IC_BUSY BIT(4) +#define RCAR_IC_TACK BIT(2) +#define RCAR_IC_DTE BIT(0) + +#define IRQ_WAIT 1000 + +static void sh_irq_dte(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) + break; + udelay(10); + } +} + +static int sh_irq_dte_with_tack(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) + break; + if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR)) + return -ETIMEDOUT; + udelay(10); + } + return 0; +} + +static void sh_irq_busy(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) + break; + udelay(10); + } +} + +static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + + clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); + setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); + + writeb(priv->iccl, priv->base + RCAR_IIC_ICCL); + writeb(priv->icch, priv->base + RCAR_IIC_ICCH); + writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC); + + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY, + priv->base + RCAR_IIC_ICCR); + sh_irq_dte(dev); + + clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK); + writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR); + return sh_irq_dte_with_tack(dev); +} + +static void rcar_iic_finish(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + + writeb(0, priv->base + RCAR_IIC_ICSR); + clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); +} + +static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i, ret = -EREMOTEIO; + + if (rcar_iic_set_addr(dev, msg->addr, 1) != 0) + goto err; + + udelay(10); + + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, + priv->base + RCAR_IIC_ICCR); + + for (i = 0; i < msg->len; i++) { + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + + msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff; + + if (msg->len - 1 == i) { + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK, + priv->base + RCAR_IIC_ICCR); + } + } + + sh_irq_busy(dev); + ret = 0; + +err: + rcar_iic_finish(dev); + return ret; +} + +static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i, ret = -EREMOTEIO; + + if (rcar_iic_set_addr(dev, msg->addr, 0) != 0) + goto err; + + udelay(10); + + for (i = 0; i < msg->len; i++) { + writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR); + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + } + + if (msg->flags & I2C_M_STOP) { + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS, + priv->base + RCAR_IIC_ICCR); + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + } + + sh_irq_busy(dev); + ret = 0; + +err: + rcar_iic_finish(dev); + return ret; +} + +static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + int ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = rcar_iic_read_common(dev, msg); + else + ret = rcar_iic_write_common(dev, msg); + + if (ret) + return -EREMOTEIO; + } + + return ret; +} + +static int rcar_iic_set_speed(struct udevice *dev, uint speed) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + const unsigned int ratio_high = 4; + const unsigned int ratio_low = 5; + int clkrate, denom; + + clkrate = clk_get_rate(&priv->clk); + if (clkrate < 0) + return clkrate; + + /* + * Calculate the value for ICCL and ICCH. From the data sheet: + * iccl = (p-clock / transfer-rate) * (L / (L + H)) + * icch = (p clock / transfer rate) * (H / (L + H)) + * where L and H are the SCL low and high ratio. + */ + denom = speed * (ratio_high + ratio_low); + priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom); + priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom); + + return 0; +} + +static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int ret; + + rcar_iic_set_addr(dev, addr, 1); + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, + priv->base + RCAR_IIC_ICCR); + ret = sh_irq_dte_with_tack(dev); + rcar_iic_finish(dev); + + return ret; +} + +static int rcar_iic_probe(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + rcar_iic_finish(dev); + + return rcar_iic_set_speed(dev, 100000); +} + +static const struct dm_i2c_ops rcar_iic_ops = { + .xfer = rcar_iic_xfer, + .probe_chip = rcar_iic_probe_chip, + .set_bus_speed = rcar_iic_set_speed, +}; + +static const struct udevice_id rcar_iic_ids[] = { + { .compatible = "renesas,rmobile-iic" }, + { } +}; + +U_BOOT_DRIVER(iic_rcar) = { + .name = "iic_rcar", + .id = UCLASS_I2C, + .of_match = rcar_iic_ids, + .probe = rcar_iic_probe, + .priv_auto_alloc_size = sizeof(struct rcar_iic_priv), + .ops = &rcar_iic_ops, +}; From 90997cda7614bc1a751b107ae292f725ab161b25 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Nov 2017 22:49:19 +0100 Subject: [PATCH 07/34] net: ravb: Fix reset GPIO handling Fix handling of the reset GPIO. Drop the _nodev() suffix from the gpio_request_by_name() call as there is now a proper DM capable GPIO driver. Also check if the GPIO is valid before freeing it in remove path, otherwise U-Boot will crash. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Nobuhiro Iwamatsu --- drivers/net/ravb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index dc7a52534e..26d95f178f 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -492,8 +492,8 @@ static int ravb_probe(struct udevice *dev) if (ret < 0) goto err_mdio_alloc; - gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0, - ð->reset_gpio, GPIOD_IS_OUT); + gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, + GPIOD_IS_OUT); mdiodev = mdio_alloc(); if (!mdiodev) { @@ -528,7 +528,8 @@ static int ravb_remove(struct udevice *dev) free(eth->phydev); mdio_unregister(eth->bus); mdio_free(eth->bus); - dm_gpio_free(dev, ð->reset_gpio); + if (dm_gpio_is_valid(ð->reset_gpio)) + dm_gpio_free(dev, ð->reset_gpio); unmap_physmem(eth->iobase, MAP_NOCACHE); return 0; From 5d1b875dfa8786ecc285443f4afe962e64f0e59d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 14:50:37 +0100 Subject: [PATCH 08/34] ARM: rmobile: Fix eMMC signal voltage on ULCB The eMMC is 1V8 device only and the signaling is always 1V8, fix the DT for ULCB to describe the hardware correctly. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/ulcb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index e21cf332c9..b0ad11897c 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -247,7 +247,7 @@ sdhi2_pins: sd2 { groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; - power-source = <3300>; + power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { From fade9f2f1680fd4ddc1c149785e9a6d7fc282350 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 20:59:23 +0100 Subject: [PATCH 09/34] ARM: rmobile: Enable Micrel KSZ90x1 PHY driver on ULCB Enable the Micrel KSZ90x1 driver on ULCB, since the board is populated with KSZ9031 and without this driver, the PHY cannot be operated. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/r8a7795_ulcb_defconfig | 2 ++ configs/r8a7796_ulcb_defconfig | 2 ++ include/configs/ulcb.h | 1 - 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 50d36891cc..94a9580a74 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -31,6 +31,8 @@ CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y CONFIG_PINCTRL=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index c8edfabc91..e827d75ccc 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -32,6 +32,8 @@ CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y CONFIG_PINCTRL=y diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index b54e63c2a2..e9b64ae6e8 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -33,7 +33,6 @@ /* use to RPC(SPI Multi I/O Bus Controller) */ /* Ethernet RAVB */ -#define CONFIG_PHY_MICREL #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI From fab5c41b8e5e9cd2db03a58919463dcbe5244e20 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 23:13:37 +0100 Subject: [PATCH 10/34] ARM: rmobile: Drop CONFIG_USB_MAX_CONTROLLER_COUNT on Gen3 boards The USB support has been switched to DM, so this macro is no longer meaningful, drop it. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/salvator-x.h | 7 ------- include/configs/ulcb.h | 7 ------- 2 files changed, 14 deletions(-) diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 77a12de963..8616b36ecc 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -59,13 +59,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - /* SDHI */ #define CONFIG_SH_SDHI_FREQ 200000000 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index e9b64ae6e8..a4795c5ff3 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -80,13 +80,6 @@ unsigned char ulcb_softspi_read(void); #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - /* SDHI */ #define CONFIG_SH_SDHI_FREQ 200000000 From d4bde6fa18a8d6587483df3eb3a98b9dd6b08931 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 21:15:36 +0100 Subject: [PATCH 11/34] ARM: rmobile: Drop SDHI address macros from Gen3 Since the RCar Gen3 no longer uses the SH SDHI driver, but rather uses the Matsushita SD driver, which loads all the properties from device tree, these macros are no longer used, remove them. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/include/mach/r8a7795.h | 7 ------- arch/arm/mach-rmobile/include/mach/r8a7796.h | 7 ------- arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h | 6 ------ 3 files changed, 20 deletions(-) diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795.h b/arch/arm/mach-rmobile/include/mach/r8a7795.h index 2d004b6a54..23e4399479 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7795.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7795.h @@ -26,11 +26,4 @@ #define MSTP10_BITS 0xFFFEFFE0 #define MSTP11_BITS 0x00000000 -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - #endif /* __ASM_ARCH_R8A7795_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h index dab6082012..67e24bcf98 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7796.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7796.h @@ -26,11 +26,4 @@ #define MSTP10_BITS 0xFFFEFFE0 #define MSTP11_BITS 0x000000B7 -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - #endif /* __ASM_ARCH_R8A7796_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index 39726355e6..507859342c 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -68,12 +68,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 - /* PFC */ #define PFC_PUEN5 0xE6060414 #define PUEN_SSI_SDATA4 BIT(17) From 8e8ebd32698986b0e11e491adb3d61bfc01d941c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Nov 2017 08:20:34 +0100 Subject: [PATCH 12/34] ARM: rmobile: Remove CONFIG_CMD_SDRAM from Salvator-X This command is useless on Salvator-X as it is reading DRAM info from SPD. We have no SPD on Salvator-X. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/r8a7795_salvator-x_defconfig | 1 - configs/r8a7796_salvator-x_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index e32aceba54..807ab55784 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -14,7 +14,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 8f22645efb..1949426677 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -15,7 +15,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y From 7bcdd0c1f82edfcfb4de1c5d5953d9e0954371d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Nov 2017 08:25:21 +0100 Subject: [PATCH 13/34] ARM: rmobile: Clean up GIC macros Pull out the GIC macros from the board configuration files into the common Gen3 configuration file since these macros are the same for all Gen3 systems. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/rcar-gen3-common.h | 5 +++++ include/configs/salvator-x.h | 5 ----- include/configs/ulcb.h | 5 ----- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 6deed0dcd7..dd6863e64e 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -31,6 +31,11 @@ #define CONFIG_ARCH_CPU_INIT +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF1010000 +#define GICC_BASE 0xF1020000 + /* console */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 8616b36ecc..5004fa31b6 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -42,11 +42,6 @@ /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - /* i2c */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SH diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index a4795c5ff3..41ba5972a6 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -50,11 +50,6 @@ /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - /* CPLD SPI */ #define CONFIG_CMD_SPI #define CONFIG_SOFT_SPI From 796411b08af2b2fdcbe00d7f70ca04d9253dc2aa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 Sep 2017 12:33:11 +0200 Subject: [PATCH 14/34] ARM: rmobile: Enable xHCI on RCar Gen3 boards Enable the XHCI support on all boards. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/r8a7795_salvator-x_defconfig | 1 + configs/r8a7795_ulcb_defconfig | 1 + configs/r8a7796_salvator-x_defconfig | 1 + configs/r8a7796_ulcb_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 807ab55784..00d534b79b 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 94a9580a74..4c57ffc013 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 1949426677..4a36469f62 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index e827d75ccc..989edf66f9 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y From 5271dda05030982a94ced178fdc031e8f76da988 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 Sep 2017 00:27:33 +0200 Subject: [PATCH 15/34] ARM: rmobile: Zap Gen3 PFC tables These old PFC tables are no longer needed as there is now a proper PFC pinmux driver in drivers/pinctrl/renesas . Remove them . Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/Makefile | 4 +- arch/arm/mach-rmobile/include/mach/gpio.h | 6 - .../mach-rmobile/include/mach/r8a7795-gpio.h | 1016 ---- .../mach-rmobile/include/mach/r8a7796-gpio.h | 1084 ---- arch/arm/mach-rmobile/pfc-r8a7795.c | 5005 ---------------- arch/arm/mach-rmobile/pfc-r8a7796.c | 5253 ----------------- 6 files changed, 2 insertions(+), 12366 deletions(-) delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7795.c delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7796.c diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 2aea527bae..8aa2b4f82a 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o -obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o +obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7795.o +obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7796.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h index 02b29364c5..448d189e92 100644 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ b/arch/arm/mach-rmobile/include/mach/gpio.h @@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void); #elif defined(CONFIG_R8A7794) #include "r8a7794-gpio.h" void r8a7794_pinmux_init(void); -#elif defined(CONFIG_R8A7795) -#include "r8a7795-gpio.h" -void r8a7795_pinmux_init(void); -#elif defined(CONFIG_R8A7796) -#include "r8a7796-gpio.h" -void r8a7796_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h deleted file mode 100644 index 554063ab8f..0000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7795_GPIO_H__ -#define __ASM_R8A7795_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ - -/* V2(ES2.0) */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_GFN_SD3_DAT3, - GPIO_GFN_SD3_DAT2, - GPIO_GFN_SD3_DAT1, - GPIO_GFN_SD3_DAT0, - GPIO_GFN_SD3_CMD, - GPIO_GFN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_GFN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_USB3_OVC, - GPIO_GFN_USB3_PWEN, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_FN_FSCLKST2x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_A25, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_A24, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_A23, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_FSCLKST2x_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - GPIO_FN_SATA_DEVSLP_B, - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0x, - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CFE_1x, - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SSI_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - GPIO_IFN_SSI_SCK01239, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - GPIO_IFN_SSI_WS01239, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - GPIO_FN_SATA_DEVSLP_A, - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_ISEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_RIF3_D1_A, - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5_A, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_HSCK2_C, - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOEx, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_USB3_PWEN, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - GPIO_IFN_USB3_OVC, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, -}; - -#endif /* __ASM_R8A7795_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h deleted file mode 100644 index 2359e36a14..0000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h +++ /dev/null @@ -1,1084 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7796_GPIO_H__ -#define __ASM_R8A7796_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_FN_SD3_DAT3, - GPIO_FN_SD3_DAT2, - GPIO_FN_SD3_DAT1, - GPIO_FN_SD3_DAT0, - GPIO_FN_SD3_CMD, - GPIO_FN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_FN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_GP6_31, - GPIO_GFN_GP6_30, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_PWMFSW0, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_FN_SPV_EVEN, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0_B, - - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CEF_1_B, - - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SS1_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - - GPIO_IFN_SSI_SCK0129, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - - GPIO_IFN_SSI_WS0129, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_FN_FSO_TOE_A, - - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_IEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_EIF3_D1_A, - - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_FSO_CFE_1_A, - GPIO_FN_HSCK2_C, - - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOE_B, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_GP6_30, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_FSO_CFE_0_A, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - - GPIO_IFN_GP6_31, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, - -}; - -#endif /* __ASM_R8A7796_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c deleted file mode 100644 index 93aaf31ed9..0000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7795.c +++ /dev/null @@ -1,5005 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c - * This file is r8a7795 processor support - PFC hardware block. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_28(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define ES_CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_28(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - GFN_SD3_DAT3, - GFN_SD3_DAT2, - GFN_SD3_DAT1, - GFN_SD3_DAT0, - GFN_SD3_CMD, - GFN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - GFN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_USB3_OVC, - GFN_USB3_PWEN, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - FN_FSCLKST2x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_FSCLKST2x_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - IFN_SD2_CMD, - FN_NFDATA9, - IFN_SD2_DAT0, - FN_NFDATA10, - IFN_SD2_DAT1, - FN_NFDATA11, - IFN_SD2_DAT2, - FN_NFDATA12, - IFN_SD2_DAT3, - FN_NFDATA13, - IFN_SD2_DS, - FN_NFALE, - FN_SATA_DEVSLP_B, - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - IFN_SD3_DAT0, - FN_NFDATA0, - IFN_SD3_DAT1, - FN_NFDATA1, - IFN_SD3_DAT2, - FN_NFDATA2, - IFN_SD3_DAT3, - FN_NFDATA3, - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - IFN_SD3_DS, - FN_NFCLE, - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0x, - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CFE_1x, - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SSI_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - IFN_SSI_SCK01239, - FN_MSIOF1_TXD_F, - FN_MOUT0, - IFN_SSI_WS01239, - FN_MSIOF1_SS1_F, - FN_MOUT1, - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - IFN_SSI_WS6, - FN_SIM0_D_D, - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - FN_SATA_DEVSLP_A, - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_ISEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_RIF3_D1_A, - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5_A, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_HSCK2_C, - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOEx, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_USB3_PWEN, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - IFN_USB3_OVC, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, - /* reserved[3]*/ - - /* MOD_SEL1 */ - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - /* reserved[15..8] */ - /* reserved[7..1] */ - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_GMARK, - SD3_DAT2_GMARK, - SD3_DAT1_GMARK, - SD3_DAT0_GMARK, - SD3_CMD_GMARK, - SD3_CLK_GMARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_GMARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - USB3_OVC_GMARK, - USB3_PWEN_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - FSCLKST2x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - FSCLKST2x_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - SD2_CMD_IMARK, - NFDATA9_MARK, - SD2_DAT0_IMARK, - NFDATA10_MARK, - SD2_DAT1_IMARK, - NFDATA11_MARK, - SD2_DAT2_IMARK, - NFDATA12_MARK, - SD2_DAT3_IMARK, - NFDATA13_MARK, - SD2_DS_IMARK, - NFALE_MARK, - SATA_DEVSLP_B_MARK, - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - SD3_DAT0_IMARK, - NFDATA0_MARK, - SD3_DAT1_IMARK, - NFDATA1_MARK, - SD3_DAT2_IMARK, - NFDATA2_MARK, - SD3_DAT3_IMARK, - NFDATA3_MARK, - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - SD3_DS_IMARK, - NFCLE_MARK, - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0x_MARK, - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CFE_1x_MARK, - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SSI_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - SSI_SCK01239_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - SSI_WS01239_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - SSI_WS6_IMARK, - SIM0_D_D_MARK, - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - SATA_DEVSLP_A_MARK, - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_ISEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - RIF3_D1_A_MARK, - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_A_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - HSCK2_C_MARK, - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOEx_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - USB3_PWEN_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - USB3_OVC_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD), - PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC), - PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_GFN(SD3_DAT3), - GPIO_GFN(SD3_DAT2), - GPIO_GFN(SD3_DAT1), - GPIO_GFN(SD3_DAT0), - GPIO_GFN(SD3_CMD), - GPIO_GFN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_GFN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(USB3_OVC), - GPIO_GFN(USB3_PWEN), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_FN(FSCLKST2x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(FSCLKST2x_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - GPIO_FN(SATA_DEVSLP_B), - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0x), - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CFE_1x), - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SSI_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - GPIO_IFN(SSI_SCK01239), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - GPIO_IFN(SSI_WS01239), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - GPIO_FN(SATA_DEVSLP_A), - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_ISEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(RIF3_D1_A), - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5_A), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(HSCK2_C), - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOEx), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(USB3_PWEN), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(USB3_OVC), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, GFN_SD3_DAT3, - GP_4_11_FN, GFN_SD3_DAT2, - GP_4_10_FN, GFN_SD3_DAT1, - GP_4_9_FN, GFN_SD3_DAT0, - GP_4_8_FN, GFN_SD3_CMD, - GP_4_7_FN, GFN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, GFN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_USB3_OVC, - GP_6_30_FN, GFN_USB3_PWEN, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, FN_FSCLKST2x_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, 0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - FN_SATA_DEVSLP_B, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD2_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B, - FN_ADICHS2, FN_SCK5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - 0, 0, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CFE_1x, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0x, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - 0, 0, 0, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_RIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - 0, 0, 0, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - FN_SATA_DEVSLP_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, 0, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, 0, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) { - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, 0, - 0, 0, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - 0, 0, - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, 0, - /* reserved[3]*/ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, 0, - 0, 0, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, 0, - 0, 0, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, 0, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - 0, 0, - 0, 0, - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, 0, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - 0, 0, - /* reserved[15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved[7..1] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - } - }, - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - - -static struct pinmux_info r8a7795_pinmux_info = { - .name = "r8a7795_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7795_pinmux_init(void) -{ - register_pinmux(&r8a7795_pinmux_info); -} diff --git a/arch/arm/mach-rmobile/pfc-r8a7796.c b/arch/arm/mach-rmobile/pfc-r8a7796.c deleted file mode 100644 index f734f96dd0..0000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7796.c +++ /dev/null @@ -1,5253 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c - * This file is r8a7796 processor support - PFC hardware block. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - FN_SD3_DAT3, - FN_SD3_DAT2, - FN_SD3_DAT1, - FN_SD3_DAT0, - FN_SD3_CMD, - FN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - FN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_GP6_30, - GFN_GP6_31, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_PWMFSW0, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - FN_SPV_EVEN, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - - IFN_SD2_CMD, - FN_NFDATA9, - - IFN_SD2_DAT0, - FN_NFDATA10, - - IFN_SD2_DAT1, - FN_NFDATA11, - - IFN_SD2_DAT2, - FN_NFDATA12, - - IFN_SD2_DAT3, - FN_NFDATA13, - - IFN_SD2_DS, - FN_NFALE, - - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - - IFN_SD3_DAT0, - FN_NFDATA0, - - IFN_SD3_DAT1, - FN_NFDATA1, - - IFN_SD3_DAT2, - FN_NFDATA2, - - IFN_SD3_DAT3, - FN_NFDATA3, - - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - - IFN_SD3_DS, - FN_NFCLE, - - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0_B, - - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CEF_1_B, - - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SS1_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - - IFN_SSI_SCK0129, - FN_MSIOF1_TXD_F, - FN_MOUT0, - - IFN_SSI_WS0129, - FN_MSIOF1_SS1_F, - FN_MOUT1, - - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - FN_FSO_TOE_A, - - IFN_SSI_WS6, - FN_SIM0_D_D, - - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_IEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_EIF3_D1_A, - - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_FSO_CFE_1_A, - FN_HSCK2_C, - - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOE_B, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_GP6_30, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_FSO_CFE_0_A, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - - IFN_GP6_31, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - FN_SEL_FSO_0, FN_SEL_FSO_1, - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - - /* MOD_SEL1 */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - FN_SEL_SSI_0, - FN_SEL_SSI_1, - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - FN_SEL_NDF_0, - FN_SEL_NDF_1, - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_MARK, - SD3_DAT2_MARK, - SD3_DAT1_MARK, - SD3_DAT0_MARK, - SD3_CMD_MARK, - SD3_CLK_MARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_MARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - GP6_30_GMARK, - GP6_31_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - SPV_EVEN_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - - SD2_CMD_IMARK, - NFDATA9_MARK, - - SD2_DAT0_IMARK, - NFDATA10_MARK, - - SD2_DAT1_IMARK, - NFDATA11_MARK, - - SD2_DAT2_IMARK, - NFDATA12_MARK, - - SD2_DAT3_IMARK, - NFDATA13_MARK, - - SD2_DS_IMARK, - NFALE_MARK, - - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - - SD3_DAT0_IMARK, - NFDATA0_MARK, - - SD3_DAT1_IMARK, - NFDATA1_MARK, - - SD3_DAT2_IMARK, - NFDATA2_MARK, - - SD3_DAT3_IMARK, - NFDATA3_MARK, - - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - - SD3_DS_IMARK, - NFCLE_MARK, - - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0_B_MARK, - - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CEF_1_B_MARK, - - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SS1_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - - SSI_SCK0129_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - - SSI_WS0129_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - FSO_TOE_A_MARK, - - SSI_WS6_IMARK, - SIM0_D_D_MARK, - - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_IEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - EIF3_D1_A_MARK, - - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - FSO_CFE_1_A_MARK, - HSCK2_C_MARK, - - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOE_B_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - GP6_30_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - FSO_CFE_0_A_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - GP6_31_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD), - PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(GP6_30_GMARK, GFN_GP6_30), - PINMUX_DATA(GP6_31_GMARK, GFN_GP6_31), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - - /* ipsr setting .. underconstruction */ -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_FN(SD3_DAT3), - GPIO_FN(SD3_DAT2), - GPIO_FN(SD3_DAT1), - GPIO_FN(SD3_DAT0), - GPIO_FN(SD3_CMD), - GPIO_FN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_FN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(GP6_30), - GPIO_GFN(GP6_31), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(PWMFSW0), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_FN(SPV_EVEN), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0_B), - - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CEF_1_B), - - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SS1_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - - GPIO_IFN(SSI_SCK0129), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - - GPIO_IFN(SSI_WS0129), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_FN(FSO_TOE_A), - - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_IEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(EIF3_D1_A), - - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(FSO_CFE_1_A), - GPIO_FN(HSCK2_C), - - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOE_B), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(GP6_30), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(FSO_CFE_0_A), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(GP6_31), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, FN_SD3_DAT3, - GP_4_11_FN, FN_SD3_DAT2, - GP_4_10_FN, FN_SD3_DAT1, - GP_4_9_FN, FN_SD3_DAT0, - GP_4_8_FN, FN_SD3_CMD, - GP_4_7_FN, FN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, FN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_GP6_31, - GP_6_30_FN, GFN_GP6_30, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, - FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, - FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD3_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - 0, FN_ADICHS2, 0, FN_RIF0_CLK_B, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CEF_1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0_B, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_EIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, FN_FSO_TOE_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, - 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, - 2, 1, 2, 1, 1, 1) { - /* SEL_MSIOF3 [3] */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, 0, - /* SEL_MSIOF2 [2] */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* SEL_MSIOF1 [3] */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - - /* SEL_LBSC [1] */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* SEL_IEBUS [1] */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* SEL_I2C2 [1] */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* SEL_I2C1 [1] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* SEL_HSCIF4 [1] */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* SEL_HSCIF3 [2] */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* SEL_HSCIF1 [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - - /* SEL_FSO [1] */ - FN_SEL_FSO_0, FN_SEL_FSO_1, - /* SEL_HSCIF2 [2] */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* SEL_ETHERAVB [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* SEL_DRIF3 [1] */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* SEL_DRIF2 [1] */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* SEL_DRIF1 [2] */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - - /* SEL_DRIF0 [2] */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* SEL_CANFD0 [1] */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* SEL_ADG [2] */ - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - /* reserved [3] */ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* SEL_TSIF1 [2] */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - /* SEL_TSIF0 [3] */ - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - 0, - 0, - 0, - /* SEL_TIMER_TMU [1] */ - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - /* SEL_SSP1_1 [2] */ - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - - /* SEL_SSP1_0 [3] */ - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - 0, - 0, - 0, - /* SEL_SSI [1] */ - FN_SEL_SSI_0, - FN_SEL_SSI_1, - /* SEL_SPEED_PULSE_IF [1] */ - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - /* SEL_SIMCARD [2] */ - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - /* SEL_SDHI2 [1] */ - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - - /* SEL_SCIF4 [2] */ - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - 0, - /* SEL_SCIF3 [1] */ - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - /* SEL_SCIF2 [1] */ - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - /* SEL_SCIF1 [1] */ - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - /* SEL_SCIF [1] */ - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - /* SEL_REMOCON [1] */ - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - /* reserved [2] */ - 0, 0, - - 0, 0, - /* SEL_RCAN [1] */ - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - /* SEL_PWM6 [1] */ - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - /* SEL_PWM5 [1] */ - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - /* SEL_PWM4 [1] */ - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - /* SEL_PWM3 [1] */ - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - /* SEL_PWM2 [1] */ - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - /* SEL_PWM1 [1] */ - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, - 3, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1) { - /* I2C_SEL_5 [1] */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - /* I2C_SEL_3 [1] */ - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - /* I2C_SEL_0 [1] */ - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - /* SEL_FM [2] */ - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - /* SEL_SCIF5 [1] */ - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - - /* SEL_I2C6 [3] */ - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - 0, - 0, - 0, - 0, - 0, - /* SEL_NDF [1] */ - FN_SEL_NDF_0, - FN_SEL_NDF_1, - /* SEL_SSI2 [1] */ - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - /* SEL_SSI9 [1] */ - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - /* SEL_TIMER_TME2 [1] */ - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - /* SEL_ADG_B [1] */ - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - - /* SEL_ADG_C [1] */ - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - /* reserved [16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - /* SEL_VIN4 [1] */ - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - } - }, - - /* under construction */ - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - -static struct pinmux_info r8a7796_pinmux_info = { - .name = "r8a7796_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7796_pinmux_init(void) -{ - register_pinmux(&r8a7796_pinmux_info); -} From e23eb942ad103f6d3dd15d9346bb1ea132899963 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 22:43:57 +0100 Subject: [PATCH 16/34] ARM: rmobile: Stop using rcar-common/common.c on Gen3 Since the Gen3 clock driver now has a .remove callback, it is no longer necessary to shut the clock down before booting Linux in the arch_preboot_os hook. Stop using it and while doing so, remove all the ad-hoc config options which this hook used. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/salvator-x/Makefile | 2 +- board/renesas/ulcb/Makefile | 2 +- include/configs/salvator-x.h | 8 -------- include/configs/ulcb.h | 8 -------- 4 files changed, 2 insertions(+), 18 deletions(-) diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index 61b0d063e5..5b4dea91c1 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := salvator-x.o ../rcar-common/common.o +obj-y := salvator-x.o diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index 6fe0b480f7..406fdc8fa4 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ulcb.o cpld.o ../rcar-common/common.o +obj-y := ulcb.o cpld.o diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 5004fa31b6..605c9c64b8 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -62,12 +62,4 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __SALVATOR_X_H */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 41ba5972a6..8f989bbce5 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -83,12 +83,4 @@ unsigned char ulcb_softspi_read(void); #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __ULCB_H */ From 654f37da64065cbd2f300bc5747d83cc3c401a08 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 22:53:04 +0100 Subject: [PATCH 17/34] ARM: rmobile: Dispose of r8a779x.h for Gen3 These files no longer contain anything useful, so remove them. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/include/mach/r8a7795.h | 29 -------------------- arch/arm/mach-rmobile/include/mach/r8a7796.h | 29 -------------------- arch/arm/mach-rmobile/include/mach/rmobile.h | 6 ++-- 3 files changed, 2 insertions(+), 62 deletions(-) delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7795.h delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7796.h diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795.h b/arch/arm/mach-rmobile/include/mach/r8a7795.h deleted file mode 100644 index 23e4399479..0000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-rmobile/include/mach/r8a7795.h - * This file defines registers and value for r8a7795. - * - * Copyright (C) 2015 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7795_H -#define __ASM_ARCH_R8A7795_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00640800 -#define MSTP1_BITS 0xF3EE9390 -#define MSTP2_BITS 0x340FAFDC -#define MSTP3_BITS 0xD80C7CDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0x40BFFF46 -#define MSTP6_BITS 0xE5FBEECF -#define MSTP7_BITS 0x39FFFF0E -#define MSTP8_BITS 0x01F19FF4 -#define MSTP9_BITS 0xFFDFFFFF -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x00000000 - -#endif /* __ASM_ARCH_R8A7795_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h deleted file mode 100644 index 67e24bcf98..0000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h - * This file defines registers and value for r8a7796. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7796_H -#define __ASM_ARCH_R8A7796_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00200000 -#define MSTP1_BITS 0xFFFFFFFF -#define MSTP2_BITS 0x340E2FDC -#define MSTP3_BITS 0xFFFFFFDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0xC3FFFFFF -#define MSTP6_BITS 0xFFFFFFFF -#define MSTP7_BITS 0xFFFFFFFF -#define MSTP8_BITS 0x01F1FFF7 -#define MSTP9_BITS 0xFFFFFFFE -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x000000B7 - -#endif /* __ASM_ARCH_R8A7796_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 654349b0b3..5958eda1dd 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -16,10 +16,8 @@ #include #elif defined(CONFIG_R8A7794) #include -#elif defined(CONFIG_R8A7795) -#include -#elif defined(CONFIG_R8A7796) -#include +#elif defined(CONFIG_RCAR_GEN3) +#include #else #error "SOC Name not defined" #endif From 262e91566fde7b5564f4a9d3f2fb019cd3c0eb0c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 23:54:10 +0100 Subject: [PATCH 18/34] ARM: rmobile: Add PRR CPU ID macros Replace the ad-hoc values in the PRR CPU ID table with macros, so that users can use rmobile_get_cpu_type() can compare the returned value with these macros to figure out on which CPU they are running. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/cpu_info.c | 18 +++++++++--------- arch/arm/mach-rmobile/include/mach/rmobile.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index faa53197d5..04bac66391 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -49,15 +49,15 @@ static const struct { u16 cpu_type; u8 cpu_name[10]; } rmobile_cpuinfo[] = { - { 0x37, "SH73A0" }, - { 0x40, "R8A7740" }, - { 0x45, "R8A7790" }, - { 0x47, "R8A7791" }, - { 0x4A, "R8A7792" }, - { 0x4B, "R8A7793" }, - { 0x4C, "R8A7794" }, - { 0x4F, "R8A7795" }, - { 0x52, "R8A7796" }, + { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" }, + { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, + { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, + { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, + { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" }, + { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" }, + { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, + { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, + { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 5958eda1dd..b3140d1c5d 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -23,6 +23,17 @@ #endif #endif /* CONFIG_ARCH_RMOBILE */ +/* PRR CPU IDs */ +#define RMOBILE_CPU_TYPE_SH73A0 0x37 +#define RMOBILE_CPU_TYPE_R8A7740 0x40 +#define RMOBILE_CPU_TYPE_R8A7790 0x45 +#define RMOBILE_CPU_TYPE_R8A7791 0x47 +#define RMOBILE_CPU_TYPE_R8A7792 0x4A +#define RMOBILE_CPU_TYPE_R8A7793 0x4B +#define RMOBILE_CPU_TYPE_R8A7794 0x4C +#define RMOBILE_CPU_TYPE_R8A7795 0x4F +#define RMOBILE_CPU_TYPE_R8A7796 0x52 + #ifndef __ASSEMBLY__ u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); From a523af69e83480b054b4fdd1b8fa928cd9aa4873 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Nov 2017 23:24:01 +0100 Subject: [PATCH 19/34] ARM: rmobile: Unify memory map for RCar Gen3 Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now, select which one is used based on which SoC is selected. Since this is done in C code instead of statically assigned now, the decision can be taken by PRR SoC match as well, which will be done in a subsequent patch. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/Makefile | 4 +- arch/arm/mach-rmobile/cpu_info.c | 3 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + arch/arm/mach-rmobile/memmap-gen3.c | 66 ++++++++++++++++++++ arch/arm/mach-rmobile/memmap-r8a7795.c | 30 --------- arch/arm/mach-rmobile/memmap-r8a7796.c | 30 --------- 6 files changed, 72 insertions(+), 62 deletions(-) create mode 100644 arch/arm/mach-rmobile/memmap-gen3.c delete mode 100644 arch/arm/mach-rmobile/memmap-r8a7795.c delete mode 100644 arch/arm/mach-rmobile/memmap-r8a7796.c diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 8aa2b4f82a..440604cce5 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7795.o -obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7796.o +obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o +obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 04bac66391..5c8cb3f666 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -18,6 +18,9 @@ int arch_cpu_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { +#if defined(CONFIG_RCAR_GEN3) + rcar_gen3_memmap_fixup(); +#endif dcache_enable(); } #endif diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index b3140d1c5d..b413859a4d 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -38,6 +38,7 @@ u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); u32 rmobile_get_cpu_rev_fraction(void); +void rcar_gen3_memmap_fixup(void); #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c new file mode 100644 index 0000000000..f3156ab01a --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -0,0 +1,66 @@ +/* + * Renesas RCar Gen3 memory map tables + * + * Copyright (C) 2017 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +static struct mm_region r8a7795_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +static struct mm_region r8a7796_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe0000000UL, + .phys = 0xe0000000UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = r8a7795_mem_map; + +void rcar_gen3_memmap_fixup(void) +{ + u32 cpu_type = rmobile_get_cpu_type(); + + switch (cpu_type) { + case RMOBILE_CPU_TYPE_R8A7795: + mem_map = r8a7795_mem_map; + break; + case RMOBILE_CPU_TYPE_R8A7796: + mem_map = r8a7796_mem_map; + break; + } +} diff --git a/arch/arm/mach-rmobile/memmap-r8a7795.c b/arch/arm/mach-rmobile/memmap-r8a7795.c deleted file mode 100644 index c2c5e48aaf..0000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7795.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2016 Nobuhiro Iwamatsu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -static struct mm_region r8a7795_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7795_mem_map; diff --git a/arch/arm/mach-rmobile/memmap-r8a7796.c b/arch/arm/mach-rmobile/memmap-r8a7796.c deleted file mode 100644 index 648743d51e..0000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7796.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2017 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -static struct mm_region r8a7796_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7796_mem_map; From f2b2bd66602ea035263d2ac12241183dd099c361 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 00:05:08 +0100 Subject: [PATCH 20/34] ARM: rmobile: Unify R8A7795 and R8A7796 in rmobile Makefile Since both R8A7795 and R8A7796 now use the same files, unify the Makefile entry to CONFIG_RCAR_GEN3. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 440604cce5..3949378806 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o -obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o +obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o From bee22aa8227100645b77ef75dfbd70c1b70666ae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 00:01:32 +0100 Subject: [PATCH 21/34] ARM: rmobile: Drop CPU type ifdef from salvator-x We can now use rmobile_get_cpu_type() to check the CPU ID rather than using a macro, make it so. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/salvator-x/salvator-x.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index debd1db721..1b8ae574c5 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -79,17 +79,19 @@ int board_early_init_f(void) int board_init(void) { + u32 cpu_type = rmobile_get_cpu_type(); + /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; -#if defined(CONFIG_R8A7795) - /* GSX: force power and clock supply */ - writel(0x0000001F, SYSC_PWRONCR2); - while (readl(SYSC_PWRSR2) != 0x000003E0) - mdelay(20); + if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) { + /* GSX: force power and clock supply */ + writel(0x0000001F, SYSC_PWRONCR2); + while (readl(SYSC_PWRSR2) != 0x000003E0) + mdelay(20); - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); -#endif + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); + } /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); From ef5f1979ffd85bfbf5b32faf823e2f1129208c1e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 05:45:46 +0100 Subject: [PATCH 22/34] ARM: rmobile: Zap checkboard on Gen3 The checkboard() function showing hard-coded board model for which the U-Boot was built is superseded on Gen3 by show_board_info() displaying the Model from device tree. Add small ifdef to stop compiling the function into U-Boot. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c index d91bc26703..bdb353062f 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-rmobile/board.c @@ -8,8 +8,10 @@ #include #include +#ifndef CONFIG_RCAR_GEN3 int checkboard(void) { printf("Board: %s\n", sysinfo.board_string); return 0; } +#endif From 1bb8ea3beb2b51be25cad85c7f49d0220bf4e9cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 05:48:30 +0100 Subject: [PATCH 23/34] ARM: rmobile: Zap rmobile_sysinfo on Gen3 Since checkboard() is gone, rmobile_sysinfo is also pointless on Gen3. Furthermore, nuke ad-hoc CONFIG_RCAR_BOARD_STRING which is also dead. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/salvator-x/salvator-x.c | 4 ---- board/renesas/ulcb/ulcb.c | 4 ---- include/configs/salvator-x.h | 2 -- include/configs/ulcb.h | 2 -- 4 files changed, 12 deletions(-) diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 1b8ae574c5..f21360c4c5 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -142,10 +142,6 @@ int dram_init_banksize(void) return 0; } -const struct rmobile_sysinfo sysinfo = { - CONFIG_RCAR_BOARD_STRING -}; - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index ca1b71975b..000dd51ab7 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -129,7 +129,3 @@ int dram_init_banksize(void) #endif return 0; } - -const struct rmobile_sysinfo sysinfo = { - CONFIG_RCAR_BOARD_STRING -}; diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 605c9c64b8..805c0c254e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -12,8 +12,6 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "Salvator-X" - #include "rcar-gen3-common.h" /* SCIF */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 8f989bbce5..001756c8e4 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -12,8 +12,6 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "ULCB" - #include "rcar-gen3-common.h" /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ From aee24b594a0fd9814b7819b565a35c84b4710b70 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 05:37:53 +0100 Subject: [PATCH 24/34] ARM: rmobile: Configure DRAM sizes from DT Drop the ad-hoc DRAM configuration with macros and just decode the DRAM configuration from device tree instead. This makes it far cleaner and easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- board/renesas/salvator-x/salvator-x.c | 28 ++++----------------------- board/renesas/ulcb/ulcb.c | 28 ++++----------------------- 2 files changed, 8 insertions(+), 48 deletions(-) diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index f21360c4c5..882a35c140 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -109,36 +109,16 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->ram_size += PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->ram_size += PHYS_SDRAM_4_SIZE; -#endif + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -#endif + fdtdec_setup_memory_banksize(); + return 0; } diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 000dd51ab7..ed891c833c 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -97,35 +97,15 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->ram_size += PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->ram_size += PHYS_SDRAM_4_SIZE; -#endif + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -#endif + fdtdec_setup_memory_banksize(); + return 0; } From 8c1b52f4b00b877567e9a9ccb56f74723eb0844f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 06:01:20 +0100 Subject: [PATCH 25/34] ARM: rmobile: Zap ad-hoc DRAM configuration macros These macros are no longer needed since the DRAM configuration is parsed from the DT. Drop them all. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/rcar-gen3-common.h | 24 +++--------------------- include/configs/ulcb.h | 8 -------- 2 files changed, 3 insertions(+), 29 deletions(-) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index dd6863e64e..2815e241de 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -48,30 +48,12 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 -#if defined(CONFIG_R8A7795) #define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x500000000 -#define PHYS_SDRAM_2_SIZE 0x40000000u -#define PHYS_SDRAM_3 0x600000000 -#define PHYS_SDRAM_3_SIZE 0x40000000u -#define PHYS_SDRAM_4 0x700000000 -#define PHYS_SDRAM_4_SIZE 0x40000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#elif defined(CONFIG_R8A7796) -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x0600000000 -#define PHYS_SDRAM_2_SIZE 0x80000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#endif +#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_LOAD_ADDR 0x48080000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE +#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 001756c8e4..d6092d5096 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,14 +14,6 @@ #include "rcar-gen3-common.h" -/* M3 ULCB has 2 banks, each with 1 GiB of RAM */ -#if defined(CONFIG_R8A7796) -#undef PHYS_SDRAM_1_SIZE -#undef PHYS_SDRAM_2_SIZE -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2_SIZE 0x40000000u -#endif - /* SCIF */ #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 From 61e2ff8e822d73e152cacf60130b86f88eccee6c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 06:38:12 +0100 Subject: [PATCH 26/34] ARM: rmobile: Clean up ad-hoc clock macros As we have a proper clock framework driver, these macros are not needed, so drop them and clean up the whitelist. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/salvator-x.h | 13 +------------ include/configs/ulcb.h | 13 +------------ scripts/config_whitelist.txt | 3 --- 3 files changed, 2 insertions(+), 27 deletions(-) diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 805c0c254e..740e0517be 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -17,7 +17,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ /* [A] Hyper Flash */ /* use to RPC(SPI Multi I/O Bus Controller) */ @@ -28,14 +27,7 @@ /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ @@ -52,9 +44,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index d6092d5096..c613c733f5 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -17,7 +17,6 @@ /* SCIF */ #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ /* [A] Hyper Flash */ /* use to RPC(SPI Multi I/O Bus Controller) */ @@ -28,14 +27,7 @@ /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ @@ -65,9 +57,6 @@ unsigned char ulcb_softspi_read(void); #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4ce87484c3..c2fe81e552 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -346,7 +346,6 @@ CONFIG_CPU_SH7785 CONFIG_CPU_SH_TYPE_R CONFIG_CPU_TYPE_R CONFIG_CPU_VR41XX -CONFIG_CP_CLK_FREQ CONFIG_CQSPI_DECODER CONFIG_CQSPI_REF_CLK CONFIG_CRC32 @@ -1886,8 +1885,6 @@ CONFIG_RUN_FROM_DDR1 CONFIG_RUN_FROM_IRAM_ONLY CONFIG_RX_DESCR_NUM CONFIG_S32V234 -CONFIG_S3D2_CLK_FREQ -CONFIG_S3D4_CLK_FREQ CONFIG_S5P CONFIG_S5PC100 CONFIG_S5PC110 From 76080d0c1568b78dc1949aa24246f1d8cdfeeb49 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Nov 2017 08:37:23 +0100 Subject: [PATCH 27/34] ARM: rmobile: Remove SCIF configs Since we use DM and DT, these SCIF configuration options are useless. Remove them. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/salvator-x.h | 7 ------- include/configs/ulcb.h | 7 ------- 2 files changed, 14 deletions(-) diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 740e0517be..f59adb0aac 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -14,13 +14,6 @@ #include "rcar-gen3-common.h" -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index c613c733f5..29f37c17d1 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,13 +14,6 @@ #include "rcar-gen3-common.h" -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI From aff151e5b278cbe12f4383e42d271b982bdc60d7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Nov 2017 21:49:48 +0100 Subject: [PATCH 28/34] ARM: rmobile: Convert PRR to DM and OF control Implement DM driver for the Renesas PRR into RCar cpu info and convert all users with DM and OF enabled to this new driver. This means all of the boards with DM and OF enabled can fetch PRR address from DT, which is useful on ie. V3M which has different PRR address than the rest of Gen3 SoCs. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/cpu_info-rcar.c | 61 +++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index c373eef73d..b443611cbb 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -8,19 +8,20 @@ #include #include -#define PRR 0xFF000044 #define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 #define R8A7796_REV_1_1 0x5210 +static u32 rmobile_get_prr(void); + u32 rmobile_get_cpu_type(void) { - return (readl(PRR) & 0x00007F00) >> 8; + return (rmobile_get_prr() & 0x00007F00) >> 8; } u32 rmobile_get_cpu_rev_integer(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; @@ -30,10 +31,62 @@ u32 rmobile_get_cpu_rev_integer(void) u32 rmobile_get_cpu_rev_fraction(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; else return prr & 0x0000000F; } + +#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON) +static u32 rmobile_get_prr(void) +{ + /* + * On RCar/RMobile Gen2 and older systems, the PRR is always + * located at the address below. On newer systems, the PRR + * may be located at different address, but that information + * is obtained from DT. This code will be removed when all + * of the older systems get converted to DM and OF control. + */ + return readl(0xFF000044); +} +#else + +#include +#include +#include + +struct renesas_prr_priv { + fdt_addr_t regs; +}; + +enum { + PRR_RCAR, +}; + +static u32 rmobile_get_prr(void) +{ + struct regmap *map; + + map = syscon_get_regmap_by_driver_data(PRR_RCAR); + if (!map) { + printf("PRR regmap failed!\n"); + hang(); + } + + return readl(map->base); +} + +static const struct udevice_id renesas_prr_ids[] = { + { .compatible = "renesas,prr", .data = PRR_RCAR }, + { } +}; + +U_BOOT_DRIVER(renesas_prr) = { + .name = "renesas_prr", + .id = UCLASS_SYSCON, + .of_match = renesas_prr_ids, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif From d7f0b85269f4ca08ade437cb32d53eb4d7539226 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Nov 2017 21:56:01 +0100 Subject: [PATCH 29/34] ARM: rmobile: Use PRR driver on all Gen3 boards Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is needed very early and turn on the CONFIG_SYSCON to allow the PRR driver to bind as a syscon uclass. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a7795.dtsi | 1 + arch/arm/dts/r8a7796.dtsi | 1 + configs/r8a7795_salvator-x_defconfig | 2 ++ configs/r8a7795_ulcb_defconfig | 2 ++ configs/r8a7796_salvator-x_defconfig | 2 ++ configs/r8a7796_ulcb_defconfig | 2 ++ 6 files changed, 10 insertions(+) diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index 615b652131..405ae9c781 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -394,6 +394,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 9e6a5f231e..6a6bfd4e19 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -377,6 +377,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 00d534b79b..8c7ad6b356 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 4c57ffc013..4eaedfc3cc 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 4a36469f62..849c668a5f 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 989edf66f9..8fa49c2dd9 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y From 02e80f0c11e4ae0ff6672df30f8520b393f269ad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Nov 2017 07:36:22 +0100 Subject: [PATCH 30/34] ARM: rmobile: Migrate boards to RCar IIC drivers Stop using the old ad-hoc SH I2C driver and use the new RCar IIC driver instead. The SH I2C driver should be deprecated and removed eventually. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/ulcb.dtsi | 4 ++++ configs/r8a7795_salvator-x_defconfig | 3 +++ configs/r8a7795_ulcb_defconfig | 3 +++ configs/r8a7796_salvator-x_defconfig | 3 +++ configs/r8a7796_ulcb_defconfig | 3 +++ include/configs/salvator-x.h | 12 ------------ include/configs/ulcb.h | 12 ------------ 7 files changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index b0ad11897c..9b9d70ea27 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -190,6 +190,10 @@ }; }; +&i2c_dvfs { + status = "okay"; +}; + &ohci1 { status = "okay"; }; diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 8c7ad6b356..5a09473efa 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -31,6 +32,8 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 4eaedfc3cc..75316d7621 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -31,6 +32,8 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 849c668a5f..9055c291bb 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -32,6 +33,8 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 8fa49c2dd9..9a55ba9597 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -32,6 +33,8 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index f59adb0aac..33624e6c4e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -25,18 +25,6 @@ /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 29f37c17d1..b330ea703a 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -38,18 +38,6 @@ void ulcb_softspi_scl(int); unsigned char ulcb_softspi_read(void); #endif -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 From 2489bb54a51e9e74a52231de04072628a455025c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 17:42:16 +0100 Subject: [PATCH 31/34] pinctrl: rmobile: Add support for setting single pins Add code to handle single pins nodes from DT in addition to already support groups handling. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/pfc.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 1675485d66..b7b74985a3 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -448,6 +448,22 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } +static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, + unsigned func_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; + int idx = sh_pfc_get_pin_index(pfc, pin->pin); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); +} + static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, unsigned func_selector) { @@ -642,6 +658,19 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, return 0; } +static int sh_pfc_pinconf_pin_set(struct udevice *dev, + unsigned int pin_selector, + unsigned int param, unsigned int arg) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; + + sh_pfc_pinconf_set(pmx, pin->pin, param, arg); + + return 0; +} static int sh_pfc_pinconf_group_set(struct udevice *dev, unsigned int group_selector, @@ -671,8 +700,10 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCONF) .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), .pinconf_params = sh_pfc_pinconf_params, + .pinconf_set = sh_pfc_pinconf_pin_set, .pinconf_group_set = sh_pfc_pinconf_group_set, #endif + .pinmux_set = sh_pfc_pinctrl_pin_set, .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, }; From f6e545a73f8842400f76de4b185b31bea782ff85 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 18:07:29 +0100 Subject: [PATCH 32/34] pfc: rmobile: Add hook to configure pin as GPIO Add hook into the PFC driver to allow the GPIO driver to toggle GPSR registers into GPIO mode when GPIO is requested. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/pfc.c | 29 +++++++++++++++++++++++++++++ drivers/pinctrl/renesas/sh_pfc.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index b7b74985a3..6670072504 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -448,6 +448,35 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + struct sh_pfc_pin_config *cfg; + const struct sh_pfc_pin *pin = NULL; + int i, idx; + + for (i = 1; i < pfc->info->nr_pins; i++) { + if (priv->pfc.info->pins[i].pin != pin_selector) + continue; + + pin = &priv->pfc.info->pins[i]; + break; + } + + if (!pin) + return -EINVAL; + + idx = sh_pfc_get_pin_index(pfc, pin->pin); + cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); +} + static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, unsigned func_selector) { diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 7aef2d360b..f82417b1a3 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -243,6 +243,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) const struct sh_pfc_bias_info * sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, unsigned int num, unsigned int pin); +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector); extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; From 52c8034bb426c69e96474aed8cbd18269c61ba78 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 18:08:53 +0100 Subject: [PATCH 33/34] gpio: rmobile: Set GPIO mode in GPSR when requested When requesting a GPIO, set the PFC GPSR register to GPIO mode, otherwise the GPIO cannot work. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/gpio/gpio-rcar.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 8504dceb84..cb9f425884 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -10,6 +10,7 @@ #include #include #include +#include "../pinctrl/renesas/sh_pfc.h" #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ @@ -29,7 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; struct rcar_gpio_priv { - void __iomem *regs; + void __iomem *regs; + int pfc_offset; }; static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) @@ -113,7 +115,22 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } +static int rcar_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct rcar_gpio_priv *priv = dev_get_priv(dev); + struct udevice *pctldev; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev); + if (ret) + return ret; + + return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset); +} + static const struct dm_gpio_ops rcar_gpio_ops = { + .request = rcar_gpio_request, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, @@ -135,6 +152,7 @@ static int rcar_gpio_probe(struct udevice *dev) ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", NULL, 3, 0, &args); + priv->pfc_offset = ret == 0 ? args.args[1] : -1; uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; ret = clk_get_by_index(dev, 0, &clk); From ab61e175713a0400c6ece6348e8f655998cf574d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Nov 2017 20:32:44 +0100 Subject: [PATCH 34/34] ARM: rmobile: Rework the ULCB CPLD driver Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/ulcb.dtsi | 9 ++ board/renesas/ulcb/cpld.c | 208 ++++++++++++++++++--------------- configs/r8a7795_ulcb_defconfig | 1 + configs/r8a7796_ulcb_defconfig | 1 + include/configs/ulcb.h | 13 --- 5 files changed, 127 insertions(+), 105 deletions(-) diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index 9b9d70ea27..59fcf71182 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,6 +24,15 @@ stdout-path = "serial0:115200n8"; }; + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; + audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c index a1fecf18e5..50de56837e 100644 --- a/board/renesas/ulcb/cpld.c +++ b/board/renesas/ulcb/cpld.c @@ -8,14 +8,12 @@ */ #include -#include -#include #include - -#define SCLK (192 + 8) /* GPIO6 8 */ -#define SSTBZ (64 + 3) /* GPIO2 3 */ -#define MOSI (192 + 7) /* GPIO6 8 */ -#define MISO (192 + 10) /* GPIO6 10 */ +#include +#include +#include +#include +#include #define CPLD_ADDR_MODE 0x00 /* RW */ #define CPLD_ADDR_MUX 0x02 /* RW */ @@ -23,111 +21,89 @@ #define CPLD_ADDR_RESET 0x80 /* RW */ #define CPLD_ADDR_VERSION 0xFF /* R */ -static int cpld_initialized; +struct renesas_ulcb_sysreset_priv { + struct gpio_desc miso; + struct gpio_desc mosi; + struct gpio_desc sck; + struct gpio_desc sstbz; +}; -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* Always active */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* Always active */ -} - -void ulcb_softspi_sda(int set) -{ - gpio_set_value(MOSI, set); -} - -void ulcb_softspi_scl(int set) -{ - gpio_set_value(SCLK, set); -} - -unsigned char ulcb_softspi_read(void) -{ - return !!gpio_get_value(MISO); -} - -static void cpld_rw(u8 write) -{ - gpio_set_value(MOSI, write); - gpio_set_value(SSTBZ, 0); - gpio_set_value(SCLK, 1); - gpio_set_value(SCLK, 0); - gpio_set_value(SSTBZ, 1); -} - -static u32 cpld_read(u8 addr) +static u32 cpld_read(struct udevice *dev, u8 addr) { + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); u32 data = 0; + int i; - spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - cpld_rw(0); + dm_gpio_set_value(&priv->mosi, 0); /* READ */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); - spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + data |= dm_gpio_get_value(&priv->miso); /* MSB first */ + dm_gpio_set_value(&priv->sck, 0); + } - return swab32(data); + return data; } -static void cpld_write(u8 addr, u32 data) +static void cpld_write(struct udevice *dev, u8 addr, u32 data) { - data = swab32(data); + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + int i; - spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - cpld_rw(1); -} - -static void cpld_init(void) -{ - if (cpld_initialized) - return; - - /* PULL-UP on MISO line */ - setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); - - gpio_request(SCLK, NULL); - gpio_request(SSTBZ, NULL); - gpio_request(MOSI, NULL); - gpio_request(MISO, NULL); - - gpio_direction_output(SCLK, 0); - gpio_direction_output(SSTBZ, 1); - gpio_direction_output(MOSI, 0); - gpio_direction_input(MISO); - - /* Dummy read */ - cpld_read(CPLD_ADDR_VERSION); - - cpld_initialized = 1; + dm_gpio_set_value(&priv->mosi, 1); /* WRITE */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); } static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u32 addr, val; + int ret; - cpld_init(); + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_GET_DRIVER(sysreset_renesas_ulcb), + &dev); + if (ret) + return ret; if (argc == 2 && strcmp(argv[1], "info") == 0) { printf("CPLD version:\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_VERSION)); + cpld_read(dev, CPLD_ADDR_VERSION)); printf("H3 Mode setting (MD0..28):\t0x%08x\n", - cpld_read(CPLD_ADDR_MODE)); + cpld_read(dev, CPLD_ADDR_MODE)); printf("Multiplexer settings:\t\t0x%08x\n", - cpld_read(CPLD_ADDR_MUX)); + cpld_read(dev, CPLD_ADDR_MUX)); printf("DIPSW (SW6):\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_DIPSW6)); + cpld_read(dev, CPLD_ADDR_DIPSW6)); return 0; } @@ -143,10 +119,10 @@ static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (argc == 3 && strcmp(argv[1], "read") == 0) { - printf("0x%x\n", cpld_read(addr)); + printf("0x%x\n", cpld_read(dev, addr)); } else if (argc == 4 && strcmp(argv[1], "write") == 0) { val = simple_strtoul(argv[3], NULL, 16); - cpld_write(addr, val); + cpld_write(dev, addr, val); } return 0; @@ -160,8 +136,56 @@ U_BOOT_CMD( "cpld write addr val\n" ); -void reset_cpu(ulong addr) +static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type) { - cpld_init(); - cpld_write(CPLD_ADDR_RESET, 1); + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; } + +static int renesas_ulcb_sysreset_probe(struct udevice *dev) +{ + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + + if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso, + GPIOD_IS_IN)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi, + GPIOD_IS_OUT)) + return -EINVAL; + + /* PULL-UP on MISO line */ + setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); + + /* Dummy read */ + cpld_read(dev, CPLD_ADDR_VERSION); + + return 0; +} + +static struct sysreset_ops renesas_ulcb_sysreset = { + .request = renesas_ulcb_sysreset_request, +}; + +static const struct udevice_id renesas_ulcb_sysreset_ids[] = { + { .compatible = "renesas,ulcb-cpld" }, + { } +}; + +U_BOOT_DRIVER(sysreset_renesas_ulcb) = { + .name = "renesas_ulcb_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_ulcb_sysreset, + .probe = renesas_ulcb_sysreset_probe, + .of_match = renesas_ulcb_sysreset_ids, + .priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv), +}; diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 75316d7621..0959bb44c9 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -47,6 +47,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 9a55ba9597..fe0b4fc93d 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index b330ea703a..dfd6436b3c 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -25,19 +25,6 @@ /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* CPLD SPI */ -#define CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define SPI_DELAY udelay(0) -#define SPI_SDA(val) ulcb_softspi_sda(val) -#define SPI_SCL(val) ulcb_softspi_scl(val) -#define SPI_READ ulcb_softspi_read() -#ifndef __ASSEMBLY__ -void ulcb_softspi_sda(int); -void ulcb_softspi_scl(int); -unsigned char ulcb_softspi_read(void); -#endif - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1