Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net
This commit is contained in:
commit
97c8cb524c
@ -15,12 +15,12 @@
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compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
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aliases {
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spi0 = &fspi;
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eth0 = &enetc0;
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eth1 = &enetc2;
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eth2 = &mscc_felix_port0;
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eth3 = &mscc_felix_port1;
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eth4 = &mscc_felix_port2;
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eth5 = &mscc_felix_port3;
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ethernet0 = &enetc0;
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ethernet1 = &enetc2;
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ethernet2 = &mscc_felix_port0;
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ethernet3 = &mscc_felix_port1;
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ethernet4 = &mscc_felix_port2;
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ethernet5 = &mscc_felix_port3;
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};
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};
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@ -14,11 +14,11 @@
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aliases {
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console = &uart0;
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eth0 = "/eth@10002000";
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eth2 = &swp_0;
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eth3 = ð_3;
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eth4 = &dsa_eth0;
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eth5 = ð_5;
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ethernet0 = "/eth@10002000";
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ethernet2 = &swp_0;
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ethernet3 = ð_3;
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ethernet4 = &dsa_eth0;
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ethernet5 = ð_5;
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gpio1 = &gpio_a;
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gpio2 = &gpio_b;
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gpio3 = &gpio_c;
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@ -587,6 +587,14 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label)
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f2 = "-";
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f3 = env_get("board");
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f4 = ".dtb";
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if (!f1) {
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f1 = "";
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f2 = "";
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}
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if (!f3) {
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f2 = "";
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f3 = "";
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}
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}
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len = strlen(label->fdtdir);
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@ -673,6 +673,14 @@ config SNI_AVE
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This driver implements support for the Socionext AVE Ethernet
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controller, as found on the Socionext UniPhier family.
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config SNI_NETSEC
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bool "Socionext NETSEC Ethernet support"
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depends on DM_ETH && SYNQUACER_SPI
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select PHYLIB
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help
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This driver implements support for the Socionext SynQuacer NETSEC
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ethernet controller, as found on the Socionext SynQuacer family.
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source "drivers/net/mscc_eswitch/Kconfig"
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config ETHER_ON_FEC1
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@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
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obj-$(CONFIG_FSL_PFE) += pfe_eth/
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obj-y += qe/
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obj-$(CONFIG_SNI_AVE) += sni_ave.o
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obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
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obj-y += ti/
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obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
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obj-y += mscc_eswitch/
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@ -172,8 +172,6 @@ struct eqos_mtl_regs {
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
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#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
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#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
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#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
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@ -321,6 +319,7 @@ struct eqos_priv {
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void *rx_pkt;
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bool started;
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bool reg_access_ok;
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bool clk_ck_enabled;
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};
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/*
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@ -591,12 +590,13 @@ static int eqos_start_clks_stm32(struct udevice *dev)
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goto err_disable_clk_rx;
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}
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if (clk_valid(&eqos->clk_ck)) {
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if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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pr_err("clk_enable(clk_ck) failed: %d", ret);
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goto err_disable_clk_tx;
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}
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eqos->clk_ck_enabled = true;
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}
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#endif
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@ -648,8 +648,6 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_rx);
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clk_disable(&eqos->clk_master_bus);
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if (clk_valid(&eqos->clk_ck))
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clk_disable(&eqos->clk_ck);
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#endif
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debug("%s: OK\n", __func__);
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@ -1222,7 +1220,6 @@ static int eqos_start(struct udevice *dev)
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}
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/* Configure MTL */
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writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
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/* Enable Store and Forward mode for TX */
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/* Program Tx operating mode */
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@ -1236,9 +1233,7 @@ static int eqos_start(struct udevice *dev)
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/* Enable Store and Forward mode for RX, since no jumbo frame */
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setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
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EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
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EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
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EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
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EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
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/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
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val = readl(&eqos->mac_regs->hw_feature1);
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@ -1314,12 +1309,6 @@ static int eqos_start(struct udevice *dev)
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eqos->config->config_mac <<
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EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
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clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
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EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
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EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
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0x2 <<
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EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
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/* Multicast and Broadcast Queue Enable */
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setbits_le32(&eqos->mac_regs->unused_0a4,
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0x00100000);
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@ -5673,6 +5673,10 @@ static int e1000_write_hwaddr(struct eth_device *dev)
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DEBUGOUT("%s: mac=%pM\n", __func__, mac);
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if ((hw->eeprom.type == e1000_eeprom_invm) &&
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!(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
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return -ENOSYS;
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memset(current_mac, 0, 6);
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/* Read from EEPROM, not from registers, to make sure
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@ -1245,6 +1245,7 @@ struct e1000_hw {
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#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
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#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
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#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
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#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
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#define E1000_FLUDONE_ATTEMPTS 20000
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#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
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#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
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@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
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/* alloc Rx buffer from main memory */
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rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
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if (!rx_buf_pool)
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if (!rx_buf_pool) {
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free(rx_bd_ring_base);
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return -ENOMEM;
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}
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memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
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debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
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@ -314,10 +314,12 @@ read_error:
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int octeontx_smi_probe(struct udevice *dev)
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{
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int ret, subnode, cnt = 0, node = dev_ofnode(dev).of_offset;
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struct mii_dev *bus;
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struct octeontx_smi_priv *priv;
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pci_dev_t bdf = dm_pci_get_bdf(dev);
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struct octeontx_smi_priv *priv;
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struct mii_dev *bus;
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int ret, cnt = 0;
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ofnode subnode;
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u64 baseaddr;
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debug("SMI PCI device: %x\n", bdf);
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if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) {
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@ -325,14 +327,12 @@ int octeontx_smi_probe(struct udevice *dev)
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return -1;
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}
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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"cavium,thunder-8890-mdio-nexus");
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fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
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ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
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"cavium,thunder-8890-mdio");
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if (ret)
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dev_for_each_subnode(subnode, dev) {
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if (!ofnode_device_is_compatible(subnode,
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"cavium,thunder-8890-mdio"))
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continue;
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if (ofnode_read_u64(subnode, "reg", &baseaddr))
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continue;
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bus = mdio_alloc();
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priv = malloc(sizeof(*priv));
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if (!bus || !priv) {
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@ -347,9 +347,7 @@ int octeontx_smi_probe(struct udevice *dev)
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bus->priv = priv;
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priv->mode = CLAUSE22;
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priv->baseaddr = (void __iomem *)fdtdec_get_addr(gd->fdt_blob,
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subnode,
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"reg");
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priv->baseaddr = (void __iomem *)baseaddr;
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debug("mdio base addr %p\n", priv->baseaddr);
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/* use given name or generate its own unique name */
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1134
drivers/net/sni_netsec.c
Normal file
1134
drivers/net/sni_netsec.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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* The EMAC clock is either 200 or 300 MHz, so we need a divider
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* of 128 to get the MDIO frequency below the required 2.5 MHz.
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*/
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
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if (!priv->use_internal_phy)
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
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MDIO_CMD_MII_CLK_CSR_SHIFT;
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mii_cmd |= MDIO_CMD_MII_BUSY;
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@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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* The EMAC clock is either 200 or 300 MHz, so we need a divider
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* of 128 to get the MDIO frequency below the required 2.5 MHz.
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*/
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
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if (!priv->use_internal_phy)
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mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
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MDIO_CMD_MII_CLK_CSR_SHIFT;
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mii_cmd |= MDIO_CMD_MII_WRITE;
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mii_cmd |= MDIO_CMD_MII_BUSY;
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@ -69,8 +69,11 @@ void eth_set_current_to_next(void)
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/*
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* Typically this will simply return the active device.
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* In the case where the most recent active device was unset, this will attempt
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* to return the first device. If that device doesn't exist or fails to probe,
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* this function will return NULL.
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* to return the device with sequence id 0 (which can be configured by the
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* device tree). If this fails, fall back to just getting the first device.
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* The latter is non-deterministic and depends on the order of the probing.
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* If that device doesn't exist or fails to probe, this function will return
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* NULL.
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*/
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struct udevice *eth_get_dev(void)
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{
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@ -80,9 +83,13 @@ struct udevice *eth_get_dev(void)
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if (!uc_priv)
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return NULL;
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if (!uc_priv->current)
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eth_errno = uclass_first_device(UCLASS_ETH,
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&uc_priv->current);
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if (!uc_priv->current) {
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eth_errno = uclass_get_device_by_seq(UCLASS_ETH, 0,
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&uc_priv->current);
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if (eth_errno)
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eth_errno = uclass_first_device(UCLASS_ETH,
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&uc_priv->current);
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}
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return uc_priv->current;
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}
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@ -598,8 +605,8 @@ static int eth_pre_remove(struct udevice *dev)
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return 0;
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}
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UCLASS_DRIVER(eth) = {
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.name = "eth",
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UCLASS_DRIVER(ethernet) = {
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.name = "ethernet",
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.id = UCLASS_ETH,
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.post_bind = eth_post_bind,
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.pre_unbind = eth_pre_unbind,
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@ -213,7 +213,7 @@ static int dm_test_ofnode_read_aliases(struct unit_test_state *uts)
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ofnode node;
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int size;
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node = ofnode_get_aliases_node("eth3");
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node = ofnode_get_aliases_node("ethernet3");
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ut_assert(ofnode_valid(node));
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ut_asserteq_str("sbe5", ofnode_get_name(node));
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@ -183,7 +183,7 @@ static int dm_test_alias_highest_id(struct unit_test_state *uts)
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{
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int ret;
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ret = dev_read_alias_highest_id("eth");
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ret = dev_read_alias_highest_id("ethernet");
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ut_asserteq(5, ret);
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ret = dev_read_alias_highest_id("gpio");
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