Added edge conditioning register (ecr) for PPC405GPr.
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@ -236,6 +236,7 @@
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#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
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#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
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#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
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#define ecr (0xAA) /* edge conditioning register (405GPr) */
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/* Bit definitions */
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#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
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