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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2017-09-18 15:44:57 -04:00
commit 975f97b431
45 changed files with 851 additions and 101 deletions
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1
arch/arm/dts/Makefile
View File

@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
rk3368-sheep.dtb \

327
arch/arm/dts/rk3288-vyasa.dts Normal file
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@ -0,0 +1,327 @@
/*
* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3288.dtsi"
/ {
model = "Amarula Vyasa-RK3288";
compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
chosen {
stdout-path = &uart2;
};
memory {
device_type = "memory";
reg = <0 0x80000000>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
/* Add a dummy value to cause of-platdata think this is bytes */
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int &global_pwroff>;
wakeup-source;
rockchip,system-power-controller;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
regulators {
vdd_cpu: vdd_log: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_log";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_tp: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_codec: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_codec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_gps: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_gps";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_lcd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc33_sd: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_sd";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_lan: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_lan";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};
};
&sdmmc {
u-boot,dm-pre-reloc;
status = "okay";
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};
&wdt {
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

10
arch/arm/dts/rk3368-lion-u-boot.dtsi
View File

@ -13,6 +13,7 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &emmc, &sdmmc;
tick-timer = "/timer@ff810000";
};
};
@ -70,24 +71,25 @@
};
&emmc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&sdmmc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&spi1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
spiflash: w25q32dw@0 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
};
&timer0 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
status = "okay";
};

12
arch/arm/dts/rk3399-puma.dtsi
View File

@ -89,6 +89,17 @@
};
};
usbhub_enable: usbhub_enable {
compatible = "regulator-fixed";
regulator-name = "usbhub_enable";
enable-active-low;
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
@ -514,7 +525,6 @@
};
&dwc3_typec1 {
rockchip,vbus-gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
};

22
arch/arm/dts/rv1108-evb.dts
View File

@ -20,6 +20,15 @@
chosen {
stdout-path = "serial2:1500000n8";
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&gmac {
@ -52,3 +61,16 @@
&uart2 {
status = "okay";
};
&usb20_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci {
status = "okay";
};

24
arch/arm/dts/rv1108.dtsi
View File

@ -175,6 +175,30 @@
status = "disabled";
};
usb_host_ehci: usb@30140000 {
compatible = "generic-ehci";
reg = <0x30140000 0x20000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usb_host_ohci: usb@30160000 {
compatible = "generic-ohci";
reg = <0x30160000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usb20_otg: usb@30180000 {
compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
"snps,dwc2";
reg = <0x30180000 0x40000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
hnp-srp-disable;
dr_mode = "otg";
status = "disabled";
};
sfc: sfc@301c0000 {
compatible = "rockchip,sfc";
reg = <0x301c0000 0x200>;

32
arch/arm/include/asm/arch-rockchip/grf_rk322x.h
View File

@ -54,6 +54,32 @@ struct rk322x_grf {
unsigned int os_reg[8];
unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
unsigned int ddrc_stat;
unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
unsigned int sig_detect_con[2];
unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
unsigned int sig_detect_status[2];
unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
unsigned int sig_detect_clr[2];
unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
unsigned int emmc_det;
unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
unsigned int host0_con[3];
unsigned int reserved15;
unsigned int host1_con[3];
unsigned int reserved16;
unsigned int host2_con[3];
unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
unsigned int usbphy0_con[27];
unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
unsigned int usbphy1_con[27];
unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
unsigned int otg_con0;
unsigned int uoc_status0;
unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
unsigned int mac_con[2];
unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
unsigned int macphy_con[4];
unsigned int macphy_status;
};
check_member(rk322x_grf, ddrc_stat, 0x604);
@ -516,4 +542,10 @@ enum {
CON_IOMUX_PWM0SEL_SHIFT = 0,
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
/* GRF_MACPHY_CON0 */
enum {
MACPHY_CFG_ENABLE_SHIFT = 0,
MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,
};
#endif

23
arch/arm/mach-rockchip/rk322x-board.c
View File

@ -7,6 +7,7 @@
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
@ -67,6 +68,14 @@ int board_init(void)
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
/*
* The integrated macphy is enabled by default, disable it
* for saving power consuming.
*/
rk_clrsetreg(&grf->macphy_con[0],
MACPHY_CFG_ENABLE_MASK,
0 << MACPHY_CFG_ENABLE_SHIFT);
return 0;
}
@ -136,3 +145,17 @@ int board_usb_cleanup(int index, enum usb_init_type init)
return 0;
}
#endif
#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
int fb_set_reboot_flag(void)
{
struct rk322x_grf *grf;
printf("Setting reboot to fastboot flag ...\n");
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
/* Set boot mode to fastboot */
writel(BOOT_FASTBOOT, &grf->os_reg[0]);
return 0;
}
#endif

11
arch/arm/mach-rockchip/rk3288/Kconfig
View File

@ -84,6 +84,15 @@ config TARGET_POPMETAL_RK3288
2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
GPIOs and display interface.
config TARGET_VYASA_RK3288
bool "Vyasa-RK3288"
select BOARD_LATE_INIT
help
Vyasa is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
provide access to display pins, I2C, SPI, UART and GPIOs.
config TARGET_ROCK2
bool "Radxa Rock 2"
select BOARD_LATE_INIT
@ -129,6 +138,8 @@ config SPL_LIBGENERIC_SUPPORT
config SPL_SERIAL_SUPPORT
default y
source "board/amarula/vyasa-rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"
source "board/firefly/firefly-rk3288/Kconfig"

34
arch/arm/mach-rockchip/rk3399-board-spl.c
View File

@ -5,19 +5,17 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/sdram.h>
#include <asm/arch/timer.h>
#include <asm/io.h>
#include <debug_uart.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <power/regulator.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
@ -53,7 +51,6 @@ void secure_timer_init(void)
void board_debug_uart_init(void)
{
#include <asm/arch/grf_rk3399.h>
#define GRF_BASE 0xff770000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
@ -80,13 +77,12 @@ void board_debug_uart_init(void)
#endif
}
#define GRF_EMMCCORE_CON11 0xff77f02c
#define SGRF_DDR_RGN_CON16 0xff330040
#define SGRF_SLV_SECURE_CON4 0xff33e3d0
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
int ret;
#define EARLY_UART
@ -103,9 +99,6 @@ void board_init_f(ulong dummy)
printascii("U-Boot SPL board init");
#endif
/* Emmc clock generator: disable the clock multipilier */
rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
@ -121,8 +114,13 @@ void board_init_f(ulong dummy)
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
secure_timer_init();

2
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
View File

@ -1115,7 +1115,7 @@ static int conv_of_platdata(struct udevice *dev)
int ret;
ret = regmap_init_mem_platdata(dev, dtplat->reg,
ARRAY_SIZE(dtplat->reg) / 4,
ARRAY_SIZE(dtplat->reg) / 2,
&plat->map);
if (ret)
return ret;

12
board/amarula/vyasa-rk3288/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_VYASA_RK3288
config SYS_BOARD
default "vyasa-rk3288"
config SYS_VENDOR
default "amarula"
config SYS_CONFIG_NAME
default "vyasa-rk3288"
endif

6
board/amarula/vyasa-rk3288/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
VYASA RK3288
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/amarula/vyasa-rk3288
F: include/configs/vyasa-rk3288.h
F: configs/vyasa-rk3288_defconfig

7
board/amarula/vyasa-rk3288/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# Copyright (C) 2017 Amarula Solutions
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += vyasa-rk3288.o

7
board/amarula/vyasa-rk3288/vyasa-rk3288.c Normal file
View File

@ -0,0 +1,7 @@
/*
* Copyright (C) 2017 Amarula Solutions
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>

24
board/theobroma-systems/lion_rk3368/README
View File

@ -26,12 +26,32 @@ Build the full U-Boot and a FIT image including the ATF
> make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
Write to a SD-card
==================
Flash the image
===============
Copy the SPL to offset 32k and the FIT image containing the payloads
(U-Boot proper, ATF, devicetree) to offset 256k card.
SD-Card
-------
> dd if=spl-3368.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
eMMC
----
rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
help of the Rockchip loader binary.
> git clone https://github.com/rockchip-linux/rkdeveloptool
> cd rkdeveloptool
> autoreconf -i && && ./configure && make
> git clone https://github.com/rockchip-linux/rkbin.git
> ./rkdeveloptool db rkbin/rk33/rk3368_loader_v2.00.256.bin
> ./rkdeveloptool wl 64 ../spl.img
> ./rkdeveloptool wl 512 ../u-boot.itb
If everything went according to plan, you should see the following
output on UART0:

51
board/theobroma-systems/puma_rk3399/README
View File

@ -55,18 +55,53 @@ Compile the U-Boot
Package the image
=================
> tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img
> make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
Creating a SPL image for SD-Card/eMMC
> tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
Creating a SPL image for SPI-NOR
> tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
> make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
Flash the image
===============
Copy the SPL to offset 32k and the FIT image containing the payloads
(U-Boot proper, ATF, M0 Firmware, devicetree) to offset 256k on a SD
card.
Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
image to offset 256k card.
> dd if=spl.img of=/dev/sdb seek=64
SD-Card
-------
> dd if=spl_mmc.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
After powering up the board (with the inserted SD card), you should see
a U-Boot console on UART0 (115200n8).
eMMC
----
rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
help of the Rockchip loader binary.
> git clone https://github.com/rockchip-linux/rkdeveloptool
> cd rkdeveloptool
> autoreconf -i && ./configure && make
> git clone https://github.com/rockchip-linux/rkbin.git
> ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
> ./rkdeveloptool wl 64 ../spl_mmc.img
> ./rkdeveloptool wl 512 ../u-boot.itb
NOR-Flash
---------
Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
we assume you have a SD-Card with a partition containing the required files
ready.
> load mmc 1:1 ${kernel_addr_r} spl_nor.img
> sf probe
> sf erase 0 +$filesize
> sf write $kernel_addr_r 0 ${filesize}
> load mmc 1:1 ${kernel_addr_r} u-boot.itb
> sf erase 0x40000 +$filesize
> sf write $kernel_addr_r 0x40000 ${filesize}
Reboot the system and you should see a U-Boot console on UART0 (115200n8).

2
board/theobroma-systems/puma_rk3399/puma-rk3399.c
View File

@ -107,7 +107,7 @@ static void setup_serial(void)
u8 low[cpuid_length/2], high[cpuid_length/2];
char cpuid_str[cpuid_length * 2 + 1];
u64 serialno;
char serialno_str[16];
char serialno_str[17];
/* retrieve the device */
ret = uclass_get_device_by_driver(UCLASS_MISC,

2
common/Makefile
View File

@ -63,7 +63,7 @@ obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o
endif # !CONFIG_SPL_BUILD
obj-$(CONFIG_$(SPL_)BOOTSTAGE) += bootstage.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o

21
configs/evb-rv1108_defconfig
View File

@ -5,8 +5,16 @@ CONFIG_TARGET_EVB_RV1108=y
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_CMD_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x62000000
CONFIG_FASTBOOT_BUF_SIZE=0x08000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@ -26,6 +34,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RV1108=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_BAUDRATE=1500000
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
@ -33,4 +42,16 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Rockchip"
CONFIG_G_DNL_VENDOR_NUM=0x2207
CONFIG_G_DNL_PRODUCT_NUM=0x110a
CONFIG_ERRNO_STR=y

7
configs/lion-rk3368_defconfig
View File

@ -19,6 +19,11 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its"
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_SPL=y
@ -37,10 +42,12 @@ CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y

1
configs/puma-rk3399_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y

2
configs/sheep-rk3368_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_SHEEP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
@ -14,6 +15,7 @@ CONFIG_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000

63
configs/vyasa-rk3288_defconfig Normal file
View File

@ -0,0 +1,63 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_VYASA_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa"
CONFIG_DEBUG_UART=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SPL_SIMPLE_BUS is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y

2
drivers/clk/rockchip/clk_rk3368.c
View File

@ -485,7 +485,7 @@ static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;

19
drivers/clk/rockchip/clk_rk3399.c
View File

@ -950,9 +950,24 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
return ret;
}
static int rk3399_clk_enable(struct clk *clk)
{
switch (clk->id) {
case HCLK_HOST0:
case HCLK_HOST0_ARB:
case HCLK_HOST1:
case HCLK_HOST1_ARB:
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
}
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
.enable = rk3399_clk_enable,
};
static int rk3399_clk_probe(struct udevice *dev)
@ -975,7 +990,7 @@ static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3399_cru *)devfdt_get_addr(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
}
@ -1159,7 +1174,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
priv->pmucru = (struct rk3399_pmucru *)devfdt_get_addr(dev);
priv->pmucru = dev_read_addr_ptr(dev);
#endif
return 0;
}

7
drivers/core/read.c
View File

@ -57,6 +57,13 @@ fdt_addr_t dev_read_addr(struct udevice *dev)
return dev_read_addr_index(dev, 0);
}
void *dev_read_addr_ptr(struct udevice *dev)
{
fdt_addr_t addr = dev_read_addr(dev);
return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
}
fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property,
fdt_size_t *sizep)
{

3
drivers/gpio/rk_gpio.c
View File

@ -103,8 +103,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
char *end;
int ret;
/* This only supports RK3288 at present */
priv->regs = (struct rockchip_gpio_regs *)devfdt_get_addr(dev);
priv->regs = dev_read_addr_ptr(dev);
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
if (ret)
return ret;

2
drivers/i2c/rk_i2c.c
View File

@ -382,7 +382,7 @@ static int rockchip_i2c_probe(struct udevice *bus)
{
struct rk_i2c *priv = dev_get_priv(bus);
priv->regs = (void *)devfdt_get_addr(bus);
priv->regs = dev_read_addr_ptr(bus);
return 0;
}

2
drivers/misc/rockchip-efuse.c
View File

@ -142,7 +142,7 @@ static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
{
struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
plat->base = (void *)dev_read_addr(dev);
plat->base = dev_read_addr_ptr(dev);
return 0;
}

2
drivers/mmc/rockchip_dw_mmc.c
View File

@ -58,7 +58,7 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
struct dwmci_host *host = &priv->host;
host->name = dev->name;
host->ioaddr = (void *)devfdt_get_addr(dev);
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;

5
drivers/mmc/rockchip_sdhci.c
View File

@ -9,7 +9,6 @@
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <mapmem.h>
@ -46,7 +45,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
host->name = dev->name;
host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]);
host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
max_frequency = dtplat->max_frequency;
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
#else
@ -82,7 +81,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
host->ioaddr = devfdt_get_addr_ptr(dev);
host->ioaddr = dev_read_addr_ptr(dev);
#endif
return 0;

11
drivers/net/designware.c
View File

@ -737,16 +737,14 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
#endif
struct eth_pdata *pdata = &dw_pdata->eth_pdata;
const char *phy_mode;
const fdt32_t *cell;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
#endif
int ret = 0;
pdata->iobase = devfdt_get_addr(dev);
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
@ -754,10 +752,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
pdata->max_speed = 0;
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
#ifdef CONFIG_DM_GPIO
if (dev_read_bool(dev, "snps,reset-active-low"))

5
drivers/net/phy/micrel_ksz90x1.c
View File

@ -9,11 +9,11 @@
* (C) Copyright 2017 Adaptrum, Inc.
* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
*/
#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>
@ -120,8 +120,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
return -EOPNOTSUPP;
for (i = 0; i < ofcfg->grpsz; i++) {
val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
ofcfg->grp[i].name, -1);
val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
/* Default register value for KSZ9021 */

3
drivers/pinctrl/rockchip/pinctrl_rk3368.c
View File

@ -632,8 +632,7 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
u32 cell[3];
int ret;
ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;

2
drivers/power/pmic/rk8xx.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>

11
drivers/ram/rockchip/dmc-rk3368.c
View File

@ -893,18 +893,11 @@ static int conv_of_platdata(struct udevice *dev)
{
struct rk3368_sdram_params *plat = dev_get_platdata(dev);
struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
int ret;
plat->ddr_freq = of_plat->rockchip_ddr_frequency;
plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
plat->memory_schedule = of_plat->rockchip_memory_schedule;
ret = regmap_init_mem_platdata(dev, of_plat->reg,
ARRAY_SIZE(of_plat->reg) / 2,
&plat->map);
if (ret)
return ret;
return 0;
}
#endif
@ -933,8 +926,8 @@ static int rk3368_dmc_probe(struct udevice *dev)
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
#ifdef CONFIG_TPL_BUILD
pctl = regmap_get_range(plat->map, 0);
ddrphy = regmap_get_range(plat->map, 1);
pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);

2
drivers/spi/rk_spi.c
View File

@ -184,7 +184,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
plat->base = devfdt_get_addr(bus);
plat->base = dev_read_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {

1
drivers/sysreset/Makefile
View File

@ -13,6 +13,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
endif
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += sysreset_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o

78
drivers/timer/rockchip_timer.c
View File

@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <dm/ofnode.h>
#include <mapmem.h>
#include <asm/arch/timer.h>
#include <dt-structs.h>
@ -25,17 +26,72 @@ struct rockchip_timer_priv {
struct rk_timer *timer;
};
static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
{
struct rockchip_timer_priv *priv = dev_get_priv(dev);
uint64_t timebase_h, timebase_l;
uint64_t cntr;
timebase_l = readl(&priv->timer->timer_curr_value0);
timebase_h = readl(&priv->timer->timer_curr_value1);
timebase_l = readl(&timer->timer_curr_value0);
timebase_h = readl(&timer->timer_curr_value1);
cntr = timebase_h << 32 | timebase_l;
return cntr;
}
#if CONFIG_IS_ENABLED(BOOTSTAGE)
ulong timer_get_boot_us(void)
{
uint64_t ticks = 0;
uint32_t rate;
uint64_t us;
int ret;
ret = dm_timer_init();
if (!ret) {
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
} else if (ret == -EAGAIN) {
/* We have been called so early that the DM is not ready,... */
ofnode node = offset_to_ofnode(-1);
struct rk_timer *timer = NULL;
/*
* ... so we try to access the raw timer, if it is specified
* via the tick-timer property in /chosen.
*/
node = ofnode_get_chosen_node("tick-timer");
if (!ofnode_valid(node)) {
debug("%s: no /chosen/tick-timer\n", __func__);
return 0;
}
timer = (struct rk_timer *)ofnode_get_addr(node);
/* This timer is down-counting */
ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
if (ofnode_read_u32(node, "clock-frequency", &rate)) {
debug("%s: could not read clock-frequency\n", __func__);
return 0;
}
#endif
} else {
return 0;
}
us = (ticks * 1000) / rate;
return us;
}
#endif
static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
{
struct rockchip_timer_priv *priv = dev_get_priv(dev);
uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
/* timers are down-counting */
cntr = timebase_h << 32 | timebase_l;
*count = ~0ull - cntr;
return 0;
}
@ -45,7 +101,9 @@ static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_timer_priv *priv = dev_get_priv(dev);
priv->timer = (struct rk_timer *)devfdt_get_addr(dev);
priv->timer = dev_read_addr_ptr(dev);
if (!priv->timer)
return -ENOENT;
#endif
return 0;
@ -58,6 +116,12 @@ static int rockchip_timer_start(struct udevice *dev)
const uint32_t reload_val_l = reload_val & 0xffffffff;
const uint32_t reload_val_h = reload_val >> 32;
/* don't reinit, if the timer is already running and set up */
if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
(readl(&priv->timer->timer_load_count0) == reload_val_l) &&
(readl(&priv->timer->timer_load_count1) == reload_val_h))
return 0;
/* disable timer and reset all control */
writel(0, &priv->timer->timer_ctrl_reg);
/* write reload value */
@ -76,7 +140,7 @@ static int rockchip_timer_probe(struct udevice *dev)
struct rockchip_timer_priv *priv = dev_get_priv(dev);
struct rockchip_timer_plat *plat = dev_get_platdata(dev);
priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
uc_priv->clock_rate = plat->dtd.clock_frequency;
#endif

52
drivers/timer/timer-uclass.c
View File

@ -8,6 +8,7 @@
#include <dm.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <dm/root.h>
#include <clk.h>
#include <errno.h>
#include <timer.h>
@ -54,9 +55,10 @@ static int timer_pre_probe(struct udevice *dev)
if (IS_ERR_VALUE(ret))
return ret;
uc_priv->clock_rate = ret;
} else
uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
dev_of_offset(dev), "clock-frequency", 0);
} else {
uc_priv->clock_rate =
dev_read_u32_default(dev, "clock-frequency", 0);
}
#endif
return 0;
@ -83,37 +85,43 @@ u64 timer_conv_64(u32 count)
int notrace dm_timer_init(void)
{
__maybe_unused const void *blob = gd->fdt_blob;
struct udevice *dev = NULL;
int node = -ENOENT;
__maybe_unused ofnode node;
int ret;
if (gd->timer)
return 0;
/*
* Directly access gd->dm_root to suppress error messages, if the
* virtual root driver does not yet exist.
*/
if (gd->dm_root == NULL)
return -EAGAIN;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Check for a chosen timer to be used for tick */
node = fdtdec_get_chosen_node(blob, "tick-timer");
node = ofnode_get_chosen_node("tick-timer");
if (ofnode_valid(node) &&
uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
/*
* If the timer is not marked to be bound before
* relocation, bind it anyway.
*/
if (!lists_bind_fdt(dm_root(), node, &dev)) {
ret = device_probe(dev);
if (ret)
return ret;
}
}
#endif
if (node < 0) {
/* No chosen timer, trying first available timer */
if (!dev) {
/* Fall back to the first available timer */
ret = uclass_first_device_err(UCLASS_TIMER, &dev);
if (ret)
return ret;
} else {
if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, &dev)) {
/*
* If the timer is not marked to be bound before
* relocation, bind it anyway.
*/
if (node > 0 &&
!lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
&dev)) {
ret = device_probe(dev);
if (ret)
return ret;
}
}
}
if (dev) {

1
include/configs/rk3368_common.h
View File

@ -51,6 +51,7 @@
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif

3
include/configs/rv1108_common.h
View File

@ -28,4 +28,7 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
/* rockchip ohci host driver */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif

23
include/configs/vyasa-rk3288.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Amarula Solutions
*
* Configuration settings for Amarula Vyasa RK3288.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
#define CONFIG_SYS_MMC_ENV_DEV 1
#undef CONFIG_CMD_USB_MASS_STORAGE
#endif

15
include/dm/read.h
View File

@ -112,6 +112,16 @@ fdt_addr_t dev_read_addr_index(struct udevice *dev, int index);
*/
fdt_addr_t dev_read_addr(struct udevice *dev);
/**
* dev_read_addr_ptr() - Get the reg property of a device
* as a pointer
*
* @dev: Device to read from
*
* @return pointer or NULL if not found
*/
void *dev_read_addr_ptr(struct udevice *dev);
/**
* dev_read_addr_size() - get address and size from a device property
*
@ -417,6 +427,11 @@ static inline fdt_addr_t dev_read_addr(struct udevice *dev)
return devfdt_get_addr(dev);
}
static inline void *dev_read_addr_ptr(struct udevice *dev)
{
return devfdt_get_addr_ptr(dev);
}
static inline fdt_addr_t dev_read_addr_size(struct udevice *dev,
const char *propname,
fdt_size_t *sizep)