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Convert CONFIG_SYS_SRIO et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_SRIO1
   CONFIG_SRIO2
   CONFIG_SRIO_PCIE_BOOT_MASTER
   CONFIG_SYS_SRIO

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-16 13:10:39 -05:00
parent 3b8dfc42a2
commit 97396cc9ce
20 changed files with 61 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
README
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@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
- CONFIG_SYS_SRIO:
Chip has SRIO or not
- CONFIG_SRIO1:
Board has SRIO 1 port available
- CONFIG_SRIO2:
Board has SRIO 2 port available
- CONFIG_SRIO_PCIE_BOOT_MASTER
Board can support master function for Boot from SRIO and PCIE
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region

15
arch/powerpc/Kconfig
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@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK
bool "Lock some portion of L1 for initial ram stack"
depends on MPC83xx || MPC85xx
config SYS_SRIO
bool "Serial RapidIO support"
config SRIO1
bool "Board has SRIO 1 port available"
depends on SYS_SRIO
config SRIO2
bool "Board has SRIO 2 port available"
depends on SYS_SRIO
config SRIO_PCIE_BOOT_MASTER
bool "Board can support master function for Boot from SRIO and PCIE"
depends on SYS_SRIO
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"

2
configs/MPC8548CDS_36BIT_defconfig
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@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

2
configs/MPC8548CDS_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

2
configs/MPC8548CDS_legacy_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

4
configs/P2041RDB_NAND_defconfig
View File

@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/P2041RDB_SDCARD_defconfig
View File

@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/P2041RDB_SPIFLASH_defconfig
View File

@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/P2041RDB_defconfig
View File

@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/T2080QDS_NAND_defconfig
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@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y

4
configs/T2080QDS_SDCARD_defconfig
View File

@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y

4
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y

4
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

4
configs/T2080QDS_defconfig
View File

@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_SYS_SRIO=y
CONFIG_SRIO1=y
CONFIG_SRIO2=y
CONFIG_SRIO_PCIE_BOOT_MASTER=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y

3
include/configs/MPC8548CDS.h
View File

@ -13,9 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__

5
include/configs/P2041RDB.h
View File

@ -32,11 +32,6 @@
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#endif

2
include/configs/T102xRDB.h
View File

@ -49,8 +49,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* PCIe Boot - Master */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE

6
include/configs/T208xQDS.h
View File

@ -14,11 +14,6 @@
#include <linux/stringify.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#endif
/* High Level Configuration Options */
@ -52,7 +47,6 @@
#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)

1
include/configs/T208xRDB.h
View File

@ -47,7 +47,6 @@
#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)