Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Please pull UniPhier updates v2019.01 - import DIV_ROUND_CLOSEST_ULL macro from Linux - import improvement and fix of Denali NAND driver from Linux - add NAND 200MHz clock to clk driver - allow CONFIG_BOOTCOMMAND to run custom boot command/script - sync DT with Linux 4.20
This commit is contained in:
Tom Rini
commit
9735326fff
@ -116,6 +116,28 @@
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi1: spi@54006100 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006100 0x100>;
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interrupts = <0 216 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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@ -432,6 +454,8 @@
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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@ -446,6 +470,8 @@
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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@ -460,6 +486,8 @@
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<&mio_clk 14>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
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<&mio_rst 14>;
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phy-names = "usb";
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phys = <&usb_phy2>;
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has-transaction-translator;
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};
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@ -488,6 +516,27 @@
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-ld11-pinctrl";
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};
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usb-phy {
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compatible = "socionext,uniphier-ld11-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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};
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};
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};
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soc-glue@5f900000 {
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@ -571,7 +620,8 @@
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -145,6 +145,10 @@
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};
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};
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&usb {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -75,3 +75,7 @@
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drive-strength = <9>;
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};
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};
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&usb {
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status = "okay";
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};
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@ -224,6 +224,50 @@
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi1: spi@54006100 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006100 0x100>;
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interrupts = <0 216 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi2: spi@54006200 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006200 0x100>;
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interrupts = <0 229 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi3: spi@54006300 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006300 0x100>;
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interrupts = <0 230 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi3>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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@ -567,6 +611,50 @@
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efuse@200 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x200 0x68>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* USB cells */
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usb_rterm0: trim@54,4 {
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reg = <0x54 1>;
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bits = <4 2>;
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};
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usb_rterm1: trim@55,4 {
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reg = <0x55 1>;
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bits = <4 2>;
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};
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usb_rterm2: trim@58,4 {
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reg = <0x58 1>;
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bits = <4 2>;
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};
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usb_rterm3: trim@59,4 {
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reg = <0x59 1>;
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bits = <4 2>;
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};
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usb_sel_t0: trim@54,0 {
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reg = <0x54 1>;
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bits = <0 4>;
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};
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usb_sel_t1: trim@55,0 {
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reg = <0x55 1>;
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bits = <0 4>;
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};
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usb_sel_t2: trim@58,0 {
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reg = <0x58 1>;
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bits = <0 4>;
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};
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usb_sel_t3: trim@59,0 {
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reg = <0x59 1>;
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bits = <0 4>;
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};
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usb_hs_i0: trim@56,0 {
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reg = <0x56 1>;
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bits = <0 4>;
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};
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usb_hs_i2: trim@5a,0 {
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reg = <0x5a 1>;
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bits = <0 4>;
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};
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};
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};
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@ -634,6 +722,157 @@
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};
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};
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_usb: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host";
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interrupts = <0 134 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
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<&pinctrl_usb2>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
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resets = <&usb_rst 15>;
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phys = <&usb_hsphy0>, <&usb_hsphy1>,
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<&usb_hsphy2>, <&usb_hsphy3>,
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<&usb_ssphy0>, <&usb_ssphy1>;
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dr_mode = "host";
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};
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus0: regulator@100 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus1: regulator@110 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus2: regulator@120 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x120 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus3: regulator@130 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x130 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
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<&usb_hs_i0>;
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};
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usb_hsphy1: hs-phy@210 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus1>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
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<&usb_hs_i0>;
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||||
};
|
||||
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usb_hsphy2: hs-phy@220 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x220 0x10>;
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||||
#phy-cells = <0>;
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||||
clock-names = "link", "phy";
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||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
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||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb_vbus2>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_hsphy3: hs-phy@230 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x230 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb_vbus3>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb_vbus0>;
|
||||
};
|
||||
|
||||
usb_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 19>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 19>;
|
||||
vbus-supply = <&usb_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb: usb@65b00000 {
|
||||
compatible = "socionext,uniphier-ld20-dwc3";
|
||||
reg = <0x65b00000 0x1000>;
|
||||
@ -660,7 +899,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -63,6 +63,17 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -381,7 +392,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -131,6 +131,26 @@
|
||||
function = "sd1";
|
||||
};
|
||||
|
||||
pinctrl_spi0: spi0 {
|
||||
groups = "spi0";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
pinctrl_spi1: spi1 {
|
||||
groups = "spi1";
|
||||
function = "spi1";
|
||||
};
|
||||
|
||||
pinctrl_spi2: spi2 {
|
||||
groups = "spi2";
|
||||
function = "spi2";
|
||||
};
|
||||
|
||||
pinctrl_spi3: spi3 {
|
||||
groups = "spi3";
|
||||
function = "spi3";
|
||||
};
|
||||
|
||||
pinctrl_system_bus: system-bus {
|
||||
groups = "system_bus", "system_bus_cs1";
|
||||
function = "system_bus";
|
||||
|
||||
@ -73,11 +73,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -92,10 +92,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -68,11 +68,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -87,10 +87,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -71,6 +71,17 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -317,6 +328,8 @@
|
||||
<&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
phy-names = "usb";
|
||||
phys = <&usb_phy0>;
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
@ -331,6 +344,8 @@
|
||||
<&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
phy-names = "usb";
|
||||
phys = <&usb_phy1>;
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
@ -342,6 +357,34 @@
|
||||
pinctrl: pinctrl {
|
||||
compatible = "socionext,uniphier-pro4-pinctrl";
|
||||
};
|
||||
|
||||
usb-phy {
|
||||
compatible = "socionext,uniphier-pro4-usb2-phy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb_phy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <0>;
|
||||
vbus-supply = <&usb0_vbus>;
|
||||
};
|
||||
|
||||
usb_phy3: phy@3 {
|
||||
reg = <3>;
|
||||
#phy-cells = <0>;
|
||||
vbus-supply = <&usb1_vbus>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
@ -434,6 +477,60 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb0_rst 4>;
|
||||
phys = <&usb_phy2>, <&usb0_ssphy>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x100>;
|
||||
|
||||
usb0_vbus: regulator@0 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
||||
reg = <0 0x10>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_ssphy: ss-phy@10 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-ssphy";
|
||||
reg = <0x10 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
vbus-supply = <&usb0_vbus>;
|
||||
};
|
||||
|
||||
usb0_rst: reset@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb0: usb@65b00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3";
|
||||
status = "disabled";
|
||||
@ -452,6 +549,49 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb1_rst 4>;
|
||||
phys = <&usb_phy3>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x100>;
|
||||
|
||||
usb1_vbus: regulator@0 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
||||
reg = <0 0x10>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_rst: reset@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb1: usb@65d00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3";
|
||||
status = "disabled";
|
||||
@ -478,7 +618,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -156,6 +156,28 @@
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -475,7 +497,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
|
||||
|
||||
@ -167,6 +167,28 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -557,6 +579,103 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
|
||||
resets = <&usb0_rst 15>;
|
||||
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
||||
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 14>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 14>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb0: usb@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3";
|
||||
status = "disabled";
|
||||
@ -575,6 +694,91 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
|
||||
resets = <&usb1_rst 15>;
|
||||
phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 15>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 15>, <&sys_clk 21>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 15>, <&sys_rst 21>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb1: usb@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3";
|
||||
status = "disabled";
|
||||
@ -601,7 +805,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -144,6 +144,28 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
spi1: spi@54006100 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006100 0x100>;
|
||||
interrupts = <0 216 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -384,6 +406,50 @@
|
||||
efuse@200 {
|
||||
compatible = "socionext,uniphier-efuse";
|
||||
reg = <0x200 0x68>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* USB cells */
|
||||
usb_rterm0: trim@54,4 {
|
||||
reg = <0x54 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm1: trim@55,4 {
|
||||
reg = <0x55 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm2: trim@58,4 {
|
||||
reg = <0x58 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_rterm3: trim@59,4 {
|
||||
reg = <0x59 1>;
|
||||
bits = <4 2>;
|
||||
};
|
||||
usb_sel_t0: trim@54,0 {
|
||||
reg = <0x54 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t1: trim@55,0 {
|
||||
reg = <0x55 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t2: trim@58,0 {
|
||||
reg = <0x58 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_sel_t3: trim@59,0 {
|
||||
reg = <0x59 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i0: trim@56,0 {
|
||||
reg = <0x56 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
usb_hs_i2: trim@5a,0 {
|
||||
reg = <0x5a 1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -465,6 +531,109 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
||||
resets = <&usb0_rst 15>;
|
||||
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
||||
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 12>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 16>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 17>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 17>;
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 18>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 12>, <&sys_rst 18>;
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb0: usb@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3";
|
||||
status = "disabled";
|
||||
@ -483,6 +652,101 @@
|
||||
};
|
||||
};
|
||||
|
||||
_usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
|
||||
resets = <&usb1_rst 15>;
|
||||
phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
|
||||
<&usb1_ssphy0>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_vbus0: regulator@100 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x100 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_vbus1: regulator@110 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
||||
reg = <0x110 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 13>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 21>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 21>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXME: U-Boot own node */
|
||||
usb1: usb@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3";
|
||||
status = "disabled";
|
||||
@ -509,7 +773,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -63,6 +63,17 @@
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
spi: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
status = "disabled";
|
||||
reg = <0x54006000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
@ -385,7 +396,8 @@
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clocks = <&sys_clk 2>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -66,20 +66,20 @@ int board_late_init(void)
|
||||
switch (uniphier_boot_device_raw()) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
printf("eMMC Boot");
|
||||
env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd");
|
||||
env_set("bootdev", "emmc");
|
||||
break;
|
||||
case BOOT_DEVICE_NAND:
|
||||
printf("NAND Boot");
|
||||
env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd");
|
||||
env_set("bootdev", "nand");
|
||||
nand_denali_wp_disable();
|
||||
break;
|
||||
case BOOT_DEVICE_NOR:
|
||||
printf("NOR Boot");
|
||||
env_set("bootcmd", "run tftpboot; run distro_bootcmd");
|
||||
env_set("bootdev", "nor");
|
||||
break;
|
||||
case BOOT_DEVICE_USB:
|
||||
printf("USB Boot");
|
||||
env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd");
|
||||
env_set("bootdev", "usb");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown");
|
||||
|
||||
@ -9,6 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
|
||||
CONFIG_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
|
||||
CONFIG_LOGLEVEL=6
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
|
||||
@ -8,6 +8,7 @@ CONFIG_SPL=y
|
||||
CONFIG_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
|
||||
CONFIG_LOGLEVEL=6
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
|
||||
@ -7,6 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y
|
||||
CONFIG_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
|
||||
CONFIG_LOGLEVEL=6
|
||||
CONFIG_CMD_CONFIG=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
|
||||
@ -6,13 +6,12 @@
|
||||
|
||||
#include "clk-uniphier.h"
|
||||
|
||||
/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
|
||||
#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
|
||||
UNIPHIER_CLK_RATE(128, 200000000), \
|
||||
UNIPHIER_CLK_RATE(128, 50000000), \
|
||||
UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
|
||||
|
||||
#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
|
||||
UNIPHIER_CLK_RATE(128, 200000000), \
|
||||
UNIPHIER_CLK_RATE(128, 50000000), \
|
||||
UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
|
||||
|
||||
const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
||||
@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
||||
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
|
||||
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
|
||||
UNIPHIER_LD4_SYS_CLK_NAND(2),
|
||||
UNIPHIER_CLK_RATE(3, 200000000),
|
||||
UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
|
||||
@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
||||
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
|
||||
UNIPHIER_LD11_SYS_CLK_NAND(2),
|
||||
UNIPHIER_CLK_RATE(3, 200000000),
|
||||
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
|
||||
@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
||||
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
|
||||
UNIPHIER_LD11_SYS_CLK_NAND(2),
|
||||
UNIPHIER_CLK_RATE(3, 200000000),
|
||||
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
|
||||
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
|
||||
|
||||
@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr)
|
||||
#define DENALI_INVALID_BANK -1
|
||||
#define DENALI_NR_BANKS 4
|
||||
|
||||
/*
|
||||
* The bus interface clock, clk_x, is phase aligned with the core clock. The
|
||||
* clk_x is an integral multiple N of the core clk. The value N is configured
|
||||
* at IP delivery time, and its available value is 4, 5, or 6. We need to align
|
||||
* to the largest value to make it work with any possible configuration.
|
||||
*/
|
||||
#define DENALI_CLK_X_MULT 6
|
||||
|
||||
static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
|
||||
{
|
||||
return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
|
||||
@ -595,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
|
||||
}
|
||||
|
||||
iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
|
||||
/*
|
||||
* The ->setup_dma() hook kicks DMA by using the data/command
|
||||
* interface, which belongs to a different AXI port from the
|
||||
* register interface. Read back the register to avoid a race.
|
||||
*/
|
||||
ioread32(denali->reg + DMA_ENABLE);
|
||||
|
||||
denali_reset_irq(denali);
|
||||
denali->setup_dma(denali, dma_addr, page, write);
|
||||
@ -946,7 +944,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
{
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
const struct nand_sdr_timings *timings;
|
||||
unsigned long t_clk;
|
||||
unsigned long t_x, mult_x;
|
||||
int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
|
||||
int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
|
||||
int addr_2_data_mask;
|
||||
@ -957,15 +955,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
return PTR_ERR(timings);
|
||||
|
||||
/* clk_x period in picoseconds */
|
||||
t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
|
||||
if (!t_clk)
|
||||
t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
|
||||
if (!t_x)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* The bus interface clock, clk_x, is phase aligned with the core clock.
|
||||
* The clk_x is an integral multiple N of the core clk. The value N is
|
||||
* configured at IP delivery time, and its available value is 4, 5, 6.
|
||||
*/
|
||||
mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
|
||||
if (mult_x < 4 || mult_x > 6)
|
||||
return -EINVAL;
|
||||
|
||||
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
|
||||
return 0;
|
||||
|
||||
/* tREA -> ACC_CLKS */
|
||||
acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
|
||||
acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
|
||||
acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
|
||||
|
||||
tmp = ioread32(denali->reg + ACC_CLKS);
|
||||
@ -974,7 +981,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
iowrite32(tmp, denali->reg + ACC_CLKS);
|
||||
|
||||
/* tRWH -> RE_2_WE */
|
||||
re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
|
||||
re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
|
||||
re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
|
||||
|
||||
tmp = ioread32(denali->reg + RE_2_WE);
|
||||
@ -983,7 +990,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
iowrite32(tmp, denali->reg + RE_2_WE);
|
||||
|
||||
/* tRHZ -> RE_2_RE */
|
||||
re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
|
||||
re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
|
||||
re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
|
||||
|
||||
tmp = ioread32(denali->reg + RE_2_RE);
|
||||
@ -997,8 +1004,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
* With WE_2_RE properly set, the Denali controller automatically takes
|
||||
* care of the delay; the driver need not set NAND_WAIT_TCCS.
|
||||
*/
|
||||
we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
|
||||
t_clk);
|
||||
we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
|
||||
we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
|
||||
|
||||
tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
|
||||
@ -1013,7 +1019,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
if (denali->revision < 0x0501)
|
||||
addr_2_data_mask >>= 1;
|
||||
|
||||
addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
|
||||
addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
|
||||
addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
|
||||
|
||||
tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
|
||||
@ -1023,7 +1029,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
|
||||
/* tREH, tWH -> RDWR_EN_HI_CNT */
|
||||
rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
|
||||
t_clk);
|
||||
t_x);
|
||||
rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
|
||||
|
||||
tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
|
||||
@ -1032,11 +1038,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
|
||||
|
||||
/* tRP, tWP -> RDWR_EN_LO_CNT */
|
||||
rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
|
||||
t_clk);
|
||||
rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
|
||||
rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
|
||||
t_clk);
|
||||
rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
|
||||
t_x);
|
||||
rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
|
||||
rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
|
||||
rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
|
||||
|
||||
@ -1046,8 +1051,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
|
||||
|
||||
/* tCS, tCEA -> CS_SETUP_CNT */
|
||||
cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
|
||||
(int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
|
||||
cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
|
||||
(int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
|
||||
0);
|
||||
cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
|
||||
|
||||
|
||||
@ -292,6 +292,7 @@ struct udevice;
|
||||
|
||||
struct denali_nand_info {
|
||||
struct nand_chip nand;
|
||||
unsigned long clk_rate; /* core clock rate */
|
||||
unsigned long clk_x_rate; /* bus interface clock rate */
|
||||
int active_bank; /* currently selected bank */
|
||||
struct udevice *dev;
|
||||
|
||||
@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev)
|
||||
{
|
||||
struct denali_nand_info *denali = dev_get_priv(dev);
|
||||
const struct denali_dt_data *data;
|
||||
struct clk clk;
|
||||
struct clk clk, clk_x, clk_ecc;
|
||||
struct resource res;
|
||||
int ret;
|
||||
|
||||
@ -87,15 +87,49 @@ static int denali_dt_probe(struct udevice *dev)
|
||||
|
||||
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &clk);
|
||||
ret = clk_get_by_name(dev, "nand", &clk);
|
||||
if (ret)
|
||||
ret = clk_get_by_index(dev, 0, &clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_by_name(dev, "nand_x", &clk_x);
|
||||
if (ret)
|
||||
clk_x.dev = NULL;
|
||||
|
||||
ret = clk_get_by_name(dev, "ecc", &clk_ecc);
|
||||
if (ret)
|
||||
clk_ecc.dev = NULL;
|
||||
|
||||
ret = clk_enable(&clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
denali->clk_x_rate = clk_get_rate(&clk);
|
||||
if (clk_x.dev) {
|
||||
ret = clk_enable(&clk_x);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (clk_ecc.dev) {
|
||||
ret = clk_enable(&clk_ecc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (clk_x.dev) {
|
||||
denali->clk_rate = clk_get_rate(&clk);
|
||||
denali->clk_x_rate = clk_get_rate(&clk_x);
|
||||
} else {
|
||||
/*
|
||||
* Hardcode the clock rates for the backward compatibility.
|
||||
* This works for both SOCFPGA and UniPhier.
|
||||
*/
|
||||
dev_notice(dev,
|
||||
"necessary clock is missing. default clock rates are used.\n");
|
||||
denali->clk_rate = 50000000;
|
||||
denali->clk_x_rate = 200000000;
|
||||
}
|
||||
|
||||
return denali_init(denali);
|
||||
}
|
||||
|
||||
@ -124,6 +124,8 @@
|
||||
"third_image=u-boot.bin\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run ${bootdev}preboot"
|
||||
|
||||
#define CONFIG_ROOTPATH "/nfs/root/path"
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs $bootargs root=/dev/nfs rw " \
|
||||
@ -169,8 +171,32 @@
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"script=boot.scr\0" \
|
||||
"scriptaddr=0x85000000\0" \
|
||||
"nor_base=0x42000000\0" \
|
||||
"emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
|
||||
"nandboot=run bootcmd_ubifs0\0" \
|
||||
"norboot=run tftpboot\0" \
|
||||
"usbboot=run bootcmd_usb0\0" \
|
||||
"emmcscript=setenv devtype mmc && " \
|
||||
"mmcsetn && " \
|
||||
"setenv devnum ${mmc_first_dev} && " \
|
||||
"run loadscript_fat\0" \
|
||||
"nandscript=echo Running ${script} from ubi ... && " \
|
||||
"ubi part UBI && " \
|
||||
"ubifsmount ubi0:boot && " \
|
||||
"ubifsload ${loadaddr} ${script} && " \
|
||||
"source\0" \
|
||||
"norscript=echo Running ${script} from tftp ... && " \
|
||||
"tftpboot ${script} &&" \
|
||||
"source\0" \
|
||||
"usbscript=usb start && " \
|
||||
"setenv devtype usb && " \
|
||||
"setenv devnum 0 && " \
|
||||
"run loadscript_fat\0" \
|
||||
"loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \
|
||||
"load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \
|
||||
"source\0" \
|
||||
"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
|
||||
"tftpboot $tmp_addr $second_image && " \
|
||||
"setexpr tmp_addr $nor_base + 0x70000 && " \
|
||||
|
||||
@ -102,6 +102,18 @@
|
||||
(((__x) - ((__d) / 2)) / (__d)); \
|
||||
} \
|
||||
)
|
||||
/*
|
||||
* Same as above but for u64 dividends. divisor must be a 32-bit
|
||||
* number.
|
||||
*/
|
||||
#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
|
||||
{ \
|
||||
typeof(divisor) __d = divisor; \
|
||||
unsigned long long _tmp = (x) + (__d) / 2; \
|
||||
do_div(_tmp, __d); \
|
||||
_tmp; \
|
||||
} \
|
||||
)
|
||||
|
||||
/*
|
||||
* Multiplies an integer by a fraction, while avoiding unnecessary
|
||||
|
||||
Loading…
Reference in New Issue
Block a user