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pci: freescale: Drop old code

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Drop this old pre-driver model code.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2021-08-01 18:54:22 -06:00 committed by Tom Rini
parent 595232ad1f
commit 97229af027
16 changed files with 0 additions and 351 deletions
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59
board/freescale/common/cds_pci_ft.c
View File

@ -9,68 +9,9 @@
#include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
static void cds_pci_fixup(void *blob)
{
int node;
const char *path;
int len, slot, i;
u32 *map = NULL, *piccells = NULL;
int off, cells;
node = fdt_path_offset(blob, "/aliases");
if (node >= 0) {
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
node = fdt_path_offset(blob, path);
if (node >= 0) {
map = fdt_getprop_w(blob, node, "interrupt-map", &len);
}
/* Each item in "interrupt-map" property is translated with
* following cells:
* PCI #address-cells, PCI #interrupt-cells,
* PIC address, PIC #address-cells, PIC #interrupt-cells.
*/
cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
if (off <= 0)
return;
cells += 1;
piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
if (piccells == NULL)
return;
cells += *piccells;
piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
if (piccells == NULL)
return;
cells += *piccells;
}
}
if (map) {
len /= sizeof(u32);
slot = get_pci_slot();
for (i=0;i<len;i+=cells) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
map+=cells;
}
}
}
#endif
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
return 0;
}

1
board/freescale/common/p_corenet/Makefile
View File

@ -4,5 +4,4 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += law.o
obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o

25
board/freescale/common/p_corenet/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

114
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -168,113 +168,6 @@ void lbc_sdram_init(void)
#endif /* enable SDRAM init */
}
#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
mpc85xx_config_via_usb2, {0,0,0}},
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
mpc85xx_config_via_ac97, {0,0,0}},
{},
};
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info;
u32 devdisr, pordevsr, io_sel;
u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
int first_free_busno = 0;
char buf[32];
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
porpllsr = in_be32(&gur->porpllsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
#ifdef CONFIG_PCI1
pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info, 1);
set_next_law(pci_info.mem_phys,
law_size_bits(pci_info.mem_size), pci_info.law);
set_next_law(pci_info.io_phys,
law_size_bits(pci_info.io_size), pci_info.law);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
strmhz(buf, pci_speed),
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
pci_info.regs);
pci1_hose.config_table = pci_mpc85xxcds_config_table;
first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
#ifdef CONFIG_PCIX_CHECK
if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
}
#endif
} else {
printf("PCI1: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCI2
{
uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
if (pci_dual) {
printf("PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf("PCI2: disabled\n");
}
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
#endif /* CONFIG_PCI2 */
fsl_pcie_init_board(first_free_busno);
}
#endif
void configure_rgmii(void)
{
unsigned short temp;
@ -354,10 +247,3 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
void ft_pci_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

11
board/freescale/p1010rdb/p1010rdb.c
View File

@ -129,13 +129,6 @@ int board_early_init_r(void)
return 0;
}
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */
int config_board_mux(int ctrl_type)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -617,10 +610,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
base = env_get_bootm_low();
size = env_get_bootm_size();
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
#endif
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB)

11
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -239,13 +239,6 @@ int checkboard(void)
return 0;
}
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@ -363,10 +356,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
#endif
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);

1
board/freescale/t102xrdb/Makefile
View File

@ -10,7 +10,6 @@ else
obj-y += t102xrdb.o
obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o

25
board/freescale/t102xrdb/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007-2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

1
board/freescale/t104xrdb/Makefile
View File

@ -8,7 +8,6 @@ else
obj-y += t104xrdb.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DIU_FB)+= diu.o
endif
obj-y += ddr.o

25
board/freescale/t104xrdb/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

1
board/freescale/t208xqds/Makefile
View File

@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o

25
board/freescale/t208xqds/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007-2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

1
board/freescale/t208xrdb/Makefile
View File

@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o

25
board/freescale/t208xrdb/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007-2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

1
board/freescale/t4rdb/Makefile
View File

@ -10,7 +10,6 @@ else
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o

25
board/freescale/t4rdb/pci.c
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif