leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG

Browse Source 
Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:52 -05:00
parent 85b5511708
commit 97148cb614
11 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -541,7 +541,7 @@ The following options need to be configured:
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
CONFIG_SH_ETHER_USE_PORT
CFG_SH_ETHER_USE_PORT
Define the number of ports to be used
CFG_SH_ETHER_PHY_ADDR

6
drivers/net/sh_eth.c
View File

@ -30,8 +30,8 @@
#include "sh_eth.h"
#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#ifndef CFG_SH_ETHER_USE_PORT
# error "Please define CFG_SH_ETHER_USE_PORT"
#endif
#ifndef CFG_SH_ETHER_PHY_ADDR
# error "Please define CFG_SH_ETHER_PHY_ADDR"
@ -693,7 +693,7 @@ static int sh_ether_probe(struct udevice *udev)
priv->bus = miiphy_get_dev_by_name(udev->name);
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port = CFG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);

2
include/configs/alt.h
View File

@ -21,7 +21,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/condor.h
View File

@ -14,7 +14,7 @@
/* Environment compatibility */
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/gose.h
View File

@ -20,7 +20,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/grpeach.h
View File

@ -17,7 +17,7 @@
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/koelsch.h
View File

@ -20,7 +20,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/lager.h
View File

@ -21,7 +21,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/porter.h
View File

@ -22,7 +22,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/silk.h
View File

@ -22,7 +22,7 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK

2
include/configs/stout.h
View File

@ -26,7 +26,7 @@
#define CFG_SCIF_A
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK