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zynq: Update CLK in bdinfo

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ARM has specific clk entries which should be also setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2014-01-20 11:05:37 +01:00
parent d6c9bbaad1
commit 96a5d4dc1e
1 changed files with 5 additions and 0 deletions
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5
arch/arm/cpu/armv7/zynq/clk.c
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@ -161,6 +161,8 @@ static void init_ddr_clocks(void)
clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
DIV_ROUND_CLOSEST(prate, div0), div1);
clks[dci_clk].name = "dci";
gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
}
static void init_cpu_clocks(void)
@ -593,6 +595,9 @@ int set_cpu_clk_info(void)
init_periph_clocks();
init_aper_clocks();
gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
gd->bd->bi_dsp_freq = 0;
return 0;
}