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board: ls1012a: FRWY-LS1012A board support

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FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE
MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
[yorks: rebase and fix SPDX tag]
[yorks: fix board/freescale/ls1012afrdm/Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Bhaskar Upadhaya 2018-05-23 11:03:30 +05:30 committed by York Sun
parent 7191d45348
commit 9629ccdde7
9 changed files with 330 additions and 9 deletions
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12
arch/arm/Kconfig
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@ -1034,6 +1034,18 @@ config TARGET_LS1012A2G5RDB
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
config TARGET_LS1012AFRWY
bool "Support ls1012afrwy"
select ARCH_LS1012A
select ARM64
imply SCSI
imply SCSI_AHCI
help
Support for Freescale LS1012AFRWY platform.
The LS1012A FRWY board (FRWY) is a high-performance
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A

1
arch/arm/cpu/armv8/Kconfig
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@ -91,6 +91,7 @@ config PSCI_RESET
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1012AFRWY && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \

3
arch/arm/dts/Makefile
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@ -228,7 +228,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb
fsl-ls1012a-frdm.dtb \
fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb

43
arch/arm/dts/fsl-ls1012a-frwy.dts Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1012a FRWY board device tree source
*
* Copyright 2018 NXP
*
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "FRWY-LS1012A Board";
aliases {
spi0 = &qspi;
};
chosen {
stdout-path = &duart0;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: w25q16dw@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c0 {
status = "okay";
};
&duart0 {
status = "okay";
};

36
board/freescale/ls1012afrdm/Kconfig
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@ -12,9 +12,14 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012afrdm"
config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"
default 0x40400000
endif
if FSL_PFE
@ -22,10 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select PHYLIB
imply PHY_REALTEK
config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
imply PHY_ATHEROS
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
@ -45,6 +47,30 @@ config PFE_EMAC2_PHY_ADDR
endif
source "board/freescale/common/Kconfig"
if TARGET_LS1012AFRWY
config SYS_BOARD
default "ls1012afrdm"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1012afrwy"
config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40020000
config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"
default 0x40060000
endif
if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
source "board/freescale/common/Kconfig"
endif

7
board/freescale/ls1012afrdm/MAINTAINERS
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@ -4,3 +4,10 @@ S: Maintained
F: board/freescale/ls1012afrdm/
F: include/configs/ls1012afrdm.h
F: configs/ls1012afrdm_qspi_defconfig
LS1012AFRWY BOARD
M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
S: Maintained
F: board/freescale/ls1012afrwy/
F: include/configs/ls1012afrwy.h
F: configs/ls1012afrwy_qspi_defconfig

68
board/freescale/ls1012afrdm/ls1012afrdm.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
*/
#include <common.h>
@ -13,6 +13,7 @@
#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <fsl_esdhc.h>
#include <hwconfig.h>
#include <environment.h>
#include <fsl_mmdc.h>
@ -20,16 +21,66 @@
DECLARE_GLOBAL_DATA_PTR;
static inline int get_board_version(void)
{
struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
int val;
val = in_be32(&pgpio->gpdat);
return val;
}
int checkboard(void)
{
#ifdef CONFIG_TARGET_LS1012AFRDM
puts("Board: LS1012AFRDM ");
#else
int rev;
rev = get_board_version();
puts("Board: FRWY-LS1012A ");
puts("Version");
switch (rev) {
case BOARD_REV_A:
puts(": RevA ");
break;
case BOARD_REV_B:
puts(": RevB ");
break;
default:
puts(": unknown");
break;
}
#endif
return 0;
}
#ifdef CONFIG_TARGET_LS1012AFRWY
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";
char esdhc1_path[] = "/soc/esdhc@1580000";
do_fixup_by_path(blob, esdhc0_path, "status", "okay",
sizeof("okay"), 1);
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
sizeof("disabled"), 1);
return 0;
}
#endif
int dram_init(void)
{
static const struct fsl_mmdc_info mparam = {
#ifdef CONFIG_TARGET_LS1012AFRWY
int board_rev;
#endif
struct fsl_mmdc_info mparam = {
0x04180000, /* mdctl */
0x00030035, /* mdpdc */
0x12554000, /* mdotc */
@ -45,9 +96,20 @@ int dram_init(void)
0xa1390003, /* mpzqhwctrl */
};
#ifdef CONFIG_TARGET_LS1012AFRWY
board_rev = get_board_version();
if (board_rev & BOARD_REV_B) {
mparam.mdctl = 0x05180000;
gd->ram_size = SYS_SDRAM_SIZE_1024;
} else {
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();

50
configs/ls1012afrwy_qspi_defconfig Normal file
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@ -0,0 +1,50 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

119
include/configs/ls1012afrwy.h Normal file
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@ -0,0 +1,119 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __LS1012AFRWY_H__
#define __LS1012AFRWY_H__
#include "ls1012a_common.h"
/* Board Rev*/
#define BOARD_REV_A 0x0
#define BOARD_REV_B 0x200
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define SYS_SDRAM_SIZE_512 0x20000000
#define SYS_SDRAM_SIZE_1024 0x40000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#ifndef CONFIG_SPL_BUILD
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0)
#endif
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET 0x1D0000
#undef FSL_QSPI_FLASH_SIZE
#define FSL_QSPI_FLASH_SIZE SZ_16M
#undef CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x10000 /*64 KB*/
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE 0x10000 /*64 KB*/
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x1fc000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0x96000000\0" \
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
"console=ttyS0,115200\0" \
BOOTENV \
"boot_scripts=ls1012afrwy_boot.scr\0" \
"boot_script_hdr=hdr_ls1012afrwy_bs.out\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
"for distro_bootpart in ${devplist}; do " \
"if fstype ${devtype} " \
"${devnum}:${distro_bootpart} " \
"bootfstype; then " \
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#include <asm/fsl_secure_boot.h>
#endif /* __LS1012AFRWY_H__ */