blackfin: Fit u-boot image size into limited nor flash on blackfin.
- Disable NAND driver on bf537-stamp. - Make MMC_SPI optional. - Disable LCD driver on bf527-ezkit. - Enlarge BF609 nor flash reserved size from 256k to 512k bytes. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
This commit is contained in:
@@ -149,10 +149,15 @@
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#define CONFIG_MUSB_TIMEOUT 100000
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#define CONFIG_MUSB_TIMEOUT 100000
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#endif
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#endif
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/* Don't waste time transferring a logo over the UART */
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#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
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/*# define CONFIG_VIDEO*/
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#endif
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/*
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/*
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* Video Settings
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* Video Settings
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*/
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*/
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#ifdef CONFIG_VIDEO
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#ifdef CONFIG_BF527_EZKIT_REV_2_1
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#ifdef CONFIG_BF527_EZKIT_REV_2_1
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# define CONFIG_LQ035Q1_SPI_BUS 0
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# define CONFIG_LQ035Q1_SPI_BUS 0
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# define CONFIG_LQ035Q1_SPI_CS 7
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# define CONFIG_LQ035Q1_SPI_CS 7
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@@ -166,7 +171,7 @@
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#else
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#else
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# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
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# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
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#endif
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#endif
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#endif /* CONFIG_VIDEO */
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/*
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/*
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* Misc Settings
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* Misc Settings
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@@ -175,11 +180,6 @@
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#define CONFIG_RTC_BFIN
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 1
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#define CONFIG_UART_CONSOLE 1
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/* Don't waste time transferring a logo over the UART */
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#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
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# define CONFIG_VIDEO
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#endif
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/*
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/*
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* Pull in common ADI header for remaining command/environment setup
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* Pull in common ADI header for remaining command/environment setup
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@@ -52,7 +52,7 @@
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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@@ -135,15 +135,17 @@
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/*
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/*
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* SPI_MMC Settings
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* SPI_MMC Settings
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*/
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*/
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#define CONFIG_MMC_SPI
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#ifdef CONFIG_MMC_SPI
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#define CONFIG_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC_SPI
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#endif
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/*
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/*
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* NAND Settings
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* NAND Settings
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*/
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*/
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/* #define CONFIG_NAND_PLAT */
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/* #define CONFIG_NAND_PLAT */
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#ifdef CONFIG_NAND_PLAT
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#define CONFIG_SYS_NAND_BASE 0x20212000
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#define CONFIG_SYS_NAND_BASE 0x20212000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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@@ -158,7 +160,7 @@
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
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#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
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#endif /* CONFIG_NAND_PLAT */
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/*
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/*
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* CF-CARD IDE-HDD Support
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* CF-CARD IDE-HDD Support
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@@ -156,6 +156,8 @@
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#undef CONFIG_UART_CONSOLE_IS_JTAG
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#undef CONFIG_UART_CONSOLE_IS_JTAG
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#endif
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#endif
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#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
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/*
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/*
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* Run core 1 from L1 SRAM start address when init uboot on core 0
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* Run core 1 from L1 SRAM start address when init uboot on core 0
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*/
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*/
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