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ARM: IGEP0033: Update timing to run DDR at 400MHz.

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We can run the DDR at 400MHz, so update the timings for that purpose.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
This commit is contained in:
Enric Balletbo i Serra
2013-09-10 11:12:26 +02:00
committed by Tom Rini
parent e3cf969205
commit 94b32f60fe
2 changed files with 14 additions and 14 deletions
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4
board/isee/igep0033/board.c
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@@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
303, OSC-1, 1, -1, -1, -1, -1};
400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
@@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
void sdram_init(void)
{
config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif