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Cleanup and update towards support for Amlogic Meson AXG SoCs :

Browse Source 
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
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Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
This commit is contained in:
Tom Rini 2018-11-29 09:33:33 -05:00
commit 93e72ac472
86 changed files with 5177 additions and 759 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
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@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxl-s905x-p212.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

554
arch/arm/dts/meson-axg-s400.dts Normal file
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@ -0,0 +1,554 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "meson-axg.dtsi"
#include <dt-bindings/input/input.h>
/ {
compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
model = "Amlogic Meson AXG S400 Development Board";
adc_keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
button-next {
label = "Next";
linux,code = <KEY_NEXT>;
press-threshold-microvolt = <1116000>; /* 62% */
};
button-prev {
label = "Previous";
linux,code = <KEY_PREVIOUS>;
press-threshold-microvolt = <900000>; /* 50% */
};
button-wifi {
label = "Wifi";
linux,code = <KEY_WLAN>;
press-threshold-microvolt = <684000>; /* 38% */
};
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <468000>; /* 26% */
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <252000>; /* 14% */
};
button-voice {
label = "Voice";
linux,code = <KEY_VOICECOMMAND>;
press-threshold-microvolt = <0>; /* 0% */
};
};
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
};
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
status = "okay";
sound-name-prefix = "Linein";
};
lineout: audio-codec@1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
status = "okay";
sound-name-prefix = "Lineout";
};
spdif_dit: audio-codec@2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
};
dmics: audio-codec@3 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <7>;
wakeup-delay-ms = <50>;
status = "okay";
sound-name-prefix = "MIC";
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v>;
gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
usb_pwr: regulator-usb_pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
speaker-leds {
compatible = "gpio-leds";
aled1 {
label = "speaker:aled1";
gpios = <&gpio_speaker 7 0>;
};
aled2 {
label = "speaker:aled2";
gpios = <&gpio_speaker 6 0>;
};
aled3 {
label = "speaker:aled3";
gpios = <&gpio_speaker 5 0>;
};
aled4 {
label = "speaker:aled4";
gpios = <&gpio_speaker 4 0>;
};
aled5 {
label = "speaker:aled5";
gpios = <&gpio_speaker 3 0>;
};
aled6 {
label = "speaker:aled6";
gpios = <&gpio_speaker 2 0>;
};
};
sound {
compatible = "amlogic,axg-sound-card";
model = "AXG-S400";
audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
<&tdmin_lb>, <&tdmout_c>;
audio-widgets = "Line", "Lineout",
"Line", "Linein",
"Speaker", "Speaker1 Left",
"Speaker", "Speaker1 Right";
audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
"SPDIFOUT IN 0", "FRDDR_A OUT 3",
"TDMOUT_C IN 1", "FRDDR_B OUT 2",
"SPDIFOUT IN 1", "FRDDR_B OUT 3",
"TDMOUT_C IN 2", "FRDDR_C OUT 2",
"SPDIFOUT IN 2", "FRDDR_C OUT 3",
"TDM_C Playback", "TDMOUT_C OUT",
"TDMIN_A IN 2", "TDM_C Capture",
"TDMIN_A IN 5", "TDM_C Loopback",
"TDMIN_B IN 2", "TDM_C Capture",
"TDMIN_B IN 5", "TDM_C Loopback",
"TDMIN_C IN 2", "TDM_C Capture",
"TDMIN_C IN 5", "TDM_C Loopback",
"TDMIN_LB IN 2", "TDM_C Loopback",
"TDMIN_LB IN 5", "TDM_C Capture",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT",
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
"TODDR_A IN 4", "PDM Capture",
"TODDR_B IN 4", "PDM Capture",
"TODDR_C IN 4", "PDM Capture",
"TODDR_A IN 6", "TDMIN_LB OUT",
"TODDR_B IN 6", "TDMIN_LB OUT",
"TODDR_C IN 6", "TDMIN_LB OUT",
"Lineout", "Lineout AOUTL",
"Lineout", "Lineout AOUTR",
"Speaker1 Left", "SPK1 OUT_A",
"Speaker1 Left", "SPK1 OUT_B",
"Speaker1 Right", "SPK1 OUT_C",
"Speaker1 Right", "SPK1 OUT_D",
"Linein AINL", "Linein",
"Linein AINR", "Linein";
assigned-clocks = <&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <589824000>,
<270950400>,
<393216000>;
status = "okay";
dai-link@0 {
sound-dai = <&frddr_a>;
};
dai-link@1 {
sound-dai = <&frddr_b>;
};
dai-link@2 {
sound-dai = <&frddr_c>;
};
dai-link@3 {
sound-dai = <&toddr_a>;
};
dai-link@4 {
sound-dai = <&toddr_b>;
};
dai-link@5 {
sound-dai = <&toddr_c>;
};
dai-link@6 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-rx-mask-1 = <1 1>;
mclk-fs = <256>;
codec@0 {
sound-dai = <&lineout>;
};
codec@1 {
sound-dai = <&speaker_amp1>;
};
codec@2 {
sound-dai = <&linein>;
};
};
dai-link@7 {
sound-dai = <&spdifout>;
codec {
sound-dai = <&spdif_dit>;
};
};
dai-link@8 {
sound-dai = <&pdm>;
codec {
sound-dai = <&dmics>;
};
};
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_y_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
eee-broken-1000t;
};
};
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1_z_pins>;
pinctrl-names = "default";
speaker_amp1: audio-codec@1b {
compatible = "ti,tas5707";
reg = <0x1b>;
reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
AVDD-supply = <&vcc_3v3>;
DVDD-supply = <&vcc_3v3>;
PVDD_A-supply = <&main_12v>;
PVDD_B-supply = <&main_12v>;
PVDD_C-supply = <&main_12v>;
PVDD_D-supply = <&main_12v>;
sound-name-prefix = "SPK1";
};
};
&i2c_AO {
status = "okay";
pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
pinctrl-names = "default";
gpio_speaker: gpio-controller@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vddao_3v3>;
};
};
&pdm {
pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
<&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* wifi module */
&sd_emmc_b {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* emmc storage */
&sd_emmc_c {
status = "disabled";
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <180000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&spdifout {
pinctrl-0 = <&spdif_out_a20_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_a {
pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
<&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_b {
pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
<&tdmb_din3_pins>, <&mclk_b_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_c {
pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
<&tdmc_din1_pins>, <&tdmc_dout2_pins>,
<&mclk_c_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmin_c {
status = "okay";
};
&tdmin_lb {
status = "okay";
};
&tdmout_c {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

1589
arch/arm/dts/meson-axg.dtsi Normal file
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52
arch/arm/include/asm/arch-meson/axg.h Normal file
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@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __AXG_H__
#define __AXG_H__
#define AXG_AOBUS_BASE 0xff800000
#define AXG_PERIPHS_BASE 0xff634400
#define AXG_HIU_BASE 0xff63c000
#define AXG_ETH_BASE 0xff3f0000
/* Always-On Peripherals registers */
#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2))
#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90)
#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93)
#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94)
#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95)
#define AXG_AO_BOOT_DEVICE 0xF
#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000
#define AXG_AO_MEM_SIZE_SHIFT 16
#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
/* Peripherals registers */
#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2))
#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50)
#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51)
#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
#define AXG_ETH_REG_0_CLK_EN BIT(12)
/* HIU registers */
#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2))
#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40)
/* Ethernet memory power domain */
#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
#endif /* __AXG_H__ */

20
arch/arm/include/asm/arch-meson/boot.h Normal file
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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __MESON_BOOT_H__
#define __MESON_BOOT_H__
/* Boot device */
#define BOOT_DEVICE_RESERVED 0
#define BOOT_DEVICE_EMMC 1
#define BOOT_DEVICE_NAND 2
#define BOOT_DEVICE_SPI 3
#define BOOT_DEVICE_SD 4
#define BOOT_DEVICE_USB 5
int meson_get_boot_device(void);
#endif /* __MESON_BOOT_H__ */

104
arch/arm/include/asm/arch-meson/clock-axg.h Normal file
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@ -0,0 +1,104 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 - AmLogic, Inc.
* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
* Copyright 2018 - BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef _ARCH_MESON_CLOCK_AXG_H_
#define _ARCH_MESON_CLOCK_AXG_H_
/*
* Clock controller register offsets
*
* Register offsets from the data sheet are listed in comment blocks below.
* Those offsets must be multiplied by 4 before adding them to the base address
* to get the right value
*/
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
#define HHI_GP0_PLL_CNTL4 0x4c
#define HHI_GP0_PLL_CNTL5 0x50
#define HHI_GP0_PLL_STS 0x54
#define HHI_GP0_PLL_CNTL1 0x58
#define HHI_HIFI_PLL_CNTL 0x80
#define HHI_HIFI_PLL_CNTL2 0x84
#define HHI_HIFI_PLL_CNTL3 0x88
#define HHI_HIFI_PLL_CNTL4 0x8C
#define HHI_HIFI_PLL_CNTL5 0x90
#define HHI_HIFI_PLL_STS 0x94
#define HHI_HIFI_PLL_CNTL1 0x98
#define HHI_XTAL_DIVN_CNTL 0xbc
#define HHI_GCLK2_MPEG0 0xc0
#define HHI_GCLK2_MPEG1 0xc4
#define HHI_GCLK2_MPEG2 0xc8
#define HHI_GCLK2_OTHER 0xd0
#define HHI_GCLK2_AO 0xd4
#define HHI_PCIE_PLL_CNTL 0xd8
#define HHI_PCIE_PLL_CNTL1 0xdC
#define HHI_PCIE_PLL_CNTL2 0xe0
#define HHI_PCIE_PLL_CNTL3 0xe4
#define HHI_PCIE_PLL_CNTL4 0xe8
#define HHI_PCIE_PLL_CNTL5 0xec
#define HHI_PCIE_PLL_CNTL6 0xf0
#define HHI_PCIE_PLL_STS 0xf4
#define HHI_MEM_PD_REG0 0x100
#define HHI_VPU_MEM_PD_REG0 0x104
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_AO 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_SYS_CPU_RESET_CNTL 0x160
#define HHI_VID_CLK_DIV 0x164
#define HHI_SPICC_HCLK_CNTL 0x168
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1a0
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL 0x280
#define HHI_MPLL_CNTL2 0x284
#define HHI_MPLL_CNTL3 0x288
#define HHI_MPLL_CNTL4 0x28C
#define HHI_MPLL_CNTL5 0x290
#define HHI_MPLL_CNTL6 0x294
#define HHI_MPLL_CNTL7 0x298
#define HHI_MPLL_CNTL8 0x29C
#define HHI_MPLL_CNTL9 0x2A0
#define HHI_MPLL_CNTL10 0x2A4
#define HHI_MPLL3_CNTL0 0x2E0
#define HHI_MPLL3_CNTL1 0x2E4
#define HHI_PLL_TOP_MISC 0x2E8
#define HHI_SYS_PLL_CNTL1 0x2FC
#define HHI_SYS_PLL_CNTL 0x300
#define HHI_SYS_PLL_CNTL2 0x304
#define HHI_SYS_PLL_CNTL3 0x308
#define HHI_SYS_PLL_CNTL4 0x30c
#define HHI_SYS_PLL_CNTL5 0x310
#define HHI_SYS_PLL_STS 0x314
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
#endif

4
arch/arm/include/asm/arch-meson/clock.h → arch/arm/include/asm/arch-meson/clock-gx.h
View File

@ -3,8 +3,8 @@
* Copyright 2016 - AmLogic, Inc.
* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
*/
#ifndef _ARCH_MESON_CLOCK_H_
#define _ARCH_MESON_CLOCK_H_
#ifndef _ARCH_MESON_CLOCK_GX_H_
#define _ARCH_MESON_CLOCK_GX_H_
/*
* Clock controller register offsets

6
arch/arm/include/asm/arch-meson/eth.h
View File

@ -10,13 +10,13 @@
#include <phy.h>
enum {
/* Use GXL Internal RMII PHY */
MESON_GXL_USE_INTERNAL_RMII_PHY = 1,
/* Use Internal RMII PHY */
MESON_USE_INTERNAL_RMII_PHY = 1,
};
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_gx_eth_init(phy_interface_t mode, unsigned int flags);
void meson_eth_init(phy_interface_t mode, unsigned int flags);
#endif /* __MESON_ETH_H__ */

1
arch/arm/include/asm/arch-meson/gx.h
View File

@ -21,6 +21,7 @@
#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
#define GX_AO_BOOT_DEVICE 0xF
#define GX_AO_MEM_SIZE_MASK 0xFFFF0000
#define GX_AO_MEM_SIZE_SHIFT 16
#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000

3
arch/arm/include/asm/arch-meson/mem.h
View File

@ -10,6 +10,7 @@
/* Configure the reserved memory zones exported by the secure registers
* into EFI and DTB reserved memory entries.
*/
void meson_gx_init_reserved_memory(void *fdt);
void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size);
void meson_init_reserved_memory(void *fdt);
#endif /* __MESON_MEM_H__ */

132
arch/arm/mach-meson/Kconfig
View File

@ -1,89 +1,49 @@
if ARCH_MESON
config MESON_GXBB
bool "Support Meson GXBaby"
config MESON64_COMMON
bool
select ARM64
select CLK
select DM
select DM_SERIAL
select SYSCON
select REGMAP
select BOARD_LATE_INIT
imply CMD_DM
config MESON_GX
bool
select MESON64_COMMON
choice
prompt "Platform select"
default MESON_GXBB
config MESON_GXBB
bool "GXBB"
select MESON_GX
help
The Amlogic Meson GXBaby (S905) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
Select this if your SoC is an S905
config MESON_GXL
bool "Support Meson GXL"
select ARM64
select CLK
select DM
select DM_SERIAL
imply CMD_DM
bool "GXL"
select MESON_GX
help
The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
Select this if your SoC is an S905X/D or S805X
config MESON_GXM
bool "Support Meson GXM"
select ARM64
select CLK
select DM
select DM_SERIAL
bool "GXM"
select MESON_GX
help
The Amlogic Meson GXM (S912) is an ARM SoC with an
octo-core Cortex-A53 CPU and a Mali-T860 GPU.
Select this if your SoC is an S912
if MESON_GXBB
config TARGET_ODROID_C2
bool "ODROID-C2"
config MESON_AXG
bool "AXG"
select MESON64_COMMON
help
ODROID-C2 is a single board computer based on Meson GXBaby
with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
slot, eMMC, IR receiver and a 40-pin GPIO header.
Select this if your SoC is an A113X/D
config TARGET_NANOPI_K2
bool "NANOPI_K2"
help
NANOPI_K2 is a single board computer based on Meson GXBaby
with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB,
micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header.
endif
if MESON_GXL
config TARGET_P212
bool "P212"
help
P212 is a reference dessign board based on Meson GXL S905X SoC
with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
config TARGET_LIBRETECH_CC
bool "LIBRETECH-CC"
help
LibreTech CC is a single board computer based on Meson GXL
with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
eMMC, IR receiver and a 40-pin GPIO header.
config TARGET_KHADAS_VIM
bool "KHADAS-VIM"
help
Khadas VIM is a single board computer based on Meson GXL
with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
eMMC, IR receiver and a 40-pin GPIO header.
endif
if MESON_GXM
config TARGET_KHADAS_VIM2
bool "KHADAS-VIM2"
help
Khadas VIM2 is a single board computer based on Meson GXM
with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
eMMC, IR receiver and a 40-pin GPIO header.
endif
endchoice
config SYS_SOC
default "meson"
@ -91,16 +51,32 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x1000
source "board/amlogic/odroid-c2/Kconfig"
config SYS_VENDOR
string "Vendor name"
default "amlogic"
help
This option contains information about board name.
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
be used.
source "board/amlogic/nanopi-k2/Kconfig"
config SYS_BOARD
string "Board name"
default "odroid-c2" if MESON_GXBB
default "p212" if MESON_GXL
default "q200" if MESON_GXM
default "s400" if MESON_AXG
default ""
help
This option contains information about board name.
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
be used.
source "board/amlogic/p212/Kconfig"
source "board/amlogic/libretech-cc/Kconfig"
source "board/amlogic/khadas-vim/Kconfig"
source "board/amlogic/khadas-vim2/Kconfig"
config SYS_CONFIG_NAME
string "Board configuration name"
default "meson64"
help
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
endif

4
arch/arm/mach-meson/Makefile
View File

@ -2,4 +2,6 @@
#
# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
obj-y += board.o sm.o eth.o
obj-y += board-common.o sm.o
obj-$(CONFIG_MESON_GX) += board-gx.o
obj-$(CONFIG_MESON_AXG) += board-axg.o

118
arch/arm/mach-meson/board-axg.c Normal file
View File

@ -0,0 +1,118 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/axg.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
int meson_get_boot_device(void)
{
return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
}
/* Configure the reserved memory zones exported by the secure registers
* into EFI and DTB reserved memory entries.
*/
void meson_init_reserved_memory(void *fdt)
{
u64 bl31_size, bl31_start;
u64 bl32_size, bl32_start;
u32 reg;
/*
* Get ARM Trusted Firmware reserved memory zones in :
* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
*/
reg = readl(AXG_AO_SEC_GP_CFG3);
bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
bl31_start = readl(AXG_AO_SEC_GP_CFG5);
bl32_start = readl(AXG_AO_SEC_GP_CFG4);
/* Add BL31 reserved zone */
if (bl31_start && bl31_size)
meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
/* Add BL32 reserved zone */
if (bl32_start && bl32_size)
meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
}
static struct mm_region axg_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xf0000000UL,
.phys = 0xf0000000UL,
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = axg_mem_map;
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
AXG_ETH_REG_0_TX_PHASE(1) |
AXG_ETH_REG_0_TX_RATIO(4) |
AXG_ETH_REG_0_PHY_CLK_EN |
AXG_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
AXG_ETH_REG_0_INVERT_RMII_CLK |
AXG_ETH_REG_0_CLK_EN);
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
/* Enable power gate */
clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
}

117
arch/arm/mach-meson/board-common.c Normal file
View File

@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*/
#include <common.h>
#include <asm/arch/boot.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <asm/arch/mem.h>
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>
#include <efi_loader.h>
DECLARE_GLOBAL_DATA_PTR;
__weak int board_init(void)
{
return 0;
}
int dram_init(void)
{
const fdt64_t *val;
int offset;
int len;
offset = fdt_path_offset(gd->fdt_blob, "/memory");
if (offset < 0)
return -EINVAL;
val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
if (len < sizeof(*val) * 2)
return -EINVAL;
/* Use unaligned access since cache is still disabled */
gd->ram_size = get_unaligned_be64(&val[1]);
return 0;
}
__weak int meson_ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_init_reserved_memory(blob);
return meson_ft_board_setup(blob, bd);
}
void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
{
int ret;
ret = fdt_add_mem_rsv(fdt, start, size);
if (ret)
printf("Could not reserve zone @ 0x%llx\n", start);
if (IS_ENABLED(CONFIG_EFI_LOADER)) {
efi_add_memory_map(start,
ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
EFI_RESERVED_MEMORY_TYPE, false);
}
}
static void meson_set_boot_source(void)
{
const char *source;
switch (meson_get_boot_device()) {
case BOOT_DEVICE_EMMC:
source = "emmc";
break;
case BOOT_DEVICE_NAND:
source = "nand";
break;
case BOOT_DEVICE_SPI:
source = "spi";
break;
case BOOT_DEVICE_SD:
source = "sd";
break;
case BOOT_DEVICE_USB:
source = "usb";
break;
default:
source = "unknown";
}
env_set("boot_source", source);
}
__weak int meson_board_late_init(void)
{
return 0;
}
int board_late_init(void)
{
meson_set_boot_source();
return meson_board_late_init();
}
void reset_cpu(ulong addr)
{
psci_system_reset();
}

108
arch/arm/mach-meson/board.c → arch/arm/mach-meson/board-gx.c
View File

@ -1,64 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>
#include <linux/sizes.h>
#include <efi_loader.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
int meson_get_boot_device(void)
{
const fdt64_t *val;
int offset;
int len;
offset = fdt_path_offset(gd->fdt_blob, "/memory");
if (offset < 0)
return -EINVAL;
val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
if (len < sizeof(*val) * 2)
return -EINVAL;
/* Use unaligned access since cache is still disabled */
gd->ram_size = get_unaligned_be64(&val[1]);
return 0;
return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
}
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
}
static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
{
int ret;
ret = fdt_add_mem_rsv(fdt, start, size);
if (ret)
printf("Could not reserve zone @ 0x%llx\n", start);
if (IS_ENABLED(CONFIG_EFI_LOADER)) {
efi_add_memory_map(start,
ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
EFI_RESERVED_MEMORY_TYPE, false);
}
}
void meson_gx_init_reserved_memory(void *fdt)
/* Configure the reserved memory zones exported by the secure registers
* into EFI and DTB reserved memory entries.
*/
void meson_init_reserved_memory(void *fdt)
{
u64 bl31_size, bl31_start;
u64 bl32_size, bl32_start;
@ -70,7 +36,6 @@ void meson_gx_init_reserved_memory(void *fdt)
* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
*/
reg = readl(GX_AO_SEC_GP_CFG3);
bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
@ -102,9 +67,11 @@ void meson_gx_init_reserved_memory(void *fdt)
meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}
void reset_cpu(ulong addr)
phys_size_t get_effective_memsize(void)
{
psci_system_reset();
/* Size is reported in MiB, convert it in bytes */
return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
}
static struct mm_region gx_mem_map[] = {
@ -128,3 +95,44 @@ static struct mm_region gx_mem_map[] = {
};
struct mm_region *mem_map = gx_mem_map;
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
GX_ETH_REG_0_TX_PHASE(1) |
GX_ETH_REG_0_TX_RATIO(4) |
GX_ETH_REG_0_PHY_CLK_EN |
GX_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
GX_ETH_REG_0_CLK_EN);
/* Use GXL RMII Internal PHY */
if (IS_ENABLED(CONFIG_MESON_GXL) &&
(flags & MESON_USE_INTERNAL_RMII_PHY)) {
writel(0x10110181, GX_ETH_REG_2);
writel(0xe40908ff, GX_ETH_REG_3);
}
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
/* Enable power gate */
clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
}

53
arch/arm/mach-meson/eth.c
View File

@ -1,53 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/eth.h>
#include <phy.h>
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
GX_ETH_REG_0_TX_PHASE(1) |
GX_ETH_REG_0_TX_RATIO(4) |
GX_ETH_REG_0_PHY_CLK_EN |
GX_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
GX_ETH_REG_0_CLK_EN);
/* Use GXL RMII Internal PHY */
if (IS_ENABLED(CONFIG_MESON_GXL) &&
(flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
writel(0x10110181, GX_ETH_REG_2);
writel(0xe40908ff, GX_ETH_REG_3);
}
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
/* Enable power gate */
clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
}

1
arch/arm/mach-meson/sm.c
View File

@ -6,7 +6,6 @@
*/
#include <common.h>
#include <asm/arch/gx.h>
#include <linux/kernel.h>
#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020

12
board/amlogic/khadas-vim/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_KHADAS_VIM
config SYS_BOARD
default "khadas-vim"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "khadas-vim"
endif

6
board/amlogic/khadas-vim/MAINTAINERS
View File

@ -1,6 +0,0 @@
KHADAS-VIM
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/khadas-vim/
F: include/configs/khadas-vim.h
F: configs/khadas-vim_defconfig

57
board/amlogic/khadas-vim/khadas-vim.c
View File

@ -1,57 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/mem.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_GXL_USE_INTERNAL_RMII_PHY);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

12
board/amlogic/khadas-vim2/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_KHADAS_VIM2
config SYS_BOARD
default "khadas-vim2"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "khadas-vim2"
endif

12
board/amlogic/libretech-cc/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_LIBRETECH_CC
config SYS_BOARD
default "libretech-cc"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "libretech-cc"
endif

6
board/amlogic/libretech-cc/MAINTAINERS
View File

@ -1,6 +0,0 @@
LIBRETECH-CC
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/libretech-cc/
F: include/configs/libretech-cc.h
F: configs/libretech-cc_defconfig

6
board/amlogic/libretech-cc/Makefile
View File

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 BayLibre, SAS
# Author: Neil Armstrong <narmstrong@baylibre.com>
obj-y := libretech-cc.o

57
board/amlogic/libretech-cc/libretech-cc.c
View File

@ -1,57 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_GXL_USE_INTERNAL_RMII_PHY);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

12
board/amlogic/nanopi-k2/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_NANOPI_K2
config SYS_BOARD
default "nanopi-k2"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "nanopi-k2"
endif

6
board/amlogic/nanopi-k2/MAINTAINERS
View File

@ -1,6 +0,0 @@
NANOPI-K2
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/nanopi-k2/
F: include/configs/nanopi-k2.h
F: configs/nanopi-k2_defconfig

7
board/amlogic/nanopi-k2/Makefile
View File

@ -1,7 +0,0 @@
#
# (C) Copyright 2018 Thomas McKahan
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := nanopi-k2.o

55
board/amlogic/nanopi-k2/nanopi-k2.c
View File

@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Thomas McKahan
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

12
board/amlogic/odroid-c2/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_ODROID_C2
config SYS_BOARD
default "odroid-c2"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "odroid-c2"
endif

2
board/amlogic/odroid-c2/MAINTAINERS
View File

@ -1,6 +1,8 @@
ODROID-C2
M: Beniamino Galvani <b.galvani@gmail.com>
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/odroid-c2/
F: include/configs/odroid-c2.h
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig

0
board/amlogic/nanopi-k2/README → board/amlogic/odroid-c2/README.nanopi-k2
View File

0
board/amlogic/odroid-c2/README → board/amlogic/odroid-c2/README.odroid-c2
View File

14
board/amlogic/odroid-c2/odroid-c2.c
View File

@ -17,18 +17,13 @@
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@ -46,10 +41,3 @@ int misc_init_r(void)
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

12
board/amlogic/p212/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_P212
config SYS_BOARD
default "p212"
config SYS_VENDOR
default "amlogic"
config SYS_CONFIG_NAME
default "p212"
endif

2
board/amlogic/p212/MAINTAINERS
View File

@ -3,4 +3,6 @@ M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/p212/
F: include/configs/p212.h
F: configs/khadas-vim_defconfig
F: configs/libretech-cc_defconfig
F: configs/p212_defconfig

0
board/amlogic/khadas-vim/README → board/amlogic/p212/README.khadas-vim
View File

0
board/amlogic/libretech-cc/README → board/amlogic/p212/README.libretech-cc
View File

0
board/amlogic/p212/README → board/amlogic/p212/README.p212
View File

16
board/amlogic/p212/p212.c
View File

@ -18,19 +18,14 @@
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_GXL_USE_INTERNAL_RMII_PHY);
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@ -48,10 +43,3 @@ int misc_init_r(void)
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

6
board/amlogic/khadas-vim2/MAINTAINERS → board/amlogic/q200/MAINTAINERS
View File

@ -1,6 +1,6 @@
KHADAS-VIM2
Q200
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/khadas-vim2/
F: include/configs/khadas-vim2.h
F: board/amlogic/q200/
F: include/configs/q200.h
F: configs/khadas-vim2_defconfig

2
board/amlogic/khadas-vim/Makefile → board/amlogic/q200/Makefile
View File

@ -3,4 +3,4 @@
# (C) Copyright 2016 BayLibre, SAS
# Author: Neil Armstrong <narmstrong@baylibre.com>
obj-y := khadas-vim.o
obj-y := q200.o

0
board/amlogic/khadas-vim2/README → board/amlogic/q200/README.khadas-vim2
View File

102
board/amlogic/q200/README.q200 Normal file
View File

@ -0,0 +1,102 @@
U-Boot for Amlogic Q200
=======================
Q200 is a reference board manufactured by Amlogic with the following
specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T860 GPU
- 2/3GB DDR4 SDRAM
- 10/100/1000 Ethernet
- HDMI 2.0 4K/60Hz display
- 2 x USB 2.0 Host, 1 x USB 2.0 Device
- 16GB/32GB/64GB eMMC
- 2MB SPI Flash
- microSD
- SDIO Wifi Module, Bluetooth
- IR receiver
Currently the u-boot port supports the following devices:
- serial
- eMMC, microSD
- Ethernet
- I2C
- Regulators
- Reset controller
- Clock controller
- USB Host
- ADC
U-Boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim2_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
> cd amlogic-u-boot
> make gxm_q200_v1_defconfig
> make
> export FIPDIR=$PWD/fip
Go back to mainline U-Boot source tree then :
> mkdir fip
> cp $FIPDIR/gxl/bl2.bin fip/
> cp $FIPDIR/gxl/acs.bin fip/
> cp $FIPDIR/gxl/bl21.bin fip/
> cp $FIPDIR/gxl/bl30.bin fip/
> cp $FIPDIR/gxl/bl301.bin fip/
> cp $FIPDIR/gxl/bl31.img fip/
> cp u-boot.bin fip/bl33.bin
> $FIPDIR/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
> $FIPDIR/blx_fix.sh \
fip/bl2_acs.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/bl21.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
> $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

14
board/amlogic/khadas-vim2/khadas-vim2.c → board/amlogic/q200/q200.c
View File

@ -18,18 +18,13 @@
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int board_init(void)
{
return 0;
}
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
/* Reset PHY on GPIOZ_14 */
clrbits_le32(GX_GPIO_EN(3), BIT(14));
@ -53,10 +48,3 @@ int misc_init_r(void)
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
meson_gx_init_reserved_memory(blob);
return 0;
}

6
board/amlogic/s400/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
S400
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/s400/
F: include/configs/s400.h
F: configs/s400_defconfig

2
board/amlogic/khadas-vim2/Makefile → board/amlogic/s400/Makefile
View File

@ -3,4 +3,4 @@
# (C) Copyright 2016 BayLibre, SAS
# Author: Neil Armstrong <narmstrong@baylibre.com>
obj-y := khadas-vim2.o
obj-y := s400.o

110
board/amlogic/s400/README Normal file
View File

@ -0,0 +1,110 @@
U-Boot for Amlogic S400
=======================
S400 is a reference board manufactured by Amlogic with the following
specifications:
- Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
- 1GB DDR4 SDRAM
- 10/100 Ethernet
- 2 x USB 2.0 Host
- eMMC
- Infrared receiver
- SDIO WiFi Module
- MIPI DSI Connector
- Audio HAT Connector
- PCI-E M.2 Connectors
Schematics are available from Amlogic on demand.
Currently the u-boot port supports the following devices:
- serial
- eMMC
- Ethernet
- I2C
- Regulators
- Reset controller
- Clock controller
- USB Host
- ADC
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make s400_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
> cd amlogic-u-boot
> make axg_s400_v1_defconfig
> make
> export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
> mkdir fip
> cp $FIPDIR/axg/bl2.bin fip/
> cp $FIPDIR/axg/acs.bin fip/
> cp $FIPDIR/axg/bl21.bin fip/
> cp $FIPDIR/axg/bl30.bin fip/
> cp $FIPDIR/axg/bl301.bin fip/
> cp $FIPDIR/axg/bl31.img fip/
> cp u-boot.bin fip/bl33.bin
> $FIPDIR/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
> $FIPDIR/blx_fix.sh \
fip/bl2_acs.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/bl21.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
--output fip/bl30_new.bin.enc \
--level v3 --type bl30
> $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
--output fip/bl31.img.enc \
--level v3 --type bl31
> $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
--output fip/bl33.bin.enc \
--level v3 --type bl33
> $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
--output fip/bl2.n.bin.sig
> $FIPDIR/axg/aml_encrypt_axg --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc --level v3
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

21
board/amlogic/s400/s400.c Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/axg.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#include <asm/arch/mem.h>
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
return 0;
}

1
configs/khadas-vim2_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXM=y
CONFIG_TARGET_KHADAS_VIM2=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim2"

1
configs/khadas-vim_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXL=y
CONFIG_TARGET_KHADAS_VIM=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim"

1
configs/libretech-cc_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXL=y
CONFIG_TARGET_LIBRETECH_CC=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-cc"

2
configs/nanopi-k2_defconfig
View File

@ -1,8 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXBB=y
CONFIG_TARGET_NANOPI_K2=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" nanopi-k2"

1
configs/odroid-c2_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXBB=y
CONFIG_TARGET_ODROID_C2=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-c2"

1
configs/p212_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXL=y
CONFIG_TARGET_P212=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p212"

38
configs/s400_defconfig Normal file
View File

@ -0,0 +1,38 @@
CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_AXG=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" s400"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y

2
drivers/clk/Makefile
View File

@ -9,8 +9,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/

6
drivers/clk/clk_meson.c
View File

@ -6,7 +6,7 @@
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock-gx.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <div64.h>
@ -79,7 +79,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
struct meson_gate gates[] = {
static struct meson_gate gates[] = {
/* Everything Else (EE) domain gates */
MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
@ -791,7 +791,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
return -ENOENT;
}
printf("clock %lu has rate %lu\n", id, rate);
debug("clock %lu has rate %lu\n", id, rate);
return rate;
}

316
drivers/clk/clk_meson_axg.c Normal file
View File

@ -0,0 +1,316 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
* (C) Copyright 2018 - BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <asm/arch/clock-axg.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
#include <div64.h>
#include <dt-bindings/clock/axg-clkc.h>
#include "clk_meson.h"
#define XTAL_RATE 24000000
struct meson_clk {
struct regmap *map;
};
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
static struct meson_gate gates[] = {
/* Everything Else (EE) domain gates */
MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
/* Always On (AO) domain gates */
MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
/* PLL Gates */
/* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
/* CLKID_CLK81 is critical for the system */
/* Peripheral Gates */
MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
};
static int meson_set_gate(struct clk *clk, bool on)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct meson_gate *gate;
if (clk->id >= ARRAY_SIZE(gates))
return -ENOENT;
gate = &gates[clk->id];
if (gate->reg == 0)
return 0;
regmap_update_bits(priv->map, gate->reg,
BIT(gate->bit), on ? BIT(gate->bit) : 0);
return 0;
}
static int meson_clk_enable(struct clk *clk)
{
return meson_set_gate(clk, true);
}
static int meson_clk_disable(struct clk *clk)
{
return meson_set_gate(clk, false);
}
static unsigned long meson_clk81_get_rate(struct clk *clk)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
unsigned long parent_rate;
uint reg;
int parents[] = {
-1,
-1,
CLKID_FCLK_DIV7,
CLKID_MPLL1,
CLKID_MPLL2,
CLKID_FCLK_DIV4,
CLKID_FCLK_DIV3,
CLKID_FCLK_DIV5
};
/* mux */
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
reg = (reg >> 12) & 7;
switch (reg) {
case 0:
parent_rate = XTAL_RATE;
break;
case 1:
return -ENOENT;
default:
parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
}
/* divider */
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
reg = reg & ((1 << 7) - 1);
return parent_rate / reg;
}
static long mpll_rate_from_params(unsigned long parent_rate,
unsigned long sdm,
unsigned long n2)
{
unsigned long divisor = (SDM_DEN * n2) + sdm;
if (n2 < N2_MIN)
return -EINVAL;
return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
}
static struct parm meson_mpll0_parm[3] = {
{HHI_MPLL_CNTL7, 0, 14}, /* psdm */
{HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
};
static struct parm meson_mpll1_parm[3] = {
{HHI_MPLL_CNTL8, 0, 14}, /* psdm */
{HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
};
static struct parm meson_mpll2_parm[3] = {
{HHI_MPLL_CNTL9, 0, 14}, /* psdm */
{HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
};
/*
* MultiPhase Locked Loops are outputs from a PLL with additional frequency
* scaling capabilities. MPLL rates are calculated as:
*
* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
*/
static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *psdm, *pn2;
unsigned long sdm, n2;
unsigned long parent_rate;
uint reg;
switch (id) {
case CLKID_MPLL0:
psdm = &meson_mpll0_parm[0];
pn2 = &meson_mpll0_parm[1];
break;
case CLKID_MPLL1:
psdm = &meson_mpll1_parm[0];
pn2 = &meson_mpll1_parm[1];
break;
case CLKID_MPLL2:
psdm = &meson_mpll2_parm[0];
pn2 = &meson_mpll2_parm[1];
break;
default:
return -ENOENT;
}
parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
regmap_read(priv->map, psdm->reg_off, &reg);
sdm = PARM_GET(psdm->width, psdm->shift, reg);
regmap_read(priv->map, pn2->reg_off, &reg);
n2 = PARM_GET(pn2->width, pn2->shift, reg);
return mpll_rate_from_params(parent_rate, sdm, n2);
}
static struct parm meson_fixed_pll_parm[3] = {
{HHI_MPLL_CNTL, 0, 9}, /* pm */
{HHI_MPLL_CNTL, 9, 5}, /* pn */
{HHI_MPLL_CNTL, 16, 2}, /* pod */
};
static struct parm meson_sys_pll_parm[3] = {
{HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
{HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
{HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
};
static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *pm, *pn, *pod;
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
u16 n, m, od;
uint reg;
switch (id) {
case CLKID_FIXED_PLL:
pm = &meson_fixed_pll_parm[0];
pn = &meson_fixed_pll_parm[1];
pod = &meson_fixed_pll_parm[2];
break;
case CLKID_SYS_PLL:
pm = &meson_sys_pll_parm[0];
pn = &meson_sys_pll_parm[1];
pod = &meson_sys_pll_parm[2];
break;
default:
return -ENOENT;
}
regmap_read(priv->map, pn->reg_off, &reg);
n = PARM_GET(pn->width, pn->shift, reg);
regmap_read(priv->map, pm->reg_off, &reg);
m = PARM_GET(pm->width, pm->shift, reg);
regmap_read(priv->map, pod->reg_off, &reg);
od = PARM_GET(pod->width, pod->shift, reg);
return ((parent_rate_mhz * m / n) >> od) * 1000000;
}
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
{
ulong rate;
switch (id) {
case CLKID_FIXED_PLL:
case CLKID_SYS_PLL:
rate = meson_pll_get_rate(clk, id);
break;
case CLKID_FCLK_DIV2:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
break;
case CLKID_FCLK_DIV3:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
break;
case CLKID_FCLK_DIV4:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
break;
case CLKID_FCLK_DIV5:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
break;
case CLKID_FCLK_DIV7:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
break;
case CLKID_MPLL0:
case CLKID_MPLL1:
case CLKID_MPLL2:
rate = meson_mpll_get_rate(clk, id);
break;
case CLKID_CLK81:
rate = meson_clk81_get_rate(clk);
break;
default:
if (gates[id].reg != 0) {
/* a clock gate */
rate = meson_clk81_get_rate(clk);
break;
}
return -ENOENT;
}
debug("clock %lu has rate %lu\n", id, rate);
return rate;
}
static ulong meson_clk_get_rate(struct clk *clk)
{
return meson_clk_get_rate_by_id(clk, clk->id);
}
static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
debug("meson-clk-axg: probed\n");
return 0;
}
static struct clk_ops meson_clk_ops = {
.disable = meson_clk_disable,
.enable = meson_clk_enable,
.get_rate = meson_clk_get_rate,
};
static const struct udevice_id meson_clk_ids[] = {
{ .compatible = "amlogic,axg-clkc" },
{ }
};
U_BOOT_DRIVER(meson_clk_axg) = {
.name = "meson_clk_axg",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
.priv_auto_alloc_size = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};

1
drivers/mmc/meson_gx_mmc.c
View File

@ -278,6 +278,7 @@ int meson_mmc_bind(struct udevice *dev)
static const struct udevice_id meson_mmc_match[] = {
{ .compatible = "amlogic,meson-gx-mmc" },
{ .compatible = "amlogic,meson-axg-mmc" },
{ /* sentinel */ }
};

2
drivers/net/designware.c
View File

@ -838,6 +838,8 @@ static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "altr,socfpga-stmmac" },
{ .compatible = "amlogic,meson6-dwmac" },
{ .compatible = "amlogic,meson-gx-dwmac" },
{ .compatible = "amlogic,meson-gxbb-dwmac" },
{ .compatible = "amlogic,meson-axg-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ }
};

18
drivers/pinctrl/meson/Kconfig
View File

@ -1,15 +1,27 @@
if ARCH_MESON
config PINCTRL_MESON
depends on PINCTRL_GENERIC
select PINCTRL_GENERIC
bool
config PINCTRL_MESON_GX_PMX
select PINCTRL_MESON
bool
config PINCTRL_MESON_AXG_PMX
select PINCTRL_MESON
bool
config PINCTRL_MESON_GXBB
bool "Amlogic Meson GXBB SoC pinctrl driver"
select PINCTRL_MESON
select PINCTRL_MESON_GX_PMX
config PINCTRL_MESON_GXL
bool "Amlogic Meson GXL SoC pinctrl driver"
select PINCTRL_MESON
select PINCTRL_MESON_GX_PMX
config PINCTRL_MESON_AXG
bool "Amlogic Meson AXG SoC pinctrl driver"
select PINCTRL_MESON_AXG_PMX
endif

3
drivers/pinctrl/meson/Makefile
View File

@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += pinctrl-meson.o
obj-$(CONFIG_PINCTRL_MESON_GX_PMX) += pinctrl-meson-gx-pmx.o
obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o

125
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Jerome Brunet <jbrunet@baylibre.com>
* Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
*/
#include <asm/gpio.h>
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include "pinctrl-meson-axg.h"
static int meson_axg_pmx_get_bank(struct udevice *dev, unsigned int pin,
struct meson_pmx_bank **bank)
{
int i;
struct meson_pinctrl *priv = dev_get_priv(dev);
struct meson_axg_pmx_data *pmx = priv->data->pmx_data;
for (i = 0; i < pmx->num_pmx_banks; i++)
if (pin >= pmx->pmx_banks[i].first &&
pin <= pmx->pmx_banks[i].last) {
*bank = &pmx->pmx_banks[i];
return 0;
}
return -EINVAL;
}
static int meson_axg_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
unsigned int pin,
unsigned int *reg,
unsigned int *offset)
{
int shift;
shift = pin - bank->first;
*reg = bank->reg + (bank->offset + (shift << 2)) / 32;
*offset = (bank->offset + (shift << 2)) % 32;
return 0;
}
static int meson_axg_pmx_update_function(struct udevice *dev,
unsigned int pin, unsigned int func)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
struct meson_pmx_bank *bank;
unsigned int offset;
unsigned int reg;
unsigned int tmp;
int ret;
ret = meson_axg_pmx_get_bank(dev, pin, &bank);
if (ret)
return ret;
meson_axg_pmx_calc_reg_and_offset(bank, pin, &reg, &offset);
tmp = readl(priv->reg_mux + (reg << 2));
tmp &= ~(0xf << offset);
tmp |= (func & 0xf) << offset;
writel(tmp, priv->reg_mux + (reg << 2));
return ret;
}
static int meson_axg_pinmux_group_set(struct udevice *dev,
unsigned int group_selector,
unsigned int func_selector)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
const struct meson_pmx_group *group;
const struct meson_pmx_func *func;
struct meson_pmx_axg_data *pmx_data;
int i, ret;
group = &priv->data->groups[group_selector];
pmx_data = (struct meson_pmx_axg_data *)group->data;
func = &priv->data->funcs[func_selector];
debug("pinmux: set group %s func %s\n", group->name, func->name);
for (i = 0; i < group->num_pins; i++) {
ret = meson_axg_pmx_update_function(dev, group->pins[i],
pmx_data->func);
if (ret)
return ret;
}
return 0;
}
const struct pinctrl_ops meson_axg_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
.get_functions_count = meson_pinmux_get_functions_count,
.get_function_name = meson_pinmux_get_function_name,
.pinmux_group_set = meson_axg_pinmux_group_set,
.set_state = pinctrl_generic_set_state,
};
static int meson_axg_gpio_request(struct udevice *dev,
unsigned int offset, const char *label)
{
return meson_axg_pmx_update_function(dev->parent, offset, 0);
}
static const struct dm_gpio_ops meson_axg_gpio_ops = {
.request = meson_axg_gpio_request,
.set_value = meson_gpio_set,
.get_value = meson_gpio_get,
.get_function = meson_gpio_get_direction,
.direction_input = meson_gpio_direction_input,
.direction_output = meson_gpio_direction_output,
};
const struct driver meson_axg_gpio_driver = {
.name = "meson-axg-gpio",
.id = UCLASS_GPIO,
.probe = meson_gpio_probe,
.ops = &meson_axg_gpio_ops,
};

979
drivers/pinctrl/meson/pinctrl-meson-axg.c Normal file
View File

@ -0,0 +1,979 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright (C) 2018 Neil Armstrong <narmstrong@baylibre.com>
*
* Based on code from Linux kernel:
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
#include "pinctrl-meson-axg.h"
#define EE_OFF 14
/* emmc */
static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
static const unsigned int emmc_clk_pins[] = {BOOT_8};
static const unsigned int emmc_cmd_pins[] = {BOOT_10};
static const unsigned int emmc_ds_pins[] = {BOOT_13};
/* nand */
static const unsigned int nand_ce0_pins[] = {BOOT_8};
static const unsigned int nand_ale_pins[] = {BOOT_9};
static const unsigned int nand_cle_pins[] = {BOOT_10};
static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
static const unsigned int nand_rb0_pins[] = {BOOT_13};
/* nor */
static const unsigned int nor_hold_pins[] = {BOOT_3};
static const unsigned int nor_d_pins[] = {BOOT_4};
static const unsigned int nor_q_pins[] = {BOOT_5};
static const unsigned int nor_c_pins[] = {BOOT_6};
static const unsigned int nor_wp_pins[] = {BOOT_9};
static const unsigned int nor_cs_pins[] = {BOOT_14};
/* sdio */
static const unsigned int sdio_d0_pins[] = {GPIOX_0};
static const unsigned int sdio_d1_pins[] = {GPIOX_1};
static const unsigned int sdio_d2_pins[] = {GPIOX_2};
static const unsigned int sdio_d3_pins[] = {GPIOX_3};
static const unsigned int sdio_clk_pins[] = {GPIOX_4};
static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
/* spi0 */
static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
/* spi1 */
static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
/* i2c0 */
static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
/* i2c1 */
static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
/* i2c2 */
static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
/* i2c3 */
static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
/* uart_a */
static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
/* uart_b */
static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
/* uart_ao_b */
static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
/* pwm_a */
static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
/* pwm_b */
static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
/* pwm_c */
static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
/* pwm_d */
static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
/* pwm_vs */
static const unsigned int pwm_vs_pins[] = {GPIOA_0};
/* spdif_in */
static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
/* spdif_out */
static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
/* jtag_ee */
static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
/* eth */
static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
/* pdm */
static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
static const unsigned int pdm_din0_pins[] = {GPIOA_15};
static const unsigned int pdm_din1_pins[] = {GPIOA_16};
static const unsigned int pdm_din2_pins[] = {GPIOA_17};
static const unsigned int pdm_din3_pins[] = {GPIOA_18};
/* mclk */
static const unsigned int mclk_c_pins[] = {GPIOA_0};
static const unsigned int mclk_b_pins[] = {GPIOA_1};
/* tdm */
static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
static const unsigned int tdma_fs_pins[] = {GPIOX_13};
static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
static const unsigned int tdma_din0_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
static const unsigned int tdma_din1_pins[] = {GPIOX_15};
static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
static struct meson_pmx_group meson_axg_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0, EE_OFF),
GPIO_GROUP(GPIOZ_1, EE_OFF),
GPIO_GROUP(GPIOZ_2, EE_OFF),
GPIO_GROUP(GPIOZ_3, EE_OFF),
GPIO_GROUP(GPIOZ_4, EE_OFF),
GPIO_GROUP(GPIOZ_5, EE_OFF),
GPIO_GROUP(GPIOZ_6, EE_OFF),
GPIO_GROUP(GPIOZ_7, EE_OFF),
GPIO_GROUP(GPIOZ_8, EE_OFF),
GPIO_GROUP(GPIOZ_9, EE_OFF),
GPIO_GROUP(GPIOZ_10, EE_OFF),
GPIO_GROUP(BOOT_0, EE_OFF),
GPIO_GROUP(BOOT_1, EE_OFF),
GPIO_GROUP(BOOT_2, EE_OFF),
GPIO_GROUP(BOOT_3, EE_OFF),
GPIO_GROUP(BOOT_4, EE_OFF),
GPIO_GROUP(BOOT_5, EE_OFF),
GPIO_GROUP(BOOT_6, EE_OFF),
GPIO_GROUP(BOOT_7, EE_OFF),
GPIO_GROUP(BOOT_8, EE_OFF),
GPIO_GROUP(BOOT_9, EE_OFF),
GPIO_GROUP(BOOT_10, EE_OFF),
GPIO_GROUP(BOOT_11, EE_OFF),
GPIO_GROUP(BOOT_12, EE_OFF),
GPIO_GROUP(BOOT_13, EE_OFF),
GPIO_GROUP(BOOT_14, EE_OFF),
GPIO_GROUP(GPIOA_0, EE_OFF),
GPIO_GROUP(GPIOA_1, EE_OFF),
GPIO_GROUP(GPIOA_2, EE_OFF),
GPIO_GROUP(GPIOA_3, EE_OFF),
GPIO_GROUP(GPIOA_4, EE_OFF),
GPIO_GROUP(GPIOA_5, EE_OFF),
GPIO_GROUP(GPIOA_6, EE_OFF),
GPIO_GROUP(GPIOA_7, EE_OFF),
GPIO_GROUP(GPIOA_8, EE_OFF),
GPIO_GROUP(GPIOA_9, EE_OFF),
GPIO_GROUP(GPIOA_10, EE_OFF),
GPIO_GROUP(GPIOA_11, EE_OFF),
GPIO_GROUP(GPIOA_12, EE_OFF),
GPIO_GROUP(GPIOA_13, EE_OFF),
GPIO_GROUP(GPIOA_14, EE_OFF),
GPIO_GROUP(GPIOA_15, EE_OFF),
GPIO_GROUP(GPIOA_16, EE_OFF),
GPIO_GROUP(GPIOA_17, EE_OFF),
GPIO_GROUP(GPIOA_19, EE_OFF),
GPIO_GROUP(GPIOA_20, EE_OFF),
GPIO_GROUP(GPIOX_0, EE_OFF),
GPIO_GROUP(GPIOX_1, EE_OFF),
GPIO_GROUP(GPIOX_2, EE_OFF),
GPIO_GROUP(GPIOX_3, EE_OFF),
GPIO_GROUP(GPIOX_4, EE_OFF),
GPIO_GROUP(GPIOX_5, EE_OFF),
GPIO_GROUP(GPIOX_6, EE_OFF),
GPIO_GROUP(GPIOX_7, EE_OFF),
GPIO_GROUP(GPIOX_8, EE_OFF),
GPIO_GROUP(GPIOX_9, EE_OFF),
GPIO_GROUP(GPIOX_10, EE_OFF),
GPIO_GROUP(GPIOX_11, EE_OFF),
GPIO_GROUP(GPIOX_12, EE_OFF),
GPIO_GROUP(GPIOX_13, EE_OFF),
GPIO_GROUP(GPIOX_14, EE_OFF),
GPIO_GROUP(GPIOX_15, EE_OFF),
GPIO_GROUP(GPIOX_16, EE_OFF),
GPIO_GROUP(GPIOX_17, EE_OFF),
GPIO_GROUP(GPIOX_18, EE_OFF),
GPIO_GROUP(GPIOX_19, EE_OFF),
GPIO_GROUP(GPIOX_20, EE_OFF),
GPIO_GROUP(GPIOX_21, EE_OFF),
GPIO_GROUP(GPIOX_22, EE_OFF),
GPIO_GROUP(GPIOY_0, EE_OFF),
GPIO_GROUP(GPIOY_1, EE_OFF),
GPIO_GROUP(GPIOY_2, EE_OFF),
GPIO_GROUP(GPIOY_3, EE_OFF),
GPIO_GROUP(GPIOY_4, EE_OFF),
GPIO_GROUP(GPIOY_5, EE_OFF),
GPIO_GROUP(GPIOY_6, EE_OFF),
GPIO_GROUP(GPIOY_7, EE_OFF),
GPIO_GROUP(GPIOY_8, EE_OFF),
GPIO_GROUP(GPIOY_9, EE_OFF),
GPIO_GROUP(GPIOY_10, EE_OFF),
GPIO_GROUP(GPIOY_11, EE_OFF),
GPIO_GROUP(GPIOY_12, EE_OFF),
GPIO_GROUP(GPIOY_13, EE_OFF),
GPIO_GROUP(GPIOY_14, EE_OFF),
GPIO_GROUP(GPIOY_15, EE_OFF),
/* bank BOOT */
GROUP(emmc_nand_d0, 1),
GROUP(emmc_nand_d1, 1),
GROUP(emmc_nand_d2, 1),
GROUP(emmc_nand_d3, 1),
GROUP(emmc_nand_d4, 1),
GROUP(emmc_nand_d5, 1),
GROUP(emmc_nand_d6, 1),
GROUP(emmc_nand_d7, 1),
GROUP(emmc_clk, 1),
GROUP(emmc_cmd, 1),
GROUP(emmc_ds, 1),
GROUP(nand_ce0, 2),
GROUP(nand_ale, 2),
GROUP(nand_cle, 2),
GROUP(nand_wen_clk, 2),
GROUP(nand_ren_wr, 2),
GROUP(nand_rb0, 2),
GROUP(nor_hold, 3),
GROUP(nor_d, 3),
GROUP(nor_q, 3),
GROUP(nor_c, 3),
GROUP(nor_wp, 3),
GROUP(nor_cs, 3),
/* bank GPIOZ */
GROUP(spi0_clk, 1),
GROUP(spi0_mosi, 1),
GROUP(spi0_miso, 1),
GROUP(spi0_ss0, 1),
GROUP(spi0_ss1, 1),
GROUP(spi0_ss2, 1),
GROUP(i2c0_sck, 1),
GROUP(i2c0_sda, 1),
GROUP(i2c1_sck_z, 1),
GROUP(i2c1_sda_z, 1),
GROUP(uart_rts_b_z, 2),
GROUP(uart_cts_b_z, 2),
GROUP(uart_tx_b_z, 2),
GROUP(uart_rx_b_z, 2),
GROUP(pwm_a_z, 2),
GROUP(pwm_b_z, 2),
GROUP(spdif_in_z, 3),
GROUP(spdif_out_z, 3),
GROUP(uart_ao_tx_b_z, 2),
GROUP(uart_ao_rx_b_z, 2),
GROUP(uart_ao_cts_b_z, 2),
GROUP(uart_ao_rts_b_z, 2),
/* bank GPIOX */
GROUP(sdio_d0, 1),
GROUP(sdio_d1, 1),
GROUP(sdio_d2, 1),
GROUP(sdio_d3, 1),
GROUP(sdio_clk, 1),
GROUP(sdio_cmd, 1),
GROUP(i2c1_sck_x, 1),
GROUP(i2c1_sda_x, 1),
GROUP(i2c2_sck_x, 1),
GROUP(i2c2_sda_x, 1),
GROUP(uart_rts_a, 1),
GROUP(uart_cts_a, 1),
GROUP(uart_tx_a, 1),
GROUP(uart_rx_a, 1),
GROUP(uart_rts_b_x, 2),
GROUP(uart_cts_b_x, 2),
GROUP(uart_tx_b_x, 2),
GROUP(uart_rx_b_x, 2),
GROUP(jtag_tdo_x, 2),
GROUP(jtag_tdi_x, 2),
GROUP(jtag_clk_x, 2),
GROUP(jtag_tms_x, 2),
GROUP(spi1_clk_x, 4),
GROUP(spi1_mosi_x, 4),
GROUP(spi1_miso_x, 4),
GROUP(spi1_ss0_x, 4),
GROUP(pwm_a_x18, 3),
GROUP(pwm_a_x20, 1),
GROUP(pwm_b_x, 3),
GROUP(pwm_c_x10, 3),
GROUP(pwm_c_x17, 3),
GROUP(pwm_d_x11, 3),
GROUP(pwm_d_x16, 3),
GROUP(eth_txd0_x, 4),
GROUP(eth_txd1_x, 4),
GROUP(eth_txen_x, 4),
GROUP(eth_rgmii_rx_clk_x, 4),
GROUP(eth_rxd0_x, 4),
GROUP(eth_rxd1_x, 4),
GROUP(eth_rx_dv_x, 4),
GROUP(eth_mdio_x, 4),
GROUP(eth_mdc_x, 4),
GROUP(tdma_sclk, 1),
GROUP(tdma_sclk_slv, 2),
GROUP(tdma_fs, 1),
GROUP(tdma_fs_slv, 2),
GROUP(tdma_din0, 1),
GROUP(tdma_dout0_x14, 2),
GROUP(tdma_dout0_x15, 1),
GROUP(tdma_dout1, 2),
GROUP(tdma_din1, 3),
/* bank GPIOY */
GROUP(eth_txd0_y, 1),
GROUP(eth_txd1_y, 1),
GROUP(eth_txen_y, 1),
GROUP(eth_rgmii_rx_clk_y, 1),
GROUP(eth_rxd0_y, 1),
GROUP(eth_rxd1_y, 1),
GROUP(eth_rx_dv_y, 1),
GROUP(eth_mdio_y, 1),
GROUP(eth_mdc_y, 1),
GROUP(eth_rxd2_rgmii, 1),
GROUP(eth_rxd3_rgmii, 1),
GROUP(eth_rgmii_tx_clk, 1),
GROUP(eth_txd2_rgmii, 1),
GROUP(eth_txd3_rgmii, 1),
/* bank GPIOA */
GROUP(spdif_out_a1, 4),
GROUP(spdif_out_a11, 3),
GROUP(spdif_out_a19, 2),
GROUP(spdif_out_a20, 1),
GROUP(spdif_in_a1, 3),
GROUP(spdif_in_a7, 3),
GROUP(spdif_in_a19, 1),
GROUP(spdif_in_a20, 2),
GROUP(spi1_clk_a, 3),
GROUP(spi1_mosi_a, 3),
GROUP(spi1_miso_a, 3),
GROUP(spi1_ss0_a, 3),
GROUP(spi1_ss1, 3),
GROUP(pwm_a_a, 3),
GROUP(pwm_b_a, 3),
GROUP(pwm_c_a, 3),
GROUP(pwm_vs, 2),
GROUP(i2c2_sda_a, 3),
GROUP(i2c2_sck_a, 3),
GROUP(i2c3_sda_a6, 4),
GROUP(i2c3_sck_a7, 4),
GROUP(i2c3_sda_a12, 4),
GROUP(i2c3_sck_a13, 4),
GROUP(i2c3_sda_a19, 4),
GROUP(i2c3_sck_a20, 4),
GROUP(pdm_dclk_a14, 1),
GROUP(pdm_dclk_a19, 3),
GROUP(pdm_din0, 1),
GROUP(pdm_din1, 1),
GROUP(pdm_din2, 1),
GROUP(pdm_din3, 1),
GROUP(mclk_c, 1),
GROUP(mclk_b, 1),
GROUP(tdmc_sclk, 1),
GROUP(tdmc_sclk_slv, 2),
GROUP(tdmc_fs, 1),
GROUP(tdmc_fs_slv, 2),
GROUP(tdmc_din0, 2),
GROUP(tdmc_dout0, 1),
GROUP(tdmc_din1, 2),
GROUP(tdmc_dout1, 1),
GROUP(tdmc_din2, 2),
GROUP(tdmc_dout2, 1),
GROUP(tdmc_din3, 2),
GROUP(tdmc_dout3, 1),
GROUP(tdmb_sclk, 1),
GROUP(tdmb_sclk_slv, 2),
GROUP(tdmb_fs, 1),
GROUP(tdmb_fs_slv, 2),
GROUP(tdmb_din0, 2),
GROUP(tdmb_dout0, 1),
GROUP(tdmb_din1, 2),
GROUP(tdmb_dout1, 1),
GROUP(tdmb_din2, 2),
GROUP(tdmb_dout2, 1),
GROUP(tdmb_din3, 2),
GROUP(tdmb_dout3, 1),
};
/* uart_ao_a */
static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
/* uart_ao_b */
static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
/* i2c_ao */
static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
/* i2c_ao_slave */
static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
/* ir_in */
static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
/* ir_out */
static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
/* pwm_ao_a */
static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
/* pwm_ao_b */
static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
/* pwm_ao_c */
static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
/* pwm_ao_d */
static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
/* jtag_ao */
static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
static struct meson_pmx_group meson_axg_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0, 0),
GPIO_GROUP(GPIOAO_1, 0),
GPIO_GROUP(GPIOAO_2, 0),
GPIO_GROUP(GPIOAO_3, 0),
GPIO_GROUP(GPIOAO_4, 0),
GPIO_GROUP(GPIOAO_5, 0),
GPIO_GROUP(GPIOAO_6, 0),
GPIO_GROUP(GPIOAO_7, 0),
GPIO_GROUP(GPIOAO_8, 0),
GPIO_GROUP(GPIOAO_9, 0),
GPIO_GROUP(GPIOAO_10, 0),
GPIO_GROUP(GPIOAO_11, 0),
GPIO_GROUP(GPIOAO_12, 0),
GPIO_GROUP(GPIOAO_13, 0),
GPIO_GROUP(GPIO_TEST_N, 0),
/* bank AO */
GROUP(uart_ao_tx_a, 1),
GROUP(uart_ao_rx_a, 1),
GROUP(uart_ao_cts_a, 2),
GROUP(uart_ao_rts_a, 2),
GROUP(uart_ao_tx_b, 1),
GROUP(uart_ao_rx_b, 1),
GROUP(uart_ao_cts_b, 1),
GROUP(uart_ao_rts_b, 1),
GROUP(i2c_ao_sck_4, 2),
GROUP(i2c_ao_sda_5, 2),
GROUP(i2c_ao_sck_8, 2),
GROUP(i2c_ao_sda_9, 2),
GROUP(i2c_ao_sck_10, 2),
GROUP(i2c_ao_sda_11, 2),
GROUP(i2c_ao_slave_sck, 1),
GROUP(i2c_ao_slave_sda, 1),
GROUP(remote_input_ao, 1),
GROUP(remote_out_ao, 1),
GROUP(pwm_ao_a, 3),
GROUP(pwm_ao_b_ao2, 3),
GROUP(pwm_ao_b_ao12, 3),
GROUP(pwm_ao_c_ao8, 3),
GROUP(pwm_ao_c_ao13, 3),
GROUP(pwm_ao_d, 3),
GROUP(jtag_ao_tdi, 4),
GROUP(jtag_ao_tdo, 4),
GROUP(jtag_ao_clk, 4),
GROUP(jtag_ao_tms, 4),
};
static const char * const gpio_periphs_groups[] = {
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
"GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
"GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
"GPIOA_20",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
"GPIOX_20", "GPIOX_21", "GPIOX_22",
"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
"GPIOY_15",
};
static const char * const emmc_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_cmd", "emmc_ds",
};
static const char * const nand_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"nand_ce0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_wr", "nand_rb0",
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs",
"nor_hold", "nor_wp",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_cmd", "sdio_clk",
};
static const char * const spi0_groups[] = {
"spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
"spi0_ss1", "spi0_ss2"
};
static const char * const spi1_groups[] = {
"spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
"spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
"spi1_ss1"
};
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
static const char * const uart_b_groups[] = {
"uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
};
static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
};
static const char * const i2c0_groups[] = {
"i2c0_sck", "i2c0_sda",
};
static const char * const i2c1_groups[] = {
"i2c1_sck_z", "i2c1_sda_z",
"i2c1_sck_x", "i2c1_sda_x",
};
static const char * const i2c2_groups[] = {
"i2c2_sck_x", "i2c2_sda_x",
"i2c2_sda_a", "i2c2_sck_a",
};
static const char * const i2c3_groups[] = {
"i2c3_sda_a6", "i2c3_sck_a7",
"i2c3_sda_a12", "i2c3_sck_a13",
"i2c3_sda_a19", "i2c3_sck_a20",
};
static const char * const eth_groups[] = {
"eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
"eth_txd2_rgmii", "eth_txd3_rgmii",
"eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
"eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
"eth_mdc_x",
"eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
"eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
"eth_mdc_y",
};
static const char * const pwm_a_groups[] = {
"pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b_z", "pwm_b_x", "pwm_b_a",
};
static const char * const pwm_c_groups[] = {
"pwm_c_x10", "pwm_c_x17", "pwm_c_a",
};
static const char * const pwm_d_groups[] = {
"pwm_d_x11", "pwm_d_x16",
};
static const char * const pwm_vs_groups[] = {
"pwm_vs",
};
static const char * const spdif_out_groups[] = {
"spdif_out_z", "spdif_out_a1", "spdif_out_a11",
"spdif_out_a19", "spdif_out_a20",
};
static const char * const spdif_in_groups[] = {
"spdif_in_z", "spdif_in_a1", "spdif_in_a7",
"spdif_in_a19", "spdif_in_a20",
};
static const char * const jtag_ee_groups[] = {
"jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
"jtag_tms_x",
};
static const char * const pdm_groups[] = {
"pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
"pdm_dclk_a14", "pdm_dclk_a19",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
"GPIO_TEST_N",
};
static const char * const uart_ao_a_groups[] = {
"uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
};
static const char * const uart_ao_b_groups[] = {
"uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
};
static const char * const i2c_ao_groups[] = {
"i2c_ao_sck_4", "i2c_ao_sda_5",
"i2c_ao_sck_8", "i2c_ao_sda_9",
"i2c_ao_sck_10", "i2c_ao_sda_11",
};
static const char * const i2c_ao_slave_groups[] = {
"i2c_ao_slave_sck", "i2c_ao_slave_sda",
};
static const char * const remote_input_ao_groups[] = {
"remote_input_ao",
};
static const char * const remote_out_ao_groups[] = {
"remote_out_ao",
};
static const char * const pwm_ao_a_groups[] = {
"pwm_ao_a",
};
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b_ao2", "pwm_ao_b_ao12",
};
static const char * const pwm_ao_c_groups[] = {
"pwm_ao_c_ao8", "pwm_ao_c_ao13",
};
static const char * const pwm_ao_d_groups[] = {
"pwm_ao_d",
};
static const char * const jtag_ao_groups[] = {
"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
};
static const char * const mclk_c_groups[] = {
"mclk_c",
};
static const char * const mclk_b_groups[] = {
"mclk_b",
};
static const char * const tdma_groups[] = {
"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
"tdma_din1",
};
static const char * const tdmc_groups[] = {
"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
"tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1",
"tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3",
};
static const char * const tdmb_groups[] = {
"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
"tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1",
"tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3",
};
static struct meson_pmx_func meson_axg_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(spi0),
FUNCTION(spi1),
FUNCTION(sdio),
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_ao_b_z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(eth),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_vs),
FUNCTION(spdif_out),
FUNCTION(spdif_in),
FUNCTION(jtag_ee),
FUNCTION(pdm),
FUNCTION(mclk_b),
FUNCTION(mclk_c),
FUNCTION(tdma),
FUNCTION(tdmb),
FUNCTION(tdmc),
};
static struct meson_pmx_func meson_axg_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao_a),
FUNCTION(uart_ao_b),
FUNCTION(i2c_ao),
FUNCTION(i2c_ao_slave),
FUNCTION(remote_input_ao),
FUNCTION(remote_out_ao),
FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
FUNCTION(pwm_ao_c),
FUNCTION(pwm_ao_d),
FUNCTION(jtag_ao),
};
static struct meson_bank meson_axg_periphs_banks[] = {
/* name first last pullen pull dir out in */
BANK("Z", GPIOZ_0, GPIOZ_10, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
BANK("BOOT", BOOT_0, BOOT_14, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("A", GPIOA_0, GPIOA_20, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
BANK("X", GPIOX_0, GPIOX_22, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
BANK("Y", GPIOY_0, GPIOY_15, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
};
static struct meson_bank meson_axg_aobus_banks[] = {
/* name first last pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0),
BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0),
BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
};
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
.pmx_banks = meson_axg_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
};
static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
};
static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
.pmx_banks = meson_axg_aobus_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
};
struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
.pin_base = 11,
.groups = meson_axg_periphs_groups,
.funcs = meson_axg_periphs_functions,
.banks = meson_axg_periphs_banks,
.num_pins = 100,
.num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
.num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
.gpio_driver = &meson_axg_gpio_driver,
.pmx_data = &meson_axg_periphs_pmx_banks_data,
};
struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
.name = "aobus-banks",
.pin_base = 0,
.groups = meson_axg_aobus_groups,
.funcs = meson_axg_aobus_functions,
.banks = meson_axg_aobus_banks,
.num_pins = 14,
.num_groups = ARRAY_SIZE(meson_axg_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_axg_aobus_functions),
.num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
.gpio_driver = &meson_axg_gpio_driver,
.pmx_data = &meson_axg_aobus_pmx_banks_data,
};
static const struct udevice_id meson_axg_pinctrl_match[] = {
{
.compatible = "amlogic,meson-axg-periphs-pinctrl",
.data = (ulong)&meson_axg_periphs_pinctrl_data,
},
{
.compatible = "amlogic,meson-axg-aobus-pinctrl",
.data = (ulong)&meson_axg_aobus_pinctrl_data,
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(meson_axg_pinctrl) = {
.name = "meson-axg-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(meson_axg_pinctrl_match),
.probe = meson_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
.ops = &meson_axg_pinctrl_ops,
};

66
drivers/pinctrl/meson/pinctrl-meson-axg.h Normal file
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@ -0,0 +1,66 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
* Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
*/
#ifndef __PINCTRL_MESON_AXG_H__
#define __PINCTRL_MESON_AXG_H__
#include "pinctrl-meson.h"
struct meson_pmx_bank {
const char *name;
unsigned int first;
unsigned int last;
unsigned int reg;
unsigned int offset;
};
struct meson_axg_pmx_data {
struct meson_pmx_bank *pmx_banks;
unsigned int num_pmx_banks;
};
#define BANK_PMX(n, f, l, r, o) \
{ \
.name = n, \
.first = f, \
.last = l, \
.reg = r, \
.offset = o, \
}
struct meson_pmx_axg_data {
unsigned int func;
};
#define PMX_DATA(f) \
{ \
.func = f, \
}
#define GROUP(grp, f) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.data = (const struct meson_pmx_axg_data[]){ \
PMX_DATA(f), \
}, \
}
#define GPIO_GROUP(gpio, b) \
{ \
.name = #gpio, \
.pins = (const unsigned int[]){ PIN(gpio, b) }, \
.num_pins = 1, \
.data = (const struct meson_pmx_axg_data[]){ \
PMX_DATA(0), \
}, \
}
extern const struct pinctrl_ops meson_axg_pinctrl_ops;
extern const struct driver meson_axg_gpio_driver;
#endif /* __PINCTRL_MESON_AXG_H__ */

97
drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c Normal file
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@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
*/
#include <asm/gpio.h>
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include "pinctrl-meson-gx.h"
static void meson_gx_pinmux_disable_other_groups(struct meson_pinctrl *priv,
unsigned int pin,
int sel_group)
{
struct meson_pmx_group *group;
struct meson_gx_pmx_data *pmx_data;
void __iomem *addr;
int i, j;
for (i = 0; i < priv->data->num_groups; i++) {
group = &priv->data->groups[i];
pmx_data = (struct meson_gx_pmx_data *)group->data;
if (pmx_data->is_gpio || i == sel_group)
continue;
for (j = 0; j < group->num_pins; j++) {
if (group->pins[j] == pin) {
/* We have found a group using the pin */
debug("pinmux: disabling %s\n", group->name);
addr = priv->reg_mux + pmx_data->reg * 4;
writel(readl(addr) & ~BIT(pmx_data->bit), addr);
}
}
}
}
static int meson_gx_pinmux_group_set(struct udevice *dev,
unsigned int group_selector,
unsigned int func_selector)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
const struct meson_pmx_group *group;
const struct meson_pmx_func *func;
struct meson_gx_pmx_data *pmx_data;
void __iomem *addr;
int i;
group = &priv->data->groups[group_selector];
pmx_data = (struct meson_gx_pmx_data *)group->data;
func = &priv->data->funcs[func_selector];
debug("pinmux: set group %s func %s\n", group->name, func->name);
/*
* Disable groups using the same pins.
* The selected group is not disabled to avoid glitches.
*/
for (i = 0; i < group->num_pins; i++) {
meson_gx_pinmux_disable_other_groups(priv,
group->pins[i],
group_selector);
}
/* Function 0 (GPIO) doesn't need any additional setting */
if (func_selector) {
addr = priv->reg_mux + pmx_data->reg * 4;
writel(readl(addr) | BIT(pmx_data->bit), addr);
}
return 0;
}
const struct pinctrl_ops meson_gx_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
.get_functions_count = meson_pinmux_get_functions_count,
.get_function_name = meson_pinmux_get_function_name,
.pinmux_group_set = meson_gx_pinmux_group_set,
.set_state = pinctrl_generic_set_state,
};
static const struct dm_gpio_ops meson_gx_gpio_ops = {
.set_value = meson_gpio_set,
.get_value = meson_gpio_get,
.get_function = meson_gpio_get_direction,
.direction_input = meson_gpio_direction_input,
.direction_output = meson_gpio_direction_output,
};
const struct driver meson_gx_gpio_driver = {
.name = "meson-gx-gpio",
.id = UCLASS_GPIO,
.probe = meson_gpio_probe,
.ops = &meson_gx_gpio_ops,
};

48
drivers/pinctrl/meson/pinctrl-meson-gx.h Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
* Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __PINCTRL_MESON_GX_H__
#define __PINCTRL_MESON_GX_H__
#include "pinctrl-meson.h"
struct meson_gx_pmx_data {
bool is_gpio;
unsigned int reg;
unsigned int bit;
};
#define PMX_DATA(r, b, g) \
{ \
.reg = r, \
.bit = b, \
.is_gpio = g, \
}
#define GROUP(grp, r, b) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.data = (const struct meson_gx_pmx_data[]){ \
PMX_DATA(r, b, false), \
}, \
}
#define GPIO_GROUP(gpio, b) \
{ \
.name = #gpio, \
.pins = (const unsigned int[]){ PIN(gpio, b) }, \
.num_pins = 1, \
.data = (const struct meson_gx_pmx_data[]){ \
PMX_DATA(0, 0, true), \
}, \
}
extern const struct pinctrl_ops meson_gx_pinctrl_ops;
extern const struct driver meson_gx_gpio_driver;
#endif /* __PINCTRL_MESON_GX_H__ */

6
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
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@ -11,7 +11,7 @@
#include <dm/pinctrl.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-gx.h"
#define EE_OFF 15
@ -417,6 +417,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
.gpio_driver = &meson_gx_gpio_driver,
};
struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
@ -429,6 +430,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
.gpio_driver = &meson_gx_gpio_driver,
};
static const struct udevice_id meson_gxbb_pinctrl_match[] = {
@ -449,5 +451,5 @@ U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
.of_match = of_match_ptr(meson_gxbb_pinctrl_match),
.probe = meson_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
.ops = &meson_pinctrl_ops,
.ops = &meson_gx_pinctrl_ops,
};

6
drivers/pinctrl/meson/pinctrl-meson-gxl.c
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@ -11,7 +11,7 @@
#include <dm/pinctrl.h>
#include <dt-bindings/gpio/meson-gxl-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-gx.h"
#define EE_OFF 11
@ -699,6 +699,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
.gpio_driver = &meson_gx_gpio_driver,
};
struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
@ -711,6 +712,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
.num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
.gpio_driver = &meson_gx_gpio_driver,
};
static const struct udevice_id meson_gxl_pinctrl_match[] = {
@ -731,5 +733,5 @@ U_BOOT_DRIVER(meson_gxl_pinctrl) = {
.of_match = of_match_ptr(meson_gxl_pinctrl_match),
.probe = meson_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
.ops = &meson_pinctrl_ops,
.ops = &meson_gx_pinctrl_ops,
};

109
drivers/pinctrl/meson/pinctrl-meson.c
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@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
static const char *meson_pinctrl_dummy_name = "_dummy";
static int meson_pinctrl_get_groups_count(struct udevice *dev)
int meson_pinctrl_get_groups_count(struct udevice *dev)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
return priv->data->num_groups;
}
static const char *meson_pinctrl_get_group_name(struct udevice *dev,
unsigned selector)
const char *meson_pinctrl_get_group_name(struct udevice *dev,
unsigned int selector)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
@ -38,87 +38,21 @@ static const char *meson_pinctrl_get_group_name(struct udevice *dev,
return priv->data->groups[selector].name;
}
static int meson_pinmux_get_functions_count(struct udevice *dev)
int meson_pinmux_get_functions_count(struct udevice *dev)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
return priv->data->num_funcs;
}
static const char *meson_pinmux_get_function_name(struct udevice *dev,
unsigned selector)
const char *meson_pinmux_get_function_name(struct udevice *dev,
unsigned int selector)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
return priv->data->funcs[selector].name;
}
static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
unsigned int pin, int sel_group)
{
struct meson_pmx_group *group;
void __iomem *addr;
int i, j;
for (i = 0; i < priv->data->num_groups; i++) {
group = &priv->data->groups[i];
if (group->is_gpio || i == sel_group)
continue;
for (j = 0; j < group->num_pins; j++) {
if (group->pins[j] == pin) {
/* We have found a group using the pin */
debug("pinmux: disabling %s\n", group->name);
addr = priv->reg_mux + group->reg * 4;
writel(readl(addr) & ~BIT(group->bit), addr);
}
}
}
}
static int meson_pinmux_group_set(struct udevice *dev,
unsigned group_selector,
unsigned func_selector)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
const struct meson_pmx_group *group;
const struct meson_pmx_func *func;
void __iomem *addr;
int i;
group = &priv->data->groups[group_selector];
func = &priv->data->funcs[func_selector];
debug("pinmux: set group %s func %s\n", group->name, func->name);
/*
* Disable groups using the same pins.
* The selected group is not disabled to avoid glitches.
*/
for (i = 0; i < group->num_pins; i++) {
meson_pinmux_disable_other_groups(priv,
group->pins[i],
group_selector);
}
/* Function 0 (GPIO) doesn't need any additional setting */
if (func_selector) {
addr = priv->reg_mux + group->reg * 4;
writel(readl(addr) | BIT(group->bit), addr);
}
return 0;
}
const struct pinctrl_ops meson_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
.get_functions_count = meson_pinmux_get_functions_count,
.get_function_name = meson_pinmux_get_function_name,
.pinmux_group_set = meson_pinmux_group_set,
.set_state = pinctrl_generic_set_state,
};
static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
enum meson_reg_type reg_type,
unsigned int *reg, unsigned int *bit)
@ -149,7 +83,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
return 0;
}
static int meson_gpio_get(struct udevice *dev, unsigned int offset)
int meson_gpio_get(struct udevice *dev, unsigned int offset)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
@ -162,7 +96,7 @@ static int meson_gpio_get(struct udevice *dev, unsigned int offset)
return !!(readl(priv->reg_gpio + reg) & BIT(bit));
}
static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
@ -177,7 +111,7 @@ static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
return 0;
}
static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit, val;
@ -192,7 +126,7 @@ static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
}
static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
@ -207,8 +141,8 @@ static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
return 0;
}
static int meson_gpio_direction_output(struct udevice *dev,
unsigned int offset, int value)
int meson_gpio_direction_output(struct udevice *dev,
unsigned int offset, int value)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
@ -229,7 +163,7 @@ static int meson_gpio_direction_output(struct udevice *dev,
return 0;
}
static int meson_gpio_probe(struct udevice *dev)
int meson_gpio_probe(struct udevice *dev)
{
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
struct gpio_dev_priv *uc_priv;
@ -241,21 +175,6 @@ static int meson_gpio_probe(struct udevice *dev)
return 0;
}
static const struct dm_gpio_ops meson_gpio_ops = {
.set_value = meson_gpio_set,
.get_value = meson_gpio_get,
.get_function = meson_gpio_get_direction,
.direction_input = meson_gpio_direction_input,
.direction_output = meson_gpio_direction_output,
};
static struct driver meson_gpio_driver = {
.name = "meson-gpio",
.id = UCLASS_GPIO,
.probe = meson_gpio_probe,
.ops = &meson_gpio_ops,
};
static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
{
int index, len = 0;
@ -334,7 +253,7 @@ int meson_pinctrl_probe(struct udevice *dev)
sprintf(name, "meson-gpio");
/* Create child device UCLASS_GPIO and bind it */
device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
dev_set_of_offset(gpio_dev, gpio);
return 0;

37
drivers/pinctrl/meson/pinctrl-meson.h
View File

@ -12,9 +12,7 @@ struct meson_pmx_group {
const char *name;
const unsigned int *pins;
unsigned int num_pins;
bool is_gpio;
unsigned int reg;
unsigned int bit;
const void *data;
};
struct meson_pmx_func {
@ -33,6 +31,8 @@ struct meson_pinctrl_data {
unsigned int num_groups;
unsigned int num_funcs;
unsigned int num_banks;
const struct driver *gpio_driver;
void *pmx_data;
};
struct meson_pinctrl {
@ -89,23 +89,6 @@ struct meson_bank {
#define PIN(x, b) (b + x)
#define GROUP(grp, r, b) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
}
#define GPIO_GROUP(gpio, b) \
{ \
.name = #gpio, \
.pins = (const unsigned int[]){ PIN(gpio, b) }, \
.num_pins = 1, \
.is_gpio = true, \
}
#define FUNCTION(fn) \
{ \
.name = #fn, \
@ -131,6 +114,20 @@ struct meson_bank {
extern const struct pinctrl_ops meson_pinctrl_ops;
int meson_pinctrl_get_groups_count(struct udevice *dev);
const char *meson_pinctrl_get_group_name(struct udevice *dev,
unsigned int selector);
int meson_pinmux_get_functions_count(struct udevice *dev);
const char *meson_pinmux_get_function_name(struct udevice *dev,
unsigned int selector);
int meson_pinctrl_probe(struct udevice *dev);
int meson_gpio_get(struct udevice *dev, unsigned int offset);
int meson_gpio_set(struct udevice *dev, unsigned int offset, int value);
int meson_gpio_get_direction(struct udevice *dev, unsigned int offset);
int meson_gpio_direction_input(struct udevice *dev, unsigned int offset);
int meson_gpio_direction_output(struct udevice *dev, unsigned int offset,
int value);
int meson_gpio_probe(struct udevice *dev);
#endif /* __PINCTRL_MESON_H__ */

16
include/configs/khadas-vim.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for Khadas VIM
*
* Copyright (C) 2017 Baylibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

18
include/configs/khadas-vim2.h
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@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for Khadas VIM2
*
* Copyright (C) 2017 Baylibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MISC_INIT_R
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxm-khadas-vim2.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

16
include/configs/libretech-cc.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for LibreTech CC
*
* Copyright (C) 2017 Baylibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

57
include/configs/meson-gx-common.h → include/configs/meson64.h
View File

@ -1,11 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for Amlogic Meson GX SoCs
* Configuration for Amlogic Meson 64bits SoCs
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*/
#ifndef __MESON_GX_COMMON_CONFIG_H
#define __MESON_GX_COMMON_CONFIG_H
#ifndef __MESON64_CONFIG_H
#define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */
#if defined(CONFIG_MESON_AXG)
#define GICD_BASE 0xffc01000
#define GICC_BASE 0xffc02000
#else /* MESON GXL and GXBB */
#define GICD_BASE 0xc4301000
#define GICC_BASE 0xc4302000
#endif
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
@ -17,10 +26,19 @@
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xc4301000
#define GICC_BASE 0xc4302000
/* ROM USB boot support, auto-execute boot.scr at scriptaddr */
#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
"bootcmd_romusb=" \
"if test \"${boot_source}\" = \"usb\" && " \
"test -n \"${scriptaddr}\"; then " \
"echo '(ROM USB boot)'; " \
"source ${scriptaddr}; " \
"fi\0"
#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \
"romusb "
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
@ -28,25 +46,28 @@
#define BOOT_TARGET_DEVICES_USB(func)
#endif
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#endif
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_addr_r=0x08008000\0" \
"scriptaddr=0x08000000\0" \
"kernel_addr_r=0x08080000\0" \
"pxefile_addr_r=0x01080000\0" \
"ramdisk_addr_r=0x13000000\0" \
"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
BOOTENV
#endif
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_addr_r=0x01000000\0" \
"scriptaddr=0x1f000000\0" \
"kernel_addr_r=0x01080000\0" \
"pxefile_addr_r=0x01080000\0" \
"ramdisk_addr_r=0x13000000\0" \
MESON_FDTFILE_SETTING \
BOOTENV
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */
#endif /* __MESON_GX_COMMON_CONFIG_H */
#endif /* __MESON64_CONFIG_H */

16
include/configs/nanopi-k2.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for NANOPI-K2
* (C) Copyright 2018 Thomas McKahan
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Serial setup */
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-nanopi-k2.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

16
include/configs/odroid-c2.h
View File

@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for ODROID-C2
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Serial setup */
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

18
include/configs/p212.h
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@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for Amlogic P212
*
* Copyright (C) 2017 Baylibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Serial setup */
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
#include <configs/meson-gx-common.h>
#endif /* __CONFIG_H */

26
include/dt-bindings/clock/axg-aoclkc.h Normal file
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@ -0,0 +1,26 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
#define CLKID_AO_REMOTE 0
#define CLKID_AO_I2C_MASTER 1
#define CLKID_AO_I2C_SLAVE 2
#define CLKID_AO_UART1 3
#define CLKID_AO_UART2 4
#define CLKID_AO_IR_BLASTER 5
#define CLKID_AO_SAR_ADC 6
#define CLKID_AO_CLK81 7
#define CLKID_AO_SAR_ADC_SEL 8
#define CLKID_AO_SAR_ADC_DIV 9
#define CLKID_AO_SAR_ADC_CLK 10
#define CLKID_AO_ALT_XTAL 11
#endif

94
include/dt-bindings/clock/axg-audio-clkc.h Normal file
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@ -0,0 +1,94 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2018 Baylibre SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31
#define AUD_CLKID_TDMIN_B 32
#define AUD_CLKID_TDMIN_C 33
#define AUD_CLKID_TDMIN_LB 34
#define AUD_CLKID_TDMOUT_A 35
#define AUD_CLKID_TDMOUT_B 36
#define AUD_CLKID_TDMOUT_C 37
#define AUD_CLKID_FRDDR_A 38
#define AUD_CLKID_FRDDR_B 39
#define AUD_CLKID_FRDDR_C 40
#define AUD_CLKID_TODDR_A 41
#define AUD_CLKID_TODDR_B 42
#define AUD_CLKID_TODDR_C 43
#define AUD_CLKID_LOOPBACK 44
#define AUD_CLKID_SPDIFIN 45
#define AUD_CLKID_SPDIFOUT 46
#define AUD_CLKID_RESAMPLE 47
#define AUD_CLKID_POWER_DETECT 48
#define AUD_CLKID_MST_A_MCLK 49
#define AUD_CLKID_MST_B_MCLK 50
#define AUD_CLKID_MST_C_MCLK 51
#define AUD_CLKID_MST_D_MCLK 52
#define AUD_CLKID_MST_E_MCLK 53
#define AUD_CLKID_MST_F_MCLK 54
#define AUD_CLKID_SPDIFOUT_CLK 55
#define AUD_CLKID_SPDIFIN_CLK 56
#define AUD_CLKID_PDM_DCLK 57
#define AUD_CLKID_PDM_SYSCLK 58
#define AUD_CLKID_MST_A_SCLK 79
#define AUD_CLKID_MST_B_SCLK 80
#define AUD_CLKID_MST_C_SCLK 81
#define AUD_CLKID_MST_D_SCLK 82
#define AUD_CLKID_MST_E_SCLK 83
#define AUD_CLKID_MST_F_SCLK 84
#define AUD_CLKID_MST_A_LRCLK 86
#define AUD_CLKID_MST_B_LRCLK 87
#define AUD_CLKID_MST_C_LRCLK 88
#define AUD_CLKID_MST_D_LRCLK 89
#define AUD_CLKID_MST_E_LRCLK 90
#define AUD_CLKID_MST_F_LRCLK 91
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
#define AUD_CLKID_TDMIN_A_SCLK 123
#define AUD_CLKID_TDMIN_B_SCLK 124
#define AUD_CLKID_TDMIN_C_SCLK 125
#define AUD_CLKID_TDMIN_LB_SCLK 126
#define AUD_CLKID_TDMOUT_A_SCLK 127
#define AUD_CLKID_TDMOUT_B_SCLK 128
#define AUD_CLKID_TDMOUT_C_SCLK 129
#define AUD_CLKID_TDMIN_A_LRCLK 130
#define AUD_CLKID_TDMIN_B_LRCLK 131
#define AUD_CLKID_TDMIN_C_LRCLK 132
#define AUD_CLKID_TDMIN_LB_LRCLK 133
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

76
include/dt-bindings/clock/axg-clkc.h Normal file
View File

@ -0,0 +1,76 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Meson-AXG clock tree IDs
*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#ifndef __AXG_CLKC_H
#define __AXG_CLKC_H
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_AUDIO_LOCKER 16
#define CLKID_MIPI_DSI_HOST 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
#define CLKID_SPICC0 21
#define CLKID_I2C 22
#define CLKID_RNG0 23
#define CLKID_UART0 24
#define CLKID_MIPI_DSI_PHY 25
#define CLKID_SPICC1 26
#define CLKID_PCIE_A 27
#define CLKID_PCIE_B 28
#define CLKID_HIU_IFACE 29
#define CLKID_ASSIST_MISC 30
#define CLKID_SD_EMMC_B 31
#define CLKID_SD_EMMC_C 32
#define CLKID_DMA 33
#define CLKID_SPI 34
#define CLKID_AUDIO 35
#define CLKID_ETH 36
#define CLKID_UART1 37
#define CLKID_G2D 38
#define CLKID_USB0 39
#define CLKID_USB1 40
#define CLKID_RESET 41
#define CLKID_USB 42
#define CLKID_AHB_ARB0 43
#define CLKID_EFUSE 44
#define CLKID_BOOT_ROM 45
#define CLKID_AHB_DATA_BUS 46
#define CLKID_AHB_CTRL_BUS 47
#define CLKID_USB1_DDR_BRIDGE 48
#define CLKID_USB0_DDR_BRIDGE 49
#define CLKID_MMC_PCLK 50
#define CLKID_VPU_INTR 51
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
#define CLKID_GIC 53
#define CLKID_AO_MEDIA_CPU 54
#define CLKID_AO_AHB_SRAM 55
#define CLKID_AO_AHB_BUS 56
#define CLKID_AO_IFACE 57
#define CLKID_AO_I2C 58
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
#define CLKID_HIFI_PLL 69
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */

116
include/dt-bindings/gpio/meson-axg-gpio.h Normal file
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/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
#define _DT_BINDINGS_MESON_AXG_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_TEST_N 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define BOOT_0 11
#define BOOT_1 12
#define BOOT_2 13
#define BOOT_3 14
#define BOOT_4 15
#define BOOT_5 16
#define BOOT_6 17
#define BOOT_7 18
#define BOOT_8 19
#define BOOT_9 20
#define BOOT_10 21
#define BOOT_11 22
#define BOOT_12 23
#define BOOT_13 24
#define BOOT_14 25
#define GPIOA_0 26
#define GPIOA_1 27
#define GPIOA_2 28
#define GPIOA_3 29
#define GPIOA_4 30
#define GPIOA_5 31
#define GPIOA_6 32
#define GPIOA_7 33
#define GPIOA_8 34
#define GPIOA_9 35
#define GPIOA_10 36
#define GPIOA_11 37
#define GPIOA_12 38
#define GPIOA_13 39
#define GPIOA_14 40
#define GPIOA_15 41
#define GPIOA_16 42
#define GPIOA_17 43
#define GPIOA_18 44
#define GPIOA_19 45
#define GPIOA_20 46
#define GPIOX_0 47
#define GPIOX_1 48
#define GPIOX_2 49
#define GPIOX_3 50
#define GPIOX_4 51
#define GPIOX_5 52
#define GPIOX_6 53
#define GPIOX_7 54
#define GPIOX_8 55
#define GPIOX_9 56
#define GPIOX_10 57
#define GPIOX_11 58
#define GPIOX_12 59
#define GPIOX_13 60
#define GPIOX_14 61
#define GPIOX_15 62
#define GPIOX_16 63
#define GPIOX_17 64
#define GPIOX_18 65
#define GPIOX_19 66
#define GPIOX_20 67
#define GPIOX_21 68
#define GPIOX_22 69
#define GPIOY_0 70
#define GPIOY_1 71
#define GPIOY_2 72
#define GPIOY_3 73
#define GPIOY_4 74
#define GPIOY_5 75
#define GPIOY_6 76
#define GPIOY_7 77
#define GPIOY_8 78
#define GPIOY_9 79
#define GPIOY_10 80
#define GPIOY_11 81
#define GPIOY_12 82
#define GPIOY_13 83
#define GPIOY_14 84
#define GPIOY_15 85
#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */

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include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*
* Copyright (c) 2018 Baylibre SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
#define AXG_ARB_TODDR_A 0
#define AXG_ARB_TODDR_B 1
#define AXG_ARB_TODDR_C 2
#define AXG_ARB_FRDDR_A 3
#define AXG_ARB_FRDDR_B 4
#define AXG_ARB_FRDDR_C 5
#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */

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include/dt-bindings/reset/amlogic,meson-axg-reset.h Normal file
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/*
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2017 Amlogic, inc.
* Author: Yixun Lan <yixun.lan@amlogic.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD)
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
/* RESET0 */
#define RESET_HIU 0
#define RESET_PCIE_A 1
#define RESET_PCIE_B 2
#define RESET_DDR_TOP 3
/* 4 */
#define RESET_VIU 5
#define RESET_PCIE_PHY 6
#define RESET_PCIE_APB 7
/* 8 */
/* 9 */
#define RESET_VENC 10
#define RESET_ASSIST 11
/* 12 */
#define RESET_VCBUS 13
/* 14 */
/* 15 */
#define RESET_GIC 16
#define RESET_CAPB3_DECODE 17
/* 18-21 */
#define RESET_SYS_CPU_CAPB3 22
#define RESET_CBUS_CAPB3 23
#define RESET_AHB_CNTL 24
#define RESET_AHB_DATA 25
#define RESET_VCBUS_CLK81 26
#define RESET_MMC 27
/* 28-31 */
/* RESET1 */
/* 32 */
/* 33 */
#define RESET_USB_OTG 34
#define RESET_DDR 35
#define RESET_AO_RESET 36
/* 37 */
#define RESET_AHB_SRAM 38
/* 39 */
/* 40 */
#define RESET_DMA 41
#define RESET_ISA 42
#define RESET_ETHERNET 43
/* 44 */
#define RESET_SD_EMMC_B 45
#define RESET_SD_EMMC_C 46
#define RESET_ROM_BOOT 47
#define RESET_SYS_CPU_0 48
#define RESET_SYS_CPU_1 49
#define RESET_SYS_CPU_2 50
#define RESET_SYS_CPU_3 51
#define RESET_SYS_CPU_CORE_0 52
#define RESET_SYS_CPU_CORE_1 53
#define RESET_SYS_CPU_CORE_2 54
#define RESET_SYS_CPU_CORE_3 55
#define RESET_SYS_PLL_DIV 56
#define RESET_SYS_CPU_AXI 57
#define RESET_SYS_CPU_L2 58
#define RESET_SYS_CPU_P 59
#define RESET_SYS_CPU_MBIST 60
/* 61-63 */
/* RESET2 */
/* 64 */
/* 65 */
#define RESET_AUDIO 66
/* 67 */
#define RESET_MIPI_HOST 68
#define RESET_AUDIO_LOCKER 69
#define RESET_GE2D 70
/* 71-76 */
#define RESET_AO_CPU_RESET 77
/* 78-95 */
/* RESET3 */
#define RESET_RING_OSCILLATOR 96
/* 97-127 */
/* RESET4 */
/* 128 */
/* 129 */
#define RESET_MIPI_PHY 130
/* 131-140 */
#define RESET_VENCL 141
#define RESET_I2C_MASTER_2 142
#define RESET_I2C_MASTER_1 143
/* 144-159 */
/* RESET5 */
/* 160-191 */
/* RESET6 */
#define RESET_PERIPHS_GENERAL 192
#define RESET_PERIPHS_SPICC 193
/* 194 */
/* 195 */
#define RESET_PERIPHS_I2C_MASTER_0 196
/* 197-200 */
#define RESET_PERIPHS_UART_0 201
#define RESET_PERIPHS_UART_1 202
/* 203-204 */
#define RESET_PERIPHS_SPI_0 205
#define RESET_PERIPHS_I2C_MASTER_3 206
/* 207-223 */
/* RESET7 */
#define RESET_USB_DDR_0 224
#define RESET_USB_DDR_1 225
#define RESET_USB_DDR_2 226
#define RESET_USB_DDR_3 227
/* 228 */
#define RESET_DEVICE_MMC_ARB 229
/* 230 */
#define RESET_VID_LOCK 231
#define RESET_A9_DMC_PIPEL 232
#define RESET_DMC_VPU_PIPEL 233
/* 234-255 */
#endif

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include/dt-bindings/reset/axg-aoclkc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
#define RESET_AO_REMOTE 0
#define RESET_AO_I2C_MASTER 1
#define RESET_AO_I2C_SLAVE 2
#define RESET_AO_UART1 3
#define RESET_AO_UART2 4
#define RESET_AO_IR_BLASTER 5
#endif