Merge branch 'master' of git://git.denx.de/u-boot-blackfin

This commit is contained in:
Tom Rini 2013-12-16 09:13:25 -05:00
commit 93b7b7fdad
12 changed files with 36 additions and 18 deletions

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@ -18,8 +18,6 @@
#include <asm/mach-common/bits/core.h>
#include <asm/serial.h>
#define BUG() while (1) asm volatile("emuexcpt;");
#ifndef __ADSPBF60x__
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
@ -147,8 +145,6 @@ static struct ddr_config ddr_config_table[] = {
__attribute__((always_inline))
static inline void serial_init(void)
{
uint32_t uart_base = UART_BASE;
#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
# ifdef BFIN_BOOT_UART_USE_RTS
# define BFIN_UART_USE_RTS 1
@ -156,6 +152,7 @@ static inline void serial_init(void)
# define BFIN_UART_USE_RTS 0
# endif
if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
uint32_t uart_base = UART_BASE;
size_t i;
/* force RTS rather than relying on auto RTS */
@ -195,8 +192,8 @@ static inline void serial_init(void)
#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
if (BFIN_DEBUG_EARLY_SERIAL) {
serial_early_init(uart_base);
serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
serial_early_init(UART_BASE);
serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
}
#endif
}
@ -547,7 +544,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
__attribute__((always_inline)) static inline u16
program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
{
u16 vr_ctl;
u16 vr_ctl = 0;
serial_putc('a');
@ -731,6 +728,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
serial_putc('a');
if (BFIN_DEBUG_EARLY_SERIAL ||
CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
#ifdef __ADSPBF60x__
sdivR = bfin_read_CGU_DIV();
sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
@ -744,6 +743,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
divisor = vcoB * sdivR;
quotient = early_division(dividend, divisor);
serial_early_put_div(quotient - ANOMALY_05000230);
}
serial_putc('c');
}
@ -913,7 +914,8 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
continue;
serial_putc('z');
uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
uint32_t *hibernate_magic =
(uint32_t *)bfin_read32(DPM0_RESTORE4);
SSYNC(); /* make sure memory controller is done */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');

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@ -81,6 +81,8 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
# define NOP_PAD_ANOMALY_05000198
#endif
#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
u32 __v; \
__asm__ __volatile__( \
@ -111,7 +113,7 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
({ BUG(); 0; }); \
({ BFIN_BUG(); 0; }); \
})
#define bfin_write(addr, val) \
do { \
@ -119,7 +121,8 @@ do { \
case 1: bfin_write8(addr, val); break; \
case 2: bfin_write16(addr, val); break; \
case 4: bfin_write32(addr, val); break; \
default: BUG(); \
default: \
BFIN_BUG(); \
} \
} while (0)

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@ -19,6 +19,7 @@
#include <net.h>
#include <status_led.h>
#include <version.h>
#include <watchdog.h>
#include <asm/cplb.h>
#include <asm/mach-common/bits/mpu.h>

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@ -36,7 +36,10 @@ u_long get_vco(void)
u_long get_cclk(void)
{
static u_long cached_cclk_pll_div, cached_cclk;
u_long div, csel, ssel;
u_long div, csel;
#ifndef CGU_DIV
u_long ssel;
#endif
if (pll_is_bypassed())
return CONFIG_CLKIN_HZ;

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@ -10,6 +10,7 @@
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/io.h>
#include <asm/sdh.h>
#include <asm/portmux.h>
#include "soft_switch.h"

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@ -56,6 +56,7 @@
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
@ -63,7 +64,9 @@
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_CMD_FLASH
#define CONFIG_MONITOR_IS_IN_RAM
/*
#define CONFIG_SYS_NO_FLASH
*/
/*
* SPI Settings
@ -71,11 +74,12 @@
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
*/
/*
* Env Storage Settings

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@ -53,7 +53,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)

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@ -90,6 +90,7 @@
*/
#define CONFIG_SYS_I2C_SOFT
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */

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@ -177,6 +177,7 @@
#define CONFIG_BAUDRATE 57600
#define CONFIG_LOADS_ECHO 1
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BFIN_SERIAL
/*
* U-Boot environment variables. Use "printenv" to examine.

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@ -55,7 +55,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
@ -145,7 +145,7 @@
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 3c0000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
/*
* Pull in common ADI header for remaining command/environment setup

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@ -54,7 +54,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
@ -142,6 +142,7 @@
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
/*

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@ -55,7 +55,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
@ -144,6 +144,7 @@
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
/*