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ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

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This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Marek Vasut 2018-05-29 18:04:15 +02:00
parent 2e1de5bd97
commit 93a8ed8685
1 changed files with 0 additions and 25 deletions

25
drivers/ddr/altera/sdram_arria10.c
View File

@ -713,28 +713,3 @@ int ddr_calibration_sequence(void)
return 0;
}
void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
int i;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> 20;
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
}
/* same as above but just that we would want cacheable for ocram too */
i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
}