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Merge branch 'v2021.07-rc1' of https://github.com/lftan/u-boot

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This commit is contained in:
Tom Rini 2021-04-09 13:10:38 -04:00
commit 92c4eb7ae3
27 changed files with 341 additions and 244 deletions
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30
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
View File

@ -29,10 +29,12 @@
arch = "arm64";
compression = "none";
load = <0x00200000>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
hash {
algo = "crc32";
};
};
atf {
@ -43,20 +45,24 @@
compression = "none";
load = <0x00001000>;
entry = <0x00001000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
hash {
algo = "crc32";
};
};
fdt {
description = "U-Boot SoC64 flat device-tree";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
hash {
algo = "crc32";
};
};
};
@ -67,6 +73,11 @@
firmware = "atf";
loadables = "uboot";
fdt = "fdt";
signature {
algo = "crc32";
key-name-hint = "dev";
sign-images = "atf", "fdt", "uboot";
};
};
};
};
@ -87,10 +98,12 @@
compression = "none";
load = <0x4080000>;
entry = <0x4080000>;
kernel_blob: blob-ext {
filename = "Image";
};
hash {
algo = "crc32";
};
};
fdt {
@ -98,10 +111,12 @@
type = "flat_dt";
arch = "arm64";
compression = "none";
kernel_fdt_blob: blob-ext {
filename = "linux.dtb";
};
hash {
algo = "crc32";
};
};
};
@ -111,6 +126,11 @@
description = "Intel SoC64 FPGA";
kernel = "kernel";
fdt = "fdt";
signature {
algo = "crc32";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
};
};
};
};

14
arch/arm/mach-socfpga/Makefile
View File

@ -35,10 +35,10 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
@ -49,11 +49,11 @@ obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_SPL_BUILD
@ -70,10 +70,12 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += firewall.o
obj-y += spl_s10.o
obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
obj-y += spl_soc64.o
endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o

43
arch/arm/mach-socfpga/clock_manager.c
View File

@ -4,12 +4,13 @@
*/
#include <common.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <command.h>
#include <init.h>
#include <wait_bit.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@ -63,6 +64,42 @@ int set_cpu_clk_info(void)
return 0;
}
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
int cm_set_qspi_controller_clk_hz(u32 clk_hz)
{
u32 reg;
u32 clk_khz;
/*
* Store QSPI ref clock and set into sysmgr boot register.
* Only clock freq in kHz degree is accepted due to limited bits[27:0]
* is reserved for storing the QSPI clock freq into boot scratch cold0
* register.
*/
if (clk_hz < 1000)
return -EINVAL;
clk_khz = clk_hz / 1000;
printf("QSPI: Reference clock at %d kHz\n", clk_khz);
reg = (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
return 0;
}
unsigned int cm_get_qspi_controller_clk_hz(void)
{
return (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
}
#endif
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])

6
arch/arm/mach-socfpga/clock_manager_agilex.c
View File

@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
u32 cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",

8
arch/arm/mach-socfpga/clock_manager_s10.c
View File

@ -8,7 +8,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/handoff_s10.h>
#include <asm/arch/handoff_soc64.h>
#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
unsigned int cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();

5
arch/arm/mach-socfpga/include/mach/clock_manager.h
View File

@ -12,6 +12,11 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#endif
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

2
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
View File

@ -70,8 +70,6 @@ int cm_basic_init(const void *blob);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif /* __ASSEMBLY__ */
#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \

1
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
View File

@ -100,7 +100,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
const unsigned int cm_get_osc_clk_hz(const int osc);
const unsigned int cm_get_f2s_per_ref_clk_hz(void);

1
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
View File

@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {

39
arch/arm/mach-socfpga/include/mach/handoff_s10.h
View File

@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*
*/
#ifndef _HANDOFF_S10_H_
#define _HANDOFF_S10_H_
/*
* Offset for HW handoff from Quartus tools
*/
#define S10_HANDOFF_BASE 0xFFE3F000
#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10)
#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
#define S10_HANDOFF_MAGIC_MUX 0x504D5558
#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354
#define S10_HANDOFF_MAGIC_FPGA 0x46504741
#define S10_HANDOFF_MAGIC_DELAY 0x444C4159
#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53
#define S10_HANDOFF_MAGIC_MISC 0x4D495343
#define S10_HANDOFF_OFFSET_LENGTH 0x4
#define S10_HANDOFF_OFFSET_DATA 0x10
#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
#else
#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc)
#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
#endif
#define S10_HANDOFF_SIZE 4096
#endif /* _HANDOFF_S10_H_ */

62
arch/arm/mach-socfpga/include/mach/handoff_soc64.h Normal file
View File

@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
*
*/
#ifndef _HANDOFF_SOC64_H_
#define _HANDOFF_SOC64_H_
/*
* Offset for HW handoff from Quartus tools
*/
/* HPS handoff */
#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
#else
#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
#define SOC64_HANDOFF_MUX_LEN 96
#define SOC64_HANDOFF_IOCTL_LEN 96
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
#define SOC64_HANDOFF_FPGA_LEN 42
#else
#define SOC64_HANDOFF_FPGA_LEN 40
#endif
#define SOC64_HANDOFF_DELAY_LEN 96
#ifndef __ASSEMBLY__
#include <asm/types.h>
enum endianness {
LITTLE_ENDIAN = 0,
BIG_ENDIAN
};
int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
enum endianness big_endian);
#endif
#endif /* _HANDOFF_SOC64_H_ */

1
arch/arm/mach-socfpga/include/mach/smc_api.h
View File

@ -9,5 +9,6 @@
int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
u32 *resp_buf);
int smc_get_usercode(u32 *usercode);
#endif /* _SMC_API_H_ */

20
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
View File

@ -10,10 +10,6 @@
void sysmgr_pinmux_init(void);
void populate_sysmgr_fpgaintf_module(void);
void populate_sysmgr_pinmux(void);
void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_WDDBG 0x08
#define SYSMGR_SOC64_DMA 0x20
@ -46,7 +42,10 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
/* store qspi ref clock */
/*
* Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
* storing qspi ref clock (kHz)
*/
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
@ -89,6 +88,17 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
#define SYSMGR_SOC64_IODELAY0 0x1400
/*
* Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
* Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
* storing qspi ref clock (kHz)
*/
#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)

17
arch/arm/mach-socfpga/mailbox_s10.c
View File

@ -5,14 +5,15 @@
*/
#include <common.h>
#include <hang.h>
#include <wait_bit.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/secure.h>
#include <asm/system.h>
#include <hang.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@ -384,10 +385,10 @@ int mbox_qspi_open(void)
if (ret)
goto error;
/* We are getting QSPI ref clock and set into sysmgr boot register */
printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
writel(resp_buf[0],
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
/* Store QSPI controller ref clock frequency */
ret = cm_set_qspi_controller_clk_hz(resp_buf[0]);
if (ret)
goto error;
return 0;

17
arch/arm/mach-socfpga/smc_api.c
View File

@ -54,3 +54,20 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
return (int)resp[0];
}
int smc_get_usercode(u32 *usercode)
{
int ret;
u64 resp;
if (!usercode)
return -EINVAL;
ret = invoke_smc(INTEL_SIP_SMC_GET_USERCODE, NULL, 0,
&resp, 1);
if (ret == INTEL_SIP_SMC_STATUS_OK)
*usercode = (u32)resp;
return ret;
}

16
arch/arm/mach-socfpga/spl_agilex.c
View File

@ -25,22 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
}
#endif
void board_init_f(ulong dummy)
{
int ret;

17
arch/arm/mach-socfpga/spl_s10.c
View File

@ -26,23 +26,6 @@
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
/* TODO: Get from SDM or handoff */
return BOOT_DEVICE_MMC1;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
}
#endif
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();

25
arch/arm/mach-socfpga/spl_soc64.c Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved
*
*/
#include <common.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT)
u32 spl_boot_mode(const u32 boot_device)
{
if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
return MMCSD_MODE_FS;
else
return MMCSD_MODE_RAW;
}
#endif

55
arch/arm/mach-socfpga/system_manager_s10.c → arch/arm/mach-socfpga/system_manager_soc64.c
View File

@ -4,10 +4,11 @@
*
*/
#include <common.h>
#include <asm/arch/handoff_soc64.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
@ -64,39 +65,55 @@ void populate_sysmgr_fpgaintf_module(void)
*/
void populate_sysmgr_pinmux(void)
{
const u32 *sys_mgr_table_u32;
unsigned int len, i;
u32 len, i;
u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX, BIG_ENDIAN);
u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL, BIG_ENDIAN);
u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA, BIG_ENDIAN);
u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY, BIG_ENDIAN);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
len = (len > len_delay) ? len : len_delay;
u32 handoff_table[len];
/* setup the pin sel */
sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN;
socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
sys_mgr_table_u32[i] +
(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0);
writel(handoff_table[i + 1],
handoff_table[i] +
(u8 *)socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_PINSEL0);
}
/* setup the pin ctrl */
sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN;
socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
sys_mgr_table_u32[i] +
(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0);
writel(handoff_table[i + 1],
handoff_table[i] +
(u8 *)socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_IOCTRL0);
}
/* setup the fpga use */
sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN;
socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
sys_mgr_table_u32[i] +
writel(handoff_table[i + 1],
handoff_table[i] +
(u8 *)socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_EMAC0_USEFPGA);
}
/* setup the IO delay */
sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN;
socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
sys_mgr_table_u32[i] +
(u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0);
writel(handoff_table[i + 1],
handoff_table[i] +
(u8 *)socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_IODELAY0);
}
}

66
arch/arm/mach-socfpga/wrap_handoff_soc64.c Normal file
View File

@ -0,0 +1,66 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
*
*/
#include <asm/arch/handoff_soc64.h>
#include <asm/io.h>
#include <common.h>
#include <errno.h>
#include "log.h"
int socfpga_get_handoff_size(void *handoff_address, enum endianness endian)
{
u32 size;
size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH);
if (endian == BIG_ENDIAN)
size = swab32(size);
size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32);
debug("%s: handoff address = 0x%p handoff size = 0x%08x\n", __func__,
(u32 *)handoff_address, size);
return size;
}
int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
enum endianness big_endian)
{
u32 temp, i;
u32 *table_x32 = table;
debug("%s: handoff addr = 0x%p ", __func__, (u32 *)handoff_address);
if (big_endian) {
if (swab32(readl(SOC64_HANDOFF_BASE)) == SOC64_HANDOFF_MAGIC_BOOT) {
debug("Handoff table address = 0x%p ", table_x32);
debug("table length = 0x%x\n", table_len);
debug("%s: handoff data =\n{\n", __func__);
for (i = 0; i < table_len; i++) {
temp = readl(handoff_address +
SOC64_HANDOFF_OFFSET_DATA +
(i * sizeof(u32)));
*table_x32 = swab32(temp);
if (!(i % 2))
debug(" No.%d Addr 0x%08x: ", i,
*table_x32);
else
debug(" 0x%08x\n", *table_x32);
table_x32++;
}
debug("\n}\n");
} else {
debug("%s: Cannot find SOC64_HANDOFF_MAGIC_BOOT ", __func__);
debug("at addr 0x%p\n", (u32 *)handoff_address);
return -EPERM;
}
}
return 0;
}

56
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
View File

@ -1,56 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/handoff_s10.h>
static void sysmgr_pinmux_handoff_read(void *handoff_address,
const u32 **table,
unsigned int *table_len)
{
unsigned int handoff_entry = (swab32(readl(handoff_address +
S10_HANDOFF_OFFSET_LENGTH)) -
S10_HANDOFF_OFFSET_DATA) /
sizeof(unsigned int);
unsigned int handoff_chunk[handoff_entry], temp, i;
if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) {
/* using handoff from Quartus tools if exists */
for (i = 0; i < handoff_entry; i++) {
temp = readl(handoff_address +
S10_HANDOFF_OFFSET_DATA + (i * 4));
handoff_chunk[i] = swab32(temp);
}
*table = handoff_chunk;
*table_len = ARRAY_SIZE(handoff_chunk);
}
}
void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
{
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table,
table_len);
}
void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
{
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table,
table_len);
}
void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
{
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table,
table_len);
}
void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
{
sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table,
table_len);
}

16
arch/arm/mach-socfpga/wrap_pll_config_s10.c → arch/arm/mach-socfpga/wrap_pll_config_soc64.c
View File

@ -7,24 +7,24 @@
#include <common.h>
#include <asm/arch/clock_manager.h>
#include <asm/io.h>
#include <asm/arch/handoff_s10.h>
#include <asm/arch/handoff_soc64.h>
#include <asm/arch/system_manager.h>
const struct cm_config * const cm_get_default_config(void)
{
#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
(SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
u32 i;
u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK);
if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) {
writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK);
for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
conversion[i] = swab32(conversion[i]);
return cm_handoff_cfg;
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
} else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
#endif
@ -35,7 +35,7 @@ const unsigned int cm_get_osc_clk_hz(void)
{
#ifdef CONFIG_SPL_BUILD
u32 clock = readl(HANDOFF_CLOCK_OSC);
u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC);
writel(clock,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
@ -52,7 +52,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
const unsigned int cm_get_fpga_clk_hz(void)
{
#ifdef CONFIG_SPL_BUILD
u32 clock = readl(HANDOFF_CLOCK_FPGA);
u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA);
writel(clock,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);

4
configs/socfpga_agilex_atf_defconfig
View File

@ -14,6 +14,10 @@ CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set

4
configs/socfpga_agilex_vab_defconfig
View File

@ -15,6 +15,10 @@ CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set

4
configs/socfpga_stratix10_atf_defconfig
View File

@ -14,6 +14,10 @@ CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set

4
include/configs/socfpga_soc64_common.h
View File

@ -8,7 +8,7 @@
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
#include <asm/arch/base_addr_s10.h>
#include <asm/arch/handoff_s10.h>
#include <asm/arch/handoff_soc64.h>
#include <linux/stringify.h>
/*
@ -43,7 +43,7 @@
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
+ CONFIG_SYS_INIT_RAM_SIZE \
- S10_HANDOFF_SIZE)
- SOC64_HANDOFF_SIZE)
#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
+ 0x100000)

52
include/linux/intel-smc.h
View File

@ -519,55 +519,21 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
/*
* Request INTEL_SIP_SMC_HPS_SET_PHYINTF
* Request INTEL_SIP_SMC_GET_USERCODE
*
* Select EMACx PHY interface
* Send mailbox command to get usercode from SDM
*
* Call register usage:
* a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
* a1 EMAC number:
* 0 - EMAC0
* 1 - EMAC1
* 2 - EMAC2
* a2 Type of PHY interface:
* 0 - GMII_MII
* 1 - RGMII
* 2 - RMII
* 3 - RESET
* a3-7 not used
* a0 INTEL_SIP_SMC_GET_USERCODE
* a1-7 not used.
*
* Return status
* a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
* a1 User code
* a2-3 not used.
*/
#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61
#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
/*
* Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
*
* Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
*
* Call register usage:
* a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
* a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
* 0 - 0 degree
* 1 - 45 degrees
* 2 - 90 degrees
* 3 - 135 degrees
* 4 - 180 degrees
* 5 - 225 degrees
* 6 - 270 degrees
* 7 - 315 degrees
* a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
* (Same as above)
* a3-7 not used
*
* Return status
* a0 INTEL_SIP_SMC_STATUS_OK
*/
#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62
#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
#define INTEL_SIP_SMC_FUNCID_GET_USERCODE 61
#define INTEL_SIP_SMC_GET_USERCODE \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_GET_USERCODE)
#endif