Fix caslat calculation
Signed-off-by: John Traill <john.traill@freescale.com>
This commit is contained in:
John Traill
Jon Loeliger
parent
709d3073e7
commit
91a414c7d1
@ -44,7 +44,7 @@ extern int dma_xfer(void *dest, uint count, void *src);
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/*
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* Only one of the following three should be 1; others should be 0
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* By default the cache line interleaving is selected if
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* the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h
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* the CONFIG_DDR_INTERLEAVE flag is defined
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*/
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#define CFG_PAGE_INTERLEAVING 0
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#define CFG_BANK_INTERLEAVING 0
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@ -137,8 +137,8 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
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800,
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900,
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250,
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330, /* FIXME: Is 333 better/valid? */
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660, /* FIXME: Is 667 better/valid? */
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330,
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660,
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750,
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0, /* undefined */
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0 /* undefined */
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@ -167,7 +167,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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unsigned int dqs_cfg;
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unsigned char twr_clk, twtr_clk, twr_auto_clk;
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unsigned int tCKmin_ps, tCKmax_ps;
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unsigned int max_data_rate, effective_data_rate;
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unsigned int max_data_rate;
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unsigned int busfreq;
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unsigned sdram_cfg_1;
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unsigned int memsize;
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@ -187,6 +187,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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unsigned char d_init;
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unsigned int law_size;
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volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
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unsigned int tCycle_ps, modfreq;
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if (ddr_num == 1)
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ddr = &immap->im_ddr1;
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@ -288,7 +289,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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}
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#ifdef CONFIG_DDR_INTERLEAVE
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#ifdef CONFIG_MPC8641HPCN
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if (dimm_num != 1) {
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printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
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return 0;
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@ -340,8 +341,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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rank_density /= 2;
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}
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}
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#endif /* CONFIG_MPC8641HPCN */
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#else /* CONFIG_DDR_INTERLEAVE */
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if (dimm_num == 1) {
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@ -468,81 +467,42 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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*/
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busfreq = get_bus_freq(0) / 1000000; /* MHz */
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effective_data_rate = max_data_rate;
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if (busfreq < 90) {
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/* DDR rate out-of-range */
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puts("DDR: platform frequency is not fit for DDR rate\n");
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if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
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printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
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return 0;
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} else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
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/*
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* busfreq 90~230 range, treated as DDR 200.
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*/
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effective_data_rate = 200;
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if (spd.clk_cycle3 == 0xa0) /* 10 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0xa0)
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caslat--;
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} else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
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/*
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* busfreq 230~280 range, treated as DDR 266.
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*/
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effective_data_rate = 266;
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if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x75)
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caslat--;
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} else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
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/*
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* busfreq 280~350 range, treated as DDR 333.
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*/
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effective_data_rate = 333;
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if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x60)
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caslat--;
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} else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
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/*
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* busfreq 350~460 range, treated as DDR 400.
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*/
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effective_data_rate = 400;
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if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x50)
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caslat--;
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} else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
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/*
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* busfreq 460~560 range, treated as DDR 533.
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*/
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effective_data_rate = 533;
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if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x3D)
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caslat--;
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} else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
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/*
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* busfreq 560~700 range, treated as DDR 667.
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*/
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effective_data_rate = 667;
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if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x30)
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caslat--;
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} else if (700 <= busfreq) {
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/*
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* DDR rate out-of-range
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*/
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printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
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busfreq, max_data_rate);
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} else if (busfreq < 90) {
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printf("DDR: platform frequency too low for correct DDR1 operation\n");
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return 0;
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}
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if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
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caslat -= 2;
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} else {
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tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
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modfreq = 2 * 1000 * 1000 / tCycle_ps;
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if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
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caslat -= 1;
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else if (busfreq > max_data_rate) {
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printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
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busfreq, max_data_rate);
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return 0;
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}
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}
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/*
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* Empirically set ~MCAS-to-preamble override for DDR 2.
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* Your milage will vary.
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*/
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cpo = 0;
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if (spd.mem_type == SPD_MEMTYPE_DDR2) {
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if (busfreq <= 333) {
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cpo = 0x7;
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} else if (busfreq <= 400) {
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cpo = 0x9;
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} else {
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cpo = 0xa;
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}
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}
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/*
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* Convert caslat clocks to DDR controller value.
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@ -554,7 +514,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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caslat_ctrl = (2 * caslat - 1) & 0x0f;
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}
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debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
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debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
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caslat, caslat_ctrl);
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@ -676,7 +635,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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&& (odt_wr_cfg || odt_rd_cfg)
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&& (caslat < 4)) {
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add_lat = 4 - caslat;
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if (add_lat > trcd_clk) {
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if (add_lat >= trcd_clk) {
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add_lat = trcd_clk - 1;
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}
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}
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@ -717,22 +676,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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four_act = picos_to_clk(37500); /* By the book. 1k pages? */
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}
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/*
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* Empirically set ~MCAS-to-preamble override for DDR 2.
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* Your milage will vary.
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*/
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cpo = 0;
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if (spd.mem_type == SPD_MEMTYPE_DDR2) {
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if (effective_data_rate == 266 || effective_data_rate == 333) {
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cpo = 0x7; /* READ_LAT + 5/4 */
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} else if (effective_data_rate == 400) {
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cpo = 0x9; /* READ_LAT + 7/4 */
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} else {
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/* Pure speculation */
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cpo = 0xb;
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}
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}
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ddr->timing_cfg_2 = (0
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| ((add_lat & 0x7) << 28) /* ADD_LAT */
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| ((cpo & 0x1f) << 23) /* CPO */
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