diff --git a/.gitignore b/.gitignore index d7d55383ac..cba5eac2a0 100644 --- a/.gitignore +++ b/.gitignore @@ -5,16 +5,20 @@ # # Normal rules # - -*.rej -*.orig -*.a +.* *.o +*.o.* +*.a +*.s *.su -*~ +*.mod.c +*.i +*.lst +*.order +*.elf *.swp -*.patch *.bin +*.patch *.cfgtmp *.dts.tmp @@ -24,36 +28,21 @@ # # Top-level generic files # - /MLO* /SPL /System.map -/u-boot -/u-boot.elf -/u-boot.hex -/u-boot.imx -/u-boot-with-spl.imx -/u-boot-with-nand-spl.imx -/u-boot.map -/u-boot.srec -/u-boot.ldr -/u-boot.ldr.hex -/u-boot.ldr.srec -/u-boot.img -/u-boot.kwb -/u-boot.sha1 -/u-boot.dis -/u-boot.lds -/u-boot.ubl -/u-boot.ais -/u-boot.dtb -/u-boot.sb +/u-boot* + +# +# git files that we don't want to ignore even it they are dot-files +# +!.gitignore +!.mailmap # # Generated files # -*.depend* /LOG /errlog /reloc_off @@ -62,10 +51,13 @@ /spl/* /tpl/ +# +# Generated include files +# +/include/config/ /include/generated/ /include/spl-autoconf.mk /include/tpl-autoconf.mk -asm-offsets.s # stgit generated dirs patches-* @@ -91,3 +83,7 @@ GPATH GRTAGS GSYMS GTAGS + +*.orig +*~ +\#*# diff --git a/Kbuild b/Kbuild new file mode 100644 index 0000000000..6e1698c5bf --- /dev/null +++ b/Kbuild @@ -0,0 +1,87 @@ +# +# Kbuild for top-level directory of U-Boot +# This file takes care of the following: +# 1) Generate generic-asm-offsets.h +# 2) Generate asm-offsets.h + +##### +# 1) Generate generic-asm-offsets.h + +generic-offsets-file := include/generated/generic-asm-offsets.h + +always := $(generic-offsets-file) +targets := $(generic-offsets-file) lib/asm-offsets.s + +quiet_cmd_generic-offsets = GEN $@ +define cmd_generic-offsets + (set -e; \ + echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \ + echo "#define __GENERIC_ASM_OFFSETS_H__"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-y) $<; \ + echo ""; \ + echo "#endif" ) > $@ +endef + +# We use internal kbuild rules to avoid the "is up to date" message from make +lib/asm-offsets.s: lib/asm-offsets.c FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cc_s_c) + +$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild + $(Q)mkdir -p $(dir $@) + $(call cmd,generic-offsets) + +##### +# 2) Generate asm-offsets.h +# + +ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),) +offsets-file := include/generated/asm-offsets.h +endif + +always += $(offsets-file) +targets += $(offsets-file) +targets += arch/$(ARCH)/lib/asm-offsets.s + + +# Default sed regexp - multiline due to syntax constraints +define sed-y + "/^->/{s:->#\(.*\):/* \1 */:; \ + s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:->::; p;}" +endef + +CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY + +quiet_cmd_offsets = GEN $@ +define cmd_offsets + (set -e; \ + echo "#ifndef __ASM_OFFSETS_H__"; \ + echo "#define __ASM_OFFSETS_H__"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-y) $<; \ + echo ""; \ + echo "#endif" ) > $@ +endef + +# We use internal kbuild rules to avoid the "is up to date" message from make +arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cc_s_c) + +$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild + $(call cmd,offsets) diff --git a/MAKEALL b/MAKEALL index 562071a03e..705a0bb5e1 100755 --- a/MAKEALL +++ b/MAKEALL @@ -398,8 +398,6 @@ LIST_at91="$(targets_by_soc at91)" LIST_pxa="$(targets_by_cpu pxa)" -LIST_ixp="$(targets_by_cpu ixp)" - ######################################################################### ## SPEAr Systems ######################################################################### @@ -529,6 +527,12 @@ LIST_sparc="$(targets_by_arch sparc)" LIST_nds32="$(targets_by_arch nds32)" +######################################################################### +## ARC Systems +######################################################################### + +LIST_arc="$(targets_by_arch arc)" + #----------------------------------------------------------------------- get_target_location() { @@ -668,8 +672,6 @@ build_target() { output_dir="${OUTPUT_PREFIX}" fi - export BUILD_DIR="${output_dir}" - target_arch=$(get_target_arch ${target}) eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'` if [ "${cross_toolchain}" ] ; then @@ -680,6 +682,10 @@ build_target() { MAKE=make fi + if [ "${output_dir}" != "." ] ; then + MAKE="${MAKE} O=${output_dir}" + fi + ${MAKE} distclean >/dev/null ${MAKE} -s ${target}_config @@ -694,7 +700,7 @@ build_target() { if [ $BUILD_MANY == 1 ] ; then trap - TERM - ${MAKE} -s tidy + ${MAKE} -s clean if [ -s ${LOG_DIR}/${target}.ERR ] ; then cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target} diff --git a/Makefile b/Makefile index 0419debd8e..dd0cca0626 100755 --- a/Makefile +++ b/Makefile @@ -6,16 +6,173 @@ # VERSION = 2014 -PATCHLEVEL = 01 +PATCHLEVEL = 04 SUBLEVEL = EXTRAVERSION = -ifneq "$(SUBLEVEL)" "" -U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) -else -U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION) +NAME = + +# *DOCUMENTATION* +# To see a list of typical targets execute "make help" +# More info can be located in ./README +# Comments in this file are targeted only to the developer, do not +# expect to learn how to build the kernel reading this file. + +# Do not: +# o use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +# o print "Entering directory ..."; +MAKEFLAGS += -rR --no-print-directory + +# Avoid funny character set dependencies +unexport LC_ALL +LC_COLLATE=C +LC_NUMERIC=C +export LC_COLLATE LC_NUMERIC + +# We are using a recursive build, so we need to do a little thinking +# to get the ordering right. +# +# Most importantly: sub-Makefiles should only ever modify files in +# their own directory. If in some directory we have a dependency on +# a file in another dir (which doesn't happen often, but it's often +# unavoidable when linking the built-in.o targets which finally +# turn into vmlinux), we will call a sub make in that other dir, and +# after that we are sure that everything which is in that other dir +# is now up to date. +# +# The only cases where we need to modify files which have global +# effects are thus separated out and done before the recursive +# descending is started. They are now explicitly listed as the +# prepare rule. + +# To put more focus on warnings, be less verbose as default +# Use 'make V=1' to see the full commands + +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) endif -TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h -VERSION_FILE = $(obj)include/generated/version_autogenerated.h +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +# Call a source code checker (by default, "sparse") as part of the +# C compilation. +# +# Use 'make C=1' to enable checking of only re-compiled files. +# Use 'make C=2' to enable checking of *all* source files, regardless +# of whether they are re-compiled or not. +# +# See the file "Documentation/sparse.txt" for more details, including +# where to get the "sparse" utility. + +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) +endif +ifndef KBUILD_CHECKSRC + KBUILD_CHECKSRC = 0 +endif + +# Use make M=dir to specify directory of external module to build +# Old syntax make ... SUBDIRS=$PWD is still supported +# Setting the environment variable KBUILD_EXTMOD take precedence +ifdef SUBDIRS + KBUILD_EXTMOD ?= $(SUBDIRS) +endif + +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif + +# kbuild supports saving output files in a separate directory. +# To locate output files in a separate directory two syntaxes are supported. +# In both cases the working directory must be the root of the kernel src. +# 1) O= +# Use "make O=dir/to/store/output/files/" +# +# 2) Set KBUILD_OUTPUT +# Set the environment variable KBUILD_OUTPUT to point to the directory +# where the output files shall be placed. +# export KBUILD_OUTPUT=dir/to/store/output/files/ +# make +# +# The O= assignment takes precedence over the KBUILD_OUTPUT environment +# variable. + + +# KBUILD_SRC is set on invocation of make in OBJ directory +# KBUILD_SRC is not intended to be used by the regular user (for now) +ifeq ($(KBUILD_SRC),) + +# OK, Make called in directory where kernel src resides +# Do we want to locate output files in a separate directory? +ifeq ("$(origin O)", "command line") + KBUILD_OUTPUT := $(O) +endif + +ifeq ("$(origin W)", "command line") + export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) +endif + +# That's our default target when none is given on the command line +PHONY := _all +_all: + +# Cancel implicit rules on top Makefile +$(CURDIR)/Makefile Makefile: ; + +ifneq ($(KBUILD_OUTPUT),) +# Invoke a second make in the output directory, passing relevant variables +# check that the output directory actually exists +saved-output := $(KBUILD_OUTPUT) +KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \ + && /bin/pwd) +$(if $(KBUILD_OUTPUT),, \ + $(error output directory "$(saved-output)" does not exist)) + +PHONY += $(MAKECMDGOALS) sub-make + +$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make + @: + +sub-make: FORCE + $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \ + KBUILD_SRC=$(CURDIR) \ + KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \ + $(filter-out _all sub-make,$(MAKECMDGOALS)) + +# Leave processing to above invocation of make +skip-makefile := 1 +endif # ifneq ($(KBUILD_OUTPUT),) +endif # ifeq ($(KBUILD_SRC),) + +# We process the rest of the Makefile if this is the final invocation of make +ifeq ($(skip-makefile),) + +# If building an external module we do not care about the all: rule +# but instead _all depend on modules +PHONY += all +ifeq ($(KBUILD_EXTMOD),) +_all: all +else +_all: modules +endif + +srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR)) +objtree := $(CURDIR) +src := $(srctree) +obj := $(objtree) + +VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD)) + +export srctree objtree VPATH + +MKCONFIG := $(srctree)/mkconfig +export MKCONFIG + +# Make sure CDPATH settings don't interfere +unexport CDPATH + +######################################################################### HOSTARCH := $(shell uname -m | \ sed -e s/i.86/x86/ \ @@ -36,180 +193,376 @@ export HOSTARCH HOSTOS VENDOR= ######################################################################### -# Allow for silent builds -ifeq (,$(findstring s,$(MAKEFLAGS))) -XECHO = echo -else -XECHO = : -endif - -######################################################################### -# -# U-boot build supports generating object files in a separate external -# directory. Two use cases are supported: -# -# 1) Add O= to the make command line -# 'make O=/tmp/build all' -# -# 2) Set environment variable BUILD_DIR to point to the desired location -# 'export BUILD_DIR=/tmp/build' -# 'make' -# -# The second approach can also be used with a MAKEALL script -# 'export BUILD_DIR=/tmp/build' -# './MAKEALL' -# -# Command line 'O=' setting overrides BUILD_DIR environment variable. -# -# When none of the above methods is used the local build is performed and -# the object files are placed in the source directory. -# - -ifeq ("$(origin O)", "command line") -BUILD_DIR := $(O) -endif - -# Call a source code checker (by default, "sparse") as part of the -# C compilation. -# -# Use 'make C=1' to enable checking of re-compiled files. -# -# See the linux kernel file "Documentation/sparse.txt" for more details, -# including where to get the "sparse" utility. - -ifdef C -ifeq ("$(origin C)", "command line") -CHECKSRC := $(C) -endif -endif -ifndef CHECKSRC - CHECKSRC = 0 -endif -export CHECKSRC - -ifneq ($(BUILD_DIR),) -saved-output := $(BUILD_DIR) - -# Attempt to create a output directory. -$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) - -# Verify if it was successful. -BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) -$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) -endif # ifneq ($(BUILD_DIR),) - -OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) -SPLTREE := $(OBJTREE)/spl -TPLTREE := $(OBJTREE)/tpl -SRCTREE := $(CURDIR) -TOPDIR := $(SRCTREE) -LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE - -MKCONFIG := $(SRCTREE)/mkconfig -export MKCONFIG - -# $(obj) and (src) are defined in config.mk but here in main Makefile -# we also need them before config.mk is included which is the case for -# some targets like unconfig, clean, clobber, distclean, etc. -ifneq ($(OBJTREE),$(SRCTREE)) -obj := $(OBJTREE)/ -src := $(SRCTREE)/ -else -obj := -src := -endif -export obj src - -# Make sure CDPATH settings don't interfere -unexport CDPATH - -######################################################################### - -# The "tools" are needed early, so put this first -# Don't include stuff already done in $(LIBS) -# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC -# is "yes"), so compile examples after U-Boot is compiled. -SUBDIR_TOOLS = tools -SUBDIRS = $(SUBDIR_TOOLS) - -.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE) - -ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) - -# Include autoconf.mk before config.mk so that the config options are available -# to all top level build files. We need the dummy all: target to prevent the -# dependency target in autoconf.mk.dep from being the default. -all: -sinclude $(obj)include/autoconf.mk.dep -sinclude $(obj)include/autoconf.mk - -SUBDIR_EXAMPLES-y := examples/standalone -SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api -ifndef CONFIG_SANDBOX -SUBDIRS += $(SUBDIR_EXAMPLES-y) -endif - -# load ARCH, BOARD, and CPU configuration -include $(obj)include/config.mk -export ARCH CPU BOARD VENDOR SOC # set default to nothing for native builds ifeq ($(HOSTARCH),$(ARCH)) CROSS_COMPILE ?= endif -# load other configuration -include $(TOPDIR)/config.mk +# SHELL used by kbuild +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) -# Targets which don't build the source code -NON_BUILD_TARGETS = backup clean clobber distclean mrproper tidy unconfig +HOSTCC = gcc +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -# Only do the generic board check when actually building, not configuring -ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),) -ifeq ($(findstring _config,$(MAKECMDGOALS)),) -$(CHECK_GENERIC_BOARD) +ifeq ($(HOSTOS),cygwin) +HOSTCFLAGS += -ansi endif + +# Mac OS X / Darwin's C preprocessor is Apple specific. It +# generates numerous errors and warnings. We want to bypass it +# and use GNU C's cpp. To do this we pass the -traditional-cpp +# option to the compiler. Note that the -traditional-cpp flag +# DOES NOT have the same semantics as GNU C's flag, all it does +# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. +# +# Apple's linker is similar, thanks to the new 2 stage linking +# multiple symbol definitions are treated as errors, hence the +# -multiply_defined suppress option to turn off this error. +# +ifeq ($(HOSTOS),darwin) +# get major and minor product version (e.g. '10' and '6' for Snow Leopard) +DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') +DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') + +os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ + $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + +# Snow Leopards build environment has no longer restrictions as described above +HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") +HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") +HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") +endif + +# Decide whether to build built-in, modular, or both. +# Normally, just do built-in. + +KBUILD_MODULES := +KBUILD_BUILTIN := 1 + +# If we have only "make modules", don't compile built-in objects. +# When we're building modules with modversions, we need to consider +# the built-in objects during the descend as well, in order to +# make sure the checksums are up to date before we record them. + +ifeq ($(MAKECMDGOALS),modules) + KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1) +endif + +# If we have "make modules", compile modules +# in addition to whatever we do anyway. +# Just "make" or "make all" shall build modules as well + +# U-Boot does not need modules +#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),) +# KBUILD_MODULES := 1 +#endif + +#ifeq ($(MAKECMDGOALS),) +# KBUILD_MODULES := 1 +#endif + +export KBUILD_MODULES KBUILD_BUILTIN +export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD + +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. +# +# $(Q)ln $@ :< +# +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif + +export quiet Q KBUILD_VERBOSE + + +# Look for make include files relative to root of kernel src +MAKEFLAGS += --include-dir=$(srctree) + +# We need some generic definitions (do not try to remake the file). +$(srctree)/scripts/Kbuild.include: ; +include $(srctree)/scripts/Kbuild.include + +# Make variables (CC, etc...) + +AS = $(CROSS_COMPILE)as +# Always use GNU ld +ifneq ($(shell $(CROSS_COMPILE)ld.bfd -v 2> /dev/null),) +LD = $(CROSS_COMPILE)ld.bfd +else +LD = $(CROSS_COMPILE)ld +endif +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +AWK = awk +RANLIB = $(CROSS_COMPILE)RANLIB +DTC = dtc +CHECK = sparse + +CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ + -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) + +KBUILD_CPPFLAGS := -D__KERNEL__ + +KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ + -Wno-format-security \ + -fno-builtin -ffreestanding +KBUILD_AFLAGS := -D__ASSEMBLY__ + +# Read UBOOTRELEASE from include/config/uboot.release (if it exists) +UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) +UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) + +export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION +export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR +export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC +export CPP AR NM LDR STRIP OBJCOPY OBJDUMP +export MAKE AWK +export DTC CHECK CHECKFLAGS + +export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS +export KBUILD_CFLAGS KBUILD_AFLAGS + +# When compiling out-of-tree modules, put MODVERDIR in the module +# tree rather than in the kernel tree. The kernel tree might +# even be read-only. +export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions + +# Files to ignore in find ... statements + +RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \ + -o -name .pc -o -name .hg -o -name .git \) -prune -o +export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ + --exclude CVS --exclude .pc --exclude .hg --exclude .git + +# =========================================================================== +# Rules shared between *config targets and build targets + +# Basic helpers built in scripts/ +PHONY += scripts_basic +scripts_basic: + $(Q)$(MAKE) $(build)=scripts/basic + $(Q)rm -f .tmp_quiet_recordmcount + +# To avoid any implicit rule to kick in, define an empty command. +scripts/basic/%: scripts_basic ; + +PHONY += outputmakefile +# outputmakefile generates a Makefile in the output directory, if using a +# separate output directory. This allows convenient use of make in the +# output directory. +outputmakefile: +ifneq ($(KBUILD_SRC),) + $(Q)ln -fsn $(srctree) source + $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \ + $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL) +endif + +# To make sure we do not include .config for any of the *config targets +# catch them early, and hand them over to scripts/kconfig/Makefile +# It is allowed to specify more targets when calling make, including +# mixing *config targets and build targets. +# For example 'make oldconfig all'. +# Detect when mixed targets is specified, and make a second invocation +# of make so .config is not included in this case either (for *config). + +version_h := include/generated/version_autogenerated.h +timestamp_h := include/generated/timestamp_autogenerated.h + +no-dot-config-targets := clean clobber mrproper distclean \ + help %docs check% coccicheck \ + ubootversion backup tools-only + +config-targets := 0 +mixed-targets := 0 +dot-config := 1 + +ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),) + ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),) + dot-config := 0 + endif +endif + +ifeq ($(KBUILD_EXTMOD),) + ifneq ($(filter config %config,$(MAKECMDGOALS)),) + config-targets := 1 + ifneq ($(filter-out config %config,$(MAKECMDGOALS)),) + mixed-targets := 1 + endif + endif +endif + +ifeq ($(mixed-targets),1) +# =========================================================================== +# We're called with mixed targets (*config and build targets). +# Handle them one by one. + +PHONY += $(MAKECMDGOALS) build-one-by-one + +$(MAKECMDGOALS): build-one-by-one + @: + +build-one-by-one: + $(Q)set -e; \ + for i in $(MAKECMDGOALS); do \ + $(MAKE) -f $(srctree)/Makefile $$i; \ + done + +else +ifeq ($(config-targets),1) +# =========================================================================== +# *config targets only - make sure prerequisites are updated, and descend +# in scripts/kconfig to make the *config target + +# Read arch specific Makefile to set KBUILD_DEFCONFIG as needed. +# KBUILD_DEFCONFIG may point out an alternative default configuration +# used for 'make defconfig' + +%_config:: outputmakefile + @$(MKCONFIG) -A $(@:_config=) + +else +# =========================================================================== +# Build targets only - this includes vmlinux, arch specific targets, clean +# targets and others. In general all targets except *config targets. + +# load ARCH, BOARD, and CPU configuration +-include include/config.mk + +ifeq ($(dot-config),1) +# Read in config +-include include/autoconf.mk +-include include/autoconf.mk.dep + +# load other configuration +include $(srctree)/config.mk + +ifeq ($(wildcard include/config.mk),) +$(error "System not configured - see README") endif # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use # that (or fail if absent). Otherwise, search for a linker script in a # standard location. -LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT)) - ifndef LDSCRIPT - #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug + #LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug ifdef CONFIG_SYS_LDSCRIPT # need to strip off double quotes - LDSCRIPT := $(CONFIG_SYS_LDSCRIPT:"%"=%) + LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%) endif endif # If there is no specified link script, we look in a number of places for it ifndef LDSCRIPT ifeq ($(CONFIG_NAND_U_BOOT),y) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds endif endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds - # We don't expect a Makefile here - LDSCRIPT_MAKEFILE_DIR = - endif - ifeq ($(wildcard $(LDSCRIPT)),) -$(error could not find linker script) + LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds endif endif +else + + +endif # $(dot-config) + +KBUILD_CFLAGS += -Os #-fomit-frame-pointer + +ifdef BUILD_TAG +KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' +endif + +KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) + +KBUILD_CFLAGS += -g +# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g +# option to the assembler. +KBUILD_AFLAGS += -g + +# Report stack usage if supported +ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y) + KBUILD_CFLAGS += -fstack-usage +endif + +KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral) + +# turn jbsr into jsr for m68k +ifeq ($(ARCH),m68k) +ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) +KBUILD_AFLAGS += -Wa,-gstabs,-S +endif +endif + +ifneq ($(CONFIG_SYS_TEXT_BASE),) +KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) +endif + +export CONFIG_SYS_TEXT_BASE + +# Use UBOOTINCLUDE when you must reference the include/ directory. +# Needed to be compatible with the O= option +UBOOTINCLUDE := \ + -Iinclude \ + $(if $(KBUILD_SRC), -I$(srctree)/include) \ + -I$(srctree)/arch/$(ARCH)/include + +NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) +CHECKFLAGS += $(NOSTDINC_FLAGS) + +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ + $(NOSTDINC_FLAGS) +c_flags := $(KBUILD_CFLAGS) $(cpp_flags) + ######################################################################### # U-Boot objects....order is important (i.e. start must be first) @@ -217,80 +570,88 @@ head-y := $(CPUDIR)/start.o head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o -OBJS := $(addprefix $(obj),$(head-y)) +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) -HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) - -LIBS-y += lib/ -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ -LIBS-y += $(CPUDIR)/ +libs-y += lib/ +libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ +libs-y += $(CPUDIR)/ ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/ +libs-y += $(CPUDIR)/$(SOC)/ endif -LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/ -LIBS-$(CONFIG_OF_EMBED) += dts/ -LIBS-y += arch/$(ARCH)/lib/ -LIBS-y += fs/ -LIBS-y += net/ -LIBS-y += disk/ -LIBS-y += drivers/ -LIBS-y += drivers/dma/ -LIBS-y += drivers/gpio/ -LIBS-y += drivers/i2c/ -LIBS-y += drivers/input/ -LIBS-y += drivers/mmc/ -LIBS-y += drivers/mtd/ -LIBS-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ -LIBS-y += drivers/mtd/onenand/ -LIBS-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ -LIBS-y += drivers/mtd/spi/ -LIBS-y += drivers/net/ -LIBS-y += drivers/net/phy/ -LIBS-y += drivers/pci/ -LIBS-y += drivers/power/ \ +libs-$(CONFIG_OF_EMBED) += dts/ +libs-y += arch/$(ARCH)/lib/ +libs-y += fs/ +libs-y += net/ +libs-y += disk/ +libs-y += drivers/ +libs-$(CONFIG_DM) += drivers/core/ +libs-y += drivers/dma/ +libs-y += drivers/gpio/ +libs-y += drivers/i2c/ +libs-y += drivers/input/ +libs-y += drivers/mmc/ +libs-y += drivers/mtd/ +libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ +libs-y += drivers/mtd/onenand/ +libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ +libs-y += drivers/mtd/spi/ +libs-y += drivers/net/ +libs-y += drivers/net/phy/ +libs-y += drivers/pci/ +libs-y += drivers/power/ \ drivers/power/fuel_gauge/ \ drivers/power/mfd/ \ drivers/power/pmic/ \ drivers/power/battery/ -LIBS-y += drivers/spi/ -LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/ -LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ -LIBS-y += drivers/serial/ -LIBS-y += drivers/usb/eth/ -LIBS-y += drivers/usb/gadget/ -LIBS-y += drivers/usb/host/ -LIBS-y += drivers/usb/musb/ -LIBS-y += drivers/usb/musb-new/ -LIBS-y += drivers/usb/phy/ -LIBS-y += drivers/usb/ulpi/ -LIBS-y += common/ -LIBS-y += lib/libfdt/ -LIBS-$(CONFIG_API) += api/ -LIBS-$(CONFIG_HAS_POST) += post/ -LIBS-y += test/ +libs-y += drivers/spi/ +libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ +libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-y += drivers/serial/ +libs-y += drivers/usb/eth/ +libs-y += drivers/usb/gadget/ +libs-y += drivers/usb/host/ +libs-y += drivers/usb/musb/ +libs-y += drivers/usb/musb-new/ +libs-y += drivers/usb/phy/ +libs-y += drivers/usb/ulpi/ +libs-y += common/ +libs-y += lib/libfdt/ +libs-$(CONFIG_API) += api/ +libs-$(CONFIG_HAS_POST) += post/ +libs-y += test/ +libs-y += test/dm/ +libs-$(CONFIG_DM_DEMO) += drivers/demo/ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) -LIBS-y += arch/$(ARCH)/imx-common/ +libs-y += arch/$(ARCH)/imx-common/ endif -LIBS-$(CONFIG_ARM) += arch/arm/cpu/ -LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ +libs-$(CONFIG_ARM) += arch/arm/cpu/ +libs-$(CONFIG_PPC) += arch/powerpc/cpu/ -LIBS-y += board/$(BOARDDIR)/ +libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) + +libs-y := $(sort $(libs-y)) + +u-boot-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) tools examples + +u-boot-alldirs := $(sort $(u-boot-dirs) $(patsubst %/,%,$(filter %/, $(libs-)))) + +libs-y := $(patsubst %/, %/built-in.o, $(libs-y)) + +u-boot-init := $(head-y) +u-boot-main := $(libs-y) -LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) -LIBS := $(addprefix $(obj),$(sort $(LIBS-y))) -.PHONY : $(LIBS) # Add GCC lib -ifdef USE_PRIVATE_LIBGCC -ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o +ifdef CONFIG_USE_PRIVATE_LIBGCC +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a else -PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc +PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc endif else -PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS @@ -299,14 +660,11 @@ export PLATFORM_LIBS # Pass the version down so we can handle backwards compatibility # on the fly. LDPPFLAGS += \ - -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ + -include $(srctree)/include/u-boot/u-boot.lds.h \ -DCPUDIR=$(CPUDIR) \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -__OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) - ######################################################################### ######################################################################### @@ -331,75 +689,107 @@ ifneq ($(CONFIG_STATIC_RELA),) DO_STATIC_RELA = \ start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \ end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \ - $(obj)tools/relocate-rela $(2) $(3) $$start $$end + tools/relocate-rela $(2) $(3) $$start $$end else DO_STATIC_RELA = endif # Always append ALL so that arch config.mk's can add custom ones -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map +ALL-y += u-boot.srec u-boot.bin System.map -ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin -ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin -ALL-$(CONFIG_RAMBOOT_PBL) += $(obj)u-boot.pbl -ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin -ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img -ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin -ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin +ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin +ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img +ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb ifneq ($(CONFIG_SPL_TARGET),) -ALL-$(CONFIG_SPL) += $(obj)$(CONFIG_SPL_TARGET:"%"=%) +ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif -ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf +ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) ifeq ($(CONFIG_SPL),y) ifeq ($(CONFIG_OF_SEPARATE),y) -ALL-y += $(obj)u-boot-dtb-tegra.bin +ALL-y += u-boot-dtb-tegra.bin else -ALL-y += $(obj)u-boot-nodtb-tegra.bin +ALL-y += u-boot-nodtb-tegra.bin endif endif endif ifneq ($(CONFIG_ZYNQ),) ifeq ($(CONFIG_SPL),y) -ALL-y += $(obj)boot.bin +ALL-y += boot.bin endif endif -build := -f $(TOPDIR)/scripts/Makefile.build -C +LDFLAGS_u-boot += $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SYS_TEXT_BASE),) +LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) +endif -all: $(ALL-y) $(SUBDIR_EXAMPLES-y) +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -$(obj)u-boot.dtb: checkdtc $(obj)u-boot - $(MAKE) $(build) dts binary - mv $(obj)dts/dt.dtb $@ +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) -$(obj)u-boot-dtb.bin: $(obj)u-boot.bin $(obj)u-boot.dtb - cat $^ >$@ +quiet_cmd_cat = CAT $@ +cmd_cat = cat $(filter-out $(PHONY), $^) > $@ -$(obj)u-boot.hex: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ +append = cat $(filter-out $< $(PHONY), $^) >> $@ -$(obj)u-boot.srec: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ +quiet_cmd_pad_cat = CAT $@ +cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ -$(obj)u-boot.bin: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) - $(BOARD_SIZE_CHECK) +all: $(ALL-y) -$(obj)u-boot.ldr: $(obj)u-boot +PHONY += dtbs +dtbs dts/dt.dtb: checkdtc u-boot + $(Q)$(MAKE) $(build)=dts dtbs + +u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE + $(call if_changed,cat) + +%.imx: %.bin + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + +u-boot.dtb: dts/dt.dtb + $(call cmd,copy) + +OBJCOPYFLAGS_u-boot.hex := -O ihex + +OBJCOPYFLAGS_u-boot.srec := -O srec + +u-boot.hex u-boot.srec: u-boot FORCE + $(call if_changed,objcopy) + +OBJCOPYFLAGS_u-boot.bin := -O binary + +u-boot.bin: u-boot FORCE + $(call if_changed,objcopy) + $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) + $(BOARD_SIZE_CHECK) + +u-boot.ldr: u-boot $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) -$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary +OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex -$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary +OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec + +u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE + $(call if_changed,objcopy) # # U-Boot entry point, needed for booting of full-blown U-Boot @@ -409,79 +799,66 @@ ifndef CONFIG_SYS_UBOOT_START CONFIG_SYS_UBOOT_START := 0 endif -$(obj)u-boot.img: $(obj)u-boot.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ - -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_UBOOT_START) \ - -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ - sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ - -d $< $@ +MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -$(obj)u-boot.imx: $(obj)u-boot.bin depend - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx +MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ + -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -$(obj)u-boot.kwb: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ - -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage -$(obj)u-boot.pbl: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ - -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ - -d $< $@ +u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE + $(call if_changed,mkimage) -$(obj)u-boot.sha1: $(obj)u-boot.bin - $(obj)tools/ubsha1 $(obj)u-boot.bin +u-boot.sha1: u-boot.bin + tools/ubsha1 u-boot.bin -$(obj)u-boot.dis: $(obj)u-boot +u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -# $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate, -# $(4) is pad-to -SPL_PAD_APPEND = \ - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \ - $(1) $(obj)$(3); \ - cat $(obj)$(3) $(2) > $@; \ - rm $(obj)$(3) - ifdef CONFIG_TPL -SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin +SPL_PAYLOAD := tpl/u-boot-with-tpl.bin else -SPL_PAYLOAD := $(obj)u-boot.bin +SPL_PAYLOAD := u-boot.bin endif -$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD) - $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) +OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) +u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE + $(call if_changed,pad_cat) -$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin - $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO)) +OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_TPL_PAD_TO) +tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE + $(call if_changed,pad_cat) -$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \ - $(OBJTREE)/u-boot-with-spl.imx +SPL: spl/u-boot-spl.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \ - $(OBJTREE)/u-boot-with-nand-spl.imx +u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin - $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl +MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE) -$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \ - -T aisimage \ - -e $(CONFIG_SPL_TEXT_BASE) \ - -d $(obj)spl/u-boot-spl.bin \ - $(obj)spl/u-boot-spl.ais - $(OBJCOPY) ${OBJCFLAGS} -I binary \ - --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \ - $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais - cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \ - $(obj)u-boot.ais +u-boot.ubl: u-boot-with-spl.bin FORCE + $(call if_changed,mkimage) +MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ + $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ + -T aisimage -e $(CONFIG_SPL_TEXT_BASE) +spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) -$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin - $(MAKE) $(build) $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb +OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) +u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE + $(call if_changed,pad_cat) + +u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot-signed.sb +u-boot.sb: u-boot.bin spl/u-boot-spl.bin + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. # Both images are created using mkimage (crc etc), so that the ROM @@ -489,127 +866,240 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin # SPL image (with mkimage header) and not the binary. Otherwise the resulting image # which is loaded/copied by the ROM bootloader to SRAM doesn't fit. # The resulting image containing both U-Boot images is called u-boot.spr -$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ - -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ - -d $(obj)spl/u-boot-spl.bin $@ - $(OBJCOPY) -I binary -O binary \ - --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff $@ - cat $(obj)u-boot.img >> $@ +MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER +spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff +u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE + $(call if_changed,pad_cat) ifneq ($(CONFIG_TEGRA),) -$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ - rm $(obj)spl/u-boot-spl-pad.bin +OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) +u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE + $(call if_changed,pad_cat) ifeq ($(CONFIG_OF_SEPARATE),y) -$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb - cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@ +u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE + $(call if_changed,cat) endif endif -$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@ +u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE + $(call if_changed,cat) -$(obj)boot.bin: $(obj)spl/u-boot-spl.bin - tools/zynq-boot-bin.py -o $(obj)boot.bin -u $(obj)spl/u-boot-spl.bin +boot.bin: spl/u-boot-spl.bin + tools/zynq-boot-bin.py -o boot.bin -u spl/u-boot-spl.bin # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot # at the start padded up to the start of the SPL image. And then concat # the SPL image to the end. -$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - $(OBJCOPY) -I binary -O binary --pad-to=$(CONFIG_UBOOT_PAD_TO) \ - --gap-fill=0xff $(obj)u-boot.img $@ - cat $(obj)spl/u-boot-spl.bin >> $@ + +OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ + --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff +u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE + $(call if_changed,pad_cat) # Create a new ELF from a raw binary file. This is useful for arm64 # where static relocation needs to be performed on the raw binary, # but certain simulators only accept an ELF file (but don't do the # relocation). # FIXME refactor dts/Makefile to share target/arch detection -$(obj)u-boot.elf: $(obj)u-boot.bin +u-boot.elf: u-boot.bin @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ - $< $(obj)u-boot-elf.o - @$(LD) $(obj)u-boot-elf.o -o $@ \ + $< u-boot-elf.o + @$(LD) u-boot-elf.o -o $@ \ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) -ifeq ($(CONFIG_SANDBOX),y) -GEN_UBOOT = \ - cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ - -Wl,--start-group $(__LIBS) -Wl,--end-group \ - $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot -else -GEN_UBOOT = \ - cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ - $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot.map -o u-boot -endif +# Rule to link u-boot +# May be overridden by arch/$(ARCH)/config.mk +quiet_cmd_u-boot__ ?= LD $@ + cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \ + -T u-boot.lds $(u-boot-init) \ + --start-group $(u-boot-main) --end-group \ + $(PLATFORM_LIBS) -Map u-boot.map -$(obj)u-boot: depend \ - $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(obj)u-boot.lds - $(GEN_UBOOT) +u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds + $(call if_changed,u-boot__) ifeq ($(CONFIG_KALLSYMS),y) - smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \ - awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ - $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \ - -c common/system_map.c -o $(obj)common/system_map.o - $(GEN_UBOOT) $(obj)common/system_map.o + smap=`$(call SYSTEM_MAP,u-boot) | \ + awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ + $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ + -c $(srctree)/common/system_map.c -o common/system_map.o + $(call cmd,u-boot__) common/system_map.o endif -$(OBJS): +# The actual objects are generated when descending, +# make sure no implicit rule kicks in +$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ; + +# Handle descending into subdirectories listed in $(vmlinux-dirs) +# Preset locale variables to speed up the build process. Limit locale +# tweaks to this spot to avoid wrong language settings when running +# make menuconfig etc. +# Error messages still appears in the original language + +PHONY += $(u-boot-dirs) +$(u-boot-dirs): prepare scripts + $(Q)$(MAKE) $(build)=$@ + +tools: prepare +# The "tools" are needed early +$(filter-out tools, $(u-boot-dirs)): tools +# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC +# is "yes"), so compile examples after U-Boot is compiled. +examples: $(filter-out examples, $(u-boot-dirs)) + +define filechk_uboot.release + echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" +endef + +# Store (new) UBOOTRELEASE string in include/config/uboot.release +include/config/uboot.release: Makefile FORCE + $(call filechk,uboot.release) + + +# Things we need to do before we recursively start building the kernel +# or the modules are listed in "prepare". +# A multi level approach is used. prepareN is processed before prepareN-1. +# archprepare is used in arch Makefiles and when processed asm symlink, +# version.h and scripts_basic is processed / created. + +# Listed in dependency order +PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3 + +# prepare3 is used to check if we are building in a separate output directory, +# and if so do: +# 1) Check that make has not been executed in the kernel src $(srctree) +prepare3: include/config/uboot.release +ifneq ($(KBUILD_SRC),) + @$(kecho) ' Using $(srctree) as source for u-boot' + $(Q)if [ -f $(srctree)/include/config.mk ]; then \ + echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \ + echo >&2 " in the '$(srctree)' directory.";\ + /bin/false; \ + fi; +endif + +# prepare2 creates a makefile if using a separate output directory +prepare2: prepare3 outputmakefile + +prepare1: prepare2 $(version_h) $(timestamp_h) +ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo >&2 " Your architecture does not support generic board." + @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file." + @/bin/false +endif +endif +ifeq ($(wildcard $(LDSCRIPT)),) + @echo >&2 " Could not find linker script." + @/bin/false +endif + +archprepare: prepare1 scripts_basic + +prepare0: archprepare FORCE + $(Q)$(MAKE) $(build)=. + +# All the preparing.. +prepare: prepare0 + +# Generate some files +# --------------------------------------------------------------------------- + +define filechk_version.h + (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ + echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ + echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \ + echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; ) +endef + +define filechk_timestamp.h + (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C date +'#define U_BOOT_TIME "%T"') +endef + +$(version_h): include/config/uboot.release FORCE + $(call filechk,version.h) + +$(timestamp_h): $(srctree)/Makefile FORCE + $(call filechk,timestamp.h) + +# +# Auto-generate the autoconf.mk file (which is included by all makefiles) +# +# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. +# the dep file is only include in this top level makefile to determine when +# to regenerate the autoconf.mk file. + +quiet_cmd_autoconf_dep = GEN $@ + cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \ + -MQ include/autoconf.mk $(srctree)/include/common.h > $@ || rm $@ + +include/autoconf.mk.dep: include/config.h include/common.h + $(call cmd,autoconf_dep) + +quiet_cmd_autoconf = GEN $@ + cmd_autoconf = \ + $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ + rm $@.tmp + +include/autoconf.mk: include/config.h + $(call cmd,autoconf) + +# --------------------------------------------------------------------------- + +PHONY += depend dep +depend dep: + @echo '*** Warning: make $@ is unnecessary now.' + +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< + +u-boot.lds: $(LDSCRIPT) prepare FORCE + $(call if_changed_dep,cpp_lds) + +PHONY += nand_spl +nand_spl: prepare + $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all + @echo >&2 + @echo >&2 "==================== WARNING =====================" + @echo >&2 "nand_spl will not be included in v2014.07 release." + @echo >&2 "Please switch over to SPL." + @echo >&2 "Otherwise, this board will be removed." + @echo >&2 "==================================================" + @echo >&2 + +nand_spl/u-boot-spl-16k.bin: nand_spl @: -$(LIBS): depend $(SUBDIR_TOOLS) - $(MAKE) $(build) $(dir $(subst $(obj),,$@)) +u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE + $(call if_changed,cat) -$(SUBDIRS): depend - $(MAKE) -C $@ all +spl/u-boot-spl.bin: spl/u-boot-spl + @: +spl/u-boot-spl: tools prepare + $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all -$(SUBDIR_EXAMPLES-y): $(obj)u-boot +tpl/u-boot-tpl.bin: tools prepare + $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y -$(obj)u-boot.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ - -nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend - $(MAKE) -C nand_spl/board/$(BOARDDIR) all - -$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin - -$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend - $(MAKE) -C spl all - -$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend - $(MAKE) -C spl all CONFIG_TPL_BUILD=y - -# Explicitly make _depend in subdirs containing multiple targets to prevent -# parallel sub-makes creating .depend files simultaneously. -depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ - $(obj)include/spl-autoconf.mk \ - $(obj)include/tpl-autoconf.mk \ - $(obj)include/autoconf.mk \ - $(obj)include/generated/generic-asm-offsets.h \ - $(obj)include/generated/asm-offsets.h - -TAG_SUBDIRS = $(SUBDIRS) -TAG_SUBDIRS += $(dir $(__LIBS)) -TAG_SUBDIRS += include +TAG_SUBDIRS := $(u-boot-dirs) include FIND := find FINDFLAGS := -L -checkstack: - $(CROSS_COMPILE)objdump -d $(obj)u-boot \ - `$(FIND) $(obj) -name u-boot-spl -print` | \ - perl $(src)scripts/checkstack.pl $(ARCH) - tags ctags: - ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` etags: @@ -624,108 +1114,20 @@ SYSTEM_MAP = \ $(NM) $1 | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ LC_ALL=C sort -$(obj)System.map: $(obj)u-boot +System.map: u-boot @$(call SYSTEM_MAP,$<) > $@ -checkthumb: - @if test $(call cc-version) -lt 0404; then \ - echo -n '*** Your GCC does not produce working '; \ - echo 'binaries in THUMB mode.'; \ - echo '*** Your board is configured for THUMB mode.'; \ - false; \ - fi - -# GCC 3.x is reported to have problems generating the type of relocation -# that U-Boot wants. -# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html -checkgcc4: - @if test $(call cc-version) -lt 0400; then \ - echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ - false; \ - fi - checkdtc: @if test $(call dtc-version) -lt 0104; then \ echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \ false; \ fi -# -# Auto-generate the autoconf.mk file (which is included by all makefiles) -# -# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. -# the dep file is only include in this top level makefile to determine when -# to regenerate the autoconf.mk file. -$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h - @$(XECHO) Generating $@ ; \ - : Generate the dependancies ; \ - $(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \ - -MQ $(obj)include/autoconf.mk include/common.h > $@ || \ - rm $@ - -$(obj)include/autoconf.mk: $(obj)include/config.h - @$(XECHO) Generating $@ ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ - rm $@.tmp - -# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL) -$(obj)include/tpl-autoconf.mk: $(obj)include/config.h - @$(XECHO) Generating $@ ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\ - -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ - rm $@.tmp - -$(obj)include/spl-autoconf.mk: $(obj)include/config.h - @$(XECHO) Generating $@ ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ - rm $@.tmp - -$(obj)include/generated/generic-asm-offsets.h: $(obj)lib/asm-offsets.s - @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@ - -$(obj)lib/asm-offsets.s: $(obj)include/config.h $(src)lib/asm-offsets.c - @mkdir -p $(obj)lib - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)lib/asm-offsets.c -c -S - -$(obj)include/generated/asm-offsets.h: $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s - @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@ - -$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/config.h - @mkdir -p $(obj)$(CPUDIR)/$(SOC) - if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \ - else \ - touch $@; \ - fi - ######################################################################### -else # !config.mk -all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ -$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(filter-out tools,$(SUBDIRS)) \ -depend dep tags ctags etags cscope $(obj)System.map: - @echo "System not configured - see README" >&2 - @ exit 1 - -tools: $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) -C $@ all -endif # config.mk # ARM relocations should all be R_ARM_RELATIVE (32-bit) or # R_AARCH64_RELATIVE (64-bit). -checkarmreloc: $(obj)u-boot +checkarmreloc: u-boot @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ grep R_A | sort -u`"; \ if test "$$RELOC" != "R_ARM_RELATIVE" -a \ @@ -734,35 +1136,17 @@ checkarmreloc: $(obj)u-boot false; \ fi -$(VERSION_FILE): - @mkdir -p $(dir $(VERSION_FILE)) - @( localvers='$(shell $(TOPDIR)/scripts/setlocalversion $(TOPDIR))' ; \ - printf '#define PLAIN_VERSION "%s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - ) > $@.tmp - @( printf '#define CC_VERSION_STRING "%s"\n' \ - '$(shell $(CC) --version | head -n 1)' )>> $@.tmp - @( printf '#define LD_VERSION_STRING "%s"\n' \ - '$(shell $(LD) -v | head -n 1)' )>> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ +env: scripts_basic + $(Q)$(MAKE) $(build)=tools/$@ -$(TIMESTAMP_FILE): - @mkdir -p $(dir $(TIMESTAMP_FILE)) - @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@.tmp - @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ +tools-only: scripts_basic $(version_h) $(timestamp_h) + $(Q)$(MAKE) $(build)=tools -easylogo env gdb: - $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION} -gdbtools: gdb +tools-all: export HOST_TOOLS_ALL=y +tools-all: env tools ; -xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc - $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@ - -tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) -C tools HOST_TOOLS_ALL=y +cross_tools: export CROSS_BUILD_TOOLS=y +cross_tools: tools ; .PHONY : CHANGELOG CHANGELOG: @@ -773,106 +1157,250 @@ include/license.h: tools/bin2header COPYING cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h ######################################################################### -unconfig: - @rm -f $(obj)include/config.h $(obj)include/config.mk \ - $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ - $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \ - $(obj)include/spl-autoconf.mk \ - $(obj)include/tpl-autoconf.mk +### +# Cleaning is done on three levels. +# make clean Delete most generated files +# Leave enough to build external modules +# make mrproper Delete the current configuration, and all generated files +# make distclean Remove editor backup files, patch leftover files and the like -%_config:: unconfig - @$(MKCONFIG) -A $(@:_config=) +# Directories & files removed with 'make clean' +CLEAN_DIRS += $(MODVERDIR) +CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \ + include/autoconf.mk* include/spl-autoconf.mk \ + include/tpl-autoconf.mk -sinclude $(obj).boards.depend -$(obj).boards.depend: boards.cfg - @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@ +# Directories & files removed with 'make clobber' +CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \ + $(shell ls -1 spl 2>/dev/null))) \ + tpl +CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot* -######################################################################### -######################################################################### +# Directories & files removed with 'make mrproper' +MRPROPER_DIRS += include/config include/generated +MRPROPER_FILES += .config .config.old \ + tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \ + include/config.h include/config.mk -clean: - @rm -f $(obj)examples/standalone/atmel_df_pow2 \ - $(obj)examples/standalone/hello_world \ - $(obj)examples/standalone/interrupt \ - $(obj)examples/standalone/mem_to_mem_idma2intr \ - $(obj)examples/standalone/sched \ - $(obj)examples/standalone/smc911{11,x}_eeprom \ - $(obj)examples/standalone/test_burst \ - $(obj)examples/standalone/timer - @rm -f $(obj)examples/api/demo{,.bin} - @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \ - $(obj)tools/env/fw_printenv \ - $(obj)tools/envcrc \ - $(obj)tools/gdb/{gdbcont,gdbsend} \ - $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ - $(obj)tools/dump{env,}image \ - $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ - $(obj)tools/mk{$(BOARD),}spl \ - $(obj)tools/mxsboot \ - $(obj)tools/ncb $(obj)tools/ubsha1 \ - $(obj)tools/kernel-doc/docproc \ - $(obj)tools/proftool - @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ - $(obj)board/matrix_vision/*/bootscript.img \ - $(obj)u-boot.lds \ - $(obj)arch/blackfin/cpu/init.{lds,elf} - @rm -f $(obj)include/bmp_logo.h - @rm -f $(obj)include/bmp_logo_data.h - @rm -f $(obj)lib/asm-offsets.s - @rm -f $(obj)include/generated/asm-offsets.h - @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s - @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) - @$(MAKE) -s -C doc/DocBook/ cleandocs - @find $(OBJTREE) -type f \ - \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \ - -o -name '*.o' -o -name '*.a' -o -name '*.exe' \ - -o -name '*.cfgtmp' \) -print \ - | xargs rm -f +# clean - Delete most, but leave enough to build external modules +# +clean: rm-dirs := $(CLEAN_DIRS) +clean: rm-files := $(CLEAN_FILES) -# Removes everything not needed for testing u-boot -tidy: clean - @find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f +clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) -clobber: tidy - @find $(OBJTREE) -type f \( -name '*.srec' \ - -o -name '*.bin' -o -name u-boot.img \) \ - -print0 | xargs -0 rm -f - @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ - $(obj)cscope.* $(obj)*.*~ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) - @rm -f $(obj)u-boot.kwb - @rm -f $(obj)u-boot.pbl - @rm -f $(obj)u-boot.imx - @rm -f $(obj)u-boot-with-spl.imx - @rm -f $(obj)u-boot-with-nand-spl.imx - @rm -f $(obj)u-boot.ubl - @rm -f $(obj)u-boot.ais - @rm -f $(obj)u-boot.dtb - @rm -f $(obj)u-boot.sb - @rm -f $(obj)u-boot.spr - @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} - @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} - @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} - @rm -f $(obj)spl/u-boot-spl.lds - @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map} - @rm -f $(obj)tpl/u-boot-spl.lds - @rm -f $(obj)MLO MLO.byteswap - @rm -f $(obj)SPL - @rm -f $(obj)tools/xway-swap-bytes - @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm - @rm -fr $(obj)include/generated - @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f - @rm -f $(obj)dts/*.tmp - @rm -f $(obj)spl/u-boot-spl{,-pad}.ais +clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) -mrproper \ -distclean: clobber unconfig -ifneq ($(OBJTREE),$(SRCTREE)) - rm -rf $(obj)* -endif +PHONY += $(clean-dirs) clean archclean +$(clean-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@) + +# TODO: Do not use *.cfgtmp +clean: $(clean-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ + \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ + -o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \ + -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ + -o -name '*.symtypes' -o -name 'modules.order' \ + -o -name modules.builtin -o -name '.tmp_*.o.*' \ + -o -name '*.gcno' \) -type f -print | xargs rm -f + @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ + -path './nand_spl/*' -type l -print | xargs rm -f + +# clobber +# +clobber: rm-dirs := $(CLOBBER_DIRS) +clobber: rm-files := $(CLOBBER_FILES) + +PHONY += clobber + +clobber: clean + $(call cmd,rmdirs) + $(call cmd,rmfiles) + +# mrproper - Delete all generated files, including .config +# +mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS)) +mrproper: rm-files := $(wildcard $(MRPROPER_FILES)) +mrproper-dirs := $(addprefix _mrproper_,scripts) + +PHONY += $(mrproper-dirs) mrproper archmrproper +$(mrproper-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@) + +mrproper: clobber $(mrproper-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @rm -f arch/*/include/asm/arch arch/*/include/asm/proc + +# distclean +# +PHONY += distclean + +distclean: mrproper + @find $(srctree) $(RCS_FIND_IGNORE) \ + \( -name '*.orig' -o -name '*.rej' -o -name '*~' \ + -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \ + -o -name '.*.rej' -o -name '*.pyc' \ + -o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \ + -type f -print | xargs rm -f backup: - F=`basename $(TOPDIR)` ; cd .. ; \ + F=`basename $(srctree)` ; cd .. ; \ gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F -######################################################################### +help: + @echo 'Cleaning targets:' + @echo ' clean - Remove most generated files but keep the config and' + @echo ' necessities for testing u-boot' + @echo ' clobber - Remove most generated files but keep the config' + @echo ' mrproper - Remove all generated files + config + various backup files' + @echo ' distclean - mrproper + remove editor backup and patch files' + @echo '' +# uncomment after adding Kconfig feature +# @echo 'Configuration targets:' +# @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help +# @echo '' + @echo 'Other generic targets:' + @echo ' all - Build all necessary images depending on configuration' + @echo ' u-boot - Build the bare u-boot' + @echo ' dir/ - Build all files in dir and below' + @echo ' dir/file.[oisS] - Build specified target only' + @echo ' dir/file.lst - Build specified mixed source/assembly target only' + @echo ' (requires a recent binutils and recent build (System.map))' + @echo ' tags/TAGS - Generate tags file for editors' + @echo ' cscope - Generate cscope index' + @echo ' ubootrelease - Output the release version string' + @echo ' ubootversion - Output the version stored in Makefile' + @echo '' + @echo 'Static analysers' + @echo ' checkstack - Generate a list of stack hogs' + @echo '' + @echo 'Documentation targets:' + @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp + @echo '' + @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' + @echo ' make V=2 [targets] 2 => give reason for rebuild of target' + @echo ' make O=dir [targets] Locate all output files in "dir", including .config' + @echo ' make C=1 [targets] Check all c source with $$CHECK (sparse by default)' + @echo ' make C=2 [targets] Force check of all c source with $$CHECK' + @echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections' + @echo ' make W=n [targets] Enable extra gcc checks, n=1,2,3 where' + @echo ' 1: warnings which may be relevant and do not occur too often' + @echo ' 2: warnings which occur quite often but may still be relevant' + @echo ' 3: more obscure warnings, can most likely be ignored' + @echo ' Multiple levels can be combined with W=12 or W=123' + @echo '' + @echo 'Execute "make" or "make all" to build all targets marked with [*] ' + @echo 'For further info see the ./README file' + + +# Documentation targets +# --------------------------------------------------------------------------- +%docs: scripts_basic FORCE + $(Q)$(MAKE) $(build)=scripts build_docproc + $(Q)$(MAKE) $(build)=doc/DocBook $@ + +# Dummies... +PHONY += prepare scripts +prepare: ; +scripts: ; + +endif #ifeq ($(config-targets),1) +endif #ifeq ($(mixed-targets),1) + +PHONY += checkstack ubootrelease ubootversion + +checkstack: + $(OBJDUMP) -d u-boot $$(find . -name u-boot-spl) | \ + $(PERL) $(src)/scripts/checkstack.pl $(ARCH) + +ubootrelease: + @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + +ubootversion: + @echo $(UBOOTVERSION) + +# Single targets +# --------------------------------------------------------------------------- +# Single targets are compatible with: +# - build with mixed source and output +# - build with separate output dir 'make O=...' +# - external modules +# +# target-dir => where to store outputfile +# build-dir => directory in kernel source tree to use + +ifeq ($(KBUILD_EXTMOD),) + build-dir = $(patsubst %/,%,$(dir $@)) + target-dir = $(dir $@) +else + zap-slash=$(filter-out .,$(patsubst %/,%,$(dir $@))) + build-dir = $(KBUILD_EXTMOD)$(if $(zap-slash),/$(zap-slash)) + target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@)) +endif + +%.s: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.i: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.lst: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.s: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.symtypes: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) + +# Modules +/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%.ko: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) $(@:.ko=.o) + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost + +# FIXME Should go into a make.lib or something +# =========================================================================== + +quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs))) + cmd_rmdirs = rm -rf $(rm-dirs) + +quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))) + cmd_rmfiles = rm -f $(rm-files) + +# read all saved command lines + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard .*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + $(cmd_files): ; # Do not try to update included dependency files + include $(cmd_files) +endif + +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj + +endif # skip-makefile + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/README b/README index fb1c0fd20d..0145be2f68 100644 --- a/README +++ b/README @@ -141,7 +141,6 @@ Directory Hierarchy: /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm926ejs Files specific to ARM 926 CPUs /arm1136 Files specific to ARM 1136 CPUs - /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files @@ -472,6 +471,37 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + + CONFIG_SYS_FSL_PBL_PBI + It enables addition of RCW (Power on reset configuration) in built image. + Please refer doc/README.pblimage for more details + + CONFIG_SYS_FSL_PBL_RCW + It adds PBI(pre-boot instructions) commands in u-boot build image. + PBI commands can be used to configure SoC before it starts the execution. + Please refer doc/README.pblimage for more details + + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -536,6 +566,8 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -908,10 +940,11 @@ The following options need to be configured: CONFIG_CMD_EXPORTENV * export the environment CONFIG_CMD_EXT2 * ext2 command support CONFIG_CMD_EXT4 * ext4 command support + CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls) + that work for multiple fs types CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support - CONFIG_CMD_FDOS * Dos diskette Support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support CONFIG_CMD_FUSE * Device fuse support @@ -981,11 +1014,11 @@ The following options need to be configured: CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_MFSL * Microblaze FSL support CONFIG_CMD_XIMG Load part of Multi Image + CONFIG_CMD_UUID * Generate random UUID or GUID string CONFIG_CMD_ZYNQ_AES * Support decryption of encrypted images for zynq CONFIG_CMD_ZYNQ_RSA * Support RSA-AES for zynq. This enables CONFIG_CMD_ZYNQ_AES too. - EXAMPLE: If you want all functions except of network support you can write: @@ -1497,6 +1530,16 @@ The following options need to be configured: this to the maximum filesize (in bytes) for the buffer. Default is 4 MiB if undefined. + DFU_DEFAULT_POLL_TIMEOUT + Poll timeout [ms], is the timeout a device can send to the + host. The host must wait for this timeout before sending + a subsequent DFU_GET_STATUS request to the device. + + DFU_MANIFEST_POLL_TIMEOUT + Poll timeout [ms], which the device sends to the host when + entering dfuMANIFEST state. Host waits this timeout, before + sending again an USB request to the device. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1713,7 +1756,7 @@ CBFS (Coreboot Filesystem) support If this option is set, then U-Boot will prevent the environment variable "splashimage" from being set to a problematic address - (see README.displaying-bmps and README.arm-unaligned-accesses). + (see README.displaying-bmps). This option is useful for targets where, due to alignment restrictions, an improperly aligned BMP image will cause a data abort. If you think you will not have problems with unaligned @@ -2836,11 +2879,31 @@ CBFS (Coreboot Filesystem) support CONFIG_RSA This enables the RSA algorithm used for FIT image verification - in U-Boot. See doc/uImage/signature for more information. + in U-Boot. See doc/uImage.FIT/signature.txt for more information. The signing part is build into mkimage regardless of this option. +- bootcount support: + CONFIG_BOOTCOUNT_LIMIT + + This enables the bootcounter support, see: + http://www.denx.de/wiki/DULG/UBootBootCountLimit + + CONFIG_AT91SAM9XE + enable special bootcounter support on at91sam9xe based boards. + CONFIG_BLACKFIN + enable special bootcounter support on blackfin based boards. + CONFIG_SOC_DA8XX + enable special bootcounter support on da850 based boards. + CONFIG_BOOTCOUNT_RAM + enable support for the bootcounter in RAM + CONFIG_BOOTCOUNT_I2C + enable support for the bootcounter on an i2c (like RTC) device. + CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for + the bootcounter. + CONFIG_BOOTCOUNT_ALEN = address len - Show boot progress: CONFIG_SHOW_BOOT_PROGRESS @@ -3422,6 +3485,9 @@ typically in board_init_f() and board_init_r(). Configuration Settings: ----------------------- +- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit. + Optionally it can be defined to support 64-bit memory commands. + - CONFIG_SYS_LONGHELP: Defined when you want long help messages included; undefine this when you're short of memory. @@ -3694,12 +3760,6 @@ Configuration Settings: its config.mk file). If you find problems enabling this option on your board please report the problem and send patches! -- CONFIG_SYS_SYM_OFFSETS - This is set by architectures that use offsets for link symbols - instead of absolute values. So bss_start is obtained using an - offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than - directly. You should not need to touch this setting. - - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) This is set by OMAP boards for the max time that reset should be asserted. See doc/README.omap-reset-time for details on how diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index eb421d642d..f23f17501f 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk; -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC5xxx) diff --git a/arch/arc/config.mk b/arch/arc/config.mk new file mode 100644 index 0000000000..a3b8df779e --- /dev/null +++ b/arch/arc/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SYS_BIG_ENDIAN +CONFIG_SYS_LITTLE_ENDIAN = 1 +endif + +ifdef CONFIG_SYS_LITTLE_ENDIAN +ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc- +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc- +PLATFORM_LDFLAGS += -EB +endif + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(ARC_CROSS_COMPILE) +endif + +PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2 + +# Needed for relocation +LDFLAGS_FINAL += -pie + +# Load address for standalone apps +CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 + +# Support generic board on ARC +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile new file mode 100644 index 0000000000..cdc5002290 --- /dev/null +++ b/arch/arc/cpu/arc700/Makefile @@ -0,0 +1,13 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y += start.o + +obj-y += cache.o +obj-y += cpu.o +obj-y += interrupts.o +obj-y += reset.o +obj-y += timer.o diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c new file mode 100644 index 0000000000..39d522d22f --- /dev/null +++ b/arch/arc/cpu/arc700/cache.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* Bit values in IC_CTRL */ +#define IC_CTRL_CACHE_DISABLE (1 << 0) + +/* Bit values in DC_CTRL */ +#define DC_CTRL_CACHE_DISABLE (1 << 0) +#define DC_CTRL_INV_MODE_FLUSH (1 << 6) +#define DC_CTRL_FLUSH_STATUS (1 << 8) + +int icache_status(void) +{ + return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) != + IC_CTRL_CACHE_DISABLE; +} + +void icache_enable(void) +{ + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & + ~IC_CTRL_CACHE_DISABLE); +} + +void icache_disable(void) +{ + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); +} + +void invalidate_icache_all(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ + write_aux_reg(ARC_AUX_IC_IVIC, 1); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} + +int dcache_status(void) +{ + return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) != + DC_CTRL_CACHE_DISABLE; +} + +void dcache_enable(void) +{ + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & + ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); +} + +void dcache_disable(void) +{ + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | + DC_CTRL_CACHE_DISABLE); +} + +void flush_dcache_all(void) +{ + /* Do flush of entire cache */ + write_aux_reg(ARC_AUX_DC_FLSH, 1); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +static void dcache_flush_line(unsigned addr) +{ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_FLDL, addr); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; + +#ifndef CONFIG_SYS_ICACHE_OFF + /* + * Invalidate I$ for addresses range just flushed from D$. + * If we try to execute data flushed above it will be valid/correct + */ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_IC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_IC_IVIL, addr); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} +#endif /* CONFIG_SYS_DCACHE_OFF */ + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) + dcache_flush_line(addr); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_IVDL, addr); + } +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_all(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */ + write_aux_reg(ARC_AUX_DC_IVDC, 1); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk new file mode 100644 index 0000000000..3206ff47e3 --- /dev/null +++ b/arch/arc/cpu/arc700/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -mA7 diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c new file mode 100644 index 0000000000..50634b860f --- /dev/null +++ b/arch/arc/cpu/arc700/cpu.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SYS_ICACHE_OFF + icache_disable(); +#else + icache_enable(); + invalidate_icache_all(); +#endif + + flush_dcache_all(); +#ifdef CONFIG_SYS_DCACHE_OFF + dcache_disable(); +#else + dcache_enable(); +#endif + timer_init(); + +/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */ + if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00) + gd->arch.running_on_hw = 0; + else + gd->arch.running_on_hw = 1; + + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int arch_early_init_r(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c new file mode 100644 index 0000000000..d93a6eb547 --- /dev/null +++ b/arch/arc/cpu/arc700/interrupts.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* Bit values in STATUS32 */ +#define E1_MASK (1 << 1) /* Level 1 interrupts enable */ +#define E2_MASK (1 << 2) /* Level 2 interrupts enable */ + +int interrupt_init(void) +{ + return 0; +} + +/* + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts(void) +{ + int status = read_aux_reg(ARC_AUX_STATUS32); + int state = (status | E1_MASK | E2_MASK) ? 1 : 0; + + status &= ~(E1_MASK | E2_MASK); + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); + return state; +} + +void enable_interrupts(void) +{ + unsigned int status = read_aux_reg(ARC_AUX_STATUS32); + + status |= E1_MASK | E2_MASK; + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); +} + +static void print_reg_file(long *reg_rev, int start_num) +{ + unsigned int i; + + /* Print 3 registers per line */ + for (i = start_num; i < start_num + 25; i++) { + printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev); + if (((i + 1) % 3) == 0) + printf("\n"); + + /* Because pt_regs has registers reversed */ + reg_rev--; + } + + /* Add new-line if none was inserted in the end of loop above */ + if (((i + 1) % 3) != 0) + printf("\n"); +} + +void show_regs(struct pt_regs *regs) +{ + printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n", + regs->ret, regs->blink, regs->status32); + printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25); + printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta, + regs->sp, regs->fp); + printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start, + regs->lp_end, regs->lp_count); + + print_reg_file(&(regs->r0), 0); +} + +void bad_mode(struct pt_regs *regs) +{ + if (regs) + show_regs(regs); + + panic("Resetting CPU ...\n"); +} + +void do_memory_error(unsigned long address, struct pt_regs *regs) +{ + printf("Memory error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_instruction_error(unsigned long address, struct pt_regs *regs) +{ + printf("Instruction error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_machine_check_fault(unsigned long address, struct pt_regs *regs) +{ + printf("Machine check exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_interrupt_handler(void) +{ + printf("Interrupt fired\n"); + bad_mode(0); +} + +void do_itlb_miss(struct pt_regs *regs) +{ + printf("I TLB miss exception\n"); + bad_mode(regs); +} + +void do_dtlb_miss(struct pt_regs *regs) +{ + printf("D TLB miss exception\n"); + bad_mode(regs); +} + +void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs) +{ + printf("TLB protection violation or misaligned access @ 0x%lx\n", + address); + bad_mode(regs); +} + +void do_privilege_violation(struct pt_regs *regs) +{ + printf("Privilege violation exception\n"); + bad_mode(regs); +} + +void do_trap(struct pt_regs *regs) +{ + printf("Trap exception\n"); + bad_mode(regs); +} + +void do_extension(struct pt_regs *regs) +{ + printf("Extension instruction exception\n"); + bad_mode(regs); +} diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c new file mode 100644 index 0000000000..98ebf1d445 --- /dev/null +++ b/arch/arc/cpu/arc700/reset.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("Put your restart handler here\n"); + +#ifdef DEBUG + /* Stop debug session here */ + __asm__("brk"); +#endif + return 0; +} diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S new file mode 100644 index 0000000000..563513b690 --- /dev/null +++ b/arch/arc/cpu/arc700/start.S @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Note on the LD/ST addressing modes with address register write-back + * + * LD.a same as LD.aw + * + * LD.a reg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +.macro PUSH reg + st.a \reg, [%sp, -4] +.endm + +.macro PUSHAX aux + lr %r9, [\aux] + PUSH %r9 +.endm + +.macro SAVE_R1_TO_R24 + PUSH %r1 + PUSH %r2 + PUSH %r3 + PUSH %r4 + PUSH %r5 + PUSH %r6 + PUSH %r7 + PUSH %r8 + PUSH %r9 + PUSH %r10 + PUSH %r11 + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + PUSH %r16 + PUSH %r17 + PUSH %r18 + PUSH %r19 + PUSH %r20 + PUSH %r21 + PUSH %r22 + PUSH %r23 + PUSH %r24 +.endm + +.macro SAVE_ALL_SYS + + st %r0, [%sp] + lr %r0, [%ecr] + st %r0, [%sp, 8] /* ECR */ + st %sp, [%sp, 4] + + SAVE_R1_TO_R24 + PUSH %r25 + PUSH %gp + PUSH %fp + PUSH %blink + PUSHAX %eret + PUSHAX %erstatus + PUSH %lp_count + PUSHAX %lp_end + PUSHAX %lp_start + PUSHAX %erbta +.endm + +.align 4 +.globl _start +_start: + /* Critical system events */ + j reset /* 0 - 0x000 */ + j memory_error /* 1 - 0x008 */ + j instruction_error /* 2 - 0x010 */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr + /* Exceptions */ + j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ + j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ + j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ + j EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ + j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ + j EV_Trap /* 0x128, Trap exception (0x25) */ + j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ + +memory_error: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_memory_error + +instruction_error: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_instruction_error + +interrupt_handler: + /* Todo - save and restore CPU context when interrupts will be in use */ + bl do_interrupt_handler + rtie + +EV_MachineCheck: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_machine_check_fault + +EV_TLBMissI: + SAVE_ALL_SYS + mov %r0, %sp + j do_itlb_miss + +EV_TLBMissD: + SAVE_ALL_SYS + mov %r0, %sp + j do_dtlb_miss + +EV_TLBProtV: + SAVE_ALL_SYS + lr %r0, [%efa] + mov %r1, %sp + j do_tlb_prot_violation + +EV_PrivilegeV: + SAVE_ALL_SYS + mov %r0, %sp + j do_privilege_violation + +EV_Trap: + SAVE_ALL_SYS + mov %r0, %sp + j do_trap + +EV_Extension: + SAVE_ALL_SYS + mov %r0, %sp + j do_extension + + +reset: + /* Setup interrupt vector base that matches "__text_start" */ + sr __text_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack pointer */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Clear bss */ + mov %r0, __bss_start + mov %r1, __bss_end + +clear_bss: + st.ab 0, [%r0, 4] + brlt %r0, %r1, clear_bss + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r0 = start_addr_sp + * r1 = new__gd + * r2 = relocaddr + */ +.align 4 +.globl relocate_code +relocate_code: + /* + * r0-r12 might be clobbered by C functions + * so we use r13-r16 for storage here + */ + mov %r13, %r0 /* save addr_sp */ + mov %r14, %r1 /* save addr of gd */ + mov %r15, %r2 /* save addr of destination */ + + mov %r16, %r2 /* %r9 - relocation offset */ + sub %r16, %r16, __image_copy_start + +/* Set up the stack */ +stack_setup: + mov %sp, %r13 + mov %fp, %sp + +/* Check if monitor is loaded right in place for relocation */ + mov %r0, __image_copy_start + cmp %r0, %r15 /* skip relocation if code loaded */ + bz do_board_init_r /* in target location already */ + +/* Copy data (__image_copy_start - __image_copy_end) to new location */ + mov %r1, %r15 + mov %r2, __image_copy_end + sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ + asr %r2, %r2, 2 /* r3 <- amount of words to copy */ + mov %lp_count, %r2 + lp copy_end + ld.ab %r2,[%r0,4] + st.ab %r2,[%r1,4] +copy_end: + +/* Fix relocations related issues */ + bl do_elf_reloc_fixups +#ifndef CONFIG_SYS_ICACHE_OFF + bl invalidate_icache_all +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + bl flush_dcache_all +#endif + +/* Update position of intterupt vector table */ + lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ + add %r0, %r0, %r16 /* Update address */ + sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ + +do_board_init_r: +/* Prepare for exection of "board_init_r" in relocated monitor */ + mov %r2, board_init_r /* old address of "board_init_r()" */ + add %r2, %r2, %r16 /* new address of "board_init_r()" */ + mov %r0, %r14 /* 1-st parameter: gd_t */ + mov %r1, %r15 /* 2-nd parameter: dest_addr */ + j [%r2] diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c new file mode 100644 index 0000000000..a0acbbc01a --- /dev/null +++ b/arch/arc/cpu/arc700/timer.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */ + +int timer_init(void) +{ + write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); + /* Set max value for counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); + /* Set initial count value and restart counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_CNT, 0); + return 0; +} + +unsigned long timer_read_counter(void) +{ + return read_aux_reg(ARC_AUX_TIMER0_CNT); +} diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds new file mode 100644 index 0000000000..2d01b21b36 --- /dev/null +++ b/arch/arc/cpu/arc700/u-boot.lds @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") +OUTPUT_ARCH(arc) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : { + *(.__text_start) + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .text_end : + { + *(.__text_end) + } + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rel_dyn_start : { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela.dyn) + } + + .rel_dyn_end : { + *(.__rel_dyn_end) + } + + . = ALIGN(4); + .bss_start : { + *(.__bss_start); + } + + .bss : { + *(.bss*) + } + + .bss_end : { + *(.__bss_end); + } + + . = ALIGN(4); + .image_copy_end : { + *(.__image_copy_end) + *(.__init_end) + } +} diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h new file mode 100644 index 0000000000..5d48d11bab --- /dev/null +++ b/arch/arc/include/asm/arcregs.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_ARCREGS_H +#define _ASM_ARC_ARCREGS_H + +/* + * ARC architecture has additional address space - auxiliary registers. + * These registers are mostly used for configuration purposes. + * These registers are not memory mapped and special commands are used for + * access: "lr"/"sr". + */ + +#define ARC_AUX_IDENTITY 0x04 +#define ARC_AUX_STATUS32 0x0a + +/* Instruction cache related auxiliary registers */ +#define ARC_AUX_IC_IVIC 0x10 +#define ARC_AUX_IC_CTRL 0x11 +#define ARC_AUX_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_IC_PTAG 0x1E +#endif + +/* Timer related auxiliary registers */ +#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ +#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ +#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ + +#define ARC_AUX_INTR_VEC_BASE 0x25 + +/* Data cache related auxiliary registers */ +#define ARC_AUX_DC_IVDC 0x47 +#define ARC_AUX_DC_CTRL 0x48 + +#define ARC_AUX_DC_IVDL 0x4A +#define ARC_AUX_DC_FLSH 0x4B +#define ARC_AUX_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_DC_PTAG 0x5C +#endif + +#ifndef __ASSEMBLY__ +/* Accessors for auxiliary registers */ +#define read_aux_reg(reg) __builtin_arc_lr(reg) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(reg_immed, val) \ + __builtin_arc_sr((unsigned int)val, reg_immed) +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h new file mode 100644 index 0000000000..85721aaee3 --- /dev/null +++ b/arch/arc/include/asm/bitops.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BITOPS_H +#define __ASM_ARC_BITOPS_H + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __ASM_ARC_BITOPS_H */ diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h new file mode 100644 index 0000000000..2fa9776ca5 --- /dev/null +++ b/arch/arc/include/asm/byteorder.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BYTEORDER_H +#define __ASM_ARC_BYTEORDER_H + +#include + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) + #define __BYTEORDER_HAS_U64__ + #define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ + #include +#else + #include +#endif /* CONFIG_SYS_BIG_ENDIAN */ + +#endif /* ASM_ARC_BYTEORDER_H */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h new file mode 100644 index 0000000000..16e7568ef0 --- /dev/null +++ b/arch/arc/include/asm/cache.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CACHE_H +#define __ASM_ARC_CACHE_H + +#include + +/* + * The current upper bound for ARC L1 data cache line sizes is 128 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 128 +#endif + +#endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h new file mode 100644 index 0000000000..5761def1e7 --- /dev/null +++ b/arch/arc/include/asm/config.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CONFIG_H_ +#define __ASM_ARC_CONFIG_H_ + +#define CONFIG_LMB + +#endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h new file mode 100644 index 0000000000..4c82b503d9 --- /dev/null +++ b/arch/arc/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h new file mode 100644 index 0000000000..d644e80586 --- /dev/null +++ b/arch/arc/include/asm/global_data.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_GLOBAL_DATA_H +#define __ASM_ARC_GLOBAL_DATA_H + +/* Architecture-specific global data */ +struct arch_global_data { + int running_on_hw; +}; + +#include + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25") + +#endif /* __ASM_ARC_GLOBAL_DATA_H */ diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h new file mode 100644 index 0000000000..24b7337308 --- /dev/null +++ b/arch/arc/include/asm/io.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_IO_H +#define __ASM_ARC_IO_H + +#include +#include + +static inline void sync(void) +{ + /* Not yet implemented */ +} + +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 b; + + __asm__ __volatile__("ldb%U1 %0, %1\n" + : "=r" (b) + : "m" (*(volatile u8 __force *)addr) + : "memory"); + return b; +} + +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 s; + + __asm__ __volatile__("ldw%U1 %0, %1\n" + : "=r" (s) + : "m" (*(volatile u16 __force *)addr) + : "memory"); + return s; +} + +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 w; + + __asm__ __volatile__("ld%U1 %0, %1\n" + : "=r" (w) + : "m" (*(volatile u32 __force *)addr) + : "memory"); + return w; +} + +#define readb __raw_readb + +static inline u16 readw(const volatile void __iomem *addr) +{ + return __le16_to_cpu(__raw_readw(addr)); +} + +static inline u32 readl(const volatile void __iomem *addr) +{ + return __le32_to_cpu(__raw_readl(addr)); +} + +static inline void __raw_writeb(u8 b, volatile void __iomem *addr) +{ + __asm__ __volatile__("stb%U1 %0, %1\n" + : + : "r" (b), "m" (*(volatile u8 __force *)addr) + : "memory"); +} + +static inline void __raw_writew(u16 s, volatile void __iomem *addr) +{ + __asm__ __volatile__("stw%U1 %0, %1\n" + : + : "r" (s), "m" (*(volatile u16 __force *)addr) + : "memory"); +} + +static inline void __raw_writel(u32 w, volatile void __iomem *addr) +{ + __asm__ __volatile__("st%U1 %0, %1\n" + : + : "r" (w), "m" (*(volatile u32 __force *)addr) + : "memory"); +} + +#define writeb __raw_writeb +#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr) +#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr) + +static inline int __raw_readsb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stb.ab r8, [r1, 1]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_readsw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stw.ab r8, [r1, 2]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_readsl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab r8, [r1, 4]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +static inline int __raw_writesb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_writesw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_writesl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#endif /* __ASM_ARC_IO_H */ diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h new file mode 100644 index 0000000000..20415f0705 --- /dev/null +++ b/arch/arc/include/asm/posix_types.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_POSIX_TYPES_H +#define __ASM_ARC_POSIX_TYPES_H + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +#endif /* __ASM_ARC_POSIX_TYPES_H */ diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h new file mode 100644 index 0000000000..8f73b31c10 --- /dev/null +++ b/arch/arc/include/asm/ptrace.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_PTRACE_H +#define __ASM_ARC_PTRACE_H + +struct pt_regs { + long bta; + long lp_start; + long lp_end; + long lp_count; + long status32; + long ret; + long blink; + long fp; + long r26; /* gp */ + long r25; + long r24; + long r23; + long r22; + long r21; + long r20; + long r19; + long r18; + long r17; + long r16; + long r15; + long r14; + long r13; + long r12; + long r11; + long r10; + long r9; + long r8; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long sp; + long ecr; +}; + +#endif /* __ASM_ARC_PTRACE_H */ diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h new file mode 100644 index 0000000000..18484a17f2 --- /dev/null +++ b/arch/arc/include/asm/sections.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_SECTIONS_H +#define __ASM_ARC_SECTIONS_H + +#include + +extern ulong __text_end; + +#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h new file mode 100644 index 0000000000..909129c333 --- /dev/null +++ b/arch/arc/include/asm/string.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_STRING_H +#define __ASM_ARC_STRING_H + +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_STRCHR +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRLEN + +extern void *memset(void *ptr, int, __kernel_size_t); +extern void *memcpy(void *, const void *, __kernel_size_t); +extern void memzero(void *ptr, __kernel_size_t n); +extern int memcmp(const void *, const void *, __kernel_size_t); +extern char *strchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern int strcmp(const char *cs, const char *ct); +extern __kernel_size_t strlen(const char *); + +#endif /* __ASM_ARC_STRING_H */ diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h new file mode 100644 index 0000000000..24eeb76bd6 --- /dev/null +++ b/arch/arc/include/asm/types.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_TYPES_H +#define __ASM_ARC_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __ASM_ARC_TYPES_H */ diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h new file mode 100644 index 0000000000..0c0e8e661d --- /dev/null +++ b/arch/arc/include/asm/u-boot-arc.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_ARC_H__ +#define __ASM_ARC_U_BOOT_ARC_H__ + +int arch_early_init_r(void); + +#endif /* __ASM_ARC_U_BOOT_ARC_H__ */ diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h new file mode 100644 index 0000000000..e354edf95d --- /dev/null +++ b/arch/arc/include/asm/u-boot.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_H__ +#define __ASM_ARC_U_BOOT_H__ + +#include + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_ARC + +#endif /* __ASM_ARC_U_BOOT_H__ */ diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h new file mode 100644 index 0000000000..6cecbbb211 --- /dev/null +++ b/arch/arc/include/asm/unaligned.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile new file mode 100644 index 0000000000..7675f855d5 --- /dev/null +++ b/arch/arc/lib/Makefile @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sections.o +obj-y += relocate.o +obj-y += strchr-700.o +obj-y += strcmp.o +obj-y += strcpy-700.o +obj-y += strlen.o +obj-y += memcmp.o +obj-y += memcpy-700.o +obj-y += memset.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c new file mode 100644 index 0000000000..d185a50bd3 --- /dev/null +++ b/arch/arc/lib/bootm.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); +} + +static int cleanup_before_linux(void) +{ + disable_interrupts(); + flush_dcache_all(); + invalidate_icache_all(); + + return 0; +} + +/* Subcommand: PREP */ +static void boot_prep_linux(bootm_headers_t *images) +{ + if (image_setup_linux(images)) + hang(); +} + +/* Subcommand: GO */ +static void boot_jump_linux(bootm_headers_t *images, int flag) +{ + void (*kernel_entry)(int zero, int arch, uint params); + unsigned int r0, r2; + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel_entry = (void (*)(int, int, uint))images->ep; + + debug("## Transferring control to Linux (at address %08lx)...\n", + (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + printf("\nStarting kernel ...%s\n\n", fake ? + "(fake run for tracing)" : ""); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + + cleanup_before_linux(); + + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + r0 = 2; + r2 = (unsigned int)images->ft_addr; + } else { + r0 = 1; + r2 = (unsigned int)getenv("bootargs"); + } + + if (!fake) + kernel_entry(r0, 0, r2); +} + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + /* No need for those on ARC */ + if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE)) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + boot_jump_linux(images, flag); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images, flag); + return 0; +} diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S new file mode 100644 index 0000000000..fa5aac5f67 --- /dev/null +++ b/arch/arc/lib/memcmp.S @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __LITTLE_ENDIAN__ +#define WORD2 r2 +#define SHIFT r3 +#else /* __BIG_ENDIAN__ */ +#define WORD2 r3 +#define SHIFT r2 +#endif /* _ENDIAN__ */ + +.global memcmp +.align 4 +memcmp: + or %r12, %r0, %r1 + asl_s %r12, %r12, 30 + sub %r3, %r2, 1 + brls %r2, %r12, .Lbytewise + ld %r4, [%r0, 0] + ld %r5, [%r1, 0] + lsr.f %lp_count, %r3, 3 + lpne .Loop_end + ld_s WORD2, [%r0, 4] + ld_s %r12, [%r1, 4] + brne %r4, %r5, .Leven + ld.a %r4, [%r0, 8] + ld.a %r5, [%r1, 8] + brne WORD2, %r12, .Lodd +.Loop_end: + asl_s SHIFT, SHIFT, 3 + bhs_s .Last_cmp + brne %r4, %r5, .Leven + ld %r4, [%r0, 4] + ld %r5, [%r1, 4] +#ifdef __LITTLE_ENDIAN__ + nop_s + /* one more load latency cycle */ +.Last_cmp: + xor %r0, %r4, %r5 + bset %r0, %r0, SHIFT + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + b.d .Leven_cmp + and %r1, %r1, 24 +.Leven: + xor %r0, %r4, %r5 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 +.Leven_cmp: + asl %r2, %r4, %r1 + asl %r12, %r5, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 + .balign 4 +.Lodd: + xor %r0, WORD2, %r12 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 + asl_s %r2, %r2, %r1 + asl_s %r12, %r12, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 +#else /* __BIG_ENDIAN__ */ +.Last_cmp: + neg_s SHIFT, SHIFT + lsr %r4, %r4, SHIFT + lsr %r5, %r5, SHIFT + /* slow track insn */ +.Leven: + sub.f %r0, %r4, %r5 + mov.ne %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +.Lodd: + cmp_s WORD2, %r12 + + mov_s %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +#endif /* _ENDIAN__ */ + .balign 4 +.Lbytewise: + breq %r2, 0, .Lnil + ldb %r4, [%r0, 0] + ldb %r5, [%r1, 0] + lsr.f %lp_count, %r3 + lpne .Lbyte_end + ldb_s %r3, [%r0, 1] + ldb %r12, [%r1, 1] + brne %r4, %r5, .Lbyte_even + ldb.a %r4, [%r0, 2] + ldb.a %r5, [%r1, 2] + brne %r3, %r12, .Lbyte_odd +.Lbyte_end: + bcc .Lbyte_even + brne %r4, %r5, .Lbyte_even + ldb_s %r3, [%r0, 1] + ldb_s %r12, [%r1, 1] +.Lbyte_odd: + j_s.d [%blink] + sub %r0, %r3, %r12 +.Lbyte_even: + j_s.d [%blink] + sub %r0, %r4, %r5 +.Lnil: + j_s.d [%blink] + mov %r0, 0 diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S new file mode 100644 index 0000000000..51dd73ab8f --- /dev/null +++ b/arch/arc/lib/memcpy-700.S @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global memcpy +.align 4 +memcpy: + or %r3, %r0, %r1 + asl_s %r3, %r3, 30 + mov_s %r5, %r0 + brls.d %r2, %r3, .Lcopy_bytewise + sub.f %r3, %r2, 1 + ld_s %r12, [%r1, 0] + asr.f %lp_count, %r3, 3 + bbit0.d %r3, 2, .Lnox4 + bmsk_s %r2, %r2, 1 + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 4] +.Lnox4: + lppnz .Lendloop + ld_s %r3, [%r1, 4] + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 8] + st.ab %r3, [%r5, 4] +.Lendloop: + breq %r2, 0, .Last_store + ld %r3, [%r5, 0] +#ifdef __LITTLE_ENDIAN__ + add3 %r2, -1, %r2 + /* uses long immediate */ + xor_s %r12, %r12, %r3 + bmsk %r12, %r12, %r2 + xor_s %r12, %r12, %r3 +#else /* __BIG_ENDIAN__ */ + sub3 %r2, 31, %r2 + /* uses long immediate */ + xor_s %r3, %r3, %r12 + bmsk %r3, %r3, %r2 + xor_s %r12, %r12, %r3 +#endif /* _ENDIAN__ */ +.Last_store: + j_s.d [%blink] + st %r12, [%r5, 0] + + .balign 4 +.Lcopy_bytewise: + jcs [%blink] + ldb_s %r12, [%r1, 0] + lsr.f %lp_count, %r3 + bhs_s .Lnox1 + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 1] +.Lnox1: + lppnz .Lendbloop + ldb_s %r3, [%r1, 1] + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 2] + stb.ab %r3, [%r5, 1] +.Lendbloop: + j_s.d [%blink] + stb %r12, [%r5, 0] diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S new file mode 100644 index 0000000000..017e8af0e8 --- /dev/null +++ b/arch/arc/lib/memset.S @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ + +.global memset +.align 4 +memset: + mov_s %r4, %r0 + or %r12, %r0, %r2 + bmsk.f %r12, %r12, 1 + extb_s %r1, %r1 + asl %r3, %r1, 8 + beq.d .Laligned + or_s %r1, %r1, %r3 + brls %r2, SMALL, .Ltiny + add %r3, %r2, %r0 + stb %r1, [%r3, -1] + bclr_s %r3, %r3, 0 + stw %r1, [%r3, -2] + bmsk.f %r12, %r0, 1 + add_s %r2, %r2, %r12 + sub.ne %r2, %r2, 4 + stb.ab %r1, [%r4, 1] + and %r4, %r4, -2 + stw.ab %r1, [%r4, 2] + and %r4, %r4, -4 + + .balign 4 +.Laligned: + asl %r3, %r1, 16 + lsr.f %lp_count, %r2, 2 + or_s %r1, %r1, %r3 + lpne .Loop_end + st.ab %r1, [%r4, 4] +.Loop_end: + j_s [%blink] + + .balign 4 +.Ltiny: + mov.f %lp_count, %r2 + lpne .Ltiny_end + stb.ab %r1, [%r4, 1] +.Ltiny_end: + j_s [%blink] + +/* + * memzero: @r0 = mem, @r1 = size_t + * memset: @r0 = mem, @r1 = char, @r2 = size_t + */ + +.global memzero +.align 4 +memzero: + /* adjust bzero args to memset args */ + mov %r2, %r1 + mov %r1, 0 + /* tail call so need to tinker with blink */ + b memset diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c new file mode 100644 index 0000000000..2482bcdffc --- /dev/null +++ b/arch/arc/lib/relocate.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Base functionality is taken from x86 version with added ARC-specifics + */ +int do_elf_reloc_fixups(void) +{ + Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); + Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + + Elf32_Addr *offset_ptr_rom, *last_offset = NULL; + Elf32_Addr *offset_ptr_ram; + + do { + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE && + offset_ptr_rom > last_offset) { + unsigned int val; + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* + * Use "memcpy" because target location might be + * 16-bit aligned on ARC so we may need to read + * byte-by-byte. On attempt to read entire word by + * CPU throws an exception + */ + memcpy(&val, offset_ptr_ram, sizeof(int)); + +#ifdef __LITTLE_ENDIAN__ + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__text_end) + val = (val << 16) | (val >> 16); +#endif + + /* Check that the target points into .text */ + if (val >= CONFIG_SYS_TEXT_BASE && val <= + (unsigned int)&__bss_end) { + val += gd->reloc_off; +#ifdef __LITTLE_ENDIAN__ + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__text_end) + val = (val << 16) | (val >> 16); +#endif + memcpy(offset_ptr_ram, &val, sizeof(int)); + } else { + debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n", + re_src, re_src->r_offset, offset_ptr_ram, + val, (unsigned int)&__bss_end); + } + } else { + debug(" %p: rom reloc %x, last %p\n", re_src, + re_src->r_offset, last_offset); + } + last_offset = offset_ptr_rom; + + } while (++re_src < re_end); + + return 0; +} diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c new file mode 100644 index 0000000000..b0b46a4e9a --- /dev/null +++ b/arch/arc/lib/sections.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * For some reason linker sets linker-generated symbols to zero in PIE mode. + * A work-around is substitution of linker-generated symbols with + * compiler-generated symbols which are properly handled by linker in PAE mode. + */ + +char __bss_start[0] __attribute__((section(".__bss_start"))); +char __bss_end[0] __attribute__((section(".__bss_end"))); +char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); +char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); +char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); +char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __text_start[0] __attribute__((section(".__text_start"))); +char __text_end[0] __attribute__((section(".__text_end"))); +char __init_end[0] __attribute__((section(".__init_end"))); diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S new file mode 100644 index 0000000000..55fcc9fb00 --- /dev/null +++ b/arch/arc/lib/strchr-700.S @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * ARC700 has a relatively long pipeline and branch prediction, so we want + * to avoid branches that are hard to predict. On the other hand, the + * presence of the norm instruction makes it easier to operate on whole + * words branch-free. + */ + +.global strchr +.align 4 +strchr: + extb_s %r1, %r1 + asl %r5, %r1, 8 + bmsk %r2, %r0, 1 + or %r5, %r5, %r1 + mov_s %r3, 0x01010101 + breq.d %r2, %r0, .Laligned + asl %r4, %r5, 16 + sub_s %r0, %r0, %r2 + asl %r7, %r2, 3 + ld_s %r2, [%r0] +#ifdef __LITTLE_ENDIAN__ + asl %r7, %r3, %r7 +#else /* __BIG_ENDIAN__ */ + lsr %r7, %r3, %r7 +#endif /* _ENDIAN__ */ + or %r5, %r5, %r4 + ror %r4, %r3 + sub %r12, %r2, %r7 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0_ua + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 +#ifdef __LITTLE_ENDIAN__ + and %r7, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r7, 0, .Loop + /* Likewise this one */ + b .Lfound_char +#else /* __BIG_ENDIAN__ */ + and %r12, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r12, 0, .Loop + lsr_s %r12, %r12, 7 + bic %r2, %r7, %r6 + b.d .Lfound_char_b + and_s %r2, %r2, %r12 +#endif /* _ENDIAN__ */ + /* We require this code address to be unaligned for speed... */ +.Laligned: + ld_s %r2, [%r0] + or %r5, %r5, %r4 + ror %r4, %r3 + /* ... so that this code address is aligned, for itself and ... */ +.Loop: + sub %r12, %r2, %r3 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0 + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r3 + bic %r12, %r12, %r6 + and %r7, %r12, %r4 + breq %r7, 0, .Loop + /* + *... so that this branch is unaligned. + * Found searched-for character. + * r0 has already advanced to next word. + */ +#ifdef __LITTLE_ENDIAN__ + /* + * We only need the information about the first matching byte + * (i.e. the least significant matching byte) to be exact, + * hence there is no problem with carry effects. + */ +.Lfound_char: + sub %r3, %r7, 1 + bic %r3, %r3, %r7 + norm %r2, %r3 + sub_s %r0, %r0, 1 + asr_s %r2, %r2, 3 + j.d [%blink] + sub_s %r0, %r0, %r2 + + .balign 4 +.Lfound0_ua: + mov %r3, %r7 +.Lfound0: + sub %r3, %r6, %r3 + bic %r3, %r3, %r6 + and %r2, %r3, %r4 + or_s %r12, %r12, %r2 + sub_s %r3, %r12, 1 + bic_s %r3, %r3, %r12 + norm %r3, %r3 + add_s %r0, %r0, 3 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + sub_s %r0, %r0, %r12 + j_s.d [%blink] + mov.pl %r0, 0 +#else /* __BIG_ENDIAN__ */ +.Lfound_char: + lsr %r7, %r7, 7 + + bic %r2, %r7, %r6 +.Lfound_char_b: + norm %r2, %r2 + sub_s %r0, %r0, 4 + asr_s %r2, %r2, 3 + j.d [%blink] + add_s %r0, %r0, %r2 + +.Lfound0_ua: + mov_s %r3, %r7 +.Lfound0: + asl_s %r2, %r2, 7 + or %r7, %r6, %r4 + bic_s %r12, %r12, %r2 + sub %r2, %r7, %r3 + or %r2, %r2, %r6 + bic %r12, %r2, %r12 + bic.f %r3, %r4, %r12 + norm %r3, %r3 + + add.pl %r3, %r3, 1 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + add_s %r0, %r0, %r12 + j_s.d [%blink] + mov.mi %r0, 0 +#endif /* _ENDIAN__ */ diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S new file mode 100644 index 0000000000..8cb7d2f18c --- /dev/null +++ b/arch/arc/lib/strcmp.S @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is optimized primarily for the ARC700. + * It would be possible to speed up the loops by one cycle / word + * respective one cycle / byte by forcing double source 1 alignment, unrolling + * by a factor of two, and speculatively loading the second word / byte of + * source 1; however, that would increase the overhead for loop setup / finish, + * and strcmp might often terminate early. + */ + +.global strcmp +.align 4 +strcmp: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne %r2, 0, .Lcharloop + mov_s %r12, 0x01010101 + ror %r5, %r12 +.Lwordloop: + ld.ab %r2, [%r0, 4] + ld.ab %r3, [%r1, 4] + nop_s + sub %r4, %r2, %r12 + bic %r4, %r4, %r2 + and %r4, %r4, %r5 + brne %r4, 0, .Lfound0 + breq %r2 ,%r3, .Lwordloop +#ifdef __LITTLE_ENDIAN__ + xor %r0, %r2, %r3 /* mask for difference */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 +#endif /* _ENDIAN__ */ + cmp_s %r2, %r3 + mov_s %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 + + .balign 4 +#ifdef __LITTLE_ENDIAN__ +.Lfound0: + xor %r0, %r2, %r3 /* mask for difference */ + or %r0, %r0, %r4 /* or in zero indicator */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 + sub.f %r0, %r2, %r3 + mov.hi %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#else /* __BIG_ENDIAN__ */ + /* + * The zero-detection above can mis-detect 0x01 bytes as zeroes + * because of carry-propagateion from a lower significant zero byte. + * We can compensate for this by checking that bit0 is zero. + * This compensation is not necessary in the step where we + * get a low estimate for r2, because in any affected bytes + * we already have 0x00 or 0x01, which will remain unchanged + * when bit 7 is cleared. + */ + .balign 4 +.Lfound0: + lsr %r0, %r4, 8 + lsr_s %r1, %r2 + bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */ + bic_s %r0, %r0, %r1 /* */ + or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */ + cmp_s %r3, %r2 /* ... be independent of trailing garbage */ + or_s %r2, %r2, %r0 /* likewise for r3 > r2 */ + bic_s %r3, %r3, %r0 + rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */ + cmp_s %r2, %r3 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#endif /* _ENDIAN__ */ + + .balign 4 +.Lcharloop: + ldb.ab %r2,[%r0,1] + ldb.ab %r3,[%r1,1] + nop_s + breq %r2, 0, .Lcmpend + breq %r2, %r3, .Lcharloop +.Lcmpend: + j_s.d [%blink] + sub %r0, %r2, %r3 diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S new file mode 100644 index 0000000000..41bb53e501 --- /dev/null +++ b/arch/arc/lib/strcpy-700.S @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * If dst and src are 4 byte aligned, copy 8 bytes at a time. + * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get + * it 8 byte aligned. Thus, we can do a little read-ahead, without + * dereferencing a cache line that we should not touch. + * Note that short and long instructions have been scheduled to avoid + * branch stalls. + * The beq_s to r3z could be made unaligned & long to avoid a stall + * there, but it is not likely to be taken often, and it would also be likely + * to cost an unaligned mispredict at the next call. + */ + +.global strcpy +.align 4 +strcpy: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne.d %r2, 0, charloop + mov_s %r10, %r0 + ld_s %r3, [%r1, 0] + mov %r8, 0x01010101 + bbit0.d %r1, 2, loop_start + ror %r12, %r8 + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2,%r12 + bne r3z + mov_s %r4,%r3 + .balign 4 +loop: + ld.a %r3, [%r1, 4] + st.ab %r4, [%r10, 4] +loop_start: + ld.a %r4, [%r1, 4] + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2, %r12 + bne_s r3z + st.ab %r3, [%r10, 4] + sub %r2, %r4, %r8 + bic %r2, %r2, %r4 + tst %r2, %r12 + beq loop + mov_s %r3, %r4 +#ifdef __LITTLE_ENDIAN__ +r3z: bmsk.f %r1, %r3, 7 + lsr_s %r3, %r3, 8 +#else /* __BIG_ENDIAN__ */ +r3z: lsr.f %r1, %r3, 24 + asl_s %r3, %r3, 8 +#endif /* _ENDIAN__ */ + bne.d r3z + stb.ab %r1, [%r10, 1] + j_s [%blink] + + .balign 4 +charloop: + ldb.ab %r3, [%r1, 1] + brne.d %r3, 0, charloop + stb.ab %r3, [%r10, 1] + j [%blink] diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S new file mode 100644 index 0000000000..666e22c0d5 --- /dev/null +++ b/arch/arc/lib/strlen.S @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global strlen +.align 4 +strlen: + or %r3, %r0, 7 + ld %r2, [%r3, -7] + ld.a %r6, [%r3, -3] + mov %r4, 0x01010101 + /* uses long immediate */ +#ifdef __LITTLE_ENDIAN__ + asl_s %r1, %r0, 3 + btst_s %r0, 2 + asl %r7, %r4, %r1 + ror %r5, %r4 + sub %r1, %r2, %r7 + bic_s %r1, %r1, %r2 + mov.eq %r7, %r4 + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#else /* __BIG_ENDIAN__ */ + ror %r5, %r4 + btst_s %r0, 2 + mov_s %r1, 31 + sub3 %r7, %r1, %r0 + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + bmsk %r1, %r1, %r7 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + bmsk.ne %r12, %r12, %r7 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#endif /* _ENDIAN__ */ + +.Loop: + ld_s %r2, [%r3, 4] + ld.a %r6, [%r3, 8] + /* stall for load result */ + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + or %r12, %r12, %r1 + and %r12, %r12, %r5 + breq %r12, 0, .Loop +.Lend: + and.f %r1, %r1, %r5 + sub.ne %r3, %r3, 4 + mov.eq %r1, %r12 +#ifdef __LITTLE_ENDIAN__ + sub_s %r2, %r1, 1 + bic_s %r2, %r2, %r1 + norm %r1, %r2 + sub_s %r0, %r0, 3 + lsr_s %r1, %r1, 3 + sub %r0, %r3, %r0 + j_s.d [%blink] + sub %r0, %r0, %r1 +#else /* __BIG_ENDIAN__ */ + lsr_s %r1, %r1, 7 + mov.eq %r2, %r6 + bic_s %r1, %r1, %r2 + norm %r1, %r1 + sub %r0, %r3, %r0 + lsr_s %r1, %r1, 3 + j_s.d [%blink] + add %r0, %r0, %r1 +#endif /* _ENDIAN */ +.Learly_end: + b.d .Lend + sub_s.ne %r1, %r1, %r1 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index cfa42094ca..66ecc2ee4d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= arm-linux- - ifndef CONFIG_STANDALONE_LOAD_ADDR ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 @@ -18,7 +16,8 @@ endif LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ -fno-common -ffixed-r9 -PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) +PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ + $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y @@ -38,7 +37,17 @@ endif # Only test once ifneq ($(CONFIG_SPL_BUILD),y) -ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +archprepare: checkthumb + +checkthumb: + @if test "$(call cc-version)" -lt "0404"; then \ + echo -n '*** Your GCC does not produce working '; \ + echo 'binaries in THUMB mode.'; \ + echo '*** Your board is configured for THUMB mode.'; \ + false; \ + fi +endif endif # Try if EABI is supported, else fall back to old API, @@ -66,13 +75,8 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) # times. Also, the prefix needs to be different based on whether # CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry # before adding the correct one. -ifdef CONFIG_SPL_BUILD -PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \ - $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) -else -PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \ - $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) -endif +PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \ + $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) endif # needed for relocation @@ -107,7 +111,21 @@ endif # limit ourselves to the sections we want in the .bin. ifdef CONFIG_ARM64 -OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +endif + +ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ALL-y += SPL +endif +else +ifeq ($(CONFIG_OF_SEPARATE),y) +ALL-y += u-boot-dtb.imx +else +ALL-y += u-boot.imx +endif +endif endif diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index b4d396de84..a82c6cec9c 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -7,20 +7,3 @@ # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c deleted file mode 100644 index ebd7575039..0000000000 --- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); - DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); - DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); - DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); - DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); - DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); - DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); - DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); - DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); - DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); - DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); - DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); - DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); - DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); - DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); - DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); - DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); - DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); - DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); - DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); - - return 0; -} diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 00d1b30ba6..3e2358e132 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -70,32 +70,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -295,7 +269,6 @@ cpu_init_crit: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ .align 5 diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index bccde73317..0299902f20 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -33,7 +33,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk deleted file mode 100644 index b87ce244c3..0000000000 --- a/arch/arm/cpu/arm1176/bcm2835/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Don't attempt to override the target CPU/ABI options; -# the Raspberry Pi toolchain does the right thing by default. -PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS)) -PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index 2edd6711da..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -18,11 +18,6 @@ #include #include -int timer_init(void) -{ - return 0; -} - ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index f4631cb777..5dc2ebb27b 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -7,11 +7,3 @@ # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ffd7dd0dcd..ce620115d4 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -77,33 +77,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ - -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 2581f0ae67..772fb413e8 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -7,11 +7,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index f180eb8aa6..1a34842690 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -67,32 +67,6 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 72c69b914c..168f525ec7 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -112,24 +112,38 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, + + /* + * T124: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + }, }; -void adjust_pllp_out_freqs(void) +static inline void pllx_set_iddq(void) { +#if defined(CONFIG_TEGRA124) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH]; u32 reg; - /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ - reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */ - reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR - | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; - writel(reg, &pll->pll_out[0]); - - reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */ - reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR - | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; - writel(reg, &pll->pll_out[1]); + /* Disable IDDQ */ + reg = readl(&clkrst->crc_pllx_misc3); + reg &= ~PLLX_IDDQ_MASK; + writel(reg, &clkrst->crc_pllx_misc3); + udelay(2); + debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, + readl(&clkrst->crc_pllx_misc3)); +#endif } int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, @@ -146,6 +160,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, debug(" pllx_set_rate entry\n"); + pllx_set_iddq(); + /* Set BYPASS, m, n and p to PLLX_BASE */ reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); @@ -162,18 +178,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, reg |= (1 << PLL_DCCON_SHIFT); writel(reg, &pll->pll_misc); - /* Enable PLLX */ - reg = readl(&pll->pll_base); - reg |= PLL_ENABLE_MASK; - /* Disable BYPASS */ + reg = readl(&pll->pll_base); reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); + debug("pllx_set_rate: base = 0x%08X\n", reg); /* Set lock_enable to PLLX_MISC */ reg = readl(&pll->pll_misc); reg |= PLL_LOCK_ENABLE_MASK; writel(reg, &pll->pll_misc); + debug("pllx_set_rate: misc = 0x%08X\n", reg); + + /* Enable PLLX last, once it's all configured */ + reg = readl(&pll->pll_base); + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); + debug("pllx_set_rate: base final = 0x%08X\n", reg); return 0; } @@ -207,12 +228,6 @@ void init_pllx(void) /* set pllx */ sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - - /* adjust PLLP_out1-4 on T3x/T114 */ - if (soc_type >= CHIPID_TEGRA30) { - debug(" init_pllx: adjusting PLLP out freqs\n"); - adjust_pllp_out_freqs(); - } } void enable_cpu_clock(int enable) @@ -334,7 +349,6 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -343,20 +357,11 @@ void clock_enable_coresight(int enable) if (enable) { /* * Put CoreSight on PLLP_OUT0 and divide it down as per - * PLLP base frequency based on SoC type (T20/T30/T114). + * PLLP base frequency based on SoC type (T20/T30+). * Clock divider request would setup CSITE clock as 144MHz * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - - soc_type = tegra_get_chip(); - if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (soc_type == CHIPID_TEGRA20) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); - else - printf("%s: Unknown SoC type %X!\n", - __func__, soc_type); - + src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ @@ -373,8 +378,7 @@ void clock_enable_coresight(int enable) void halt_avp(void) { for (;;) { - writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ - | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), - FLOW_CTLR_HALT_COP_EVENTS); + writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), + FLOW_CTLR_HALT_COP_EVENTS); } } diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index 60412c7f87..b4ca44fce1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -11,9 +11,12 @@ #define IO_STABILIZATION_DELAY (1000) #if defined(CONFIG_TEGRA20) -#define NVBL_PLLP_KHZ (216000) -#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) -#define NVBL_PLLP_KHZ (408000) +#define NVBL_PLLP_KHZ 216000 +#define CSITE_KHZ 144000 +#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ + defined(CONFIG_TEGRA124) +#define NVBL_PLLP_KHZ 408000 +#define CSITE_KHZ 204000 #else #error "Unknown Tegra chip!" #endif @@ -68,3 +71,4 @@ int tegra_get_chip(void); int tegra_get_sku_info(void); int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); +void pmic_enable_cpu_vdd(void); diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk deleted file mode 100644 index 7947b50fd0..0000000000 --- a/arch/arm/cpu/arm720t/tegra114/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff794f..d10b96a1d4 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -68,7 +68,7 @@ static void enable_cpu_clocks(void) /* Wait for PLL-X to lock */ do { reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); - } while ((reg & (1 << 27)) == 0); + } while ((reg & PLL_LOCK_MASK) == 0); /* Wait until all clocks are stable */ udelay(PLL_STABILIZATION_DELAY); @@ -126,18 +126,6 @@ void t114_init_clocks(void) /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); - /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no - * special precaution needed. - */ - val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clkrst->crc_sclk_brst_pol); - writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); debug("Setting up PLLX\n"); @@ -204,45 +192,43 @@ void t114_init_clocks(void) debug("t114_init_clocks exit\n"); } -static int is_partition_powered(u32 mask) +static bool is_partition_powered(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; /* Get power gate status */ reg = readl(&pmc->pmc_pwrgate_status); - return (reg & mask) == mask; + return !!(reg & (1 << partid)); } -static int is_clamp_enabled(u32 mask) +static bool is_clamp_enabled(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; - /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */ - reg = readl(&pmc->pmc_pwrgate_timer_on); - return (reg & mask) == mask; + /* Get clamp status. */ + reg = readl(&pmc->pmc_clamp_status); + return !!(reg & (1 << partid)); } -static void power_partition(u32 status, u32 partid) +static void power_partition(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid); + debug("%s: part ID = %08X\n", __func__, partid); /* Is the partition already on? */ - if (!is_partition_powered(status)) { + if (!is_partition_powered(partid)) { /* No, toggle the partition power state (OFF -> ON) */ debug("power_partition, toggling state\n"); - clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F); - setbits_le32(&pmc->pmc_pwrgate_toggle, partid); - setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP); + writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); /* Wait for the power to come up */ - while (!is_partition_powered(status)) + while (!is_partition_powered(partid)) ; /* Wait for the clamp status to be cleared */ - while (is_clamp_enabled(status)) + while (is_clamp_enabled(partid)) ; /* Give I/O signals time to stabilize */ @@ -257,13 +243,13 @@ void powerup_cpus(void) /* We boot to the fast cluster */ debug("powerup_cpus entry: G cluster\n"); /* Power up the fast cluster rail partition */ - power_partition(CRAIL, CRAILID); + power_partition(CRAIL); /* Power up the fast cluster non-CPU partition */ - power_partition(C0NC, C0NCID); + power_partition(C0NC); /* Power up the fast cluster CPU0 partition */ - power_partition(CE0, CE0ID); + power_partition(CE0); } void start_cpu(u32 reset_vector) diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile new file mode 100644 index 0000000000..61abf45d3d --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra124/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c new file mode 100644 index 0000000000..97f5928bd7 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra124/cpu.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../tegra-common/cpu.h" + +/* Tegra124-specific CPU init code */ + +static void enable_cpu_power_rail(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("enable_cpu_power_rail entry\n"); + + /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ + pinmux_tristate_disable(PINGRP_PWR_I2C_SCL); + pinmux_tristate_disable(PINGRP_PWR_I2C_SDA); + + pmic_enable_cpu_vdd(); + + /* + * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), + * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h). + */ + writel(0x7C830, &pmc->pmc_cpupwrgood_timer); + + /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ + clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); + setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); +} + +static void enable_cpu_clocks(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + debug("enable_cpu_clocks entry\n"); + + /* Wait for PLL-X to lock */ + do { + reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + debug("%s: PLLX base = 0x%08X\n", __func__, reg); + } while ((reg & PLL_LOCK_MASK) == 0); + + debug("%s: PLLX locked, delay for stable clocks\n", __func__); + /* Wait until all clocks are stable */ + udelay(PLL_STABILIZATION_DELAY); + + debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__); + writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); + + debug("%s: Enabling clock to all CPUs\n", __func__); + /* Enable the clock to all CPUs */ + reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP | + CLR_CPU0_CLK_STP; + writel(reg, &clkrst->crc_clk_cpu_cmplx_clr); + + debug("%s: Enabling main CPU complex clocks\n", __func__); + /* Always enable the main CPU complex clocks */ + clock_enable(PERIPH_ID_CPU); + clock_enable(PERIPH_ID_CPULP); + clock_enable(PERIPH_ID_CPUG); + + debug("%s: Done\n", __func__); +} + +static void remove_cpu_resets(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + debug("remove_cpu_resets entry\n"); + + /* Take the slow and fast partitions out of reset */ + reg = CLR_NONCPURESET; + writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); + writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); + + /* Clear the SW-controlled reset of the slow cluster */ + reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_L2RESET | CLR_PRESETDBG; + writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); + + /* Clear the SW-controlled reset of the fast cluster */ + reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 | + CLR_L2RESET | CLR_PRESETDBG; + writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); +} + +/** + * The Tegra124 requires some special clock initialization, including setting up + * the DVC I2C, turning on MSELECT and selecting the G CPU cluster + */ +void tegra124_init_clocks(void) +{ + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + debug("tegra124_init_clocks entry\n"); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Change the oscillator drive strength */ + val = readl(&clkrst->crc_osc_ctrl); + val &= ~OSC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + writel(val, &clkrst->crc_osc_ctrl); + + /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */ + val = readl(&pmc->pmc_osc_edpd_over); + val &= ~PMC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); + writel(val, &pmc->pmc_osc_edpd_over); + + /* Set HOLD_CKE_LOW_EN to 1 */ + setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); + + debug("Setting up PLLX\n"); + init_pllx(); + + val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); + writel(val, &clkrst->crc_clk_sys_rate); + + /* Enable clocks to required peripherals. TBD - minimize this list */ + debug("Enabling clocks\n"); + + clock_set_enable(PERIPH_ID_CACHE2, 1); + clock_set_enable(PERIPH_ID_GPIO, 1); + clock_set_enable(PERIPH_ID_TMR, 1); + clock_set_enable(PERIPH_ID_CPU, 1); + clock_set_enable(PERIPH_ID_EMC, 1); + clock_set_enable(PERIPH_ID_I2C5, 1); + clock_set_enable(PERIPH_ID_APBDMA, 1); + clock_set_enable(PERIPH_ID_MEM, 1); + clock_set_enable(PERIPH_ID_CORESIGHT, 1); + clock_set_enable(PERIPH_ID_MSELECT, 1); + clock_set_enable(PERIPH_ID_DVFS, 1); + + /* + * Set MSELECT clock source as PLLP (00), and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. + */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* Take required peripherals out of reset */ + debug("Taking periphs out of reset\n"); + reset_set_enable(PERIPH_ID_CACHE2, 0); + reset_set_enable(PERIPH_ID_GPIO, 0); + reset_set_enable(PERIPH_ID_TMR, 0); + reset_set_enable(PERIPH_ID_COP, 0); + reset_set_enable(PERIPH_ID_EMC, 0); + reset_set_enable(PERIPH_ID_I2C5, 0); + reset_set_enable(PERIPH_ID_APBDMA, 0); + reset_set_enable(PERIPH_ID_MEM, 0); + reset_set_enable(PERIPH_ID_CORESIGHT, 0); + reset_set_enable(PERIPH_ID_MSELECT, 0); + reset_set_enable(PERIPH_ID_DVFS, 0); + + debug("tegra124_init_clocks exit\n"); +} + +static bool is_partition_powered(u32 partid) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + /* Get power gate status */ + reg = readl(&pmc->pmc_pwrgate_status); + return !!(reg & (1 << partid)); +} + +static void power_partition(u32 partid) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("%s: part ID = %08X\n", __func__, partid); + /* Is the partition already on? */ + if (!is_partition_powered(partid)) { + /* No, toggle the partition power state (OFF -> ON) */ + debug("power_partition, toggling state\n"); + writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come up */ + while (!is_partition_powered(partid)) + ; + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + } +} + +void powerup_cpus(void) +{ + debug("powerup_cpus entry\n"); + + /* We boot to the fast cluster */ + debug("powerup_cpus entry: G cluster\n"); + + /* Power up the fast cluster rail partition */ + debug("powerup_cpus: CRAIL\n"); + power_partition(CRAIL); + + /* Power up the fast cluster non-CPU partition */ + debug("powerup_cpus: C0NC\n"); + power_partition(C0NC); + + /* Power up the fast cluster CPU0 partition */ + debug("powerup_cpus: CE0\n"); + power_partition(CE0); + + debug("powerup_cpus: done\n"); +} + +void start_cpu(u32 reset_vector) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("start_cpu entry, reset_vector = %x\n", reset_vector); + + tegra124_init_clocks(); + + /* Set power-gating timer multiplier */ + writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT), + &pmc->pmc_pwrgate_timer_mult); + + enable_cpu_power_rail(); + enable_cpu_clocks(); + clock_enable_coresight(1); + remove_cpu_resets(); + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + powerup_cpus(); + debug("start_cpu exit, should continue @ reset_vector\n"); +} diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk deleted file mode 100644 index e073345223..0000000000 --- a/arch/arm/cpu/arm720t/tegra20/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010,2011 -# NVIDIA Corporation -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk deleted file mode 100644 index 2388c56db7..0000000000 --- a/arch/arm/cpu/arm720t/tegra30/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index e162357484..a80648389c 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -84,18 +84,6 @@ void t30_init_clocks(void) /* Set active CPU cluster to G */ clrbits_le32(flow->cluster_control, 1 << 0); - /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no - * special precaution needed. - */ - val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clkrst->crc_sclk_brst_pol); - writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) | diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 67537dcedc..799afff028 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 4bed4fcdd7..96994043e4 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -50,5 +50,8 @@ SECTIONS .bss : { *(.bss*) } __bss_end = .; - _end = .; + .end : + { + *(.__end) + } } diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a67b659fd0..7bf094aec1 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -55,32 +55,6 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index 99a39134de..6b51d5f355 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif +#if defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + /* Enable mci clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_MCI1, &pmc->pcer); + + at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */ + +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */ + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */ + at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */ + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */ +#endif +} +#endif + #ifdef CONFIG_MACB void at91_macb_hw_init(void) { diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index e83968fb7a..a9ec81a75c 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -26,27 +26,18 @@ #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL #endif -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init .type lowlevel_init,function lowlevel_init: - mov r5, pc /* r5 = POS1 + 4 current */ POS1: + adr r5, POS1 /* r5 = POS1 run time */ ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ /* memory control configuration 1 */ ldr r0, =SMRDATA ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 0: @@ -149,9 +140,6 @@ PLL_setup_end: ldr r0, =SMRDATA1 ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 2: diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 12b0d09d37..bdb3da183e 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -6,20 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv5te -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk index d5c978b446..69e9d5ab21 100644 --- a/arch/arm/cpu/arm926ejs/davinci/config.mk +++ b/arch/arm/cpu/arm926ejs/davinci/config.mk @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.ais +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c deleted file mode 100644 index 5fe8fa204b..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c deleted file mode 100644 index 0e2e8bf64e..0000000000 --- a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* Clock Control Module */ - DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); - DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); - DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); - - /* Enhanced SDRAM Controller */ - DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); - DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); - DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c deleted file mode 100644 index 629b727745..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, gpcr)); - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, fmcr)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 152546eb41..6c59494558 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -14,11 +14,72 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif # Specify the target for use in elftosb call -MKIMAGE_TARGET-$(CONFIG_MX23) = mx23 -MKIMAGE_TARGET-$(CONFIG_MX28) = mx28 +MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg +MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg -$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg - sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ +# Generate HAB-capable IVT +# +# Note on computing the post-IVT size field value for the U-Boot binary. +# The value is the result of adding the following: +# -> The size of U-Boot binary aligned to 64B (u-boot.bin) +# -> The size of IVT block aligned to 64B (u-boot.ivt) +# -> The size of U-Boot signature (u-boot.sig), 3904 B +# -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing +# +quiet_cmd_mkivt_mxs = MXSIVT $@ +cmd_mkivt_mxs = \ + sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ + echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ + tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ + sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg - $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@ +# Align binary to 64B +quiet_cmd_mkalign_mxs = MXSALGN $@ +cmd_mkalign_mxs = \ + dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ + mv $@ $^ + +# Assemble the CSF file +quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ +cmd_mkcsfreq_mxs = \ + ivt=$(word 1,$^) ; \ + bin=$(word 2,$^) ; \ + csf=$(word 3,$^) ; \ + sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ + sed '/^\#\#Blocks/ d' > $@ ; \ + echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ + echo " $3 0x0 0x40 \"$$ivt\"" >> $@ + +# Sign files +quiet_cmd_mkcst_mxs = MXSCST $@ +cmd_mkcst_mxs = cst -o $@ < $^ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +spl/u-boot-spl.ivt: spl/u-boot-spl.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\ + 0x00008000,0x00008040) + +u-boot.ivt: u-boot.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\ + 0x40001000,0x40001040) + +spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000) + +u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000) + +%.sig: %.csf + $(call if_changed,mkcst_mxs) + +quiet_cmd_mkimage_mxs = MKIMAGE $@ +cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage_mxs) + +u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE + $(call if_changed,mkimage_mxs) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg new file mode 100644 index 0000000000..1520bba3fb --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -0,0 +1,10 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x1000 spl/u-boot-spl.bin + LOAD 0x8000 spl/u-boot-spl.ivt + LOAD 0x8040 spl/u-boot-spl.sig + CALL HAB 0x8000 0x0 + LOAD 0x40002000 u-boot.bin + LOAD 0x40001000 u-boot.ivt + LOAD 0x40001040 u-boot.sig + CALL HAB 0x40001000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index c9cf4b3629..55510e9cd8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 OBJTREE/spl/u-boot-spl.bin - CALL 0x14 0x0 - LOAD 0x40000100 OBJTREE/u-boot.bin - CALL 0x40000100 0x0 + LOAD 0x1000 spl/u-boot-spl.bin + CALL 0x1000 0x0 + LOAD 0x40002000 u-boot.bin + CALL 0x40002000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index 676f5c8f77..bb78cb0c84 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 OBJTREE/spl/u-boot-spl.bin - LOAD IVT 0x8000 0x14 + LOAD 0x1000 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x1000 CALL HAB 0x8000 0x0 - LOAD 0x40000100 OBJTREE/u-boot.bin - LOAD IVT 0x8000 0x40000100 + LOAD 0x40002000 u-boot.bin + LOAD IVT 0x8000 0x40002000 CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 68c30afc48..d3e136991a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -13,9 +13,16 @@ #include #include #include +#include #include "mxs_init.h" +DECLARE_GLOBAL_DATA_PTR; +static gd_t gdata __section(".data"); +#ifdef CONFIG_SPL_SERIAL_SUPPORT +static bd_t bdata __section(".data"); +#endif + /* * This delay function is intended to be used only in early stage of boot, where * clock are not set up yet. The timer used here is reset on every boot and @@ -102,6 +109,28 @@ static uint8_t mxs_get_bootmode_index(void) return i; } +static void mxs_spl_fixup_vectors(void) +{ + /* + * Copy our vector table to 0x0, since due to HAB, we cannot + * be loaded to 0x0. We want to have working vectoring though, + * thus this fixup. Our vectoring table is PIC, so copying is + * fine. + */ + extern uint32_t _start; + memcpy(0x0, &_start, 0x60); +} + +static void mxs_spl_console_init(void) +{ +#ifdef CONFIG_SPL_SERIAL_SUPPORT + gd->bd = &bdata; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#endif +} + void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) @@ -109,8 +138,14 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); uint8_t bootmode = mxs_get_bootmode_index(); + gd = &gdata; + + mxs_spl_fixup_vectors(); mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); + + mxs_spl_console_init(); + mxs_power_init(); mxs_mem_init(); diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 5de2bad584..34a0fcb462 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -101,32 +101,6 @@ fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#ifdef CONFIG_SPL_TEXT_BASE - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -207,6 +181,5 @@ _reset: bx lr _hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ 1: bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd index 8b6c30e8e9..3a51879d5e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd @@ -4,8 +4,8 @@ options { } sources { - u_boot_spl="OBJTREE/spl/u-boot-spl.bin"; - u_boot="OBJTREE/u-boot.bin"; + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; } section (0) { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd index a5fa6483a9..c60615a456 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd @@ -1,6 +1,6 @@ sources { - u_boot_spl="OBJTREE/spl/u-boot-spl.bin"; - u_boot="OBJTREE/u-boot.bin"; + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; } section (0) { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 80fb9bdc8d..f4bf8ac1dd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -16,7 +16,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : @@ -49,9 +49,14 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } - .dynsym _end : { *(.dynsym) } + _image_binary_end = .; + + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile index bd0a2fbe92..add923276c 100644 --- a/arch/arm/cpu/arm926ejs/omap/Makefile +++ b/arch/arm/cpu/arm926ejs/omap/Makefile @@ -5,5 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = timer.o cpuinfo.o +obj-y = timer.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o obj-y += reset.o diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c index 02332eee0e..587d99a2bb 100644 --- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c +++ b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) +#if defined(CONFIG_OMAP) #define omap_readw(x) *(volatile unsigned short *)(x) #define omap_readl(x) *(volatile unsigned long *)(x) @@ -239,4 +239,4 @@ int print_cpuinfo (void) return 0; } -#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */ +#endif /* #if defined(CONFIG_OMAP) */ diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 76b499d87f..b6d0f65b66 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -49,9 +49,14 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } - .dynsym _end : { *(.dynsym) } + _image_binary_end = .; + + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 5360f55bc1..0717327050 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -102,32 +102,6 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -330,7 +304,6 @@ flush_dcache: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ 1: bl 1b /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index eb81a5708d..438668d6ff 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index e16b088141..7d50145836 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -71,32 +71,6 @@ _vectors_end: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk index eb81a5708d..438668d6ff 100644 --- a/arch/arm/cpu/arm_intcm/config.mk +++ b/arch/arm/cpu/arm_intcm/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 5783df1ef2..7404ea7348 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -67,32 +67,6 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0467d00d6a..119ebb3b22 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -23,6 +23,7 @@ obj-y += nonsec_virt.o obj-y += virt-v7.o endif +obj-$(CONFIG_KONA) += kona-common/ obj-$(CONFIG_OMAP_COMMON) += omap-common/ obj-$(CONFIG_TEGRA) += tegra-common/ diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index c7dad6681d..fb44cc8290 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -36,11 +36,15 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct gpio_bank gpio_bank_am33xx[4] = { +static const struct gpio_bank gpio_bank_am33xx[] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_AM43XX + { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, +#endif }; const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; @@ -198,6 +202,7 @@ static void watchdog_disable(void) } #endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) void s_init(void) { /* @@ -216,22 +221,19 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) watchdog_disable(); timer_init(); set_uart_mux_conf(); setup_clocks_for_console(); uart_soft_reset(); -#endif #ifdef CONFIG_NOR_BOOT gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; -#else +#elif defined(CONFIG_SPL_BUILD) gd = &gdata; preloader_console_init(); #endif -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) prcm_init(); set_mux_conf_regs(); #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) @@ -239,8 +241,8 @@ void s_init(void) rtc32k_enable(); #endif sdram_init(); -#endif } +#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 97c00b4925..d0bc2340c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -94,10 +94,14 @@ void enable_basic_clocks(void) &cmper->gpio1clkctrl, &cmper->gpio2clkctrl, &cmper->gpio3clkctrl, + &cmper->gpio4clkctrl, + &cmper->gpio5clkctrl, &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, &cmper->emiffwclkctrl, &cmper->emifclkctrl, &cmper->otfaemifclkctrl, + &cmper->qspiclkctrl, 0 }; diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index ef14f47ebc..9b5a47b018 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -211,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco) static u32 pll_sigma_delta_val(u32 clkout_dco) { u32 sig_val = 0; - float frac_div; - frac_div = (float) clkout_dco / 250; - frac_div = frac_div + 0.90; - sig_val = (int)frac_div; + sig_val = (clkout_dco + 225) / 250; sig_val = sig_val << 24; return sig_val; diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 8e3668f781..5294d16708 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -4,8 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO -ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap +ALL-y += MLO +ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index d05e666a74..9a625c4661 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs) */ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) { - writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); - writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); writel(0x1, &emif_reg[nr]->emif_iodft_tlgc); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); @@ -96,6 +96,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { configure_mr(nr, 0); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index d28fceb75c..3e39752380 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) ; - writel(0x0, &ddrctrl->ddrioctrl); + writel(0x80000000, &ddrctrl->ddrioctrl); config_io_ctrl(ioregs); diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds index 9302856a95..b1c28c9442 100644 --- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -38,7 +38,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram .bss : { diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile new file mode 100644 index 0000000000..98f5aa59ca --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += clk-core.o +obj-y += clk-bcm281xx.o +obj-y += clk-sdio.o +obj-y += clk-bsc.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c new file mode 100644 index 0000000000..bc8a170b40 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -0,0 +1,523 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx-specific clock tables + * + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLOCK_1K 1000 +#define CLOCK_1M (CLOCK_1K * 1000) + +/* declare a reference clock */ +#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ +static struct refclk clk_name = { \ + .clk = { \ + .name = #clk_name, \ + .parent = clk_parent, \ + .rate = clk_rate, \ + .div = clk_div, \ + .ops = &ref_clk_ops, \ + }, \ +} + +/* + * Reference clocks + */ + +/* Declare a list of reference clocks */ +DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); +DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); +DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); + +struct refclk_lkup { + struct refclk *procclk; + const char *name; +}; + +/* Lookup table for string to clk tranlation */ +#define MKSTR(x) {&x, #x} +static struct refclk_lkup refclk_str_tbl[] = { + MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), + MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), + MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), + MKSTR(var_52m), MKSTR(var_13m), +}; + +int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); + +/* convert ref clock string to clock structure pointer */ +struct refclk *refclk_str_to_clk(const char *name) +{ + int i; + struct refclk_lkup *tblp = refclk_str_tbl; + for (i = 0; i < refclk_entries; i++, tblp++) { + if (!(strcmp(name, tblp->name))) + return tblp->procclk; + } + return NULL; +} + +/* frequency tables indexed by freq_id */ +unsigned long master_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M, + 208 * CLOCK_1M, + 312 * CLOCK_1M, + 312 * CLOCK_1M +}; + +unsigned long master_ahb_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_apb_freq_tbl[8] = { + 26 * CLOCK_1M, + 26 * CLOCK_1M, + 39 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M +}; + +static struct bus_clk_data bsc1_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), +}; + +static struct bus_clk_data bsc2_apb_data = { + .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), +}; + +static struct bus_clk_data bsc3_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), +}; + +/* * Master CCU clocks */ +static struct peri_clk_data sdio1_data = { + .gate = HW_SW_GATE(0x0358, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a28, 0, 3), + .div = DIVIDER(0x0a28, 4, 14), + .trig = TRIGGER(0x0afc, 9), +}; + +static struct peri_clk_data sdio2_data = { + .gate = HW_SW_GATE(0x035c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a2c, 0, 3), + .div = DIVIDER(0x0a2c, 4, 14), + .trig = TRIGGER(0x0afc, 10), +}; + +static struct peri_clk_data sdio3_data = { + .gate = HW_SW_GATE(0x0364, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a34, 0, 3), + .div = DIVIDER(0x0a34, 4, 14), + .trig = TRIGGER(0x0afc, 12), +}; + +static struct peri_clk_data sdio4_data = { + .gate = HW_SW_GATE(0x0360, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a30, 0, 3), + .div = DIVIDER(0x0a30, 4, 14), + .trig = TRIGGER(0x0afc, 11), +}; + +static struct peri_clk_data sdio1_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0358, 20, 4), +}; + +static struct peri_clk_data sdio2_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x035c, 20, 4), +}; + +static struct peri_clk_data sdio3_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0364, 20, 4), +}; + +static struct peri_clk_data sdio4_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0360, 20, 4), +}; + +static struct bus_clk_data sdio1_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), +}; + +static struct bus_clk_data sdio2_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), +}; + +static struct bus_clk_data sdio3_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), +}; + +static struct bus_clk_data sdio4_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), +}; + +/* * Slave CCU clocks */ +static struct peri_clk_data bsc1_data = { + .gate = HW_SW_GATE(0x0458, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a64, 0, 3), + .trig = TRIGGER(0x0afc, 23), +}; + +static struct peri_clk_data bsc2_data = { + .gate = HW_SW_GATE(0x045c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a68, 0, 3), + .trig = TRIGGER(0x0afc, 24), +}; + +static struct peri_clk_data bsc3_data = { + .gate = HW_SW_GATE(0x0484, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a84, 0, 3), + .trig = TRIGGER(0x0b00, 2), +}; + +/* + * CCU clocks + */ + +static struct ccu_clock kpm_ccu_clk = { + .clk = { + .name = "kpm_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .num_policy_masks = 1, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = master_axi_freq_tbl, +}; + +static struct ccu_clock kps_ccu_clk = { + .clk = { + .name = "kps_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .num_policy_masks = 2, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .policy0_mask2_offset = 0x00000048, + .policy1_mask2_offset = 0x0000004c, + .policy2_mask2_offset = 0x00000050, + .policy3_mask2_offset = 0x00000054, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = slave_axi_freq_tbl, +}; + +/* + * Bus clocks + */ + +/* KPM bus clocks */ +static struct bus_clock sdio1_ahb_clk = { + .clk = { + .name = "sdio1_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio1_ahb_data, +}; + +static struct bus_clock sdio2_ahb_clk = { + .clk = { + .name = "sdio2_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio2_ahb_data, +}; + +static struct bus_clock sdio3_ahb_clk = { + .clk = { + .name = "sdio3_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio3_ahb_data, +}; + +static struct bus_clock sdio4_ahb_clk = { + .clk = { + .name = "sdio4_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio4_ahb_data, +}; + +static struct bus_clock bsc1_apb_clk = { + .clk = { + .name = "bsc1_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc1_apb_data, +}; + +static struct bus_clock bsc2_apb_clk = { + .clk = { + .name = "bsc2_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc2_apb_data, +}; + +static struct bus_clock bsc3_apb_clk = { + .clk = { + .name = "bsc3_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc3_apb_data, +}; + +/* KPM peripheral */ +static struct peri_clock sdio1_clk = { + .clk = { + .name = "sdio1_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_data, +}; + +static struct peri_clock sdio2_clk = { + .clk = { + .name = "sdio2_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_data, +}; + +static struct peri_clock sdio3_clk = { + .clk = { + .name = "sdio3_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_data, +}; + +static struct peri_clock sdio4_clk = { + .clk = { + .name = "sdio4_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_data, +}; + +static struct peri_clock sdio1_sleep_clk = { + .clk = { + .name = "sdio1_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_sleep_data, +}; + +static struct peri_clock sdio2_sleep_clk = { + .clk = { + .name = "sdio2_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_sleep_data, +}; + +static struct peri_clock sdio3_sleep_clk = { + .clk = { + .name = "sdio3_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_sleep_data, +}; + +static struct peri_clock sdio4_sleep_clk = { + .clk = { + .name = "sdio4_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_sleep_data, +}; + +/* KPS peripheral clock */ +static struct peri_clock bsc1_clk = { + .clk = { + .name = "bsc1_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc1_data, +}; + +static struct peri_clock bsc2_clk = { + .clk = { + .name = "bsc2_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc2_data, +}; + +static struct peri_clock bsc3_clk = { + .clk = { + .name = "bsc3_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc3_data, +}; + +/* public table for registering clocks */ +struct clk_lookup arch_clk_tbl[] = { + /* Peripheral clocks */ + CLK_LK(sdio1), + CLK_LK(sdio2), + CLK_LK(sdio3), + CLK_LK(sdio4), + CLK_LK(sdio1_sleep), + CLK_LK(sdio2_sleep), + CLK_LK(sdio3_sleep), + CLK_LK(sdio4_sleep), + CLK_LK(bsc1), + CLK_LK(bsc2), + CLK_LK(bsc3), + /* Bus clocks */ + CLK_LK(sdio1_ahb), + CLK_LK(sdio2_ahb), + CLK_LK(sdio3_ahb), + CLK_LK(sdio4_ahb), + CLK_LK(bsc1_apb), + CLK_LK(bsc2_apb), + CLK_LK(bsc3_apb), +}; + +/* public array size */ +unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c new file mode 100644 index 0000000000..ba55d0aeb1 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for a BSC/I2C port */ +int clk_bsc_enable(void *base) +{ + int ret; + char *bscstr, *apbstr; + + switch ((u32) base) { + case PMU_BSC_BASE_ADDR: + /* PMU clock is always enabled */ + return 0; + case BSC1_BASE_ADDR: + bscstr = "bsc1_clk"; + apbstr = "bsc1_apb_clk"; + break; + case BSC2_BASE_ADDR: + bscstr = "bsc2_clk"; + apbstr = "bsc2_apb_clk"; + break; + case BSC3_BASE_ADDR: + bscstr = "bsc3_clk"; + apbstr = "bsc3_apb_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + /* Note that the bus clock must be enabled first */ + + ret = clk_get_and_enable(apbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(bscstr); + if (ret) + return ret; + + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c new file mode 100644 index 0000000000..d4425835a1 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -0,0 +1,513 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx architecture clock framework + * + */ + +#include +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLK_WR_ACCESS_PASSWORD 0x00a5a501 +#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ +#define POLICY_CTL_GO 1 /* Load and refresh policy masks */ +#define POLICY_CTL_GO_ATL 4 /* Active Load */ + +/* Helper function */ +int clk_get_and_enable(char *clkstr) +{ + int ret = 0; + struct clk *c; + + debug("%s: %s\n", __func__, clkstr); + + c = clk_get(clkstr); + if (c) { + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + return ret; +} + +/* + * Poll a register in a CCU's address space, returning when the + * specified bit in that register's value is set (or clear). Delay + * a microsecond after each read of the register. Returns true if + * successful, or false if we gave up trying. + * + * Caller must ensure the CCU lock is held. + */ +#define CLK_GATE_DELAY_USEC 2000 +static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) +{ + unsigned int tries; + u32 bit_mask = 1 << bit; + + for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) { + u32 val; + bool bit_val; + + val = readl(base + offset); + bit_val = (val & bit_mask) ? 1 : 0; + if (bit_val == want) + return 0; /* success */ + udelay(1); + } + + debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n", + __func__, base + offset, bit, want); + + return -ETIMEDOUT; +} + +/* Enable a peripheral clock */ +static int peri_clk_enable(struct clk *c, int enable) +{ + int ret = 0; + u32 reg; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + struct bcm_clk_gate *gate = &cd->gate; + void *base = (void *)c->ccu_clk_mgr_base; + + + debug("%s: %s\n", __func__, c->name); + + clk_get_rate(c); /* Make sure rate and sel are filled in */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + if (enable) { + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", + __func__, c->name, c->rate, c->div, c->sel, + c->parent->rate); + + /* + * clkgate - only software controllable gates are + * supported by u-boot which includes all clocks + * that matter. This avoids bringing in a lot of extra + * complexity as done in the kernel framework. + */ + if (gate_exists(gate)) { + reg = readl(base + cd->gate.offset); + reg |= (1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + } + + /* div and pll select */ + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + bitfield_replace(reg, cd->div.shift, cd->div.width, + c->div - 1); + writel(reg, base + cd->div.offset); + } + + /* frequency selector */ + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + bitfield_replace(reg, cd->sel.shift, cd->sel.width, + c->sel); + writel(reg, base + cd->sel.offset); + } + + /* trigger */ + if (trigger_exists(&cd->trig)) { + writel((1 << cd->trig.bit), base + cd->trig.offset); + + /* wait for trigger status bit to go to 0 */ + ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0); + if (ret) + return ret; + } + + /* wait for running (status_bit = 1) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); + if (ret) + return ret; + } else { + debug("%s disable clock %s\n", __func__, c->name); + + /* clkgate */ + reg = readl(base + cd->gate.offset); + reg &= ~(1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + + /* wait for stop (status_bit = 0) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Set the rate of a peripheral clock */ +static int peri_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + int i; + unsigned long diff; + unsigned long new_rate = 0, div = 1; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + const char **clock; + + debug("%s: %s\n", __func__, c->name); + diff = rate; + + i = 0; + for (clock = cd->clocks; *clock; clock++, i++) { + struct refclk *ref = refclk_str_to_clk(*clock); + if (!ref) { + printf("%s: Lookup of %s failed\n", __func__, *clock); + return -EINVAL; + } + + /* round to the new rate */ + div = ref->clk.rate / rate; + if (div == 0) + div = 1; + + new_rate = ref->clk.rate / div; + + /* get the min diff */ + if (abs(new_rate - rate) < diff) { + diff = abs(new_rate - rate); + c->sel = i; + c->parent = &ref->clk; + c->rate = new_rate; + c->div = div; + } + } + + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__, + c->name, c->rate, c->div, c->sel, c->parent->rate); + return ret; +} + +/* Get the rate of a peripheral clock */ +static unsigned long peri_clk_get_rate(struct clk *c) +{ + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int div = 1; + const char **clock; + struct refclk *ref; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); + } else { + /* + * For peri clocks that don't have a selector, the single + * reference clock will always exist at index 0. + */ + c->sel = 0; + } + + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + div = bitfield_extract(reg, cd->div.shift, cd->div.width); + div += 1; + } + + clock = cd->clocks; + ref = refclk_str_to_clk(clock[c->sel]); + if (!ref) { + printf("%s: Can't lookup %s\n", __func__, clock[c->sel]); + return 0; + } + + c->parent = &ref->clk; + c->div = div; + c->rate = c->parent->rate / c->div; + debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__, + c->parent->rate, div, c->sel, c->rate); + + return c->rate; +} + +/* Peripheral clock operations */ +struct clk_ops peri_clk_ops = { + .enable = peri_clk_enable, + .set_rate = peri_clk_set_rate, + .get_rate = peri_clk_get_rate, +}; + +/* Enable a CCU clock */ +static int ccu_clk_enable(struct clk *c, int enable) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (!enable) + return -EINVAL; /* CCU clock cannot shutdown */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* config enable for policy engine */ + writel(1, base + ccu_clk->lvm_en_offset); + + /* wait for bit to go to 0 */ + ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0); + if (ret) + return ret; + + /* freq ID */ + if (!ccu_clk->freq_bit_shift) + ccu_clk->freq_bit_shift = 8; + + /* Set frequency id for each of the 4 policies */ + reg = ccu_clk->freq_id | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3)); + writel(reg, base + ccu_clk->policy_freq_offset); + + /* enable all clock mask */ + writel(0x7fffffff, base + ccu_clk->policy0_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask_offset); + + if (ccu_clk->num_policy_masks == 2) { + writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset); + } + + /* start policy engine */ + reg = readl(base + ccu_clk->policy_ctl_offset); + reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL); + writel(reg, base + ccu_clk->policy_ctl_offset); + + /* wait till started */ + ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0); + if (ret) + return ret; + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the CCU clock rate */ +static unsigned long ccu_clk_get_rate(struct clk *c) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + debug("%s: %s\n", __func__, c->name); + c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id]; + return c->rate; +} + +/* CCU clock operations */ +struct clk_ops ccu_clk_ops = { + .enable = ccu_clk_enable, + .get_rate = ccu_clk_get_rate, +}; + +/* Enable a bus clock */ +static int bus_clk_enable(struct clk *c, int enable) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct bus_clk_data *cd = bus_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* enable gating */ + reg = readl(base + cd->gate.offset); + if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) + debug("%s already %s\n", c->name, + enable ? "enabled" : "disabled"); + else { + int want = (enable) ? 1 : 0; + reg |= (1 << cd->gate.hw_sw_sel_bit); + + if (enable) + reg |= (1 << cd->gate.en_bit); + else + reg &= ~(1 << cd->gate.en_bit); + + writel(reg, base + cd->gate.offset); + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, + want); + if (ret) + return ret; + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the rate of a bus clock */ +static unsigned long bus_clk_get_rate(struct clk *c) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct ccu_clock *ccu_clk; + + debug("%s: %s\n", __func__, c->name); + ccu_clk = to_ccu_clk(c->parent); + + c->rate = bus_clk->freq_tbl[ccu_clk->freq_id]; + c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate; + return c->rate; +} + +/* Bus clock operations */ +struct clk_ops bus_clk_ops = { + .enable = bus_clk_enable, + .get_rate = bus_clk_get_rate, +}; + +/* Enable a reference clock */ +static int ref_clk_enable(struct clk *c, int enable) +{ + debug("%s: %s\n", __func__, c->name); + return 0; +} + +/* Reference clock operations */ +struct clk_ops ref_clk_ops = { + .enable = ref_clk_enable, +}; + +/* + * clk.h implementation follows + */ + +/* Initialize the clock framework */ +int clk_init(void) +{ + debug("%s:\n", __func__); + return 0; +} + +/* Get a clock handle, give a name string */ +struct clk *clk_get(const char *con_id) +{ + int i; + struct clk_lookup *clk_tblp; + + debug("%s: %s\n", __func__, con_id); + + clk_tblp = arch_clk_tbl; + for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) { + if (clk_tblp->con_id) { + if (!con_id || strcmp(clk_tblp->con_id, con_id)) + continue; + return clk_tblp->clk; + } + } + return NULL; +} + +/* Enable a clock */ +int clk_enable(struct clk *c) +{ + int ret = 0; + + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return -1; + + /* enable parent clock first */ + if (c->parent) + ret = clk_enable(c->parent); + + if (ret) + return ret; + + if (!c->use_cnt) { + c->use_cnt++; + ret = c->ops->enable(c, 1); + } + + return ret; +} + +/* Disable a clock */ +void clk_disable(struct clk *c) +{ + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return; + + if (c->use_cnt) { + c->use_cnt--; + c->ops->enable(c, 0); + } + + /* disable parent */ + if (c->parent) + clk_disable(c->parent); +} + +/* Get the clock rate */ +unsigned long clk_get_rate(struct clk *c) +{ + unsigned long rate; + + debug("%s: %s\n", __func__, c->name); + if (!c || !c->ops || !c->ops->get_rate) + return 0; + + rate = c->ops->get_rate(c); + debug("%s: rate = %ld\n", __func__, rate); + return rate; +} + +/* Set the clock rate */ +int clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + + debug("%s: %s rate=%ld\n", __func__, c->name, rate); + if (!c || !c->ops || !c->ops->set_rate) + return -EINVAL; + + if (c->use_cnt) + return -EINVAL; + + ret = c->ops->set_rate(c, rate); + + return ret; +} + +/* Not required for this arch */ +/* +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +*/ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h new file mode 100644 index 0000000000..882a297797 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h @@ -0,0 +1,495 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifdef CONFIG_CLK_DEBUG +#undef writel +#undef readl +static inline void writel(u32 val, void *addr) +{ + printf("Write [0x%p] = 0x%08x\n", addr, val); + *(u32 *)addr = val; +} + +static inline u32 readl(void *addr) +{ + u32 val = *(u32 *)addr; + printf("Read [0x%p] = 0x%08x\n", addr, val); + return val; +} +#endif + +struct clk; + +struct clk_lookup { + const char *dev_id; + const char *con_id; + struct clk *clk; +}; + +extern struct clk_lookup arch_clk_tbl[]; +extern unsigned int arch_clk_tbl_array_size; + +/** + * struct clk_ops - standard clock operations + * @enable: enable/disable clock, see clk_enable() and clk_disable() + * @set_rate: set the clock rate, see clk_set_rate(). + * @get_rate: get the clock rate, see clk_get_rate(). + * @round_rate: round a given clock rate, see clk_round_rate(). + * @set_parent: set the clock's parent, see clk_set_parent(). + * + * Group the common clock implementations together so that we + * don't have to keep setting the same fiels again. We leave + * enable in struct clk. + * + */ +struct clk_ops { + int (*enable) (struct clk *c, int enable); + int (*set_rate) (struct clk *c, unsigned long rate); + unsigned long (*get_rate) (struct clk *c); + unsigned long (*round_rate) (struct clk *c, unsigned long rate); + int (*set_parent) (struct clk *c, struct clk *parent); +}; + +struct clk { + struct clk *parent; + const char *name; + int use_cnt; + unsigned long rate; /* in HZ */ + + /* programmable divider. 0 means fixed ratio to parent clock */ + unsigned long div; + + struct clk_src *src; + struct clk_ops *ops; + + unsigned long ccu_clk_mgr_base; + int sel; +}; + +struct refclk *refclk_str_to_clk(const char *name); + +#define U8_MAX ((u8)~0U) +#define U32_MAX ((u32)~0U) +#define U64_MAX ((u64)~0U) + +/* The common clock framework uses u8 to represent a parent index */ +#define PARENT_COUNT_MAX ((u32)U8_MAX) + +#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ +#define BAD_CLK_NAME ((const char *)-1) + +#define BAD_SCALED_DIV_VALUE U64_MAX + +/* + * Utility macros for object flag management. If possible, flags + * should be defined such that 0 is the desired default value. + */ +#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag +#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) +#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) +#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) +#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) + +/* Clock field state tests */ + +#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) +#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) +#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) +#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) +#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) +#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) + +#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) + +#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) +#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) +#define divider_has_fraction(div) (!divider_is_fixed(div) && \ + (div)->frac_width > 0) + +#define selector_exists(sel) ((sel)->width != 0) +#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) + +/* Clock type, used to tell common block what it's part of */ +enum bcm_clk_type { + bcm_clk_none, /* undefined clock type */ + bcm_clk_bus, + bcm_clk_core, + bcm_clk_peri +}; + +/* + * Gating control and status is managed by a 32-bit gate register. + * + * There are several types of gating available: + * - (no gate) + * A clock with no gate is assumed to be always enabled. + * - hardware-only gating (auto-gating) + * Enabling or disabling clocks with this type of gate is + * managed automatically by the hardware. Such clocks can be + * considered by the software to be enabled. The current status + * of auto-gated clocks can be read from the gate status bit. + * - software-only gating + * Auto-gating is not available for this type of clock. + * Instead, software manages whether it's enabled by setting or + * clearing the enable bit. The current gate status of a gate + * under software control can be read from the gate status bit. + * To ensure a change to the gating status is complete, the + * status bit can be polled to verify that the gate has entered + * the desired state. + * - selectable hardware or software gating + * Gating for this type of clock can be configured to be either + * under software or hardware control. Which type is in use is + * determined by the hw_sw_sel bit of the gate register. + */ +struct bcm_clk_gate { + u32 offset; /* gate register offset */ + u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ + u32 en_bit; /* 0: disable; 1: enable */ + u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ + u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ +}; + +/* + * Gate flags: + * HW means this gate can be auto-gated + * SW means the state of this gate can be software controlled + * NO_DISABLE means this gate is (only) enabled if under software control + * SW_MANAGED means the status of this gate is under software control + * ENABLED means this software-managed gate is *supposed* to be enabled + */ +#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ +#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ +#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ +#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ +#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ +#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ + +/* + * Gate initialization macros. + * + * Any gate initially under software control will be enabled. + */ + +/* A hardware/software gate initially under software control */ +#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware/software gate initially under hardware control */ +#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware-or-enabled gate (enabled if not under hardware control) */ +#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ + } + +/* A software-only gate */ +#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ + FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ + } + +/* A hardware-only gate */ +#define HW_ONLY_GATE(_offset, _status_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ + } + +/* + * Each clock can have zero, one, or two dividers which change the + * output rate of the clock. Each divider can be either fixed or + * variable. If there are two dividers, they are the "pre-divider" + * and the "regular" or "downstream" divider. If there is only one, + * there is no pre-divider. + * + * A fixed divider is any non-zero (positive) value, and it + * indicates how the input rate is affected by the divider. + * + * The value of a variable divider is maintained in a sub-field of a + * 32-bit divider register. The position of the field in the + * register is defined by its offset and width. The value recorded + * in this field is always 1 less than the value it represents. + * + * In addition, a variable divider can indicate that some subset + * of its bits represent a "fractional" part of the divider. Such + * bits comprise the low-order portion of the divider field, and can + * be viewed as representing the portion of the divider that lies to + * the right of the decimal point. Most variable dividers have zero + * fractional bits. Variable dividers with non-zero fraction width + * still record a value 1 less than the value they represent; the + * added 1 does *not* affect the low-order bit in this case, it + * affects the bits above the fractional part only. (Often in this + * code a divider field value is distinguished from the value it + * represents by referring to the latter as a "divisor".) + * + * In order to avoid dealing with fractions, divider arithmetic is + * performed using "scaled" values. A scaled value is one that's + * been left-shifted by the fractional width of a divider. Dividing + * a scaled value by a scaled divisor produces the desired quotient + * without loss of precision and without any other special handling + * for fractions. + * + * The recorded value of a variable divider can be modified. To + * modify either divider (or both), a clock must be enabled (i.e., + * using its gate). In addition, a trigger register (described + * below) must be used to commit the change, and polled to verify + * the change is complete. + */ +struct bcm_clk_div { + union { + struct { /* variable divider */ + u32 offset; /* divider register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + u32 frac_width; /* field fraction width */ + + u64 scaled_div; /* scaled divider value */ + }; + u32 fixed; /* non-zero fixed divider value */ + }; + u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ +}; + +/* + * Divider flags: + * EXISTS means this divider exists + * FIXED means it is a fixed-rate divider + */ +#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ +#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ + +/* Divider initialization macros */ + +/* A fixed (non-zero) divider */ +#define FIXED_DIVIDER(_value) \ + { \ + .fixed = (_value), \ + .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ + } + +/* A divider with an integral divisor */ +#define DIVIDER(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* A divider whose divisor has an integer and fractional part */ +#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .frac_width = (_frac_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* + * Clocks may have multiple "parent" clocks. If there is more than + * one, a selector must be specified to define which of the parent + * clocks is currently in use. The selected clock is indicated in a + * sub-field of a 32-bit selector register. The range of + * representable selector values typically exceeds the number of + * available parent clocks. Occasionally the reset value of a + * selector field is explicitly set to a (specific) value that does + * not correspond to a defined input clock. + * + * We register all known parent clocks with the common clock code + * using a packed array (i.e., no empty slots) of (parent) clock + * names, and refer to them later using indexes into that array. + * We maintain an array of selector values indexed by common clock + * index values in order to map between these common clock indexes + * and the selector values used by the hardware. + * + * Like dividers, a selector can be modified, but to do so a clock + * must be enabled, and a trigger must be used to commit the change. + */ +struct bcm_clk_sel { + u32 offset; /* selector register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + + u32 parent_count; /* number of entries in parent_sel[] */ + u32 *parent_sel; /* array of parent selector values */ + u8 clk_index; /* current selected index in parent_sel[] */ +}; + +/* Selector initialization macro */ +#define SELECTOR(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .clk_index = BAD_CLK_INDEX, \ + } + +/* + * Making changes to a variable divider or a selector for a clock + * requires the use of a trigger. A trigger is defined by a single + * bit within a register. To signal a change, a 1 is written into + * that bit. To determine when the change has been completed, that + * trigger bit is polled; the read value will be 1 while the change + * is in progress, and 0 when it is complete. + * + * Occasionally a clock will have more than one trigger. In this + * case, the "pre-trigger" will be used when changing a clock's + * selector and/or its pre-divider. + */ +struct bcm_clk_trig { + u32 offset; /* trigger register offset */ + u32 bit; /* trigger bit */ + u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ +}; + +/* + * Trigger flags: + * EXISTS means this trigger exists + */ +#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ + +/* Trigger initialization macro */ +#define TRIGGER(_offset, _bit) \ + { \ + .offset = (_offset), \ + .bit = (_bit), \ + .flags = FLAG(TRIG, EXISTS), \ + } + +struct bus_clk_data { + struct bcm_clk_gate gate; +}; + +struct core_clk_data { + struct bcm_clk_gate gate; +}; + +struct peri_clk_data { + struct bcm_clk_gate gate; + struct bcm_clk_trig pre_trig; + struct bcm_clk_div pre_div; + struct bcm_clk_trig trig; + struct bcm_clk_div div; + struct bcm_clk_sel sel; + const char *clocks[]; /* must be last; use CLOCKS() to declare */ +}; +#define CLOCKS(...) { __VA_ARGS__, NULL, } +#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ + +struct refclk { + struct clk clk; +}; + +struct peri_clock { + struct clk clk; + struct peri_clk_data *data; +}; + +struct ccu_clock { + struct clk clk; + + int num_policy_masks; + unsigned long policy_freq_offset; + int freq_bit_shift; /* 8 for most CCUs */ + unsigned long policy_ctl_offset; + unsigned long policy0_mask_offset; + unsigned long policy1_mask_offset; + unsigned long policy2_mask_offset; + unsigned long policy3_mask_offset; + unsigned long policy0_mask2_offset; + unsigned long policy1_mask2_offset; + unsigned long policy2_mask2_offset; + unsigned long policy3_mask2_offset; + unsigned long lvm_en_offset; + + int freq_id; + unsigned long *freq_tbl; +}; + +struct bus_clock { + struct clk clk; + struct bus_clk_data *data; + unsigned long *freq_tbl; +}; + +struct ref_clock { + struct clk clk; +}; + +static inline int is_same_clock(struct clk *a, struct clk *b) +{ + return (a == b); +} + +#define to_clk(p) (&((p)->clk)) +#define name_to_clk(name) (&((name##_clk).clk)) +/* declare a struct clk_lookup */ +#define CLK_LK(name) \ +{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} + +static inline struct refclk *to_refclk(struct clk *clock) +{ + return container_of(clock, struct refclk, clk); +} + +static inline struct peri_clock *to_peri_clk(struct clk *clock) +{ + return container_of(clock, struct peri_clock, clk); +} + +static inline struct ccu_clock *to_ccu_clk(struct clk *clock) +{ + return container_of(clock, struct ccu_clock, clk); +} + +static inline struct bus_clock *to_bus_clk(struct clk *clock) +{ + return container_of(clock, struct bus_clock, clk); +} + +static inline struct ref_clock *to_ref_clk(struct clk *clock) +{ + return container_of(clock, struct ref_clock, clk); +} + +extern struct clk_ops peri_clk_ops; +extern struct clk_ops ccu_clk_ops; +extern struct clk_ops bus_clk_ops; +extern struct clk_ops ref_clk_ops; + +extern int clk_get_and_enable(char *clkstr); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c new file mode 100644 index 0000000000..49badcbaa7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -0,0 +1,73 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for an SDIO port */ +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) +{ + int ret; + struct clk *c; + + char *clkstr; + char *slpstr; + char *ahbstr; + + switch ((u32) base) { + case CONFIG_SYS_SDIO_BASE0: + clkstr = CONFIG_SYS_SDIO0 "_clk"; + ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO0 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE1: + clkstr = CONFIG_SYS_SDIO1 "_clk"; + ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO1 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE2: + clkstr = CONFIG_SYS_SDIO2 "_clk"; + ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO2 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE3: + clkstr = CONFIG_SYS_SDIO3 "_clk"; + ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO3 "_sleep_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + ret = clk_get_and_enable(ahbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(slpstr); + if (ret) + return ret; + + c = clk_get(clkstr); + if (c) { + ret = clk_set_rate(c, rate); + if (ret) + return ret; + + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + *actual_ratep = rate; + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c new file mode 100644 index 0000000000..3beb0ed9c7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define EN_MASK 0x08000000 /* Enable timer */ +#define SRSTEN_MASK 0x04000000 /* Enable soft reset */ +#define CLKS_SHIFT 20 /* Clock period shift */ +#define LD_SHIFT 0 /* Reload value shift */ + +void reset_cpu(ulong ignored) +{ + /* + * Set WD enable, RST enable, + * 3.9 msec clock period (8), reload value (8*3.9ms) + */ + u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); + writel(reg, SECWD2_BASE_ADDR); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index f0d9c04327..6c82c3b537 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -10,24 +10,9 @@ PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -# SEE README.arm-unaligned-accesses +# On supported platforms we set the bit which causes us to trap on unaligned +# memory access. This is the opposite of what the compiler expects to be +# the default so we must pass in -mno-unaligned-access so that it is aware +# of our decision. PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) -PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif +PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 5bde9d180b..1fea4d6663 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,7 +26,7 @@ struct clk_bit_info { }; /* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { +static struct clk_bit_info clk_bit_info[] = { {0, 0, -1}, {4, 4, -1}, {8, 8, -1}, @@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos4x12: set the mmc clock */ @@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) struct exynos4x12_clock *clk = (struct exynos4x12_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val, shift; + unsigned int shift; /* * CLK_DIV_FSYS1 @@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) addr = (unsigned int)&clk->div_fsys1; shift = dev_index * 10; - val = readl(addr); - val &= ~(0x3ff << shift); - val |= (div & 0x3ff) << shift; - writel(val, addr); + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); } /* get_lcd_clk: return lcd clock frequency */ @@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 0); /* * CLK_DIV_LCD0 @@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x1; - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); } void exynos5_set_lcd_clk(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_disp1_0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_disp1_0); + clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_disp1); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_disp1); + setbits_le32(&clk->gate_ip_disp1, 1 << 0); /* * CLK_DIV_LCD0 @@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x0; - writel(cfg, &clk->div_disp1_0); + clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); } void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_SRC_LCD0 @@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_SEL [12:15] * set mipi0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf << 12); - cfg |= (0x6 << 12); - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); /* * CLK_SRC_MASK_LCD0 @@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_MASK [12] * set src mask mipi0 0x1: Unmask */ - cfg = readl(&clk->src_mask_lcd0); - cfg |= (0x1 << 12); - writel(cfg, &clk->src_mask_lcd0); + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); /* * CLK_GATE_IP_LCD0 @@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for MIPI0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 3; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 3); /* * CLK_DIV_LCD0 @@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ - cfg &= ~(0xf << 16); - cfg |= (0x1 << 16); - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); } /* diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 904177a149..9edb47502c 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -39,6 +39,9 @@ static void exynos5_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); @@ -74,6 +77,9 @@ static void exynos5420_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { @@ -110,6 +116,9 @@ static int exynos5_mmc_config(int peripheral, int flags) bank = &gpio1->c4; bank_ext = NULL; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -683,6 +692,9 @@ static void exynos4_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); @@ -741,6 +753,21 @@ int exynos_pinmux_config(int peripheral, int flags) } #ifdef CONFIG_OF_CONTROL +static int exynos4_pinmux_decode_periph_id(const void *blob, int node) +{ + int err; + u32 cell[3]; + + err = fdtdec_get_int_array(blob, node, "interrupts", cell, + ARRAY_SIZE(cell)); + if (err) { + debug(" invalid peripheral id\n"); + return PERIPH_ID_NONE; + } + + return cell[1]; +} + static int exynos5_pinmux_decode_periph_id(const void *blob, int node) { int err; @@ -751,18 +778,15 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node) if (err) return PERIPH_ID_NONE; - /* check for invalid peripheral id */ - if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0)) - return cell[1]; - - debug(" invalid peripheral id\n"); - return PERIPH_ID_NONE; + return cell[1]; } int pinmux_decode_periph_id(const void *blob, int node) { if (cpu_is_exynos5()) return exynos5_pinmux_decode_periph_id(blob, node); + else if (cpu_is_exynos4()) + return exynos4_pinmux_decode_periph_id(blob, node); else return PERIPH_ID_NONE; } diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile new file mode 100644 index 0000000000..da225cb4f7 --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += s_init.o +obj-y += hwinit-common.o +obj-y += clk-stubs.o diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c new file mode 100644 index 0000000000..338e0e4962 --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c @@ -0,0 +1,21 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* + * These weak functions are available to kona architectures that don't + * require clock enables from the driver code. + */ +int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) +{ + return 0; +} + +int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep) +{ + return 0; +} diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c new file mode 100644 index 0000000000..2b3a84051c --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c @@ -0,0 +1,16 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/kona-common/s_init.c b/arch/arm/cpu/armv7/kona-common/s_init.c new file mode 100644 index 0000000000..6066a73c54 --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/s_init.c @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Early system init. Currently empty. + */ +void s_init(void) +{ +} diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c deleted file mode 100644 index ddb1898f36..0000000000 --- a/arch/arm/cpu/armv7/mx5/asm-offsets.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); - DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); - DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); - DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); - DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); - DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); - DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); - DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); - DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); - DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); - DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); - DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); - DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); - DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); - DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); - DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); - DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); - DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); - DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); - DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); - DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); - DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); - DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); - DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); - DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); - DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); - DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); - DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); - DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); - DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); - DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); - DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); - DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); - DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); -#if defined(CONFIG_MX53) - DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); -#endif - - /* DPLL */ - DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); - DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); - DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); - DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); - DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); - DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); - DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); - DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); - - return 0; -} diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 5617a410da..bd65a08ba2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -409,20 +409,15 @@ u32 imx_get_uartclk(void) u32 imx_get_fecclk(void) { - return decode_pll(PLL_ENET, MXC_HCLK); + return mxc_get_clock(MXC_IPG_CLK); } -int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) { - u32 reg = 0; - s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR; - - /* Enable sata clock */ - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_SATA_MASK; - writel(reg, &imx_ccm->CCGR5); + s32 timeout = 100000; + u32 reg = 0; /* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet); @@ -437,10 +432,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet); - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + reg |= en; writel(reg, &imx_ccm->analog_pll_enet); + return 0; +} - return 0 ; +static void ungate_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable SATA clock. */ + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} + +static void ungate_pcie_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable PCIe clock. */ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); +} + +int enable_sata_clock(void) +{ + ungate_sata_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); +} + +int enable_pcie_clock(void) +{ + struct anatop_regs *anatop_regs = + (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * Here be dragons! + * + * The register ANATOP_MISC1 is not documented in the Freescale + * MX6RM. The register that is mapped in the ANATOP space and + * marked as ANATOP_MISC1 is actually documented in the PMU section + * of the datasheet as PMU_MISC1. + * + * Switch LVDS clock source to SATA (0xb), disable clock INPUT and + * enable clock OUTPUT. This is important for PCI express link that + * is clocked from the i.MX6. + */ +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); + + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + + /* Party time! Ungate the clock to the PCIe. */ + ungate_sata_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); } unsigned int mxc_get_clock(enum mxc_clock clk) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba9cc..172527987d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,6 +8,8 @@ */ #include +#include +#include #include #include #include @@ -41,14 +43,19 @@ u32 get_cpu_rev(void) if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - if (!cfg) type = MXC_CPU_MX6SOLO; } + + if (type == MXC_CPU_MX6Q) { + if (cfg == 1) + type = MXC_CPU_MX6D; + } + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + 0x10); @@ -62,6 +69,9 @@ u32 __weak get_board_rev(void) if (type == MXC_CPU_MX6SOLO) cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + if (type == MXC_CPU_MX6D) + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); + return cpurev; } #endif @@ -177,10 +187,41 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +static void set_ahb_rate(u32 val) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, div; + + div = get_periph_clk() / val - 1; + reg = readl(&mxc_ccm->cbcdr); + + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); +} + +static void clear_mmdc_ch_mask(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Clear MMDC channel mask */ + writel(0, &mxc_ccm->ccdr); +} + int arch_cpu_init(void) { init_aips(); + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ + clear_mmdc_ch_mask(); + + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA @@ -336,3 +377,59 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + unsigned int val; + +#if defined CONFIG_MX6SL + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } +#endif + + writel(0x132, &pl310->pl310_tag_latency_ctrl); + writel(0x132, &pl310->pl310_data_latency_ctrl); + + val = readl(&pl310->pl310_prefetch_ctrl); + + /* Turn on the L2 I/D prefetch */ + val |= 0x30000000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + +#ifndef CONFIG_MX6Q + val |= 0x40800000; +#endif + writel(val, &pl310->pl310_prefetch_ctrl); + + val = readl(&pl310->pl310_power_ctrl); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, &pl310->pl310_power_ctrl); + + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 69fff323d3..52e0f4a6cf 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -66,7 +66,18 @@ u32 spl_boot_device(void) u32 spl_boot_mode(void) { - return gd->arch.omap_boot_params.omap_bootmode; + u32 val = gd->arch.omap_boot_params.omap_bootmode; + + if (val == MMCSD_MODE_RAW) + return MMCSD_MODE_RAW; + else if (val == MMCSD_MODE_FAT) + return MMCSD_MODE_FAT; + else +#ifdef CONFIG_SUPPORT_EMMC_BOOT + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_UNDEFINED; +#endif } void spl_board_init(void) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index dfa3760dfc..8e7411d437 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -418,55 +418,6 @@ static void setup_dplls(void) #endif } -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - - /* Configure ABE dpll */ - params = get_abe_dpll_params(*dplls_data); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; - - if (omap_revision() == DRA752_ES1_0) - /* Select the sys clk for dpll_abe */ - clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, - CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, - CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); -#endif - - /* Select the right reference clk */ - clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); -} -#endif - u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) { u32 offset_code; @@ -760,10 +711,6 @@ void prcm_init(void) timer_init(); scale_vcores(*omap_vcores); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif setup_warmreset_time(); break; default: diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk deleted file mode 100644 index 3a36ab65e1..0000000000 --- a/arch/arm/cpu/armv7/omap-common/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index cd6289b4fc..429c4becf3 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -179,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if ((omap_revision() >= OMAP5430_ES1_0) || - (omap_revision() == DRA752_ES1_0)) { + if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -309,7 +308,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * The same sequence should work on OMAP5432 as well. But strange that * it is not working */ - if (omap_revision() == DRA752_ES1_0) { + if (is_dra7xx()) { do_ext_phy_settings(base, regs); writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 85d375432f..8ebc0ce251 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -43,16 +43,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } @@ -254,6 +248,7 @@ u32 get_device_type(void) (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } +#if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information */ @@ -264,6 +259,8 @@ int print_cpuinfo(void) return 0; } +#endif + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index f5468c4c97..cad4feed00 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "pipe3-phy.h" @@ -31,7 +32,7 @@ struct omap_pipe3 sata_phy = { .dpll_map = dpll_map_sata, }; -int omap_sata_init(void) +int init_sata(int dev) { int ret; u32 val; diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 02aa129733..745603d0fe 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -39,7 +39,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk index 1d6a57c66c..ad44d63840 100644 --- a/arch/arm/cpu/armv7/omap3/config.mk +++ b/arch/arm/cpu/armv7/omap3/config.mk @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 6f7261b7b8..78577b1d1c 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -17,9 +17,6 @@ #include #include -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - #ifdef CONFIG_SPL_BUILD ENTRY(save_boot_params) ldr r4, =omap3_boot_device diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk index 1d6a57c66c..ad44d63840 100644 --- a/arch/arm/cpu/armv7/omap4/config.mk +++ b/arch/arm/cpu/armv7/omap4/config.mk @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 1b2f439241..029533c851 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = { .ddr = NULL }; +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct dplls omap4430_dplls = { .mpu = mpu_dpll_params_1200mhz, .core = core_dpll_params_1600mhz, @@ -399,91 +413,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - (*prcm)->cm_l4per_mcbsp4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -498,6 +427,10 @@ void hw_data_init(void) break; case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: case OMAP4430_ES2_2: case OMAP4430_ES2_3: diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index b0598a0774..db16548fac 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c index 31b679516f..3bf88979e5 100644 --- a/arch/arm/cpu/armv7/omap5/abb.c +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -28,18 +28,25 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; + u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + if (!is_omap54xx()) { + /* DRA7 */ + fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; + fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; + } /* * ABB parameters must be properly fused * otherwise ABB should be disabled */ vset = readl(fuse); - if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) + if (!(vset & fuse_enable_mask)) return -1; /* prepare VSET value for LDOVBB mux register */ - vset &= OMAP5_ABB_FUSE_VSET_MASK; - vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; + vset &= fuse_vset_mask; + vset >>= ffs(fuse_vset_mask) - 1; vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk index 2673af9668..ef2725affa 100644 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -7,7 +7,7 @@ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 5268a1fca5..ad971327bf 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, - (*prcm)->cm_ivahd_ivahd_clkctrl, - (*prcm)->cm_ivahd_sl2_clkctrl, - (*prcm)->cm_dsp_dsp_clkctrl, - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, @@ -639,6 +551,7 @@ void hw_data_init(void) break; case DRA752_ES1_0: + case DRA752_ES1_1: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &dra752_volts; @@ -666,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: *regs = &ioregs_dra7xx_es1; break; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 5386ae0568..93feb1623c 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -333,6 +333,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA752_ES1_0; break; + case DRA752_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = DRA752_ES1_1; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 77c428b535..7292161f3c 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, .control_padconf_mode = 0x4AE0C5A0, .control_xtal_oscillator = 0x4AE0C5A4, .control_i2c_2 = 0x4AE0C5A8, @@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = { .cm_dsp_clkstctrl = 0x4a005400, .cm_dsp_dsp_clkctrl = 0x4a005420, + /* prm irqstatus regs */ + .prm_irqstatus_mpu_2 = 0x4ae06014, + /* cm2.ckgen */ .cm_clksel_usb_60mhz = 0x4a008104, .cm_clkmode_dpll_per = 0x4a008140, @@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = { .prm_vc_val_bypass = 0x4ae07da0, .prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_clk = 0x4ae07db8, + + .prm_abbldo_mpu_setup = 0x4AE07DDC, + .prm_abbldo_mpu_ctrl = 0x4AE07DE0, }; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2e1870609a..16a91f911a 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: switch (emif_nr) { case 1: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; @@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; case DRA752_ES1_0: + case DRA752_ES1_1: default: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; } @@ -460,6 +462,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); break; case DRA752_ES1_0: + case DRA752_ES1_1: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -626,6 +629,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) sizeof(omap5_bug_00339_regs[0]); break; case DRA752_ES1_0: + case DRA752_ES1_1: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c9f9..cbe1d406df 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -8,5 +8,5 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c new file mode 100644 index 0000000000..23d697dee2 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static const struct socfpga_clock_manager *clock_manager_base = + (void *)SOCFPGA_CLKMGR_ADDRESS; + +#define CLKMGR_BYPASS_ENABLE 1 +#define CLKMGR_BYPASS_DISABLE 0 +#define CLKMGR_STAT_IDLE 0 +#define CLKMGR_STAT_BUSY 1 +#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 +#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 +#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 +#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 + +#define CLEAR_BGP_EN_PWRDN \ + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) + +#define VCO_EN_BASE \ + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) + +static inline void cm_wait_for_lock(uint32_t mask) +{ + register uint32_t inter_val; + do { + inter_val = readl(&clock_manager_base->inter) & mask; + } while (inter_val != mask); +} + +/* function to poll in the fsm busy bit */ +static inline void cm_wait_for_fsm(void) +{ + while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) + ; +} + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static inline void cm_write_bypass(uint32_t val) +{ + writel(val, &clock_manager_base->bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static inline void cm_write_ctrl(uint32_t val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* function to write a clock register that has phase information */ +static inline void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) +{ + /* poll until phase is zero */ + while (readl(reg_address) & mask) + ; + + writel(value, reg_address); + + while (readl(reg_address) & mask) + ; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * Put all plls in bypass + * Put all plls VCO registers back to reset value (bandgap power down). + * Put peripheral and main pll src to reset value to avoid glitch. + * Delay 5 us. + * Deassert bandgap power down and set numerator and denominator + * Start 7 us timer. + * set internal dividers + * Wait for 7 us timer. + * Enable plls + * Set external dividers while plls are locking + * Wait for pll lock + * Assert/deassert outreset all. + * Take all pll's out of bypass + * Clear safe mode + * set source main and peripheral clocks + * Ungate clocks + */ + +void cm_basic_init(const cm_config_t *cfg) +{ + uint32_t start, timeout; + + /* Start by being paranoid and gate all sw managed clocks */ + + /* + * We need to disable nandclk + * and then do another apb access before disabling + * gatting off the rest of the periperal clocks. + */ + writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & + readl(&clock_manager_base->per_pll_en), + &clock_manager_base->per_pll_en); + + /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ + writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | + CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | + CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, + &clock_manager_base->main_pll_en); + + writel(0, &clock_manager_base->sdr_pll_en); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll_en); + + /* Put all plls in bypass */ + cm_write_bypass( + CLKMGR_BYPASS_PERPLLSRC_SET( + CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_SDRPLLSRC_SET( + CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | + CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | + CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); + + /* + * Put all plls VCO registers back to reset value. + * Some code might have messed with them. + */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->main_pll_vco); + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->per_pll_vco); + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->sdr_pll_vco); + + /* + * The clocks to the flash devices and the L4_MAIN clocks can + * glitch when coming out of safe mode if their source values + * are different from their reset value. So the trick it to + * put them back to their reset state, and change input + * after exiting safe mode but before ungating the clocks. + */ + writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, + &clock_manager_base->per_pll_src); + writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, + &clock_manager_base->main_pll_l4src); + + /* read back for the required 5 us delay. */ + readl(&clock_manager_base->main_pll_vco); + readl(&clock_manager_base->per_pll_vco); + readl(&clock_manager_base->sdr_pll_vco); + + + /* + * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN + * with numerator and denominator. + */ + writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll_vco); + + writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll_vco); + + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll_vco); + + /* + * Time starts here + * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + */ + reset_timer(); + start = get_timer(0); + /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ + timeout = 7; + + /* main mpu */ + writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk); + + /* main main clock */ + writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk); + + /* main for dbg */ + writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk); + + /* main for cfgs2fuser0clk */ + writel(cfg->cfg2fuser0clk, + &clock_manager_base->main_pll_cfgs2fuser0clk); + + /* Peri emac0 50 MHz default to RMII */ + writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk); + + /* Peri emac1 50 MHz default to RMII */ + writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk); + + /* Peri QSPI */ + writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk); + + writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk); + + /* Peri pernandsdmmcclk */ + writel(cfg->pernandsdmmcclk, + &clock_manager_base->per_pll_pernandsdmmcclk); + + /* Peri perbaseclk */ + writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk); + + /* Peri s2fuser1clk */ + writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk); + + /* 7 us must have elapsed before we can enable the VCO */ + while (get_timer(start) < timeout) + ; + + /* Enable vco */ + /* main pll vco */ + writel(cfg->main_vco_base | VCO_EN_BASE, + &clock_manager_base->main_pll_vco); + + /* periferal pll */ + writel(cfg->peri_vco_base | VCO_EN_BASE, + &clock_manager_base->per_pll_vco); + + /* sdram pll vco */ + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | VCO_EN_BASE, + &clock_manager_base->sdr_pll_vco); + + /* L3 MP and L3 SP */ + writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv); + + writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv); + + writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv); + + /* L4 MP, L4 SP, can0, and can1 */ + writel(cfg->perdiv, &clock_manager_base->per_pll_div); + + writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv); + +#define LOCKED_MASK \ + (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ + CLKMGR_INTER_PERPLLLOCKED_MASK | \ + CLKMGR_INTER_MAINPLLLOCKED_MASK) + + cm_wait_for_lock(LOCKED_MASK); + + /* write the sdram clock counters before toggling outreset all */ + writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddrdqsclk); + + writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddr2xdqsclk); + + writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddrdqclk); + + writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, + &clock_manager_base->sdr_pll_s2fuser2clk); + + /* + * after locking, but before taking out of bypass + * assert/deassert outresetall + */ + uint32_t mainvco = readl(&clock_manager_base->main_pll_vco); + + /* assert main outresetall */ + writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll_vco); + + uint32_t periphvco = readl(&clock_manager_base->per_pll_vco); + + /* assert pheriph outresetall */ + writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll_vco); + + /* assert sdram outresetall */ + writel(cfg->sdram_vco_base | VCO_EN_BASE| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), + &clock_manager_base->sdr_pll_vco); + + /* deassert main outresetall */ + writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll_vco); + + /* deassert pheriph outresetall */ + writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll_vco); + + /* deassert sdram outresetall */ + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | VCO_EN_BASE, + &clock_manager_base->sdr_pll_vco); + + /* + * now that we've toggled outreset all, all the clocks + * are aligned nicely; so we can change any phase. + */ + cm_write_with_phase(cfg->ddrdqsclk, + (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); + + /* SDRAM DDR2XDQSCLK */ + cm_write_with_phase(cfg->ddr2xdqsclk, + (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk, + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); + + cm_write_with_phase(cfg->ddrdqclk, + (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk, + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); + + cm_write_with_phase(cfg->s2fuser2clk, + (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk, + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); + + /* Take all three PLLs out of bypass when safe mode is cleared. */ + cm_write_bypass( + CLKMGR_BYPASS_PERPLLSRC_SET( + CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_SDRPLLSRC_SET( + CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | + CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | + CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); + + /* clear safe mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) | + CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); + + /* + * now that safe mode is clear with clocks gated + * it safe to change the source mux for the flashes the the L4_MAIN + */ + writel(cfg->persrc, &clock_manager_base->per_pll_src); + writel(cfg->l4src, &clock_manager_base->main_pll_l4src); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll_en); + writel(~0, &clock_manager_base->per_pll_en); + writel(~0, &clock_manager_base->sdr_pll_en); +} diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk index d33ab7d62f..3d18491577 100644 --- a/arch/arm/cpu/armv7/socfpga/config.mk +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c39b7..2ae88bbd04 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -28,10 +28,99 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + cm_config_t cm_default_cfg = { + /* main group */ + MAIN_VCO_BASE, + CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), + CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( + CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( + CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( + CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), + CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( + CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | + CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( + CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), + + /* peripheral group */ + PERI_VCO_BASE, + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), + CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), + CLKMGR_PERPLLGRP_DIV_USBCLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | + CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | + CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | + CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( + CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), + CLKMGR_PERPLLGRP_SRC_QSPI_SET( + CONFIG_HPS_PERPLLGRP_SRC_QSPI) | + CLKMGR_PERPLLGRP_SRC_NAND_SET( + CONFIG_HPS_PERPLLGRP_SRC_NAND) | + CLKMGR_PERPLLGRP_SRC_SDMMC_SET( + CONFIG_HPS_PERPLLGRP_SRC_SDMMC), + + /* sdram pll group */ + SDR_VCO_BASE, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), + }; + debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + debug("Reconfigure Clock Manager\n"); + /* reconfigure the PLLs */ + cm_basic_init(&cm_default_cfg); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds index a7c9c9d281..4282beb395 100644 --- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -28,7 +28,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { . = ALIGN(4); diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6c9b11a452..27be451a89 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -38,12 +38,19 @@ _irq: .word _irq _fiq: .word _fiq _pad: .word 0x12345678 /* now 16*4=64 */ #else +.globl _undefined_instruction _undefined_instruction: .word undefined_instruction +.globl _software_interrupt _software_interrupt: .word software_interrupt +.globl _prefetch_abort _prefetch_abort: .word prefetch_abort +.globl _data_abort _data_abort: .word data_abort +.globl _not_used _not_used: .word not_used +.globl _irq _irq: .word irq +.globl _fiq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ @@ -63,29 +70,6 @@ _end_vect: * *************************************************************************/ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -221,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register @@ -238,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile index 886b5092d6..77e231959b 100644 --- a/arch/arm/cpu/armv7/tegra114/Makefile +++ b/arch/arm/cpu/armv7/tegra114/Makefile @@ -17,4 +17,5 @@ # along with this program. If not, see . # -obj- := +# necessary to create built-in.o +obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile new file mode 100644 index 0000000000..9478d447db --- /dev/null +++ b/arch/arm/cpu/armv7/tegra124/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# necessary to create built-in.o +obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile index 518d6d1b3e..413eba102a 100644 --- a/arch/arm/cpu/armv7/tegra30/Makefile +++ b/arch/arm/cpu/armv7/tegra30/Makefile @@ -17,4 +17,5 @@ # along with this program. If not, see . # -obj- := +# necessary to create built-in.o +obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c index 964b0d103b..d2885dc2b9 100644 --- a/arch/arm/cpu/armv7/zynq/clk.c +++ b/arch/arm/cpu/armv7/zynq/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Sören Brinkmann + * Copyright (C) 2013 Soren Brinkmann * Copyright (C) 2013 Xilinx, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ @@ -360,47 +360,47 @@ static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name, static void init_periph_clocks(void) { zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl, - "gem0", 1); + "gem0", 1); zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl, - "gem1", 1); + "gem1", 1); zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl, - "smc", 0); + "smc", 0); zynq_clk_register_periph_clk(&clks[lqspi_clk], - &slcr_base->lqspi_clk_ctrl, "lqspi", 0); + &slcr_base->lqspi_clk_ctrl, "lqspi", 0); zynq_clk_register_periph_clk(&clks[sdio0_clk], - &slcr_base->sdio_clk_ctrl, "sdio0", 0); + &slcr_base->sdio_clk_ctrl, "sdio0", 0); zynq_clk_register_periph_clk(&clks[sdio1_clk], - &slcr_base->sdio_clk_ctrl, "sdio1", 0); + &slcr_base->sdio_clk_ctrl, "sdio1", 0); zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl, - "spi0", 0); + "spi0", 0); zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl, - "spi1", 0); + "spi1", 0); zynq_clk_register_periph_clk(&clks[uart0_clk], - &slcr_base->uart_clk_ctrl, "uart0", 0); + &slcr_base->uart_clk_ctrl, "uart0", 0); zynq_clk_register_periph_clk(&clks[uart1_clk], - &slcr_base->uart_clk_ctrl, "uart1", 0); + &slcr_base->uart_clk_ctrl, "uart1", 0); zynq_clk_register_periph_clk(&clks[dbg_trc_clk], - &slcr_base->dbg_clk_ctrl, "dbg_trc", 0); + &slcr_base->dbg_clk_ctrl, "dbg_trc", 0); zynq_clk_register_periph_clk(&clks[dbg_apb_clk], - &slcr_base->dbg_clk_ctrl, "dbg_apb", 0); + &slcr_base->dbg_clk_ctrl, "dbg_apb", 0); zynq_clk_register_periph_clk(&clks[pcap_clk], - &slcr_base->pcap_clk_ctrl, "pcap", 0); + &slcr_base->pcap_clk_ctrl, "pcap", 0); zynq_clk_register_periph_clk(&clks[fclk0_clk], - &slcr_base->fpga0_clk_ctrl, "fclk0", 1); + &slcr_base->fpga0_clk_ctrl, "fclk0", 1); zynq_clk_register_periph_clk(&clks[fclk1_clk], - &slcr_base->fpga1_clk_ctrl, "fclk1", 1); + &slcr_base->fpga1_clk_ctrl, "fclk1", 1); zynq_clk_register_periph_clk(&clks[fclk2_clk], - &slcr_base->fpga2_clk_ctrl, "fclk2", 1); + &slcr_base->fpga2_clk_ctrl, "fclk2", 1); zynq_clk_register_periph_clk(&clks[fclk3_clk], - &slcr_base->fpga3_clk_ctrl, "fclk3", 1); + &slcr_base->fpga3_clk_ctrl, "fclk3", 1); } /** @@ -420,48 +420,48 @@ static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name) static void init_aper_clocks(void) { zynq_clk_register_aper_clk(&clks[usb0_aper_clk], - &slcr_base->aper_clk_ctrl, "usb0_aper"); + &slcr_base->aper_clk_ctrl, "usb0_aper"); zynq_clk_register_aper_clk(&clks[usb1_aper_clk], - &slcr_base->aper_clk_ctrl, "usb1_aper"); + &slcr_base->aper_clk_ctrl, "usb1_aper"); zynq_clk_register_aper_clk(&clks[gem0_aper_clk], - &slcr_base->aper_clk_ctrl, "gem0_aper"); + &slcr_base->aper_clk_ctrl, "gem0_aper"); zynq_clk_register_aper_clk(&clks[gem1_aper_clk], - &slcr_base->aper_clk_ctrl, "gem1_aper"); + &slcr_base->aper_clk_ctrl, "gem1_aper"); zynq_clk_register_aper_clk(&clks[sdio0_aper_clk], - &slcr_base->aper_clk_ctrl, "sdio0_aper"); + &slcr_base->aper_clk_ctrl, "sdio0_aper"); zynq_clk_register_aper_clk(&clks[sdio1_aper_clk], - &slcr_base->aper_clk_ctrl, "sdio1_aper"); + &slcr_base->aper_clk_ctrl, "sdio1_aper"); zynq_clk_register_aper_clk(&clks[spi0_aper_clk], - &slcr_base->aper_clk_ctrl, "spi0_aper"); + &slcr_base->aper_clk_ctrl, "spi0_aper"); zynq_clk_register_aper_clk(&clks[spi1_aper_clk], - &slcr_base->aper_clk_ctrl, "spi1_aper"); + &slcr_base->aper_clk_ctrl, "spi1_aper"); zynq_clk_register_aper_clk(&clks[can0_aper_clk], - &slcr_base->aper_clk_ctrl, "can0_aper"); + &slcr_base->aper_clk_ctrl, "can0_aper"); zynq_clk_register_aper_clk(&clks[can1_aper_clk], - &slcr_base->aper_clk_ctrl, "can1_aper"); + &slcr_base->aper_clk_ctrl, "can1_aper"); zynq_clk_register_aper_clk(&clks[i2c0_aper_clk], - &slcr_base->aper_clk_ctrl, "i2c0_aper"); + &slcr_base->aper_clk_ctrl, "i2c0_aper"); zynq_clk_register_aper_clk(&clks[i2c1_aper_clk], - &slcr_base->aper_clk_ctrl, "i2c1_aper"); + &slcr_base->aper_clk_ctrl, "i2c1_aper"); zynq_clk_register_aper_clk(&clks[uart0_aper_clk], - &slcr_base->aper_clk_ctrl, "uart0_aper"); + &slcr_base->aper_clk_ctrl, "uart0_aper"); zynq_clk_register_aper_clk(&clks[uart1_aper_clk], - &slcr_base->aper_clk_ctrl, "uart1_aper"); + &slcr_base->aper_clk_ctrl, "uart1_aper"); zynq_clk_register_aper_clk(&clks[gpio_aper_clk], - &slcr_base->aper_clk_ctrl, "gpio_aper"); + &slcr_base->aper_clk_ctrl, "gpio_aper"); zynq_clk_register_aper_clk(&clks[lqspi_aper_clk], - &slcr_base->aper_clk_ctrl, "lqspi_aper"); + &slcr_base->aper_clk_ctrl, "lqspi_aper"); zynq_clk_register_aper_clk(&clks[smc_aper_clk], - &slcr_base->aper_clk_ctrl, "smc_aper"); + &slcr_base->aper_clk_ctrl, "smc_aper"); } /** @@ -584,11 +584,11 @@ unsigned long get_uart_clk(int dev_index) int set_cpu_clk_info(void) { zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl, - "armpll", CONFIG_ZYNQ_PS_CLK_FREQ); + "armpll", CONFIG_ZYNQ_PS_CLK_FREQ); zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl, - "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ); + "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ); zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl, - "iopll", CONFIG_ZYNQ_PS_CLK_FREQ); + "iopll", CONFIG_ZYNQ_PS_CLK_FREQ); init_ddr_clocks(); init_cpu_clocks(); diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index cf3d92febf..5159c021a4 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -61,7 +62,7 @@ void reset_cpu(ulong addr) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); } #endif diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index f6686b4d64..c4556c94d6 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -11,32 +11,29 @@ #include #include -__weak void ps7_init(void) -{ - puts("Please copy ps7_init.c/h from hw project\n"); -} - DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong dummy) { + ps7_init(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* Set global data pointer. */ gd = &gdata; - ps7_init(); - preloader_console_init(); arch_cpu_init(); board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void) { board_init(); } +#endif u32 spl_boot_device(void) { diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index 764f04b42f..f2a5965988 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -60,17 +60,13 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; - - /* - * Deprecated: this MMU section is used by pxa at present but - * should not be used by new boards/CPUs. - */ - . = ALIGN(4096); - .mmutable : { - *(.mmutable) + .end : + { + *(.__end) } + _image_binary_end = .; + /* * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c * __bss_base and __bss_limit are for linker only (overlay ordering) @@ -91,6 +87,11 @@ SECTIONS KEEP(*(.__bss_end)); } + /* + * Zynq needs to discard more sections because the user + * is expected to pass this image on to tools for boot.bin + * generation that require them to be dropped. + */ /DISCARD/ : { *(.dynsym) } /DISCARD/ : { *(.dynbss*) } /DISCARD/ : { *(.dynstr*) } diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index b6eb6de5e3..7d93f59428 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -13,5 +13,4 @@ obj-y += cache_v8.o obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o -obj-y += gic.o obj-y += transition.o diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 546a83e8f8..4b3ee6ed6f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -19,23 +19,22 @@ * clean and invalidate one level cache. * * x0: cache level - * x1~x9: clobbered + * x1: 0 flush & invalidate, 1 invalidate only + * x2~x9: clobbered */ ENTRY(__asm_flush_dcache_level) - lsl x1, x0, #1 - msr csselr_el1, x1 /* select cache level */ + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ add x2, x2, #4 /* x2 <- log2(cache line size) */ mov x3, #0x3ff and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ - add w4, w3, w3 - sub w4, w4, 1 /* round up log2(#ways + 1) */ - clz w5, w4 /* bit position of #ways */ + clz w5, w3 /* bit position of #ways */ mov x4, #0x7fff and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ - /* x1 <- cache level << 1 */ + /* x12 <- cache level << 1 */ /* x2 <- line length offset */ /* x3 <- number of cache ways - 1 */ /* x4 <- number of cache sets - 1 */ @@ -45,11 +44,14 @@ loop_set: mov x6, x3 /* x6 <- working copy of #ways */ loop_way: lsl x7, x6, x5 - orr x9, x1, x7 /* map way and level to cisw value */ + orr x9, x12, x7 /* map way and level to cisw value */ lsl x7, x4, x2 orr x9, x9, x7 /* map set number to cisw value */ - dc cisw, x9 /* clean & invalidate by set/way */ - subs x6, x6, #1 /* decrement the way */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ b.ge loop_way subs x4, x4, #1 /* decrement the set */ b.ge loop_set @@ -58,11 +60,14 @@ loop_way: ENDPROC(__asm_flush_dcache_level) /* - * void __asm_flush_dcache_all(void) + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 flush & invalidate, 1 invalidate only * * clean and invalidate all data cache by SET/WAY. */ -ENTRY(__asm_flush_dcache_all) +ENTRY(__asm_dcache_all) + mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ lsr x11, x10, #24 @@ -76,13 +81,13 @@ ENTRY(__asm_flush_dcache_all) /* x15 <- return address */ loop_level: - lsl x1, x0, #1 - add x1, x1, x0 /* x0 <- tripled cache level */ - lsr x1, x10, x1 - and x1, x1, #7 /* x1 <- cache type */ - cmp x1, #2 + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level + bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0 @@ -96,8 +101,24 @@ skip: finished: ret +ENDPROC(__asm_dcache_all) + +ENTRY(__asm_flush_dcache_all) + mov x16, lr + mov x0, #0 + bl __asm_dcache_all + mov lr, x16 + ret ENDPROC(__asm_flush_dcache_all) +ENTRY(__asm_invalidate_dcache_all) + mov x16, lr + mov x0, #0xffff + bl __asm_dcache_all + mov lr, x16 + ret +ENDPROC(__asm_invalidate_dcache_all) + /* * void __asm_flush_dcache_range(start, end) * diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 131fdaba3f..a96ecda7e3 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -45,15 +45,31 @@ static void mmu_setup(void) /* load TTBR0 */ el = current_el(); - if (el == 1) + if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else if (el == 2) + asm volatile("msr tcr_el1, %0" + : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) + : "memory"); + asm volatile("msr mair_el1, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else if (el == 2) { asm volatile("msr ttbr0_el2, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else + asm volatile("msr tcr_el2, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el2, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else { asm volatile("msr ttbr0_el3, %0" : : "r" (gd->arch.tlb_addr) : "memory"); + asm volatile("msr tcr_el3, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el3, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); @@ -64,7 +80,7 @@ static void mmu_setup(void) */ void invalidate_dcache_all(void) { - __asm_flush_dcache_all(); + __asm_invalidate_dcache_all(); } /* @@ -161,6 +177,7 @@ int dcache_status(void) void icache_enable(void) { + __asm_invalidate_icache_all(); set_sctlr(get_sctlr() | CR_I); } diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk index 027a68ca57..f5b95591af 100644 --- a/arch/arm/cpu/armv8/config.mk +++ b/arch/arm/cpu/armv8/config.mk @@ -6,10 +6,7 @@ # PLATFORM_RELFLAGS += -fno-common -ffixed-x18 -# SEE README.arm-unaligned-accesses -PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) -PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) - PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a) +PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8) PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv8/gic.S b/arch/arm/cpu/armv8/gic.S deleted file mode 100644 index 599aa8f2ba..0000000000 --- a/arch/arm/cpu/armv8/gic.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * GIC Initialization Routines. - * - * (C) Copyright 2013 - * David Feng - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - - -/************************************************************************* - * - * void gic_init(void) __attribute__((weak)); - * - * Currently, this routine only initialize secure copy of GIC - * with Security Extensions at EL3. - * - *************************************************************************/ -WEAK(gic_init) - branch_if_slave x0, 2f - - /* Initialize Distributor and SPIs */ - ldr x1, =GICD_BASE - mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */ - str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */ - ldr w0, [x1, GICD_TYPER] - and w2, w0, #0x1f /* ITLinesNumber */ - cbz w2, 2f /* No SPIs */ - add x1, x1, (GICD_IGROUPRn + 4) - mov w0, #~0 /* Config SPIs as Grp1 */ -1: str w0, [x1], #0x4 - sub w2, w2, #0x1 - cbnz w2, 1b - - /* Initialize SGIs and PPIs */ -2: ldr x1, =GICD_BASE - mov w0, #~0 /* Config SGIs and PPIs as Grp1 */ - str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */ - mov w0, #0x1 /* Enable SGI 0 */ - str w0, [x1, GICD_ISENABLERn] - - /* Initialize Cpu Interface */ - ldr x1, =GICC_BASE - mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */ - /* Enable Ack Group1 Interrupt & */ - /* EnableGrp0 & EnableGrp1 */ - str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */ - - mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */ - str w0, [x1, GICC_PMR] - - ret -ENDPROC(gic_init) - - -/************************************************************************* - * - * void gic_send_sgi(u64 sgi) __attribute__((weak)); - * - *************************************************************************/ -WEAK(gic_send_sgi) - ldr x1, =GICD_BASE - mov w2, #0x8000 - movk w2, #0x100, lsl #16 - orr w2, w2, w0 - str w2, [x1, GICD_SGIR] - ret -ENDPROC(gic_send_sgi) - - -/************************************************************************* - * - * void wait_for_wakeup(void) __attribute__((weak)); - * - * Wait for SGI 0 from master. - * - *************************************************************************/ -WEAK(wait_for_wakeup) - ldr x1, =GICC_BASE -0: wfi - ldr w0, [x1, GICC_AIAR] - str w0, [x1, GICC_AEOIR] - cbnz w0, 0b - ret -ENDPROC(wait_for_wakeup) - - -/************************************************************************* - * - * void smp_kick_all_cpus(void) __attribute__((weak)); - * - *************************************************************************/ -WEAK(smp_kick_all_cpus) - /* Kick secondary cpus up by SGI 0 interrupt */ - mov x0, xzr /* SGI 0 */ - mov x29, lr /* Save LR */ - bl gic_send_sgi - mov lr, x29 /* Restore LR */ - ret -ENDPROC(smp_kick_all_cpus) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index bcc2603098..33d3f3688a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -50,7 +50,10 @@ reset: */ adr x0, vectors switch_el x1, 3f, 2f, 1f -3: msr vbar_el3, x0 +3: mrs x0, scr_el3 + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ + msr scr_el3, x0 + msr vbar_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ ldr x0, =COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ @@ -64,10 +67,12 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - /* Cache/BPB/TLB Invalidate */ - bl __asm_flush_dcache_all /* dCache clean&invalidate */ - bl __asm_invalidate_icache_all /* iCache invalidate */ - bl __asm_invalidate_tlb_all /* invalidate TLBs */ + /* + * Cache/BPB/TLB Invalidate + * i-cache is invalidated before enabled in icache_enable() + * tlb is invalidated before mmu is enabled in dcache_enable() + * d-cache is invalidated before enabled in dcache_enable() + */ /* Processor specific initialization */ bl lowlevel_init @@ -93,63 +98,64 @@ master_cpu: /*-----------------------------------------------------------------------*/ WEAK(lowlevel_init) - /* Initialize GIC Secure Bank Status */ mov x29, lr /* Save LR */ - bl gic_init - branch_if_master x0, x1, 1f +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f /* * Slave should wait for master clearing spin table. * This sync prevent salves observing incorrect * value of spin table and jumping to wrong place. */ - bl wait_for_wakeup +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif /* - * All processors will enter EL2 and optionally EL1. + * All slaves will enter EL2 and optionally EL1. */ bl armv8_switch_to_el2 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 bl armv8_switch_to_el1 #endif -1: +2: mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) +WEAK(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + ldr x0, =GICD_BASE + bl gic_kick_secondary_cpus +#endif + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) + /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) - /* If I-cache is enabled invalidate it */ -#ifndef CONFIG_SYS_ICACHE_OFF - ic iallu /* I+BTB cache invalidate */ - isb sy -#endif - -#ifndef CONFIG_SYS_DCACHE_OFF - /* - * Setup MAIR and TCR. - */ - ldr x0, =MEMORY_ATTRIBUTES - ldr x1, =TCR_FLAGS - - switch_el x2, 3f, 2f, 1f -3: orr x1, x1, TCR_EL3_IPS_BITS - msr mair_el3, x0 - msr tcr_el3, x1 - b 0f -2: orr x1, x1, TCR_EL2_IPS_BITS - msr mair_el2, x0 - msr tcr_el2, x1 - b 0f -1: orr x1, x1, TCR_EL1_IPS_BITS - msr mair_el1, x0 - msr tcr_el1, x1 -0: -#endif - /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c index 3b6c60ca56..2cba7169e4 100644 --- a/arch/arm/cpu/at91-common/phy.c +++ b/arch/arm/cpu/at91-common/phy.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c index 37c0cc4be5..7f4debb912 100644 --- a/arch/arm/cpu/at91-common/spl.c +++ b/arch/arm/cpu/at91-common/spl.c @@ -52,6 +52,10 @@ u32 spl_boot_device(void) { #ifdef CONFIG_SYS_USE_MMC return BOOT_DEVICE_MMC1; +#elif CONFIG_SYS_USE_NANDFLASH + return BOOT_DEVICE_NAND; +#elif CONFIG_SYS_USE_SERIALFLASH + return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_NONE; } diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds index 038335d3da..57ac1eb242 100644 --- a/arch/arm/cpu/at91-common/u-boot-spl.lds +++ b/arch/arm/cpu/at91-common/u-boot-spl.lds @@ -37,7 +37,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram .bss : { diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile deleted file mode 100644 index 4e66523c03..0000000000 --- a/arch/arm/cpu/ixp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o - -obj-y += cpu.o -obj-$(CONFIG_USE_IRQ) += interrupts.o -obj-y += timer.o diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk deleted file mode 100644 index fd47c60939..0000000000 --- a/arch/arm/cpu/ixp/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# SPDX-License-Identifier: GPL-2.0+ -# - -BIG_ENDIAN = y - -PLATFORM_RELFLAGS += -mbig-endian - -PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 - -PLATFORM_LDFLAGS += -EB -USE_PRIVATE_LIBGCC = yes - -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c deleted file mode 100644 index 4387c18d3d..0000000000 --- a/arch/arm/cpu/ixp/cpu.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include -#include - -static void cache_flush(void); - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - unsigned long id; - int speed = 0; - - asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id)); - - puts("CPU: Intel IXP425 at "); - switch ((id & 0x000003f0) >> 4) { - case 0x1c: - speed = 533; - break; - - case 0x1d: - speed = 400; - break; - - case 0x1f: - speed = 266; - break; - } - - if (speed) - printf("%d MHz\n", speed); - else - puts("unknown revision\n"); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - disable_interrupts (); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -/* FIXME */ -/* -void pci_init(void) -{ - return; -} -*/ - -int cpu_eth_init(bd_t *bis) -{ -#ifdef CONFIG_IXP4XX_NPE - npe_initialize(bis); -#endif - return 0; -} diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c deleted file mode 100644 index 7694c6a6cc..0000000000 --- a/arch/arm/cpu/ixp/interrupts.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -static struct _irq_handler IRQ_HANDLER[N_IRQS]; - -static void default_isr(void *data) -{ - printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", - (int)data, *IXP425_ICIP, *IXP425_ICIH); -} - -static int next_irq(void) -{ - return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1); -} - -void do_irq (struct pt_regs *pt_regs) -{ - int irq = next_irq(); - - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); -} - -void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) -{ - if (irq >= N_IRQS || !handle_irq) - return; - - IRQ_HANDLER[irq].m_data = data; - IRQ_HANDLER[irq].m_func = handle_irq; -} - -int arch_interrupt_init (void) -{ - int i; - - /* install default interrupt handlers */ - for (i = 0; i < N_IRQS; i++) - irq_install_handler(i, default_isr, (void *)i); - - /* configure interrupts for IRQ mode */ - *IXP425_ICLR = 0x00000000; - - return (0); -} diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S deleted file mode 100644 index 82c868a174..0000000000 --- a/arch/arm/cpu/ixp/start.S +++ /dev/null @@ -1,430 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * u-boot - Startup Code for XScale IXP - * - * Copyright (C) 2003 Kyle Harris - * - * Based on startup code example contained in the - * Intel IXP4xx Programmer's Guide and past u-boot Start.S - * samples. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MMU_Control_M 0x001 /* Enable MMU */ -#define MMU_Control_A 0x002 /* Enable address alignment faults */ -#define MMU_Control_C 0x004 /* Enable cache */ -#define MMU_Control_W 0x008 /* Enable write-buffer */ -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ -#define MMU_Control_L 0x040 /* Compatability: */ -#define MMU_Control_B 0x080 /* Enable Big-Endian */ -#define MMU_Control_S 0x100 /* Enable system protection */ -#define MMU_Control_R 0x200 /* Enable ROM protection */ -#define MMU_Control_I 0x1000 /* Enable Instruction cache */ -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) - - -/* - * Macro definitions - */ - /* Delay a bit */ - .macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc - .endm - - /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -.globl _start -_start: - ldr pc, _reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_reset: .word reset -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* disable mmu, set big-endian */ - mov r0, #0xf8 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* disable write buffer coalescing */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 1 - CPWAIT r0 - - /* set EXP CS0 to the optimum timing */ - ldr r1, =CONFIG_SYS_EXP_CS0 - ldr r2, =IXP425_EXP_CS0 - str r1, [r2] - - /* make sure flash is visible at 0 */ - mov r1, #CONFIG_SYS_SDR_CONFIG - ldr r2, =IXP425_SDR_CONFIG - str r1, [r2] - - /* disable refresh cycles */ - mov r1, #0 - ldr r3, =IXP425_SDR_REFRESH - str r1, [r3] - - /* send nop command */ - mov r1, #3 - ldr r4, =IXP425_SDR_IR - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* set SDRAM internal refresh val */ - ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT - str r1, [r3] - DELAY_FOR 0x4000, r0 - - /* send precharge-all command to close all open banks */ - mov r1, #2 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* provide 8 auto-refresh cycles */ - mov r1, #4 - mov r5, #8 -111: str r1, [r4] - DELAY_FOR 0x100, r0 - subs r5, r5, #1 - bne 111b - - /* set mode register in sdram */ - mov r1, #CONFIG_SYS_SDR_MODE_CONFIG - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* send normal operation command */ - mov r1, #6 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* remove flash mirror at 0x00000000 */ - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - bic r1, r1, #0x80000000 - str r1, [r2] - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* enable I cache */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #MMU_Control_I - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: Use Watchdog to reset */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - -reset_cpu: - ldr r1, =0x482e - ldr r2, =IXP425_OSWK - str r1, [r2] - ldr r1, =0x0fff - ldr r2, =IXP425_OSWT - str r1, [r2] - ldr r1, =0x5 - ldr r2, =IXP425_OSWE - str r1, [r2] - b reset_endless - -reset_endless: - b reset_endless diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c deleted file mode 100644 index 38e2e2879c..0000000000 --- a/arch/arm/cpu/ixp/timer.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2010 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a - * 33.333MHz crystal). - */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_IXP425_TIMER_CLK); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_IXP425_TIMER_CLK; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_IXP425_TIMER_CLK + 999999; - do_div(us, 1000000); - return us; -} - -unsigned long long get_ticks(void) -{ - ulong now = readl(IXP425_OSTS_B); - - if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) { - /* rollover of timestamp timer register */ - gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1; - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - } else { - /* move stamp forward with absolut diff ticks */ - gd->arch.timestamp += (now - gd->arch.lastinc); - } - gd->arch.lastinc = now; - return gd->arch.timestamp; -} - - -void reset_timer_masked(void) -{ - /* capture current timestamp counter */ - gd->arch.lastinc = readl(IXP425_OSTS_B); - /* start "advancing" time stamp from 0 */ - gd->arch.timestamp = 0; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - - tmp = get_ticks() + us_to_tick(usec); - - while (get_ticks() < tmp) - ; -} - -int timer_init(void) -{ - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - return 0; -} diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds deleted file mode 100644 index 676ae2c4f9..0000000000 --- a/arch/arm/cpu/ixp/u-boot.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index f2befbe515..525f5d33b7 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -7,13 +7,6 @@ # PLATFORM_CPPFLAGS += -mcpu=xscale -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) # # !WARNING! @@ -25,5 +18,5 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) # #ifdef CONFIG_SPL_BUILD -OBJCFLAGS += -j .text.0 -j .text.1 +OBJCOPYFLAGS += -j .text.0 -j .text.1 #endif diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index d8fb812dbf..ae0d13ce8f 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -84,32 +84,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -316,7 +290,6 @@ cpu_init_crit: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ .align 5 diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk index b3026cc50d..3afa685b3f 100644 --- a/arch/arm/cpu/sa1100/config.mk +++ b/arch/arm/cpu/sa1100/config.mk @@ -7,10 +7,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 27bcda598c..bf80937a7c 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -56,32 +56,6 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 4b981e46e7..0a0006b426 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -13,11 +13,6 @@ #include #include -int timer_init (void) -{ - return 0; -} - ulong get_timer (ulong base) { return get_timer_masked (); diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index edfc1a83a9..34d57349af 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -8,4 +8,5 @@ # obj-y += lowlevel_init.o -obj-y += ap.o board.o sys_info.o clock.o cache.o +obj-y += ap.o board.o clock.o cache.o +obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 60d71a6c30..91d70da656 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -1,5 +1,5 @@ /* -* (C) Copyright 2010-2011 +* (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -27,7 +27,7 @@ int tegra_get_chip(void) /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, and 0x35 for T114. + * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; debug("%s: CHIPID is 0x%02X\n", __func__, rev); @@ -72,6 +72,7 @@ int tegra_get_chip_sku(void) case SKU_ID_T33: case SKU_ID_T30: case SKU_ID_TM30MQS_P_A3: + default: return TEGRA_SOC_T30; } break; @@ -79,10 +80,19 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T114_ENG: case SKU_ID_T114_1: + default: return TEGRA_SOC_T114; } break; + case CHIPID_TEGRA124: + switch (sku_id) { + case SKU_ID_T124_ENG: + default: + return TEGRA_SOC_T124; + } + break; } + /* unknown chip/sku id */ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", __func__, chip_id, sku_id); @@ -117,8 +127,8 @@ static u32 get_odmdata(void) * ODMDATA is stored in the BCT in IRAM by the BootROM. * The BCT start and size are stored in the BIT in IRAM. * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. + * on BCTs for currently supported SoCs, which are locked down. + * If this changes in new chips, we can revisit this algorithm. */ u32 bct_start, odmdata; diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index d9cbda8a74..6a6faf4b27 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -109,12 +109,18 @@ static int uart_configs[] = { -1, -1, -1, -#else /* Tegra114 */ +#elif defined(CONFIG_TEGRA114) -1, -1, -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, +#else /* Tegra124 */ + FUNCMUX_UART1_KBC, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_GPIO, /* UARTD */ + -1, #endif }; diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c index 48e9319c75..94f5bce90e 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/cpu/tegra-common/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,6 @@ void config_cache(void) { - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; u32 reg = 0; /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ @@ -33,10 +31,10 @@ void config_cache(void) "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n"); - /* Currently, only T114 needs this L2 cache change to boot Linux */ - reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); - if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ + if (tegra_get_chip() < CHIPID_TEGRA114) return; + /* * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb912b5..11c7435505 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, value = readl(reg); - value &= ~OUT_CLK_SOURCE_MASK; - value |= source << OUT_CLK_SOURCE_SHIFT; + value &= ~OUT_CLK_SOURCE_31_30_MASK; + value |= source << OUT_CLK_SOURCE_31_30_SHIFT; value &= ~OUT_CLK_DIVISOR_MASK; value |= divisor << OUT_CLK_DIVISOR_SHIFT; @@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) { u32 *reg = get_periph_source_reg(periph_id); - clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); } /** @@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); - } else { - clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + + switch (mux_bits) { + case MASK_BITS_31_30: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, + source << OUT_CLK_SOURCE_31_29_SHIFT); + break; + + case MASK_BITS_31_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); + break; + + default: + return -1; } + udelay(2); return 0; } @@ -561,3 +575,95 @@ void clock_init(void) /* Do any special system timer/TSC setup */ arch_timer_init(); } + +static void set_avp_clock_source(u32 src) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clkrst->crc_sclk_brst_pol); + udelay(3); +} + +/* + * This function is useful on Tegra30, and any later SoCs that have compatible + * PLLP configuration registers. + */ +void tegra30_set_up_pllp(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* + * Based on the Tegra TRM, the system clock (which is the AVP clock) can + * run up to 275MHz. On power on, the default sytem clock source is set + * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to + * 408MHz which is beyond system clock's upper limit. + * + * The fix is to set the system clock to CLK_M before initializing PLLP, + * and then switch back to PLLP_OUT4, which has an appropriate divider + * configured, after PLLP has been configured + */ + set_avp_clock_source(SCLK_SOURCE_CLKM); + + /* + * PLLP output frequency set to 408Mhz + * PLLC output frequency set to 228Mhz + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); + break; + + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + break; + + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + break; + case CLOCK_OSC_FREQ_19_2: + default: + /* + * These are not supported. It is too early to print a + * message and the UART likely won't work anyway due to the + * oscillator being wrong. + */ + break; + } + + /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ + + /* OUT1, 2 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) + | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS + | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) + | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + + /* OUT3, 4 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); +} diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c index dc8a2e4d31..de20325ecf 100644 --- a/arch/arm/cpu/tegra-common/sys_info.c +++ b/arch/arm/cpu/tegra-common/sys_info.c @@ -8,7 +8,6 @@ #include #include -#ifdef CONFIG_DISPLAY_CPUINFO void upstring(char *s) { while (*s) { @@ -30,4 +29,3 @@ int print_cpuinfo(void) /* TBD: Add printf of major/minor rev info, stepping, etc. */ return 0; } -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 5c4305a418..d5194e11b5 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -61,12 +61,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -109,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_31_28} }; /* @@ -610,26 +604,24 @@ void clock_early_init(void) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + tegra30_set_up_pllp(); + /* - * PLLP output frequency set to 408Mhz * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz */ switch (clock_get_osc_freq()) { case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); break; case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); break; case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); break; diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile new file mode 100644 index 0000000000..ff77992b33 --- /dev/null +++ b/arch/arm/cpu/tegra124-common/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clock.o +obj-y += funcmux.o +obj-y += pinmux.o diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c new file mode 100644 index 0000000000..739436326e --- /dev/null +++ b/arch/arm/cpu/tegra124-common/clock.c @@ -0,0 +1,826 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 Clock control functions */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Clock types that we can use as a source. The Tegra124 has muxes for the + * peripheral clocks, and in most cases there are four options for the clock + * source. This gives us a clock 'type' and exploits what commonality exists + * in the device. + * + * Letters are obvious, except for T which means CLK_M, and S which means the + * clock derived from 32KHz. Beware that CLK_M (also called OSC in the + * datasheet) and PLL_M are different things. The former is the basic + * clock supplied to the SOC from an external oscillator. The latter is the + * memory clock PLL. + * + * See definitions in clock_id in the header file. + */ +enum clock_type_id { + CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ + CLOCK_TYPE_MCPA, /* and so on */ + CLOCK_TYPE_MCPT, + CLOCK_TYPE_PCM, + CLOCK_TYPE_PCMT, + CLOCK_TYPE_PDCT, + CLOCK_TYPE_ACPT, + CLOCK_TYPE_ASPTE, + CLOCK_TYPE_PMDACD2T, + CLOCK_TYPE_PCST, + + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + + CLOCK_TYPE_COUNT, + CLOCK_TYPE_NONE = -1, /* invalid clock type */ +}; + +enum { + CLOCK_MAX_MUX = 8 /* number of source options for each clock */ +}; + +/* + * Clock source mux for each clock type. This just converts our enum into + * a list of mux sources for use by the code. + * + * Note: + * The extra column in each clock source array is used to store the mask + * bits in its register for the source. + */ +#define CLK(x) CLOCK_ID_ ## x +static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { + { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), + CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), + CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_28}, + + /* Additional clock types on Tegra114+ */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, +}; + +/* + * Clock type for each peripheral clock source. We put the name in each + * record just so it is easy to match things up + */ +#define TYPE(name, type) type +static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { + /* 0x00 */ + TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x08 */ + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), + + /* 0x10 */ + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), + + /* 0x18 */ + TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), + + /* 0x20 */ + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), + + /* 0x28 */ + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x30 */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), + TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), + + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), + + /* 0x50 */ + TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), + + /* 0x60 */ + TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), + + /* 0x68 */ + TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE), + TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE), + + /* 0x70 */ + TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), + TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), + + /* 0x78 */ + TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), + TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), +}; + +/* + * This array translates a periph_id to a periphc_internal_id + * + * Not present/matched up: + * uint vi_sensor; _VI_SENSOR_0, 0x1A8 + * SPDIF - which is both 0x08 and 0x0c + * + */ +#define NONE(name) (-1) +#define OFFSET(name, value) PERIPHC_ ## name +static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { + /* Low word: 31:0 */ + NONE(CPU), + NONE(COP), + NONE(TRIGSYS), + NONE(ISPB), + NONE(RESERVED4), + NONE(TMR), + PERIPHC_UART1, + PERIPHC_UART2, /* and vfir 0x68 */ + + /* 8 */ + NONE(GPIO), + PERIPHC_SDMMC2, + PERIPHC_SPDIF_IN, + PERIPHC_I2S1, + PERIPHC_I2C1, + NONE(RESERVED13), + PERIPHC_SDMMC1, + PERIPHC_SDMMC4, + + /* 16 */ + NONE(TCW), + PERIPHC_PWM, + PERIPHC_I2S2, + NONE(RESERVED19), + PERIPHC_VI, + NONE(RESERVED21), + NONE(USBD), + NONE(ISP), + + /* 24 */ + NONE(RESERVED24), + NONE(RESERVED25), + PERIPHC_DISP2, + PERIPHC_DISP1, + PERIPHC_HOST1X, + NONE(VCP), + PERIPHC_I2S0, + NONE(CACHE2), + + /* Middle word: 63:32 */ + NONE(MEM), + NONE(AHBDMA), + NONE(APBDMA), + NONE(RESERVED35), + NONE(RESERVED36), + NONE(STAT_MON), + NONE(RESERVED38), + NONE(FUSE), + + /* 40 */ + NONE(KFUSE), + PERIPHC_SBC1, /* SBCx = SPIx */ + PERIPHC_NOR, + NONE(RESERVED43), + PERIPHC_SBC2, + NONE(XIO), + PERIPHC_SBC3, + PERIPHC_I2C5, + + /* 48 */ + NONE(DSI), + NONE(RESERVED49), + PERIPHC_HSI, + PERIPHC_HDMI, + NONE(CSI), + NONE(RESERVED53), + PERIPHC_I2C2, + PERIPHC_UART3, + + /* 56 */ + NONE(MIPI_CAL), + PERIPHC_EMC, + NONE(USB2), + NONE(USB3), + NONE(RESERVED60), + PERIPHC_VDE, + NONE(BSEA), + NONE(BSEV), + + /* Upper word 95:64 */ + NONE(RESERVED64), + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_I2C3, + PERIPHC_SBC4, + PERIPHC_SDMMC3, + NONE(PCIE), + PERIPHC_OWR, + + /* 72 */ + NONE(AFI), + PERIPHC_CSITE, + NONE(PCIEXCLK), + NONE(AVPUCQ), + NONE(LA), + NONE(TRACECLKIN), + NONE(SOC_THERM), + NONE(DTV), + + /* 80 */ + NONE(RESERVED80), + PERIPHC_I2CSLOW, + NONE(DSIB), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), + + /* 88 */ + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), + NONE(RESERVED93), + NONE(RESERVED94), + NONE(XUSB_DEV), + + /* V word: 31:0 */ + NONE(CPUG), + NONE(CPULP), + NONE(V_RESERVED2), + PERIPHC_MSELECT, + NONE(V_RESERVED4), + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + + /* 104 */ + PERIPHC_SBC5, + PERIPHC_SBC6, + PERIPHC_AUDIO, + NONE(APBIF), + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + + /* 112 */ + NONE(ATOMICS), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), + PERIPHC_ACTMON, + + /* 120 */ + NONE(EXTPERIPH1), + NONE(EXTPERIPH2), + NONE(EXTPERIPH3), + NONE(OOB), + PERIPHC_SATA, + PERIPHC_HDA, + NONE(TZRAM), + NONE(SE), + + /* W word: 31:0 */ + NONE(HDA2HDMICODEC), + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ + NONE(CEC), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(DDS), + NONE(W_RESERVED23), + + /* 152 */ + NONE(DP2), + NONE(AMX0), + NONE(ADX0), + NONE(DVFS), + NONE(XUSB_SS), + NONE(W_RESERVED29), + NONE(W_RESERVED30), + NONE(W_RESERVED31), + + /* X word: 31:0 */ + NONE(SPARE), + NONE(X_RESERVED1), + NONE(X_RESERVED2), + NONE(X_RESERVED3), + NONE(CAM_MCLK), + NONE(CAM_MCLK2), + PERIPHC_I2C6, + NONE(X_RESERVED7), + + /* 168 */ + NONE(X_RESERVED8), + NONE(X_RESERVED9), + NONE(X_RESERVED10), + NONE(VIM2_CLK), + NONE(X_RESERVED12), + NONE(X_RESERVED13), + NONE(EMC_DLL), + NONE(X_RESERVED15), + + /* 176 */ + NONE(HDMI_AUDIO), + NONE(CLK72MHZ), + NONE(VIC), + NONE(X_RESERVED19), + NONE(ADX1), + NONE(DPAUX), + NONE(SOR0), + NONE(X_RESERVED23), + + /* 184 */ + NONE(GPU), + NONE(AMX1), + NONE(X_RESERVED26), + NONE(X_RESERVED27), + NONE(X_RESERVED28), + NONE(X_RESERVED29), + NONE(X_RESERVED30), + NONE(X_RESERVED31), +}; + +/* + * Get the oscillator frequency, from the corresponding hardware configuration + * field. Note that Tegra30+ support 3 new higher freqs, but we map back + * to the old T20 freqs. Support for the higher oscillators is TBD. + */ +enum clock_osc_freq clock_get_osc_freq(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + reg = readl(&clkrst->crc_osc_ctrl); + reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + + if (reg & 1) /* one of the newer freqs */ + printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg); + + return reg >> 2; /* Map to most common (T20) freqs */ +} + +/* Returns a pointer to the clock source register for a peripheral */ +u32 *get_periph_source_reg(enum periph_id periph_id) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + enum periphc_internal_id internal_id; + + /* Coresight is a special case */ + if (periph_id == PERIPH_ID_CSI) + return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; + + assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); + internal_id = periph_id_to_internal_id[periph_id]; + assert(internal_id != -1); + if (internal_id >= PERIPHC_VW_FIRST) { + internal_id -= PERIPHC_VW_FIRST; + return &clkrst->crc_clk_src_vw[internal_id]; + } else { + return &clkrst->crc_clk_src[internal_id]; + } +} + +/** + * Given a peripheral ID and the required source clock, this returns which + * value should be programmed into the source mux for that peripheral. + * + * There is special code here to handle the one source type with 5 sources. + * + * @param periph_id peripheral to start + * @param source PLL id of required parent clock + * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) + * @return mux value (0-4, or -1 if not found) + */ +int get_periph_clock_source(enum periph_id periph_id, + enum clock_id parent, int *mux_bits, int *divider_bits) +{ + enum clock_type_id type; + enum periphc_internal_id internal_id; + int mux; + + assert(clock_periph_id_isvalid(periph_id)); + + internal_id = periph_id_to_internal_id[periph_id]; + assert(periphc_internal_id_isvalid(internal_id)); + + type = clock_periph_type[internal_id]; + assert(clock_type_id_isvalid(type)); + + *mux_bits = clock_source[type][CLOCK_MAX_MUX]; + + if (type == CLOCK_TYPE_PC2CC3M_T16) + *divider_bits = 16; + else + *divider_bits = 8; + + for (mux = 0; mux < CLOCK_MAX_MUX; mux++) + if (clock_source[type][mux] == parent) + return mux; + + /* if we get here, either us or the caller has made a mistake */ + printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, + parent); + return -1; +} + +void clock_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *clk; + u32 reg; + + /* Enable/disable the clock to this peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) + clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; + else + clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; + reg = readl(clk); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, clk); +} + +void reset_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *reset; + u32 reg; + + /* Enable/disable reset to the peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if (periph_id < PERIPH_ID_VW_FIRST) + reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; + else + reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; + reg = readl(reset); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, reset); +} + +#ifdef CONFIG_OF_CONTROL +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra124 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > PERIPH_ID_COUNT) + return PERIPH_ID_NONE; + + switch (clk_id) { + case PERIPH_ID_RESERVED4: + case PERIPH_ID_RESERVED25: + case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED43: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: + case PERIPH_ID_RESERVED93: + case PERIPH_ID_RESERVED94: + case PERIPH_ID_V_RESERVED2: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED29: + case PERIPH_ID_W_RESERVED30: + case PERIPH_ID_W_RESERVED31: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} +#endif /* CONFIG_OF_CONTROL */ + +void clock_early_init(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + tegra30_set_up_pllp(); + + /* + * PLLC output frequency set to 600Mhz + * PLLD output frequency set to 925Mhz + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); + break; + + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); + break; + + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); + break; + case CLOCK_OSC_FREQ_19_2: + default: + /* + * These are not supported. It is too early to print a + * message and the UART likely won't work anyway due to the + * oscillator being wrong. + */ + break; + } + + /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */ + writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); + + /* PLLC_MISC: Set LOCK_ENABLE */ + writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc); + udelay(2); + + /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ + writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); + udelay(2); +} + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + + /* Only Tegra114+ has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c new file mode 100644 index 0000000000..d19fda06c5 --- /dev/null +++ b/arch/arm/cpu/tegra124-common/funcmux.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 high-level function multiplexing */ + +#include +#include +#include +#include + +int funcmux_select(enum periph_id id, int config) +{ + int bad_config = config != FUNCMUX_DEFAULT; + + switch (id) { + case PERIPH_ID_UART4: + switch (config) { + case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ + pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD); + pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD); + pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD); + pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD); + + pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PINGRP_GPIO_PJ7); + pinmux_tristate_disable(PINGRP_GPIO_PB0); + pinmux_tristate_disable(PINGRP_GPIO_PB1); + pinmux_tristate_disable(PINGRP_GPIO_PK7); + break; + } + break; + + case PERIPH_ID_UART1: + switch (config) { + case FUNCMUX_UART1_KBC: + pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA); + + pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT); + pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT); + + pinmux_tristate_disable(PINGRP_KB_ROW9); + pinmux_tristate_disable(PINGRP_KB_ROW10); + break; + } + break; + + /* Add other periph IDs here as needed */ + + default: + debug("%s: invalid periph_id %d", __func__, id); + return -1; + } + + if (bad_config) { + debug("%s: invalid config %d for periph_id %d", __func__, + config, id); + return -1; + } + return 0; +} diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c new file mode 100644 index 0000000000..a4ab4eae40 --- /dev/null +++ b/arch/arm/cpu/tegra124-common/pinmux.c @@ -0,0 +1,730 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 pin multiplexing functions */ + +#include +#include +#include +#include + +struct tegra_pingroup_desc { + const char *name; + enum pmux_func funcs[4]; + enum pmux_func func_safe; + enum pmux_vddio vddio; + enum pmux_pin_io io; +}; + +#define PMUX_MUXCTL_SHIFT 0 +#define PMUX_PULL_SHIFT 2 +#define PMUX_TRISTATE_SHIFT 4 +#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT) +#define PMUX_IO_SHIFT 5 +#define PMUX_OD_SHIFT 6 +#define PMUX_LOCK_SHIFT 7 +#define PMUX_IO_RESET_SHIFT 8 +#define PMUX_RCV_SEL_SHIFT 9 + +#define PGRP_HSM_SHIFT 2 +#define PGRP_SCHMT_SHIFT 3 +#define PGRP_LPMD_SHIFT 4 +#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) +#define PGRP_DRVDN_SHIFT 12 +#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) +#define PGRP_DRVUP_SHIFT 20 +#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) +#define PGRP_SLWR_SHIFT 28 +#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) +#define PGRP_SLWF_SHIFT 30 +#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) + +/* Convenient macro for defining pin group properties */ +#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ + { \ + .vddio = PMUX_VDDIO_ ## vdd, \ + .funcs = { \ + PMUX_FUNC_ ## f0, \ + PMUX_FUNC_ ## f1, \ + PMUX_FUNC_ ## f2, \ + PMUX_FUNC_ ## f3, \ + }, \ + .func_safe = PMUX_FUNC_RSVD1, \ + .io = PMUX_PIN_ ## iod, \ + } + +/* Input and output pins */ +#define PINI(pg_name, vdd, f0, f1, f2, f3) \ + PIN(pg_name, vdd, f0, f1, f2, f3, INPUT) +#define PINO(pg_name, vdd, f0, f1, f2, f3) \ + PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT) + +/* A pin group number which is not used */ +#define PIN_RESERVED \ + PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE) + +const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { + /* NAME VDD f0 f1 f2 f3 */ + PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI), + PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI), + PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI), + PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI), + PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB), + PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB), + PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB), + PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB), + PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4), + PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4), + PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4), + PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA), + PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA), + PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA), + PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA), + PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA), + PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */ + PIN_RESERVED, + PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4), + PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4), + PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4), + PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4), + PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4), + PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4), + PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4), + PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4), + PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4), + PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4), + PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA), + PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4), + PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4), + PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4), + PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB), + PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB), + PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB), + PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB), + PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4), + PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4), + PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4), + PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4), + PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4), + PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4), + PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4), + PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4), + PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT), + PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE), + PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV), + PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE), + PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE), + PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB), + PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC), + PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE), + PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT), + PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE), + PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4), + PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2), + PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4), + PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4), + PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4), + PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4), + PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4), + PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4), + PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4), + PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4), + PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV), + PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS), + PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS), + PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB), + PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4), + PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4), + PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV), + PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV), + PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT), + PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE), + PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE), + PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE), + PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4), + PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC), + PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE), + PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4), + PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4), + PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4), + PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), + PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), + PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), + PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), + PIN_RESERVED, /* Reserved: 0x3280 */ + PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4), + PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4), + PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3), + PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4), + PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4), + PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4), + PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4), + PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4), + PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4), + PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4), + PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4), + PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4), + PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), + PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), + PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4), + PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4), + PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC), + PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB), + PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB), + PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB), + PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB), + PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA), + PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA), + PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA), + PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA), + PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL), + PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL), + PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4), + PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA), + PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA), + PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4), + PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4), + PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4), + PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4), + PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4), + PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4), + PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4), + PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4), + PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4), + PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4), + PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4), + PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4), + PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4), + PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4), + PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4), + PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4), + PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4), + PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4), + PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4), + PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4), + PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4), + PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4), + PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), + PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4), + PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4), + PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), + PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2), + PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), + PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4), + PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), + PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */ + PIN_RESERVED, + PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), + PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3), + PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), + PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3), + PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3), + PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3), + PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC), + PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA), + PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4), + PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1), + PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1), + PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4), + PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4), + PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), + PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved: 0x3404 */ + PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N), +}; + +void pinmux_set_tristate(enum pmux_pingrp pin, int enable) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *tri = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin */ + assert(pmux_pingrp_isvalid(pin)); + + reg = readl(tri); + if (enable) + reg |= PMUX_TRISTATE_MASK; + else + reg &= ~PMUX_TRISTATE_MASK; + writel(reg, tri); +} + +void pinmux_tristate_enable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, 1); +} + +void pinmux_tristate_disable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, 0); +} + +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pull = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and pupd */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_pupd_isvalid(pupd)); + + reg = readl(pull); + reg &= ~(0x3 << PMUX_PULL_SHIFT); + reg |= (pupd << PMUX_PULL_SHIFT); + writel(reg, pull); +} + +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *muxctl = &pmt->pmt_ctl[pin]; + int i, mux = -1; + u32 reg; + + /* Error check on pin and func */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_func_isvalid(func)); + + /* Handle special values */ + if (func == PMUX_FUNC_SAFE) + func = tegra_soc_pingroups[pin].func_safe; + + if (func & PMUX_FUNC_RSVD1) { + mux = func & 0x3; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 4; i++) { + if (tegra_soc_pingroups[pin].funcs[i] == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + reg = readl(muxctl); + reg &= ~(0x3 << PMUX_MUXCTL_SHIFT); + reg |= (mux << PMUX_MUXCTL_SHIFT); + writel(reg, muxctl); +} + +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_io = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and io */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_io_isvalid(io)); + + reg = readl(pin_io); + reg &= ~(0x1 << PMUX_IO_SHIFT); + reg |= (io & 0x1) << PMUX_IO_SHIFT; + writel(reg, pin_io); +} + +static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_lock = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and lock */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_lock_isvalid(lock)); + + if (lock == PMUX_PIN_LOCK_DEFAULT) + return 0; + + reg = readl(pin_lock); + reg &= ~(0x1 << PMUX_LOCK_SHIFT); + if (lock == PMUX_PIN_LOCK_ENABLE) { + reg |= (0x1 << PMUX_LOCK_SHIFT); + } else { + /* lock == DISABLE, which isn't possible */ + printf("%s: Warning: lock == %d, DISABLE is not allowed!\n", + __func__, lock); + } + writel(reg, pin_lock); + + return 0; +} + +static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_od = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and od */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_od_isvalid(od)); + + if (od == PMUX_PIN_OD_DEFAULT) + return 0; + + reg = readl(pin_od); + reg &= ~(0x1 << PMUX_OD_SHIFT); + if (od == PMUX_PIN_OD_ENABLE) + reg |= (0x1 << PMUX_OD_SHIFT); + writel(reg, pin_od); + + return 0; +} + +static int pinmux_set_ioreset(enum pmux_pingrp pin, + enum pmux_pin_ioreset ioreset) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_ioreset = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and ioreset */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_ioreset_isvalid(ioreset)); + + if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) + return 0; + + reg = readl(pin_ioreset); + reg &= ~(0x1 << PMUX_IO_RESET_SHIFT); + if (ioreset == PMUX_PIN_IO_RESET_ENABLE) + reg |= (0x1 << PMUX_IO_RESET_SHIFT); + writel(reg, pin_ioreset); + + return 0; +} + +static int pinmux_set_rcv_sel(enum pmux_pingrp pin, + enum pmux_pin_rcv_sel rcv_sel) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_rcv_sel = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and rcv_sel */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_rcv_sel_isvalid(rcv_sel)); + + if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT) + return 0; + + reg = readl(pin_rcv_sel); + reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT); + if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH) + reg |= (0x1 << PMUX_RCV_SEL_SHIFT); + writel(reg, pin_rcv_sel); + + return 0; +} + +void pinmux_config_pingroup(struct pingroup_config *config) +{ + enum pmux_pingrp pin = config->pingroup; + + pinmux_set_func(pin, config->func); + pinmux_set_pullupdown(pin, config->pull); + pinmux_set_tristate(pin, config->tristate); + pinmux_set_io(pin, config->io); + pinmux_set_lock(pin, config->lock); + pinmux_set_od(pin, config->od); + pinmux_set_ioreset(pin, config->ioreset); + pinmux_set_rcv_sel(pin, config->rcv_sel); +} + +void pinmux_config_table(struct pingroup_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_pingroup(&config[i]); +} + +static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwf = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwf */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwf)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwf == PGRP_SLWF_NONE) + return 0; + + reg = readl(pad_slwf); + reg &= ~PGRP_SLWF_MASK; + reg |= (slwf << PGRP_SLWF_SHIFT); + writel(reg, pad_slwf); + + return 0; +} + +static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwr = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwr */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwr)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwr == PGRP_SLWR_NONE) + return 0; + + reg = readl(pad_slwr); + reg &= ~PGRP_SLWR_MASK; + reg |= (slwr << PGRP_SLWR_SHIFT); + writel(reg, pad_slwr); + + return 0; +} + +static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvup = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvup */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvup)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvup == PGRP_DRVUP_NONE) + return 0; + + reg = readl(pad_drvup); + reg &= ~PGRP_DRVUP_MASK; + reg |= (drvup << PGRP_DRVUP_SHIFT); + writel(reg, pad_drvup); + + return 0; +} + +static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvdn = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvdn */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvdn)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvdn == PGRP_DRVDN_NONE) + return 0; + + reg = readl(pad_drvdn); + reg &= ~PGRP_DRVDN_MASK; + reg |= (drvdn << PGRP_DRVDN_SHIFT); + writel(reg, pad_drvdn); + + return 0; +} + +static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_lpmd = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad and lpmd value */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_lpmd_isvalid(lpmd)); + + /* NONE means unspecified/do not change/use POR value */ + if (lpmd == PGRP_LPMD_NONE) + return 0; + + reg = readl(pad_lpmd); + reg &= ~PGRP_LPMD_MASK; + reg |= (lpmd << PGRP_LPMD_SHIFT); + writel(reg, pad_lpmd); + + return 0; +} + +static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_schmt = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + /* NONE means unspecified/do not change/use POR value */ + if (schmt == PGRP_SCHMT_NONE) + return 0; + + reg = readl(pad_schmt); + reg &= ~(1 << PGRP_SCHMT_SHIFT); + if (schmt == PGRP_SCHMT_ENABLE) + reg |= (0x1 << PGRP_SCHMT_SHIFT); + writel(reg, pad_schmt); + + return 0; +} +static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_hsm = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + /* NONE means unspecified/do not change/use POR value */ + if (hsm == PGRP_HSM_NONE) + return 0; + + reg = readl(pad_hsm); + reg &= ~(1 << PGRP_HSM_SHIFT); + if (hsm == PGRP_HSM_ENABLE) + reg |= (0x1 << PGRP_HSM_SHIFT); + writel(reg, pad_hsm); + + return 0; +} + +void padctrl_config_pingroup(struct padctrl_config *config) +{ + enum pdrive_pingrp pad = config->padgrp; + + padgrp_set_drvup_slwf(pad, config->slwf); + padgrp_set_drvdn_slwr(pad, config->slwr); + padgrp_set_drvup(pad, config->drvup); + padgrp_set_drvdn(pad, config->drvdn); + padgrp_set_lpmd(pad, config->lpmd); + padgrp_set_schmt(pad, config->schmt); + padgrp_set_hsm(pad, config->hsm); +} + +void padgrp_config_table(struct padctrl_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + padctrl_config_pingroup(&config[i]); +} diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 32ddbdae45..0e4b3fc1dd 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -9,7 +9,7 @@ # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t +CFLAGS_warmboot_avp.o += -march=armv4t obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index 34124f9bba..0c4f5fb288 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -412,9 +412,9 @@ int get_periph_clock_source(enum periph_id periph_id, * with its 16-bit divisor */ if (type == CLOCK_TYPE_PCXTS) - *mux_bits = 4; + *mux_bits = MASK_BITS_31_28; else - *mux_bits = 2; + *mux_bits = MASK_BITS_31_30; if (type == CLOCK_TYPE_PCMT16) *divider_bits = 16; else diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 74bd22be1a..80ba2d8c1c 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -60,12 +60,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -108,7 +102,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_31_28} }; /* @@ -587,34 +581,7 @@ enum periph_id clk_id_to_periph_id(int clk_id) void clock_early_init(void) { - /* - * PLLP output frequency set to 408Mhz - * PLLC output frequency set to 228Mhz - */ - switch (clock_get_osc_freq()) { - case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); - break; - - case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); - break; - - case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); - break; - case CLOCK_OSC_FREQ_19_2: - default: - /* - * These are not supported. It is too early to print a - * message and the UART likely won't work anyway due to the - * oscillator being wrong. - */ - break; - } + tegra30_set_up_pllp(); } void arch_timer_init(void) diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 4880d0f78a..3e886680e8 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -42,7 +42,12 @@ SECTIONS __rel_dyn_end = .; } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -51,7 +56,7 @@ SECTIONS __bss_end = .; } - .dynsym _end : { *(.dynsym) } + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 4da5d246e0..33c1f99fc0 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -60,7 +60,12 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Deprecated: this MMU section is used by pxa at present but @@ -91,12 +96,13 @@ SECTIONS KEEP(*(.__bss_end)); } - .dynsym _end : { *(.dynsym) } + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } .plt : { *(.plt*) } .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } .gnu : { *(.gnu*) } .ARM.exidx : { *(.ARM.exidx*) } .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/arm/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile new file mode 100644 index 0000000000..2c3c773306 --- /dev/null +++ b/arch/arm/dts/Makefile @@ -0,0 +1,42 @@ +dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-universal_c210.dtb \ + exynos4210-trats.dtb \ + exynos4412-trats2.dtb + +dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ + exynos5250-snow.dtb \ + exynos5250-smdk5250.dtb \ + exynos5420-smdk5420.dtb +dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb +dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb \ + tegra20-whistler.dtb \ + tegra20-colibri_t20_iris.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu.dtb \ + tegra30-tec-ng.dtb \ + tegra114-dalmore.dtb \ + tegra124-venice2.dtb +dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zed.dtb \ + zynq-microzed.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi new file mode 100644 index 0000000000..71dc7ebf4a --- /dev/null +++ b/arch/arm/dts/exynos4.dtsi @@ -0,0 +1,138 @@ +/* + * Samsung's Exynos4 SoC common device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x3c>; + id = <0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x3c>; + id = <1>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x3c>; + id = <2>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x3c>; + id = <3>; + }; + + serial@13840000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13840000 0x3c>; + id = <4>; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <0 0 0>; + }; + + i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <1 1 0>; + }; + + i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <2 2 0>; + }; + + i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <3 3 0>; + }; + + i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <4 4 0>; + }; + + i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <5 5 0>; + }; + + i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <6 6 0>; + }; + + i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <7 7 0>; + }; + + sdhci@12510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12510000 0x1000>; + interrupts = <0 75 0>; + }; + + sdhci@12520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12520000 0x1000>; + interrupts = <0 76 0>; + }; + + sdhci@12530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12530000 0x1000>; + interrupts = <0 77 0>; + }; + + sdhci@12540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12540000 0x1000>; + interrupts = <0 78 0>; + }; + + gpio: gpio { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts new file mode 100644 index 0000000000..5c9d2aed68 --- /dev/null +++ b/arch/arm/dts/exynos4210-origen.dts @@ -0,0 +1,45 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "exynos4.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + chosen { + bootargs =""; + }; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts new file mode 100644 index 0000000000..992e0234c9 --- /dev/null +++ b/arch/arm/dts/exynos4210-trats.dts @@ -0,0 +1,120 @@ +/* + * Samsung's Exynos4210 based Trats board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Trats based on Exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20c6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts new file mode 100644 index 0000000000..1cdd981d6d --- /dev/null +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -0,0 +1,83 @@ +/* + * Samsung's Exynos4210 based Universal C210 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Universal C210 based on Exynos4210 rev0"; + compatible = "samsung,universal_c210", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20c6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <480>; + samsung,vl-row = <800>; + samsung,vl-width = <480>; + samsung,vl-height = <800>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <2>; + samsung,vl-hbpd = <16>; + samsung,vl-hfpd = <16>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <8>; + samsung,vl-vfpd = <8>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,pclk_name = <1>; + samsung,sclk_div = <1>; + + samsung,winid = <0>; + samsung,power-on-delay = <10000>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <0>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; +}; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts new file mode 100644 index 0000000000..7d32067fdd --- /dev/null +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -0,0 +1,434 @@ +/* + * Samsung's Exynos4412 based Trats2 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Trats2 based on Exynos4412"; + compatible = "samsung,trats2", "samsung,exynos4412"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + i2c@138d0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686_pmic"; + interrupts = <7 0>; + reg = <0x09 0 0>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-off; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-mem-idle; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-idle; + }; + + buck1_reg: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck2_reg: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-mem-off; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-mem-off; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-mem-off; + }; + }; + }; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <0>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2004002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20C6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; diff --git a/board/samsung/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts similarity index 100% rename from board/samsung/dts/exynos5250-arndale.dts rename to arch/arm/dts/exynos5250-arndale.dts diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts similarity index 98% rename from board/samsung/dts/exynos5250-smdk5250.dts rename to arch/arm/dts/exynos5250-smdk5250.dts index c4ed3467cb..9020382d97 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -146,6 +146,6 @@ }; ehci@12110000 { - samsung,vbus-gpio = <&gpio 0xbe 0>; /* X26 */ + samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */ }; }; diff --git a/board/samsung/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts similarity index 97% rename from board/samsung/dts/exynos5250-snow.dts rename to arch/arm/dts/exynos5250-snow.dts index 091cdb9e86..9b48a0ccd8 100644 --- a/board/samsung/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -110,11 +110,11 @@ }; ehci@12110000 { - samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */ + samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */ }; xhci@12000000 { - samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */ + samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */ }; tmu@10060000 { diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts similarity index 100% rename from board/samsung/dts/exynos5420-smdk5420.dts rename to arch/arm/dts/exynos5420-smdk5420.dts diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts new file mode 100644 index 0000000000..a3c9c91f32 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -0,0 +1,13 @@ +/* + + * Copyright 2012 Freescale Semiconductor, Inc. + + * Copyright 2011 Linaro Ltd. + + * + + * SPDX-License-Identifier: GPL-2.0+ + + */ + +/dts-v1/; + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +}; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts similarity index 100% rename from board/nvidia/dts/tegra114-dalmore.dts rename to arch/arm/dts/tegra114-dalmore.dts diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 626cc3c982..f52fcf14dd 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -139,7 +139,7 @@ spi@7000d800 { compatible = "nvidia,tegra114-spi"; - reg = <0x7000d480 0x200>; + reg = <0x7000d800 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts new file mode 100644 index 0000000000..2f8d1dcc37 --- /dev/null +++ b/arch/arm/dts/tegra124-venice2.dts @@ -0,0 +1,84 @@ +/dts-v1/; + +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Venice2"; + compatible = "nvidia,venice2", "nvidia,tegra124"; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d100 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@700b0400 { + status = "okay"; + cd-gpios = <&gpio 170 0>; /* gpio PV2 */ + power-gpios = <&gpio 136 0>; /* gpio PR0 */ + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */ + }; +}; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi new file mode 100644 index 0000000000..18a8b24b71 --- /dev/null +++ b/arch/arm/dts/tegra124.dtsi @@ -0,0 +1,250 @@ +#include "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra124"; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x60020000 0x1400>; + interrupts = <0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 54>; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 67>; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 103>; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d100 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 41>; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 44>; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 46>; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 68>; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 104>; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 105>; + }; + + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disabled"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disabled"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disabled"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disabled"; + }; + + usb@7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = < 53 >; + phy_type = "hsic"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + status = "disabled"; + }; +}; diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts similarity index 100% rename from board/toradex/dts/tegra20-colibri_t20_iris.dts rename to arch/arm/dts/tegra20-colibri_t20_iris.dts diff --git a/board/nvidia/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts similarity index 100% rename from board/nvidia/dts/tegra20-harmony.dts rename to arch/arm/dts/tegra20-harmony.dts diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts similarity index 100% rename from board/avionic-design/dts/tegra20-medcom-wide.dts rename to arch/arm/dts/tegra20-medcom-wide.dts diff --git a/board/compal/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts similarity index 100% rename from board/compal/dts/tegra20-paz00.dts rename to arch/arm/dts/tegra20-paz00.dts diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts similarity index 100% rename from board/avionic-design/dts/tegra20-plutux.dts rename to arch/arm/dts/tegra20-plutux.dts diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts similarity index 100% rename from board/nvidia/dts/tegra20-seaboard.dts rename to arch/arm/dts/tegra20-seaboard.dts diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi similarity index 100% rename from board/avionic-design/dts/tegra20-tamonten.dtsi rename to arch/arm/dts/tegra20-tamonten.dtsi diff --git a/board/avionic-design/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts similarity index 100% rename from board/avionic-design/dts/tegra20-tec.dts rename to arch/arm/dts/tegra20-tec.dts diff --git a/board/compulab/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts similarity index 100% rename from board/compulab/dts/tegra20-trimslice.dts rename to arch/arm/dts/tegra20-trimslice.dts diff --git a/board/nvidia/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts similarity index 100% rename from board/nvidia/dts/tegra20-ventana.dts rename to arch/arm/dts/tegra20-ventana.dts diff --git a/board/nvidia/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts similarity index 100% rename from board/nvidia/dts/tegra20-whistler.dts rename to arch/arm/dts/tegra20-whistler.dts diff --git a/board/nvidia/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts similarity index 100% rename from board/nvidia/dts/tegra30-beaver.dts rename to arch/arm/dts/tegra30-beaver.dts diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts similarity index 100% rename from board/nvidia/dts/tegra30-cardhu.dts rename to arch/arm/dts/tegra30-cardhu.dts diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi similarity index 100% rename from board/avionic-design/dts/tegra30-tamonten.dtsi rename to arch/arm/dts/tegra30-tamonten.dtsi diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/arch/arm/dts/tegra30-tec-ng.dts similarity index 100% rename from board/avionic-design/dts/tegra30-tec-ng.dts rename to arch/arm/dts/tegra30-tec-ng.dts diff --git a/board/xilinx/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts similarity index 100% rename from board/xilinx/dts/zynq-microzed.dts rename to arch/arm/dts/zynq-microzed.dts diff --git a/board/xilinx/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts similarity index 100% rename from board/xilinx/dts/zynq-zc702.dts rename to arch/arm/dts/zynq-zc702.dts diff --git a/board/xilinx/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts similarity index 100% rename from board/xilinx/dts/zynq-zc706.dts rename to arch/arm/dts/zynq-zc706.dts diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts similarity index 100% rename from board/xilinx/dts/zynq-zc770-xm010.dts rename to arch/arm/dts/zynq-zc770-xm010.dts diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts similarity index 100% rename from board/xilinx/dts/zynq-zc770-xm012.dts rename to arch/arm/dts/zynq-zc770-xm012.dts diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts similarity index 100% rename from board/xilinx/dts/zynq-zc770-xm013.dts rename to arch/arm/dts/zynq-zc770-xm013.dts diff --git a/board/xilinx/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts similarity index 100% rename from board/xilinx/dts/zynq-zed.dts rename to arch/arm/dts/zynq-zed.dts diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index ee5c872f51..b04dfbbcb9 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -23,37 +23,62 @@ endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o -$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/% - mkdir -p $(dir $@) - $(CC) -E -x c $< $(CPPFLAGS) -o $@ +quiet_cmd_cpp_cfg = CFGS $@ + cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< -$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp - $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp -$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp - $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ - -e $(CONFIG_SPL_TEXT_BASE) -d $< $@ +$(IMX_CONFIG): %.cfgtmp: % FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cpp_cfg) -$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx - $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ - $(OBJTREE)/u-boot.uim - cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ - rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) -$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin - (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ - dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \ - cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \ - $(OBJTREE)/spl/u-boot-nand-spl-pad.imx - rm $(OBJTREE)/spl/u-boot-nand-spl.imx - $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ - $(OBJTREE)/u-boot.uim - cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ - rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim +MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SYS_TEXT_BASE) + +u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) + +ifeq ($(CONFIG_OF_SEPARATE),y) +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SYS_TEXT_BASE) + +u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) +endif + +MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SPL_TEXT_BASE) + +SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) + +MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ + -e $(CONFIG_SYS_TEXT_BASE) -C none + +u-boot.uim: u-boot.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) +append = cat $(filter-out $< $(PHONY), $^) >> $@ + +quiet_cmd_pad_cat = CAT $@ +cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ + +u-boot-with-spl.imx: SPL u-boot.uim FORCE + $(call if_changed,pad_cat) + +u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE + $(call if_changed,pad_cat) + +quiet_cmd_u-boot-nand-spl_imx = GEN $@ +cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ + dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ + +spl/u-boot-nand-spl.imx: SPL FORCE + $(call if_changed,u-boot-nand-spl_imx) + +targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 9231649409..a77c4decc9 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ + case MXC_CPU_MX6D: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6DL: return "6DL"; /* Dual Lite version of the mx6 */ case MXC_CPU_MX6SOLO: diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 9febfa2719..d9f0306b0a 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -78,58 +78,7 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[12]; /* 0x224 */ - u32 testmomde_ctrl; /* 0x230 */ - u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; #ifndef CONFIG_AM43XX /* Encapsulating core pll registers */ @@ -171,7 +120,8 @@ struct cm_wkuppll { unsigned int resv11[1]; unsigned int wkup_uart0ctrl; /* offset 0xB4 */ unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ - unsigned int resv12[7]; + unsigned int wkup_adctscctrl; /* offset 0xBC */ + unsigned int resv12[6]; unsigned int divm6dpllcore; /* offset 0xD8 */ }; @@ -221,7 +171,8 @@ struct cm_perpll { unsigned int tpccclkctrl; /* offset 0xBC */ unsigned int dcan0clkctrl; /* offset 0xC0 */ unsigned int dcan1clkctrl; /* offset 0xC4 */ - unsigned int resv6[2]; + unsigned int resv6; + unsigned int epwmss1clkctrl; /* offset 0xCC */ unsigned int emiffwclkctrl; /* offset 0xD0 */ unsigned int epwmss0clkctrl; /* offset 0xD4 */ unsigned int epwmss2clkctrl; /* offset 0xD8 */ @@ -332,7 +283,9 @@ struct cm_perpll { unsigned int mcasp1clkctrl; /* offset 0x240 */ unsigned int resv11; unsigned int mmc2clkctrl; /* offset 0x248 */ - unsigned int resv12[5]; + unsigned int resv12[3]; + unsigned int qspiclkctrl; /* offset 0x258 */ + unsigned int resv121; unsigned int usb0clkctrl; /* offset 0x260 */ unsigned int resv13[103]; unsigned int l4lsclkstctrl; /* offset 0x400 */ @@ -351,7 +304,11 @@ struct cm_perpll { unsigned int gpio2clkctrl; /* offset 0x480 */ unsigned int resv20; unsigned int gpio3clkctrl; /* offset 0x488 */ - unsigned int resv21[7]; + unsigned int resv41; + unsigned int gpio4clkctrl; /* offset 0x490 */ + unsigned int resv42; + unsigned int gpio5clkctrl; /* offset 0x498 */ + unsigned int resv21[3]; unsigned int i2c1clkctrl; /* offset 0x4A8 */ unsigned int resv22; diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index c1777dfdc9..4d899528f5 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -43,7 +43,7 @@ #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B #define MT41J128MJT125_EMIF_TIM2 0x26337FDA #define MT41J128MJT125_EMIF_TIM3 0x501F830F @@ -58,6 +58,22 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + /* Micron MT41J64M16JT-125 */ #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 @@ -65,7 +81,7 @@ #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 /* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F @@ -97,7 +113,7 @@ #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B /* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF @@ -113,7 +129,7 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B /* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07 +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index a1ffd49f79..220603db5a 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -12,8 +12,8 @@ #define AM33XX_GPIO1_BASE 0x4804C000 #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 - -#define GPIO_22 22 +#define AM33XX_GPIO4_BASE 0x48320000 +#define AM33XX_GPIO5_BASE 0x48322000 /* GPIO CTRL register */ #define GPIO_CTRL_DISABLEMODULE_SHIFT 0 diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 7a7d91b714..0855d16ce5 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -29,5 +29,6 @@ #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR #define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC +#define QSPI_BASE 0x47900000 #endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h deleted file mode 100644 index 00ad1d0672..0000000000 --- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */ -#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ - .eccbytes = 32,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33},\ - .oobfree = {\ - {.offset = 34,\ - .length = 30 } } \ -} - -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57},\ - .oobfree = {\ - {.offset = 58,\ - .length = 6 } } \ -} - -#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\ - .eccbytes = 104,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\ - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\ - 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\ - 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\ - 100, 101, 102, 103, 104, 105},\ - .oobfree = {\ - {.offset = 106,\ - .length = 8 } } \ -} -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 5cd1e95257..8543f4399c 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #if defined(CONFIG_TI816X) #define BOOT_DEVICE_XIP 2 @@ -19,6 +19,7 @@ #define BOOT_DEVICE_MMC1 7 #define BOOT_DEVICE_MMC2 8 #define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_USB 13 #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_CPGMAC 71 #else @@ -38,9 +39,16 @@ #endif #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#if defined(CONFIG_AM33XX) +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#elif defined(CONFIG_AM43XX) +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#ifdef CONFIG_SPL_USB_SUPPORT +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB +#else +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#endif #elif defined(CONFIG_TI81XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 87b7d367b9..91ff2ad0e4 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,6 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include #include #define BOARD_REV_ID 0x0 @@ -17,10 +18,6 @@ u32 get_cpu_rev(void); u32 get_sysboot_value(void); -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void); -#endif - extern struct ctrl_stat *cstat; u32 get_device_type(void); void save_omap_boot_params(void); diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index ff6142b8aa..71213883d7 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin) /* The following macros are need for backward compatibility */ #define at91_set_GPIO_periph(x, y) \ - at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y) + at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_A_periph(x, y) \ at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_B_periph(x, y) \ diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h index 68c5349601..d8a87daa4a 100644 --- a/arch/arm/include/asm/arch-at91/spl.h +++ b/arch/arm/include/asm/arch-at91/spl.h @@ -14,6 +14,10 @@ enum { BOOT_DEVICE_MMC1, BOOT_DEVICE_MMC2, BOOT_DEVICE_MMC2_2, +#elif CONFIG_SYS_USE_NANDFLASH + BOOT_DEVICE_NAND, +#elif CONFIG_SYS_USE_SERIALFLASH + BOOT_DEVICE_SPI, #endif }; diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h new file mode 100644 index 0000000000..1b40a96ad4 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_GPIO_H +#define __ARCH_BCM281XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h new file mode 100644 index 0000000000..880b4e0907 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define GPIO2_BASE_ADDR 0x35003000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define PWRMGR_BASE_ADDR 0x35010000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define SECWD_BASE_ADDR 0x3500c000 +#define SECWD2_BASE_ADDR 0x35002f40 +#define TIMER_BASE_ADDR 0x3e00d000 + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 38cb42a3b3..dded857c3a 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -143,7 +143,7 @@ struct bcm2835_mbox_tag_get_arm_mem { #define BCM2835_MBOX_POWER_DEVID_SPI 7 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 -#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1) +#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) /* Device doesn't exist */ #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 27b1844ee6..98fe56e686 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -15,7 +15,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #define REG(addr) (*(volatile unsigned int *)(addr)) #define REG_P(addr) ((volatile unsigned int *)(addr)) diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h index 3e9e6065c7..9aa3f4ab27 100644 --- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h +++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h @@ -151,6 +151,7 @@ struct davinci_mmc { uint host_caps; /* Host capabilities */ uint voltages; /* Host supported voltages */ uint version; /* MMC Controller version */ + struct mmc_config cfg; }; enum { diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h index 5aa5d2d019..5afe0d4ba5 100644 --- a/arch/arm/include/asm/arch-davinci/spl.h +++ b/arch/arm/include/asm/arch-davinci/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NAND 1 #define BOOT_DEVICE_SPI 2 diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h index 243fb12b76..1b1cd0dd9e 100644 --- a/arch/arm/include/asm/arch-exynos/board.h +++ b/arch/arm/include/asm/arch-exynos/board.h @@ -14,4 +14,16 @@ */ int exynos_init(void); +/* + * Exynos board specific changes for + * board_early_init_f + */ +int exynos_early_init_f(void); + +/* + * Exynos board specific changes for + * board_power_init + */ +int exynos_power_init(void); + #endif /* EXYNOS_BOARD_H */ diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 573f75553b..fdf73b507a 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -25,8 +25,9 @@ #define EXYNOS4_SYSTIMER_BASE 0x10050000 #define EXYNOS4_WATCHDOG_BASE 0x10060000 #define EXYNOS4_TZPC_BASE 0x10110000 -#define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_DMC_CTRL_BASE 0x10400000 +#define EXYNOS4_MIU_BASE 0x10600000 +#define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 @@ -48,7 +49,6 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE @@ -68,6 +68,7 @@ #define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 #define EXYNOS4X12_FIMD_BASE 0x11C00000 @@ -87,7 +88,6 @@ #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE @@ -106,7 +106,7 @@ #define EXYNOS5_SYSREG_BASE 0x10050000 #define EXYNOS5_TZPC_BASE 0x10100000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 @@ -185,9 +185,11 @@ static inline int s5p_get_cpu_rev(void) static inline void s5p_set_cpu_id(void) { - unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + unsigned int pro_id = readl(EXYNOS4_PRO_ID); + unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; + unsigned int cpu_rev = pro_id & 0x000000FF; - switch (pro_id) { + switch (cpu_id) { case 0x200: /* Exynos4210 EVT0 */ s5p_cpu_id = 0x4210; @@ -196,10 +198,12 @@ static inline void s5p_set_cpu_id(void) case 0x210: /* Exynos4210 EVT1 */ s5p_cpu_id = 0x4210; + s5p_cpu_rev = cpu_rev; break; case 0x412: /* Exynos4412 */ s5p_cpu_id = 0x4412; + s5p_cpu_rev = cpu_rev; break; case 0x520: /* Exynos5250 */ diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739dfca..a7ca12c477 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 2a19852153..d6868fa25d 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 +#define S5P_GPIO_PART_SHIFT (24) +#define S5P_GPIO_PART_MASK (0xff) +#define S5P_GPIO_BANK_SHIFT (8) +#define S5P_GPIO_BANK_MASK (0xffff) +#define S5P_GPIO_PIN_MASK (0xff) -#define exynos4_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \ - EXYNOS4_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) +#define S5P_GPIO_SET_PART(x) \ + (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) -#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) +#define S5P_GPIO_GET_PART(x) \ + (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) -#define exynos4_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \ - EXYNOS4_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define S5P_GPIO_SET_PIN(x) \ + ((x) & S5P_GPIO_PIN_MASK) -#define exynos4x12_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ - EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) +#define EXYNOS4_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos4_gpio_part##part *) \ + EXYNOS4_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS4_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) -#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) +#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ + EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS4X12_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) -#define exynos4x12_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ - EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) +#define EXYNOS5_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ + EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS5_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) -#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) +#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ + EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS5420_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) -#define exynos4x12_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ - EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) +#define exynos4_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS4_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) -#define exynos5_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ - EXYNOS5_GPIO_PART1_BASE)->bank)) \ - - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) +#define exynos4x12_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) -#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) +#define exynos5420_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS5420_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) -#define exynos5_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \ - EXYNOS5_GPIO_PART2_BASE)->bank)) \ - - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) +#define exynos5_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS5_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) -#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \ - EXYNOS5_GPIO_PART3_BASE)->bank)) \ - - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) - - -/* EXYNOS5420 */ -#define exynos5420_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\ - EXYNOS5420_GPIO_PART1_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\ - EXYNOS5420_GPIO_PART2_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX) - -#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\ - EXYNOS5420_GPIO_PART3_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX) - -#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part4_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\ - EXYNOS5420_GPIO_PART4_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX) - -#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -static inline unsigned int s5p_gpio_base(int nr) +static inline unsigned int s5p_gpio_base(int gpio) { - if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { - if (nr < EXYNOS5420_GPIO_PART1_MAX) - return EXYNOS5420_GPIO_PART1_BASE; - else if (nr < EXYNOS5420_GPIO_PART2_MAX) - return EXYNOS5420_GPIO_PART2_BASE; - else if (nr < EXYNOS5420_GPIO_PART3_MAX) - return EXYNOS5420_GPIO_PART3_BASE; - else - return EXYNOS5420_GPIO_PART4_BASE; - } else { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART2_BASE; - else - return EXYNOS5_GPIO_PART3_BASE; - } - } else if (cpu_is_exynos4()) { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return EXYNOS4_GPIO_PART1_BASE; - else - return EXYNOS4_GPIO_PART2_BASE; + unsigned gpio_part = S5P_GPIO_GET_PART(gpio); + + switch (gpio_part) { + case 1: + return samsung_get_base_gpio_part1(); + case 2: + return samsung_get_base_gpio_part2(); + case 3: + return samsung_get_base_gpio_part3(); + case 4: + return samsung_get_base_gpio_part4(); + default: + return 0; } - - return 0; -} - -static inline unsigned int s5p_gpio_part_max(int nr) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { - if (nr < EXYNOS5420_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5420_GPIO_PART2_MAX) - return EXYNOS5420_GPIO_PART1_MAX; - else if (nr < EXYNOS5420_GPIO_PART3_MAX) - return EXYNOS5420_GPIO_PART2_MAX; - else if (nr < EXYNOS5420_GPIO_PART4_MAX) - return EXYNOS5420_GPIO_PART3_MAX; - else - return EXYNOS5420_GPIO_PART4_MAX; - } else { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; - else - return EXYNOS5_GPIO_PART2_MAX; - } - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) { - if (nr < EXYNOS4X12_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS4X12_GPIO_PART2_MAX) - return EXYNOS4X12_GPIO_PART1_MAX; - else - return EXYNOS4X12_GPIO_PART2_MAX; - } else { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return 0; - else - return EXYNOS4_GPIO_PART1_MAX; - } - } - - return 0; } #endif diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h index 40aca71678..50e5c258a9 100644 --- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h +++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h @@ -12,6 +12,7 @@ #include #include +#include #define PANEL_NAME_SIZE (32) @@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev); void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); +void exynos_init_dsim_platform_data(vidinfo_t *vid); /* panel driver init based on mipi dsi interface */ void s6e8ax0_init(void); +#ifdef CONFIG_OF_CONTROL +extern int mipi_power(void); +#endif #endif /* _DSIM_H */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 98d6530b15..0fb6461c08 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -53,6 +53,8 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) +#define SDHCI_MAX_HOSTS 4 + int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline int s5p_mmc_init(int index, int bus_width) @@ -62,4 +64,9 @@ static inline int s5p_mmc_init(int index, int bus_width) return s5p_sdhci_init(base, index, bus_width); } + +#ifdef CONFIG_OF_CONTROL +int exynos_mmc_init(const void *blob); +#endif + #endif diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 30c7f18298..5c1c3d4a93 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -36,7 +36,6 @@ enum periph_id { PERIPH_ID_SDMMC3, PERIPH_ID_I2C8 = 87, PERIPH_ID_I2C9, - PERIPH_ID_I2C10 = 203, PERIPH_ID_I2S0 = 98, PERIPH_ID_I2S1 = 99, @@ -54,8 +53,8 @@ enum periph_id { PERIPH_ID_PWM2, PERIPH_ID_PWM3, PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, - PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h new file mode 100644 index 0000000000..a35940e64f --- /dev/null +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64 diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h deleted file mode 100644 index c2e9c82049..0000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * include/asm-arm/arch-ixp425/ixp425.h - * - * Register definitions for IXP425 - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _ASM_ARM_IXP425_H_ -#define _ASM_ARM_IXP425_H_ - -#define BIT(x) (1<<(x)) - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 -#ifdef UBOOT_REG_FIX -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# endif -#endif /* UBOOT_REG_FIX */ - -/* - * - * IXP425 Memory map: - * - * Phy Phy Size Map Size Virt Description - * ========================================================================= - * - * 0x00000000 0x10000000 SDRAM 1 - * - * 0x10000000 0x10000000 SDRAM 2 - * - * 0x20000000 0x10000000 SDRAM 3 - * - * 0x30000000 0x10000000 SDRAM 4 - * - * The above four are aliases to the same memory location (0x00000000) - * - * 0x48000000 0x4000000 PCI Memory - * - * 0x50000000 0x10000000 Not Mapped EXP BUS - * - * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr - * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG - * - * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG - * - * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL - * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG - */ - -/* - * SDRAM - */ -#define IXP425_SDRAM_BASE (0x00000000) -#define IXP425_SDRAM_BASE_ALT (0x10000000) - - -/* - * PCI Configuration space - */ -#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) - -/* - * Expansion BUS Configuration registers - */ -#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) - -/* - * Peripheral space - */ -#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) - -/* - * SDRAM configuration registers - */ -#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) - -/* - * Q Manager space .. not static mapped - */ -#define IXP425_QMGR_BASE_PHYS (0x60000000) -#define IXP425_QMGR_REGION_SIZE (0x00004000) - -/* - * Expansion BUS - * - * Expansion Bus 'lives' at either base1 or base 2 depending on the value of - * Exp Bus config registers: - * - * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, - * and The expansion bus to IXP425_EXP_BUS_BASE2 - */ -#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) -#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) - -#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS - -#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) -#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) - -#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) -#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) -#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) -#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) -#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) -#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) -#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) -#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) - -#define IXP425_FLASH_WRITABLE (0x2) -#define IXP425_FLASH_DEFAULT (0xbcd23c40) -#define IXP425_FLASH_WRITE (0xbcd23c42) - -#define IXP425_EXP_CS0_OFFSET 0x00 -#define IXP425_EXP_CS1_OFFSET 0x04 -#define IXP425_EXP_CS2_OFFSET 0x08 -#define IXP425_EXP_CS3_OFFSET 0x0C -#define IXP425_EXP_CS4_OFFSET 0x10 -#define IXP425_EXP_CS5_OFFSET 0x14 -#define IXP425_EXP_CS6_OFFSET 0x18 -#define IXP425_EXP_CS7_OFFSET 0x1C -#define IXP425_EXP_CFG0_OFFSET 0x20 -#define IXP425_EXP_CFG1_OFFSET 0x24 -#define IXP425_EXP_CFG2_OFFSET 0x28 -#define IXP425_EXP_CFG3_OFFSET 0x2C - -/* - * Expansion Bus Controller registers. - */ -#ifndef __ASSEMBLY__ -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) -#else -#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) -#endif - -#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) -#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) -#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) -#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) -#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) -#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) -#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) -#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) - -#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) -#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) -#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) -#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) - -/* - * SDRAM Controller registers. - */ -#define IXP425_SDR_CONFIG_OFFSET 0x00 -#define IXP425_SDR_REFRESH_OFFSET 0x04 -#define IXP425_SDR_IR_OFFSET 0x08 - -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) - -#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) - -/* - * UART registers - */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 - -#define IXP425_UART_RBR_OFFSET 0x00 -#define IXP425_UART_THR_OFFSET 0x00 -#define IXP425_UART_DLL_OFFSET 0x00 -#define IXP425_UART_IER_OFFSET 0x04 -#define IXP425_UART_DLH_OFFSET 0x04 -#define IXP425_UART_IIR_OFFSET 0x08 -#define IXP425_UART_FCR_OFFSET 0x00 -#define IXP425_UART_LCR_OFFSET 0x0c -#define IXP425_UART_MCR_OFFSET 0x10 -#define IXP425_UART_LSR_OFFSET 0x14 -#define IXP425_UART_MSR_OFFSET 0x18 -#define IXP425_UART_SPR_OFFSET 0x1c -#define IXP425_UART_ISR_OFFSET 0x20 - -#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) - -#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) -#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) -#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) -#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) -#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) -#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) -#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) -#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) -#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) -#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) -#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) -#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) -#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS -/* - * Peripheral Space Registers - */ -#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) -#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) -#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) -#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) -#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) -#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) -#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) -#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) -#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) -#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) -#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) - -/* - * UART Register Definitions , Offsets only as there are 2 UARTS. - * IXP425_UART1_BASE , IXP425_UART2_BASE. - */ - -#undef UART_NO_RX_INTERRUPT - -#define IXP425_UART_XTAL 14745600 - -/* - * Constants to make it easy to access Interrupt Controller registers - */ -#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ -#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ -#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ -#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ -#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ -#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ -#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ -#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ - -#define N_IRQS 32 -#define IXP425_TIMER_2_IRQ 11 - -/* - * Interrupt Controller Register Definitions. - */ -#ifndef __ASSEMBLY__ -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) -#else -#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) -#endif - -#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) -#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) -#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) -#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) -#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) -#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) -#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) -#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) - -/* - * Constants to make it easy to access GPIO registers - */ -#define IXP425_GPIO_GPOUTR_OFFSET 0x00 -#define IXP425_GPIO_GPOER_OFFSET 0x04 -#define IXP425_GPIO_GPINR_OFFSET 0x08 -#define IXP425_GPIO_GPISR_OFFSET 0x0C -#define IXP425_GPIO_GPIT1R_OFFSET 0x10 -#define IXP425_GPIO_GPIT2R_OFFSET 0x14 -#define IXP425_GPIO_GPCLKR_OFFSET 0x18 -#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C - -/* - * GPIO Register Definitions. - * [Only perform 32bit reads/writes] - */ -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) - -#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) -#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) -#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) -#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) -#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) -#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) -#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) -#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) - -#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ - IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) - -/* - * Macros to make it easy to access the GPIO registers - */ -#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) -#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) -#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) -#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) \ - *IXP425_GPIO_GPITR(line) = \ - (*IXP425_GPIO_GPITR(line) & \ - ~(0x7 << (((line) & 0x7) * 3))) | \ - (0x1 << (((line) & 0x7) * 3)) \ - -/* - * Constants to make it easy to access Timer Control/Status registers - */ -#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ -#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ -#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ -#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ -#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ -#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ -#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ -#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ -#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ - -/* - * Operating System Timer Register Definitions. - */ - -#ifndef __ASSEMBLY__ -#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) -#else -#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) -#endif - -/* _B to avoid collision: also defined in npe/include/... */ -#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) -#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) -#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) -#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) -#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) -#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) -#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) -#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) - -/* - * Timer register values and bit definitions - */ -#define IXP425_OST_ENABLE BIT(0) -#define IXP425_OST_ONE_SHOT BIT(1) -/* Low order bits of reload value ignored */ -#define IXP425_OST_RELOAD_MASK (0x3) -#define IXP425_OST_DISABLED (0x0) -#define IXP425_OSST_TIMER_1_PEND BIT(0) -#define IXP425_OSST_TIMER_2_PEND BIT(1) -#define IXP425_OSST_TIMER_TS_PEND BIT(2) -#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) -#define IXP425_OSST_TIMER_WARM_RESET BIT(4) - -/* - * Constants to make it easy to access PCI Control/Status registers - */ -#define PCI_NP_AD_OFFSET 0x00 -#define PCI_NP_CBE_OFFSET 0x04 -#define PCI_NP_WDATA_OFFSET 0x08 -#define PCI_NP_RDATA_OFFSET 0x0c -#define PCI_CRP_AD_CBE_OFFSET 0x10 -#define PCI_CRP_WDATA_OFFSET 0x14 -#define PCI_CRP_RDATA_OFFSET 0x18 -#define PCI_CSR_OFFSET 0x1c -#define PCI_ISR_OFFSET 0x20 -#define PCI_INTEN_OFFSET 0x24 -#define PCI_DMACTRL_OFFSET 0x28 -#define PCI_AHBMEMBASE_OFFSET 0x2c -#define PCI_AHBIOBASE_OFFSET 0x30 -#define PCI_PCIMEMBASE_OFFSET 0x34 -#define PCI_AHBDOORBELL_OFFSET 0x38 -#define PCI_PCIDOORBELL_OFFSET 0x3C -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 - -/* - * PCI Control/Status Registers - */ -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) - -#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) -#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) -#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) -#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) -#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) -#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) -#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) -#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) -#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) -#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) -#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) -#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) -#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) -#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) -#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) -#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) -#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) -#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) -#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) -#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) -#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) -#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) - -/* - * PCI register values and bit definitions - */ - -/* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/* - * Shift value for byte enable on NP cmd/byte enable register - */ -#define IXP425_PCI_NP_CBE_BESL 4 - -/* - * PCI commands supported by NP access unit - */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 - -#if 0 -#ifndef __ASSEMBLY__ -extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); -extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); -extern void ixp425_pci_init(void *); -#endif -#endif - -/* - * Constants for CRP access into local config space - */ -#define CRP_AD_CBE_BESL 20 -#define CRP_AD_CBE_WRITE BIT(16) - -/* - * Clock Speed Definitions. - */ -#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ - - -#endif diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h deleted file mode 100644 index f499883936..0000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425pci.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IXP425PCI_H -#define _IXP425PCI_H - -#define OK 0 -#define ERROR -1 - -struct pci_controller; -extern void pci_ixp_init(struct pci_controller *hose); - -/* Mask definitions*/ -#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f - -#define PCI_NP_CBE_BESL (4) -#define PCI_NP_AD_FUNCSL (8) - -/*Register addressing definitions for PCI controller configuration - and status registers*/ - -#define PCI_CSR_BASE (0xC0000000) -/* -#define PCI_NP_AD_OFFSET (0x00) -#define PCI_NP_CBE_OFFSET (0x04) -#define PCI_NP_WDATA_OFFSET (0x08) -#define PCI_NP_RDATA_OFFSET (0x0C) -#define PCI_CRP_OFFSET (0x10) -#define PCI_CRP_WDATA_OFFSET (0x14) -#define PCI_CRP_RDATA_OFFSET (0x18) -#define PCI_CSR_OFFSET (0x1C) -#define PCI_ISR_OFFSET (0x20) -#define PCI_INTEN_OFFSET (0x24) -#define PCI_DMACTRL_OFFSET (0x28) -#define PCI_AHBMEMBASE_OFFSET (0x2C) -#define PCI_AHBIOBASE_OFFSET (0x30) -#define PCI_PCIMEMBASE_OFFSET (0x34) -#define PCI_AHBDOORBELL_OFFSET (0x38) -#define PCI_PCIDOORBELL_OFFSET (0x3C) -#define PCI_ATPDMA0_AHBADDR (0x40) -#define PCI_ATPDMA0_PCIADDR (0x44) -#define PCI_ATPDMA0_LENADDR (0x48) -#define PCI_ATPDMA1_AHBADDR (0x4C) -#define PCI_ATPDMA1_PCIADDR (0x50) -#define PCI_ATPDMA1_LENADDR (0x54) -#define PCI_PTADMA0_AHBADDR (0x58) -#define PCI_PTADMA0_PCIADDR (0x5C) -#define PCI_PTADMA0_LENADDR (0x60) -#define PCI_PTADMA1_AHBADDR (0x64) -#define PCI_PTADMA1_PCIADDR (0x68) -#define PCI_PTADMA1_LENADDR (0x6C) -*/ -/*Non prefetch registers bit definitions*/ -/* -#define NP_CMD_INTACK (0x0) -#define NP_CMD_SPECIAL (0x1) -#define NP_CMD_IOREAD (0x2) -#define NP_CMD_IOWRITE (0x3) -#define NP_CMD_MEMREAD (0x6) -#define NP_CMD_MEMWRITE (0x7) -#define NP_CMD_CONFIGREAD (0xa) -#define NP_CMD_CONFIGWRITE (0xb) -*/ - -/*Configuration Port register bit definitions*/ -#define PCI_CRP_WRITE BIT(16) - -/*ISR (Interrupt status) Register bit definitions*/ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/*INTEN (Interrupt Enable) Register bit definitions*/ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/*PCI configuration regs.*/ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDOR_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - - -/*CSR Register bit definitions*/ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/*Configuration command bit definitions*/ -#define PCI_CFG_CMD_IOAE BIT(0) -#define PCI_CFG_CMD_MAE BIT(1) -#define PCI_CFG_CMD_BME BIT(2) -#define PCI_CFG_CMD_MWIE BIT(4) -#define PCI_CFG_CMD_SER BIT(8) -#define PCI_CFG_CMD_FBBE BIT(9) -#define PCI_CFG_CMD_MDPE BIT(24) -#define PCI_CFG_CMD_STA BIT(27) -#define PCI_CFG_CMD_RTA BIT(28) -#define PCI_CFG_CMD_RMA BIT(29) -#define PCI_CFG_CMD_SSE BIT(30) -#define PCI_CFG_CMD_DPE BIT(31) - -/*DMACTRL DMA Control and status Register*/ -#define PCI_DMACTRL_APDCEN BIT(0) -#define PCI_DMACTRL_APDC0 BIT(4) -#define PCI_DMACTRL_APDE0 BIT(5) -#define PCI_DMACTRL_APDC1 BIT(6) -#define PCI_DMACTRL_APDE1 BIT(7) -#define PCI_DMACTRL_PADCEN BIT(8) -#define PCI_DMACTRL_PADC0 BIT(12) -#define PCI_DMACTRL_PADE0 BIT(13) -#define PCI_DMACTRL_PADC1 BIT(14) -#define PCI_DMACTRL_PADE1 BIT(15) - -#endif diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 197703b838..7a688e46b0 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -38,7 +38,7 @@ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file */ #ifndef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg #endif /* CONFIG_SYS_KWD_CONFIG */ /* Kirkwood has 2k of Security SRAM, use it for SP */ diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h index c0e3f206cd..42a52bc36c 100644 --- a/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h @@ -9,7 +9,7 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include +#include #include #endif diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h index f87c137c98..d0efec21ab 100644 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ b/arch/arm/include/asm/arch-mx35/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 4955ccff87..054c680a5a 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -230,9 +230,10 @@ #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #define MXC_SPI_BASE_ADDRESSES \ CSPI1_BASE_ADDR, \ CSPI2_BASE_ADDR, \ diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1312..ac7705b3b0 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -8,12 +8,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index e31ba0a955..1b4ded7feb 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -55,6 +55,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9ad3..1f19727b58 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -53,6 +53,7 @@ #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 #define PCIE_ARB_BASE_ADDR 0x01000000 @@ -405,10 +406,11 @@ struct cspi_regs { #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 -#ifdef CONFIG_MX6SL +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e0b7..f9ee0d9839 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) + +/* + * IOMUXC_GPR8 bit fields + */ +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 + +/* + * IOMUXC_GPR12 bit fields + */ +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) + /* * IOMUXC_GPR13 bit fields */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 55cc9ad6fc..2e414adf3d 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -647,7 +647,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) @@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) @@ -934,7 +934,7 @@ MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SI MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index ad31c3391a..a8456a284a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -53,7 +53,7 @@ MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) @@ -523,7 +523,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) @@ -703,7 +703,7 @@ MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 17125a6f3e..38851a135c 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -9,13 +9,7 @@ #define _SYS_PROTO_H_ #include - -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 61ec8f24e0..4d06ef83fe 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -77,59 +77,7 @@ struct ctrl_id { #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) #ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[0x1C]; /* fill up to 0x240 */ - struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - -#else /* __ASSEMBLY__ */ +#ifdef __ASSEMBLY__ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 #define GPMC_CONFIG3 0x08 diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index bcc22c43e1..18041913c4 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -419,6 +419,16 @@ enum { #define NET_GPMC_CONFIG6 0x00000FCF #define NET_GPMC_CONFIG7 0x00000f6c +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00060700 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x06000700 +#define NET_LAN9221_GPMC_CONFIG5 0x0006090A +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 65a5995020..194b93bf56 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -140,13 +140,13 @@ struct gpio { SRAM_OFFSET2) #define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) -#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ -#define OMAP3_PUBLIC_SRAM_END 0x40210000 +#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ +#define NON_SECURE_SRAM_END 0x40210000 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC /* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE +#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START #define DEBUG_LED1 149 /* gpio */ #define DEBUG_LED2 150 /* gpio */ diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h deleted file mode 100644 index bf2321932a..0000000000 --- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* - * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library. - * The OOB layout was first defined by linx kernel in commit - * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause - * we want to be compatible. - */ -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\ - 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\ - 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\ - .oobfree = {\ - {.offset = 2,\ - .length = 10 } } \ -} - -/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ -#define NET_LAN9221_GPMC_CONFIG1 0x00001000 -#define NET_LAN9221_GPMC_CONFIG2 0x00060700 -#define NET_LAN9221_GPMC_CONFIG3 0x00020201 -#define NET_LAN9221_GPMC_CONFIG4 0x06000700 -#define NET_LAN9221_GPMC_CONFIG5 0x0006090A -#define NET_LAN9221_GPMC_CONFIG6 0x87030000 -#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 2ec319c08a..8350532786 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 43b54f7cae..44fa66f8a3 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -7,6 +7,7 @@ */ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include typedef struct { u32 mtype; diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 545d9d96ad..c21fb54714 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -14,51 +14,6 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res[0xc]; diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index 551b27df14..fb842a2264 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ce8217f697..b338a1566c 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -12,6 +12,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -30,7 +31,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index fb5a568b69..5f1d7454d0 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -16,51 +16,6 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res1[0xc]; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 590235be09..19fdecec01 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,6 +44,7 @@ #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F +#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) @@ -204,6 +205,8 @@ struct s32ktimer { /* ABB efuse masks */ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) +#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h index 2ca8947730..b69165b5ee 100644 --- a/arch/arm/include/asm/arch-omap5/sata.h +++ b/arch/arm/include/asm/arch-omap5/sata.h @@ -36,13 +36,4 @@ #define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) #define TI_SATA_IDLE_SMART (0x2 << 2) -#ifdef CONFIG_SCSI_AHCI_PLAT -int omap_sata_init(void); -#else -static inline int omap_sata_init(void) -{ - return 0; -} -#endif /* CONFIG_SCSI_AHCI_PLAT */ - #endif /* _TI_SATA_H */ diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index 2d5a62e660..f70799860f 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 @@ -15,6 +15,7 @@ #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SATA 9 #define BOOT_DEVICE_SPI 10 #define BOOT_DEVICE_UART 0x43 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 9e70d48f43..9e007c87ae 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -12,6 +12,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -31,7 +32,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index 4fc5a0c3c9..5ae5c87169 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -51,10 +51,17 @@ #include /* CPU detection macros */ extern unsigned int s5p_cpu_id; +extern unsigned int s5p_cpu_rev; + +static inline int s5p_get_cpu_rev(void) +{ + return s5p_cpu_rev; +} static inline void s5p_set_cpu_id(void) { s5p_cpu_id = readl(S5PC100_PRO_ID); + s5p_cpu_rev = s5p_cpu_id & 0x000000FF; s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); } diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index ac60fe6386..da8df74a10 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 +#define S5P_GPIO_PART_SHIFT (24) +#define S5P_GPIO_PART_MASK (0xff) +#define S5P_GPIO_BANK_SHIFT (8) +#define S5P_GPIO_BANK_MASK (0xffff) +#define S5P_GPIO_PIN_MASK (0xff) + +#define S5P_GPIO_SET_PART(x) \ + (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) + +#define S5P_GPIO_GET_PART(x) \ + (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + +#define S5P_GPIO_SET_PIN(x) \ + ((x) & S5P_GPIO_PIN_MASK) + +#define S5PC100_SET_BANK(bank) \ + (((unsigned)&(((struct s5pc100_gpio *) \ + S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define S5PC110_SET_BANK(bank) \ + ((((unsigned)&(((struct s5pc110_gpio *) \ + S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define s5pc100_gpio_get(bank, pin) \ + (S5P_GPIO_SET_PART(0) | \ + S5PC100_SET_BANK(bank) | \ + S5P_GPIO_SET_PIN(pin)) + +#define s5pc110_gpio_get(bank, pin) \ + (S5P_GPIO_SET_PART(0) | \ + S5PC110_SET_BANK(bank) | \ + S5P_GPIO_SET_PIN(pin)) + static inline unsigned int s5p_gpio_base(int nr) { - return S5PC110_GPIO_BASE; + return samsung_get_base_gpio(); } - -static inline unsigned int s5p_gpio_part_max(int nr) -{ - return 0; -} - -#define s5pc110_gpio_get_nr(bank, pin) \ - ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ - - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) #endif /* Pin configurations */ diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h new file mode 100644 index 0000000000..966add3e91 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_MANAGER_H_ +#define _CLOCK_MANAGER_H_ + +typedef struct { + /* main group */ + uint32_t main_vco_base; + uint32_t mpuclk; + uint32_t mainclk; + uint32_t dbgatclk; + uint32_t mainqspiclk; + uint32_t mainnandsdmmcclk; + uint32_t cfg2fuser0clk; + uint32_t maindiv; + uint32_t dbgdiv; + uint32_t tracediv; + uint32_t l4src; + + /* peripheral group */ + uint32_t peri_vco_base; + uint32_t emac0clk; + uint32_t emac1clk; + uint32_t perqspiclk; + uint32_t pernandsdmmcclk; + uint32_t perbaseclk; + uint32_t s2fuser1clk; + uint32_t perdiv; + uint32_t gpiodiv; + uint32_t persrc; + + /* sdram pll group */ + uint32_t sdram_vco_base; + uint32_t ddrdqsclk; + uint32_t ddr2xdqsclk; + uint32_t ddrdqclk; + uint32_t s2fuser2clk; +} cm_config_t; + +extern void cm_basic_init(const cm_config_t *cfg); + +struct socfpga_clock_manager { + u32 ctrl; + u32 bypass; + u32 inter; + u32 intren; + u32 dbctrl; + u32 stat; + u32 _pad_0x18_0x3f[10]; + u32 mainpllgrp; + u32 perpllgrp; + u32 sdrpllgrp; + u32 _pad_0xe0_0x200[72]; + + u32 main_pll_vco; + u32 main_pll_misc; + u32 main_pll_mpuclk; + u32 main_pll_mainclk; + u32 main_pll_dbgatclk; + u32 main_pll_mainqspiclk; + u32 main_pll_mainnandsdmmcclk; + u32 main_pll_cfgs2fuser0clk; + u32 main_pll_en; + u32 main_pll_maindiv; + u32 main_pll_dbgdiv; + u32 main_pll_tracediv; + u32 main_pll_l4src; + u32 main_pll_stat; + u32 main_pll__pad_0x38_0x40[2]; + + u32 per_pll_vco; + u32 per_pll_misc; + u32 per_pll_emac0clk; + u32 per_pll_emac1clk; + u32 per_pll_perqspiclk; + u32 per_pll_pernandsdmmcclk; + u32 per_pll_perbaseclk; + u32 per_pll_s2fuser1clk; + u32 per_pll_en; + u32 per_pll_div; + u32 per_pll_gpiodiv; + u32 per_pll_src; + u32 per_pll_stat; + u32 per_pll__pad_0x34_0x40[3]; + + u32 sdr_pll_vco; + u32 sdr_pll_ctrl; + u32 sdr_pll_ddrdqsclk; + u32 sdr_pll_ddr2xdqsclk; + u32 sdr_pll_ddrdqclk; + u32 sdr_pll_s2fuser2clk; + u32 sdr_pll_en; + u32 sdr_pll_stat; +}; + +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) +#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \ + (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \ + (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) +#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 +#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) +#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) +#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff + +#define MAIN_VCO_BASE \ + (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ + CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)) + +#define PERI_VCO_BASE \ + (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \ + CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \ + CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)) + +#define SDR_VCO_BASE \ + (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \ + CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \ + CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)) + +#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd849..f564046bc0 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,6 +11,7 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index f3afd4d065..c6da405cc0 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_FSMC_BASE 0xD1800000 #define CONFIG_FSMC_NAND_BASE 0xD2000000 @@ -42,11 +41,9 @@ #define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE @@ -63,7 +60,6 @@ #define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x4C000000 #define CONFIG_SPEAR_EMIBASE 0x40000000 diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bca0b..7d28e16f1c 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -11,7 +11,8 @@ /* PLL registers - there are several PLLs in the clock controller */ struct clk_pll { uint pll_base; /* the control register */ - uint pll_out[2]; /* output control */ + /* pll_out[0] is output A control, pll_out[1] is output B control */ + uint pll_out[2]; uint pll_misc; /* other misc things */ }; @@ -21,6 +22,13 @@ struct clk_pll_simple { uint pll_misc; /* other misc things */ }; +struct clk_pllm { + uint pllm_base; /* the control register */ + uint pllm_out; /* output control */ + uint pllm_misc1; /* misc1 */ + uint pllm_misc2; /* misc2 */ +}; + /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ struct clk_set_clr { uint set; @@ -38,7 +46,8 @@ enum { TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/ + TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ + TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ }; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ @@ -47,7 +56,7 @@ struct clk_rst_ctlr { uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ + uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ @@ -75,7 +84,21 @@ struct clk_rst_ctlr { uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */ + uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ + + uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + + uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + + uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ + + uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + + uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; @@ -105,10 +128,10 @@ struct clk_rst_ctlr { uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */ + uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */ + uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ @@ -142,6 +165,47 @@ struct clk_rst_ctlr { uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + + uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ + uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ + uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ + uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ + uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ + uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ + uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ + uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ + uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ + uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ + uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ + uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ + uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ + uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ + uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ + uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ + uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ + uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ + uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ + uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ + uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ + uint crc_reserved51[1]; /* _reserved_51, 0x538 */ + uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ + uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ + uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ + uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ + uint crc_reserved52[1]; /* _reserved_52, 0x554 */ + uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ + uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ + + /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */ + uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ }; /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ @@ -160,6 +224,9 @@ struct clk_rst_ctlr { #define PLL_BASE_OVRRIDE_MASK (1U << 28) +#define PLL_LOCK_SHIFT 27 +#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) + #define PLL_DIVP_SHIFT 20 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) @@ -209,6 +276,20 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +#define PLLP_OUT1_RSTN_DIS (1 << 0) +#define PLLP_OUT1_RSTN_EN (0 << 0) +#define PLLP_OUT1_CLKEN (1 << 1) +#define PLLP_OUT2_RSTN_DIS (1 << 16) +#define PLLP_OUT2_RSTN_EN (0 << 16) +#define PLLP_OUT2_CLKEN (1 << 17) + +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ #define PLLU_POWERDOWN (1 << 16) #define PLL_ENABLE_POWERDOWN (1 << 14) @@ -219,9 +300,15 @@ enum { #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ +#define OSC_XOE_SHIFT 0 +#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) +#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) +#define OSC_XOBP_SHIFT 1 +#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 /* * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits @@ -233,11 +320,15 @@ enum { #define OUT_CLK_DIVISOR_SHIFT 0 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) -#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE_31_30_SHIFT 30 +#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) -#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) +#define OUT_CLK_SOURCE_31_29_SHIFT 29 +#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) + +/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ +#define OUT_CLK_SOURCE_31_28_SHIFT 28 +#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ #define SCLK_SYS_STATE_SHIFT 28U @@ -290,7 +381,7 @@ enum { #define SUPER_SCLK_DIVISOR_SHIFT 0 #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */ +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 @@ -300,23 +391,53 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_NONCPURESET (1 << 29) +/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ +#define CLR_CPURESET0 (1 << 0) +#define CLR_CPURESET1 (1 << 1) +#define CLR_CPURESET2 (1 << 2) +#define CLR_CPURESET3 (1 << 3) +#define CLR_DBGRESET0 (1 << 12) +#define CLR_DBGRESET1 (1 << 13) +#define CLR_DBGRESET2 (1 << 14) +#define CLR_DBGRESET3 (1 << 15) +#define CLR_CORERESET0 (1 << 16) +#define CLR_CORERESET1 (1 << 17) +#define CLR_CORERESET2 (1 << 18) +#define CLR_CORERESET3 (1 << 19) +#define CLR_CXRESET0 (1 << 20) +#define CLR_CXRESET1 (1 << 21) +#define CLR_CXRESET2 (1 << 22) +#define CLR_CXRESET3 (1 << 23) +#define CLR_L2RESET (1 << 24) +#define CLR_NONCPURESET (1 << 29) +#define CLR_PRESETDBG (1 << 30) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ +#define CLR_CPU0_CLK_STP (1 << 8) +#define CLR_CPU1_CLK_STP (1 << 9) +#define CLR_CPU2_CLK_STP (1 << 10) +#define CLR_CPU3_CLK_STP (1 << 11) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLL_ACTIVE_POWERDOWN (1 << 12) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLLU_POWERDOWN (1 << 16) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index e7d0fd45ee..9d8114c4ec 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -20,6 +20,21 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_COUNT, }; +/* + * Note that no Tegra clock register actually uses all of bits 31:28 as + * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in + * those cases, nothing is stored in the bits about the mux field, so it's + * safe to pretend that the mux field extends all the way to the end of the + * register. As such, the U-Boot clock driver is currently a bit lazy, and + * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps + * them all together and pretends they're all 31:28. + */ +enum { + MASK_BITS_31_30, + MASK_BITS_31_29, + MASK_BITS_31_28, +}; + #include /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -305,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); /* SoC-specific TSC init */ void arch_timer_init(void); +void tegra30_set_up_pllp(void); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h index c840c08a89..7a86acb1b2 100644 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -20,5 +20,6 @@ #define CHIPID_TEGRA20 0x20 #define CHIPID_TEGRA30 0x30 #define CHIPID_TEGRA114 0x35 +#define CHIPID_TEGRA124 0x40 #endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index ba22236ee3..1dd3154fbc 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010,2011,2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -21,7 +21,11 @@ struct pmc_ctlr { uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ +#else + uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ +#endif uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ @@ -103,6 +107,179 @@ struct pmc_ctlr { uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ uint pmc_gate; /* _GATE_0, offset 15C */ + /* The following fields are in Tegra124 and later only */ + uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + uint pmc_reserved0; /* _RESERVED, offset 1D8 */ + uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + uint pmc_todo_0[9]; /* offset 200-220 */ + uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + uint pmc_scratch45; + uint pmc_scratch46; + uint pmc_scratch47; + uint pmc_scratch48; + uint pmc_scratch49; + uint pmc_scratch50; + uint pmc_scratch51; + uint pmc_scratch52; + uint pmc_scratch53; + uint pmc_scratch54; + uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ + uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ + uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ + uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + uint pmc_secure_scratch9; + uint pmc_secure_scratch10; + uint pmc_secure_scratch11; + uint pmc_secure_scratch12; + uint pmc_secure_scratch13; + uint pmc_secure_scratch14; + uint pmc_secure_scratch15; + uint pmc_secure_scratch16; + uint pmc_secure_scratch17; + uint pmc_secure_scratch18; + uint pmc_secure_scratch19; + uint pmc_secure_scratch20; + uint pmc_secure_scratch21; + uint pmc_secure_scratch22; + uint pmc_secure_scratch23; + uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ + uint pmc_secure_scratch25; + uint pmc_secure_scratch26; + uint pmc_secure_scratch27; + uint pmc_secure_scratch28; + uint pmc_secure_scratch29; + uint pmc_secure_scratch30; + uint pmc_secure_scratch31; + uint pmc_secure_scratch32; + uint pmc_secure_scratch33; + uint pmc_secure_scratch34; + uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ + + uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ + uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ + uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ + uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ + uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ + uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ + uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ + + uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ + uint pmc_scratch57; + uint pmc_scratch58; + uint pmc_scratch59; + uint pmc_scratch60; + uint pmc_scratch61; + uint pmc_scratch62; + uint pmc_scratch63; + uint pmc_scratch64; + uint pmc_scratch65; + uint pmc_scratch66; + uint pmc_scratch67; + uint pmc_scratch68; + uint pmc_scratch69; + uint pmc_scratch70; + uint pmc_scratch71; + uint pmc_scratch72; + uint pmc_scratch73; + uint pmc_scratch74; + uint pmc_scratch75; + uint pmc_scratch76; + uint pmc_scratch77; + uint pmc_scratch78; + uint pmc_scratch79; + uint pmc_scratch80; + uint pmc_scratch81; + uint pmc_scratch82; + uint pmc_scratch83; + uint pmc_scratch84; + uint pmc_scratch85; + uint pmc_scratch86; + uint pmc_scratch87; + uint pmc_scratch88; + uint pmc_scratch89; + uint pmc_scratch90; + uint pmc_scratch91; + uint pmc_scratch92; + uint pmc_scratch93; + uint pmc_scratch94; + uint pmc_scratch95; + uint pmc_scratch96; + uint pmc_scratch97; + uint pmc_scratch98; + uint pmc_scratch99; + uint pmc_scratch100; + uint pmc_scratch101; + uint pmc_scratch102; + uint pmc_scratch103; + uint pmc_scratch104; + uint pmc_scratch105; + uint pmc_scratch106; + uint pmc_scratch107; + uint pmc_scratch108; + uint pmc_scratch109; + uint pmc_scratch110; + uint pmc_scratch111; + uint pmc_scratch112; + uint pmc_scratch113; + uint pmc_scratch114; + uint pmc_scratch115; + uint pmc_scratch116; + uint pmc_scratch117; + uint pmc_scratch118; + uint pmc_scratch119; + uint pmc_scratch1_eco; /* offset 700 */ }; #define CPU_PWRED 1 @@ -114,11 +291,101 @@ struct pmc_ctlr { #define CPUPWRREQ_OE (1 << 16) #define CPUPWRREQ_POL (1 << 15) -#define CRAILID (0) -#define CE0ID (14) -#define C0NCID (15) -#define CRAIL (1 << CRAILID) -#define CE0 (1 << CE0ID) -#define C0NC (1 << C0NCID) +#define CRAIL 0 +#define CE0 14 +#define C0NC 15 + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#if defined(CONFIG_TEGRA114) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#elif defined(CONFIG_TEGRA124) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 3 +#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT) +#endif + +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 +#if defined(CONFIG_TEGRA124) +#define MULT_16 4 +#endif + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_PCX 3 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_SAX 8 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_SOR 17 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_PARTID_VIC 23 +#define PWRGATE_TOGGLE_PARTID_IRAM 24 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) +#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) +#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) + +/* APBDEV_PMC_CNTRL2_0 0x440 */ +#define HOLD_CKE_LOW_EN (1 << 12) #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index e99f681ffd..d63af0e5fd 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -34,7 +34,12 @@ #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) #define NV_PA_CSITE_BASE 0x70040000 +#else +#define NV_PA_CSITE_BASE 0x70800000 +#endif #define TEGRA_USB_ADDR_MASK 0xFFFFC000 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE @@ -68,6 +73,7 @@ enum { SKU_ID_TM30MQS_P_A3 = 0xb1, SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, + SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ }; /* @@ -81,6 +87,7 @@ enum { TEGRA_SOC_T25, TEGRA_SOC_T30, TEGRA_SOC_T114, + TEGRA_SOC_T124, TEGRA_SOC_CNT, TEGRA_SOC_UNKNOWN = -1, diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index b6896afd96..310bbd7df9 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -11,6 +11,9 @@ #include +/* for mmc_config definition */ +#include + #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ #ifndef __ASSEMBLY__ @@ -138,6 +141,7 @@ struct mmc_host { struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + struct mmc_config cfg; /* mmc configuration */ }; void pad_init_mmc(struct mmc_host *host); diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b524a..705ca5758e 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -17,6 +17,8 @@ #ifndef _TEGRA114_H_ #define _TEGRA114_H_ +#define CONFIG_TEGRA114 + #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h new file mode 100644 index 0000000000..4e48c43bbf --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/ahb.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_AHB_H_ +#define _TEGRA124_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h new file mode 100644 index 0000000000..daf9a2b351 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -0,0 +1,496 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock PLL tables */ + +#ifndef _TEGRA124_CLOCK_TABLES_H_ +#define _TEGRA124_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SoC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock IDs that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_DP2, + PERIPH_ID_AMX0, + PERIPH_ID_ADX0, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_ADX1, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_AMX1, + PERIPH_ID_X_RESERVED26, + PERIPH_ID_X_RESERVED27, + PERIPH_ID_X_RESERVED28, + PERIPH_ID_X_RESERVED29, + PERIPH_ID_X_RESERVED30, + PERIPH_ID_X_RESERVED31, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_ADX0, + PERIPHC_AMX0, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_HDMI_AUDIO, + PERIPHC_CLK72MHZ, + PERIPHC_ADX1, + PERIPHC_AMX1, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h new file mode 100644 index 0000000000..8e39d21a7b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock control definitions */ + +#ifndef _TEGRA124_CLOCK_H_ +#define _TEGRA124_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h new file mode 100644 index 0000000000..0db1881bc6 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h new file mode 100644 index 0000000000..df94d135f8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/funcmux.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 high-level function multiplexing */ + +#ifndef _TEGRA124_FUNCMUX_H_ +#define _TEGRA124_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_KBC = 0, + FUNCMUX_UART4_GPIO = 0, +}; +#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h new file mode 100644 index 0000000000..440cbbfa3e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GP_PADCTRL_H_ +#define _TEGRA124_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h new file mode 100644 index 0000000000..1a6dcb8715 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gpio.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GPIO_H_ +#define _TEGRA124_GPIO_H_ + +/* + * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +enum gpio_pin { + GPIO_PA0 = 0, /* pin 0 */ + GPIO_PA1, + GPIO_PA2, + GPIO_PA3, + GPIO_PA4, + GPIO_PA5, + GPIO_PA6, + GPIO_PA7, + GPIO_PB0, /* pin 8 */ + GPIO_PB1, + GPIO_PB2, + GPIO_PB3, + GPIO_PB4, + GPIO_PB5, + GPIO_PB6, + GPIO_PB7, + GPIO_PC0, /* pin 16 */ + GPIO_PC1, + GPIO_PC2, + GPIO_PC3, + GPIO_PC4, + GPIO_PC5, + GPIO_PC6, + GPIO_PC7, + GPIO_PD0, /* pin 24 */ + GPIO_PD1, + GPIO_PD2, + GPIO_PD3, + GPIO_PD4, + GPIO_PD5, + GPIO_PD6, + GPIO_PD7, + GPIO_PE0, /* pin 32 */ + GPIO_PE1, + GPIO_PE2, + GPIO_PE3, + GPIO_PE4, + GPIO_PE5, + GPIO_PE6, + GPIO_PE7, + GPIO_PF0, /* pin 40 */ + GPIO_PF1, + GPIO_PF2, + GPIO_PF3, + GPIO_PF4, + GPIO_PF5, + GPIO_PF6, + GPIO_PF7, + GPIO_PG0, /* pin 48 */ + GPIO_PG1, + GPIO_PG2, + GPIO_PG3, + GPIO_PG4, + GPIO_PG5, + GPIO_PG6, + GPIO_PG7, + GPIO_PH0, /* pin 56 */ + GPIO_PH1, + GPIO_PH2, + GPIO_PH3, + GPIO_PH4, + GPIO_PH5, + GPIO_PH6, + GPIO_PH7, + GPIO_PI0, /* pin 64 */ + GPIO_PI1, + GPIO_PI2, + GPIO_PI3, + GPIO_PI4, + GPIO_PI5, + GPIO_PI6, + GPIO_PI7, + GPIO_PJ0, /* pin 72 */ + GPIO_PJ1, + GPIO_PJ2, + GPIO_PJ3, + GPIO_PJ4, + GPIO_PJ5, + GPIO_PJ6, + GPIO_PJ7, + GPIO_PK0, /* pin 80 */ + GPIO_PK1, + GPIO_PK2, + GPIO_PK3, + GPIO_PK4, + GPIO_PK5, + GPIO_PK6, + GPIO_PK7, + GPIO_PL0, /* pin 88 */ + GPIO_PL1, + GPIO_PL2, + GPIO_PL3, + GPIO_PL4, + GPIO_PL5, + GPIO_PL6, + GPIO_PL7, + GPIO_PM0, /* pin 96 */ + GPIO_PM1, + GPIO_PM2, + GPIO_PM3, + GPIO_PM4, + GPIO_PM5, + GPIO_PM6, + GPIO_PM7, + GPIO_PN0, /* pin 104 */ + GPIO_PN1, + GPIO_PN2, + GPIO_PN3, + GPIO_PN4, + GPIO_PN5, + GPIO_PN6, + GPIO_PN7, + GPIO_PO0, /* pin 112 */ + GPIO_PO1, + GPIO_PO2, + GPIO_PO3, + GPIO_PO4, + GPIO_PO5, + GPIO_PO6, + GPIO_PO7, + GPIO_PP0, /* pin 120 */ + GPIO_PP1, + GPIO_PP2, + GPIO_PP3, + GPIO_PP4, + GPIO_PP5, + GPIO_PP6, + GPIO_PP7, + GPIO_PQ0, /* pin 128 */ + GPIO_PQ1, + GPIO_PQ2, + GPIO_PQ3, + GPIO_PQ4, + GPIO_PQ5, + GPIO_PQ6, + GPIO_PQ7, + GPIO_PR0, /* pin 136 */ + GPIO_PR1, + GPIO_PR2, + GPIO_PR3, + GPIO_PR4, + GPIO_PR5, + GPIO_PR6, + GPIO_PR7, + GPIO_PS0, /* pin 144 */ + GPIO_PS1, + GPIO_PS2, + GPIO_PS3, + GPIO_PS4, + GPIO_PS5, + GPIO_PS6, + GPIO_PS7, + GPIO_PT0, /* pin 152 */ + GPIO_PT1, + GPIO_PT2, + GPIO_PT3, + GPIO_PT4, + GPIO_PT5, + GPIO_PT6, + GPIO_PT7, + GPIO_PU0, /* pin 160 */ + GPIO_PU1, + GPIO_PU2, + GPIO_PU3, + GPIO_PU4, + GPIO_PU5, + GPIO_PU6, + GPIO_PU7, + GPIO_PV0, /* pin 168 */ + GPIO_PV1, + GPIO_PV2, + GPIO_PV3, + GPIO_PV4, + GPIO_PV5, + GPIO_PV6, + GPIO_PV7, + GPIO_PW0, /* pin 176 */ + GPIO_PW1, + GPIO_PW2, + GPIO_PW3, + GPIO_PW4, + GPIO_PW5, + GPIO_PW6, + GPIO_PW7, + GPIO_PX0, /* pin 184 */ + GPIO_PX1, + GPIO_PX2, + GPIO_PX3, + GPIO_PX4, + GPIO_PX5, + GPIO_PX6, + GPIO_PX7, + GPIO_PY0, /* pin 192 */ + GPIO_PY1, + GPIO_PY2, + GPIO_PY3, + GPIO_PY4, + GPIO_PY5, + GPIO_PY6, + GPIO_PY7, + GPIO_PZ0, /* pin 200 */ + GPIO_PZ1, + GPIO_PZ2, + GPIO_PZ3, + GPIO_PZ4, + GPIO_PZ5, + GPIO_PZ6, + GPIO_PZ7, + GPIO_PAA0, /* pin 208 */ + GPIO_PAA1, + GPIO_PAA2, + GPIO_PAA3, + GPIO_PAA4, + GPIO_PAA5, + GPIO_PAA6, + GPIO_PAA7, + GPIO_PBB0, /* pin 216 */ + GPIO_PBB1, + GPIO_PBB2, + GPIO_PBB3, + GPIO_PBB4, + GPIO_PBB5, + GPIO_PBB6, + GPIO_PBB7, + GPIO_PCC0, /* pin 224 */ + GPIO_PCC1, + GPIO_PCC2, + GPIO_PCC3, + GPIO_PCC4, + GPIO_PCC5, + GPIO_PCC6, + GPIO_PCC7, + GPIO_PDD0, /* pin 232 */ + GPIO_PDD1, + GPIO_PDD2, + GPIO_PDD3, + GPIO_PDD4, + GPIO_PDD5, + GPIO_PDD6, + GPIO_PDD7, + GPIO_PEE0, /* pin 240 */ + GPIO_PEE1, + GPIO_PEE2, + GPIO_PEE3, + GPIO_PEE4, + GPIO_PEE5, + GPIO_PEE6, + GPIO_PEE7, + GPIO_PFF0, /* pin 248 */ + GPIO_PFF1, + GPIO_PFF2, + GPIO_PFF3, + GPIO_PFF4, + GPIO_PFF5, + GPIO_PFF6, + GPIO_PFF7, /* pin 255 */ +}; + +#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h new file mode 100644 index 0000000000..114fce8ada --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/hardware.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_HARDWARE_H_ +#define _TEGRA124_HARDWARE_H_ + +/* + * Include Tegra-specific hardware definitions + * Nothing needed currently for Tegra124 + */ + +#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h new file mode 100644 index 0000000000..9662e2b8aa --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -0,0 +1,620 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PINMUX_H_ +#define _TEGRA124_PINMUX_H_ + +/* + * Pin groups which we adjust. There are three basic attributes of each pin + * group which use this enum: + * + * - function + * - pullup / pulldown + * - tristate or normal + */ +enum pmux_pingrp { + PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ + PINGRP_ULPI_DATA1, + PINGRP_ULPI_DATA2, + PINGRP_ULPI_DATA3, + PINGRP_ULPI_DATA4, + PINGRP_ULPI_DATA5, + PINGRP_ULPI_DATA6, + PINGRP_ULPI_DATA7, + PINGRP_ULPI_CLK, + PINGRP_ULPI_DIR, + PINGRP_ULPI_NXT, + PINGRP_ULPI_STP, + PINGRP_DAP3_FS, + PINGRP_DAP3_DIN, + PINGRP_DAP3_DOUT, + PINGRP_DAP3_SCLK, + PINGRP_GPIO_PV0, + PINGRP_GPIO_PV1, + PINGRP_SDMMC1_CLK, + PINGRP_SDMMC1_CMD, + PINGRP_SDMMC1_DAT3, + PINGRP_SDMMC1_DAT2, + PINGRP_SDMMC1_DAT1, + PINGRP_SDMMC1_DAT0, + PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, + PINGRP_CLK2_REQ, + PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, + PINGRP_DDC_SCL, + PINGRP_DDC_SDA, + PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, + PINGRP_UART2_TXD, + PINGRP_UART2_RTS_N, + PINGRP_UART2_CTS_N, + PINGRP_UART3_TXD, + PINGRP_UART3_RXD, + PINGRP_UART3_CTS_N, + PINGRP_UART3_RTS_N, + PINGRP_GPIO_PU0, + PINGRP_GPIO_PU1, + PINGRP_GPIO_PU2, + PINGRP_GPIO_PU3, + PINGRP_GPIO_PU4, + PINGRP_GPIO_PU5, + PINGRP_GPIO_PU6, + PINGRP_GEN1_I2C_SDA, + PINGRP_GEN1_I2C_SCL, + PINGRP_DAP4_FS, + PINGRP_DAP4_DIN, + PINGRP_DAP4_DOUT, + PINGRP_DAP4_SCLK, + PINGRP_CLK3_OUT, + PINGRP_CLK3_REQ, + /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */ + PINGRP_GPIO_PC7, /* offset 0x31c0 */ + PINGRP_GPIO_PI5, + PINGRP_GPIO_PI7, + PINGRP_GPIO_PK0, + PINGRP_GPIO_PK1, + PINGRP_GPIO_PJ0, + PINGRP_GPIO_PJ2, + PINGRP_GPIO_PK3, + PINGRP_GPIO_PK4, + PINGRP_GPIO_PK2, + PINGRP_GPIO_PI3, + PINGRP_GPIO_PI6, + PINGRP_GPIO_PG0, + PINGRP_GPIO_PG1, + PINGRP_GPIO_PG2, + PINGRP_GPIO_PG3, + PINGRP_GPIO_PG4, + PINGRP_GPIO_PG5, + PINGRP_GPIO_PG6, + PINGRP_GPIO_PG7, + PINGRP_GPIO_PH0, + PINGRP_GPIO_PH1, + PINGRP_GPIO_PH2, + PINGRP_GPIO_PH3, + PINGRP_GPIO_PH4, + PINGRP_GPIO_PH5, + PINGRP_GPIO_PH6, + PINGRP_GPIO_PH7, + PINGRP_GPIO_PJ7, + PINGRP_GPIO_PB0, + PINGRP_GPIO_PB1, + PINGRP_GPIO_PK7, + PINGRP_GPIO_PI0, + PINGRP_GPIO_PI1, + PINGRP_GPIO_PI2, + PINGRP_GPIO_PI4, /* offset 0x324c */ + PINGRP_GEN2_I2C_SCL, + PINGRP_GEN2_I2C_SDA, + PINGRP_SDMMC4_CLK, + PINGRP_SDMMC4_CMD, + PINGRP_SDMMC4_DAT0, + PINGRP_SDMMC4_DAT1, + PINGRP_SDMMC4_DAT2, + PINGRP_SDMMC4_DAT3, + PINGRP_SDMMC4_DAT4, + PINGRP_SDMMC4_DAT5, + PINGRP_SDMMC4_DAT6, + PINGRP_SDMMC4_DAT7, + PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, + PINGRP_GPIO_PCC1, + PINGRP_GPIO_PBB0, + PINGRP_CAM_I2C_SCL, + PINGRP_CAM_I2C_SDA, + PINGRP_GPIO_PBB3, + PINGRP_GPIO_PBB4, + PINGRP_GPIO_PBB5, + PINGRP_GPIO_PBB6, + PINGRP_GPIO_PBB7, + PINGRP_GPIO_PCC2, + PINGRP_JTAG_RTCK, + PINGRP_PWR_I2C_SCL, + PINGRP_PWR_I2C_SDA, + PINGRP_KB_ROW0, + PINGRP_KB_ROW1, + PINGRP_KB_ROW2, + PINGRP_KB_ROW3, + PINGRP_KB_ROW4, + PINGRP_KB_ROW5, + PINGRP_KB_ROW6, + PINGRP_KB_ROW7, + PINGRP_KB_ROW8, + PINGRP_KB_ROW9, + PINGRP_KB_ROW10, + PINGRP_KB_ROW11, + PINGRP_KB_ROW12, + PINGRP_KB_ROW13, + PINGRP_KB_ROW14, + PINGRP_KB_ROW15, + PINGRP_KB_COL0, /* offset 0x32fc */ + PINGRP_KB_COL1, + PINGRP_KB_COL2, + PINGRP_KB_COL3, + PINGRP_KB_COL4, + PINGRP_KB_COL5, + PINGRP_KB_COL6, + PINGRP_KB_COL7, + PINGRP_CLK_32K_OUT, + PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */ + PINGRP_CPU_PWR_REQ, + PINGRP_PWR_INT_N, + PINGRP_CLK_32K_IN, + PINGRP_OWR, + PINGRP_DAP1_FS, + PINGRP_DAP1_DIN, + PINGRP_DAP1_DOUT, + PINGRP_DAP1_SCLK, + PINGRP_CLK1_REQ, + PINGRP_CLK1_OUT, + PINGRP_SPDIF_IN, + PINGRP_SPDIF_OUT, + PINGRP_DAP2_FS, + PINGRP_DAP2_DIN, + PINGRP_DAP2_DOUT, + PINGRP_DAP2_SCLK, + PINGRP_DVFS_PWM, + PINGRP_GPIO_X1_AUD, + PINGRP_GPIO_X3_AUD, + PINGRP_DVFS_CLK, + PINGRP_GPIO_X4_AUD, + PINGRP_GPIO_X5_AUD, + PINGRP_GPIO_X6_AUD, + PINGRP_GPIO_X7_AUD, + PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, + PINGRP_SDMMC3_CMD, + PINGRP_SDMMC3_DAT0, + PINGRP_SDMMC3_DAT1, + PINGRP_SDMMC3_DAT2, + PINGRP_SDMMC3_DAT3, + PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */ + PINGRP_PEX_L0_CLKREQ, + PINGRP_PEX_WAKE, + PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2, + PINGRP_PEX_L1_CLKREQ, + PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */ + PINGRP_SDMMC1_WP_N, + PINGRP_SDMMC3_CD_N, + PINGRP_GPIO_W2_AUD, + PINGRP_GPIO_W3_AUD, + PINGRP_USB_VBUS_EN0, + PINGRP_USB_VBUS_EN1, + PINGRP_SDMMC3_CLK_LB_IN, + PINGRP_SDMMC3_CLK_LB_OUT, + PINGRP_GMI_CLK_LB, + PINGRP_RESET_OUT_N, + PINGRP_KB_ROW16, /* offset 0x340c */ + PINGRP_KB_ROW17, + PINGRP_USB_VBUS_EN2, + PINGRP_GPIO_PFF2, + PINGRP_DP_HPD, /* last reg offset = 0x3430 */ + PINGRP_COUNT, +}; + +enum pdrive_pingrp { + PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ + PDRIVE_PINGROUP_AO2, + PDRIVE_PINGROUP_AT1, + PDRIVE_PINGROUP_AT2, + PDRIVE_PINGROUP_AT3, + PDRIVE_PINGROUP_AT4, + PDRIVE_PINGROUP_AT5, + PDRIVE_PINGROUP_CDEV1, + PDRIVE_PINGROUP_CDEV2, + PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ + PDRIVE_PINGROUP_DAP2, + PDRIVE_PINGROUP_DAP3, + PDRIVE_PINGROUP_DAP4, + PDRIVE_PINGROUP_DBG, + PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ + PDRIVE_PINGROUP_SPI, + PDRIVE_PINGROUP_UAA, + PDRIVE_PINGROUP_UAB, + PDRIVE_PINGROUP_UART2, + PDRIVE_PINGROUP_UART3, + PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ + PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ + PDRIVE_PINGROUP_GMA, + PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ + PDRIVE_PINGROUP_GMF, + PDRIVE_PINGROUP_GMG, + PDRIVE_PINGROUP_GMH, + PDRIVE_PINGROUP_OWR, + PDRIVE_PINGROUP_UAD, + PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ + PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ + PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ + PDRIVE_PINGROUP_DAP5, + PDRIVE_PINGROUP_VBUS, + PDRIVE_PINGROUP_AO3, + PDRIVE_PINGROUP_HVC, + PDRIVE_PINGROUP_SDIO4, + PDRIVE_PINGROUP_AO0, + PDRIVE_PINGROUP_COUNT, +}; + +/* + * Functions which can be assigned to each of the pin groups. The values here + * bear no relation to the values programmed into pinmux registers and are + * purely a convenience. The translation is done through a table search. + */ +enum pmux_func { + PMUX_FUNC_AHB_CLK, + PMUX_FUNC_APB_CLK, + PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_CRT, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DAP3, + PMUX_FUNC_DAP4, + PMUX_FUNC_DAP5, + PMUX_FUNC_DISPA, + PMUX_FUNC_DISPB, + PMUX_FUNC_EMC_TEST0_DLL, + PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_INT, + PMUX_FUNC_HDMI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_IDE, + PMUX_FUNC_KBC, + PMUX_FUNC_MIO, + PMUX_FUNC_MIPI_HS, + PMUX_FUNC_NAND, + PMUX_FUNC_OSC, + PMUX_FUNC_OWR, + PMUX_FUNC_PCIE, + PMUX_FUNC_PLLA_OUT, + PMUX_FUNC_PLLC_OUT1, + PMUX_FUNC_PLLM_OUT1, + PMUX_FUNC_PLLP_OUT2, + PMUX_FUNC_PLLP_OUT3, + PMUX_FUNC_PLLP_OUT4, + PMUX_FUNC_PWM, + PMUX_FUNC_PWR_INTR, + PMUX_FUNC_PWR_ON, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SFLASH, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI2_ALT, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_TRACE, + PMUX_FUNC_TWC, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_UARTE, + PMUX_FUNC_ULPI, + PMUX_FUNC_VI, + PMUX_FUNC_VI_SENSOR_CLK, + PMUX_FUNC_XIO, + /* End of Tegra2 MUX selectors */ + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK12, + PMUX_FUNC_DAP, + PMUX_FUNC_DAPSDMMC2, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DTV, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_EMC_DLL, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2C5, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_NAND_ALT, + PMUX_FUNC_POPSDIO4, + PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_SATA, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + /* End of Tegra3 MUX selectors */ + PMUX_FUNC_USB, + PMUX_FUNC_SOC, + PMUX_FUNC_CPU, + PMUX_FUNC_CLK, + PMUX_FUNC_PWRON, + PMUX_FUNC_PMI, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_RESET_OUT_N, + /* End of Tegra114 MUX selectors */ + + PMUX_FUNC_SAFE, + PMUX_FUNC_MAX, + + PMUX_FUNC_INVALID = 0x4000, + PMUX_FUNC_RSVD1 = 0x8000, + PMUX_FUNC_RSVD2 = 0x8001, + PMUX_FUNC_RSVD3 = 0x8002, + PMUX_FUNC_RSVD4 = 0x8003, +}; + +/* return 1 if a pmux_func is in range */ +#define pmux_func_isvalid(func) \ + ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \ + (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) + +/* return 1 if a pingrp is in range */ +#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; +/* return 1 if a pin_pupd_is in range */ +#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ + ((pupd) <= PMUX_PULL_UP)) + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; +/* return 1 if a pin_tristate_is in range */ +#define pmux_pin_tristate_isvalid(tristate) \ + (((tristate) >= PMUX_TRI_NORMAL) && \ + ((tristate) <= PMUX_TRI_TRISTATE)) + +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; +/* return 1 if a pin_io_is in range */ +#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ + ((io) <= PMUX_PIN_INPUT)) + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; +/* return 1 if a pin_lock is in range */ +#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ + ((lock) <= PMUX_PIN_LOCK_ENABLE)) + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; +/* return 1 if a pin_od is in range */ +#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ + ((od) <= PMUX_PIN_OD_ENABLE)) + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; +/* return 1 if a pin_ioreset_is in range */ +#define pmux_pin_ioreset_isvalid(ioreset) \ + (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ + ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) + +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +/* return 1 if a pin_rcv_sel_is in range */ +#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ + (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ + ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) + +/* Available power domains used by pin groups */ +enum pmux_vddio { + PMUX_VDDIO_BB = 0, + PMUX_VDDIO_LCD, + PMUX_VDDIO_VI, + PMUX_VDDIO_UART, + PMUX_VDDIO_DDR, + PMUX_VDDIO_NAND, + PMUX_VDDIO_SYS, + PMUX_VDDIO_AUDIO, + PMUX_VDDIO_SD, + PMUX_VDDIO_CAM, + PMUX_VDDIO_GMI, + PMUX_VDDIO_PEXCTL, + PMUX_VDDIO_SDMMC1, + PMUX_VDDIO_SDMMC3, + PMUX_VDDIO_SDMMC4, + + PMUX_VDDIO_NONE +}; + +#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX + +#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX + +#define PGRP_SCHMT_NONE -1 +#define PGRP_HSM_NONE PGRP_SCHMT_NONE + +/* return 1 if a padgrp is in range */ +#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) + +/* return 1 if a slew-rate rising/falling edge value is in range */ +#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ + (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) + +/* return 1 if a driver output pull-up/down strength code value is in range */ +#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ + (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) + +/* return 1 if a low-power mode value is in range */ +#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ + (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + +/* Tegra124 pin drive group and pin mux registers */ +#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) +#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ + PDRIVE_PINGROUP_COUNT) +struct pmux_tri_ctlr { + uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */ + uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ + + uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ + + uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ + uint pmt_reserved5[PMUX_OFFSET]; + uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ +}; + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pingroup_config { + enum pmux_pingrp pingroup; /* pin group PINGRP_... */ + enum pmux_func func; /* function to assign FUNC_... */ + enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ + enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ + enum pmux_pin_io io; /* input or output PMUX_PIN_... */ + enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ + enum pmux_pin_od od; /* open-drain or push-pull driver */ + enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ + /* VIL/VIH receivers */ +}; + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the complete configuration for a pin group */ +void pinmux_config_pingroup(struct pingroup_config *config); + +/* Set a pin group to tristate or normal */ +void pinmux_set_tristate(enum pmux_pingrp pin, int enable); + +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_table(struct pingroup_config *config, int len); + +/* Set a group of pins from a table */ +void pinmux_init(void); + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(struct padctrl_config *config, int len); + +#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h new file mode 100644 index 0000000000..b10100a636 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pmu.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PMU_H_ +#define _TEGRA124_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _TEGRA124_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h new file mode 100644 index 0000000000..e2663954bf --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/spl.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_RAM 1 + +#endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h new file mode 100644 index 0000000000..3f0309b78f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/sysctr.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_SYSCTR_H_ +#define _TEGRA124_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h new file mode 100644 index 0000000000..86ebd19453 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/tegra.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_H_ +#define _TEGRA124_H_ + +#define CONFIG_TEGRA124 + +#define NV_PA_SDRAM_BASE 0x80000000 +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ + +#include + +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h new file mode 100644 index 0000000000..7a2d7859d9 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/usb.h @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_USB_H_ +#define _TEGRA124_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7; + uint reserved7_0; + uint reserved7_1; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) +#define USB_SUSP_CLR (1 << 5) + +/* USBx_UTMIP_MISC_CFG0 */ +#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* Moved to Clock and Reset register space */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +/* Moved to Clock and Reset register space */ +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) + +/* USBx_UTMIP_PLL_CFG1_0 */ +/* Moved to Clock and Reset register space */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG0_0 */ +#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) +#define UTMIP_OTGPD (1 << 11) +#define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSDISCON_LEVEL_SHIFT 2 +#define UTMIP_HSDISCON_LEVEL_MASK \ + (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) +#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 +#define UTMIP_HSSQUELCH_LEVEL_MASK \ + (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_FORCE_PDTRK_POWERDOWN 1 +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */ +#define PTS1_SHIFT 31 +#define PTS1_MASK (1 << PTS1_SHIFT) +#define STS1 (1 << 30) + +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULPI 2 +#define PTS_ICUSB_SER 3 +#define PTS_HSIC 4 + +#define STS (1 << 28) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define WKOC (1 << 22) +#define WKDS (1 << 21) +#define WKCN (1 << 20) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) +#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 +#define UTMIP_XCVR_HSSLEW_MSB_MASK \ + (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 +#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_SHIFT 0 +#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 +#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ + (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + +#endif /* _TEGRA124_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 18856ac372..6a4b40ec76 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -8,6 +8,8 @@ #ifndef _TEGRA20_H_ #define _TEGRA20_H_ +#define CONFIG_TEGRA20 + #define NV_PA_SDRAM_BASE 0x00000000 #include diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index c02c5d8500..4ad8b1c053 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -17,6 +17,8 @@ #ifndef _TEGRA30_H_ #define _TEGRA30_H_ +#define CONFIG_TEGRA30 + #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ #include diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h index aed6c46f64..2a7ca4e00c 100644 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h @@ -9,7 +9,7 @@ #ifndef __ASSEMBLY__ -#include +#include #define ASYNC_EMIF_NUM_CS 4 #define ASYNC_EMIF_MODE_NOR 0 diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda9f5..e17c7d1f70 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,57 +55,59 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 reserved_0x000[4]; u32 pll3_ctrl; - u32 resv0[3]; + u32 reserved_0x014[3]; u32 pll7_ctrl; - u32 resv1[3]; + u32 reserved_0x024[3]; u32 pll2_ctrl; - u32 resv2[3]; + u32 reserved_0x034[3]; u32 pll2_ss; - u32 resv3[3]; + u32 reserved_0x044[3]; u32 pll2_num; - u32 resv4[3]; + u32 reserved_0x054[3]; u32 pll2_denom; - u32 resv5[3]; + u32 reserved_0x064[3]; u32 pll4_ctrl; - u32 resv6[3]; + u32 reserved_0x074[3]; u32 pll4_num; - u32 resv7[3]; + u32 reserved_0x084[3]; u32 pll4_denom; + u32 reserved_0x094[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 reserved_0x0A4[3]; u32 pll6_num; - u32 resv9[3]; + u32 reserved_0x0B4[3]; u32 pll6_denom; - u32 resv10[3]; + u32 reserved_0x0C4[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 reserved_0x0E4[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 reserved_0x0F4[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 reserved_0x104[3]; u32 reg_1p1; - u32 resv14[3]; + u32 reserved_0x114[3]; u32 reg_3p0; - u32 resv15[3]; + u32 reserved_0x124[3]; u32 reg_2p5; - u32 resv16[7]; + u32 reserved_0x134[7]; u32 ana_misc0; - u32 resv17[3]; + u32 reserved_0x154[3]; u32 ana_misc1; - u32 resv18[63]; + u32 reserved_0x164[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 reserved_0x264[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 reserved_0x274[3]; u32 pll1_ss; - u32 resv21[3]; + u32 reserved_0x284[3]; u32 pll1_num; - u32 resv22[3]; + u32 reserved_0x294[3]; u32 pll1_denom; - u32 resv23[3]; + u32 reserved_0x2A4[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 reserved_0x2B4[3]; u32 pll_lock; }; #endif @@ -164,6 +166,7 @@ struct anadig_reg { #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) #define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -184,6 +187,10 @@ struct anadig_reg { #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b8c877f939..c2f9761846 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -85,6 +85,7 @@ #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 4a39eb0d60..88807d8db4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -22,8 +22,11 @@ enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -33,6 +36,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h index 7e7f94461a..250c5bc07b 100644 --- a/arch/arm/include/asm/arch-zynq/clk.h +++ b/arch/arm/include/asm/arch-zynq/clk.h @@ -1,3 +1,9 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #ifndef _ZYNQ_CLK_H_ #define _ZYNQ_CLK_H_ diff --git a/arch/arm/include/asm/arch-zynq/spl.h b/arch/arm/include/asm/arch-zynq/spl.h index 79b2559fb3..ae8d788953 100644 --- a/arch/arm/include/asm/arch-zynq/spl.h +++ b/arch/arm/include/asm/arch-zynq/spl.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ +extern void ps7_init(void); + #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_RAM 1 #define BOOT_DEVICE_SPI 2 diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 06aab71b57..f4411400e9 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -23,5 +23,6 @@ extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); +extern int zynq_sdhci_of_init(const void *blob); #endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index ac2b2bfbed..bd3a80cdf7 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -51,4 +51,60 @@ #define GICC_IIDR 0x00fc #define GICC_DIR 0x1000 +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_SETLPIR 0x0040 +#define GICR_CLRLPIR 0x0048 +#define GICR_SEIR 0x0068 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_INVLPIR 0x00a0 +#define GICR_INVALLR 0x00b0 +#define GICR_SYNCR 0x00c0 +#define GICR_MOVLPIR 0x0100 +#define GICR_MOVALLR 0x0110 + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_IGROUPRn 0x0080 +#define GICR_ISENABLERn 0x0100 +#define GICR_ICENABLERn 0x0180 +#define GICR_ISPENDRn 0x0200 +#define GICR_ICPENDRn 0x0280 +#define GICR_ISACTIVERn 0x0300 +#define GICR_ICACTIVERn 0x0380 +#define GICR_IPRIORITYRn 0x0400 +#define GICR_ICFGR0 0x0c00 +#define GICR_ICFGR1 0x0c04 +#define GICR_IGROUPMODRn 0x0d00 +#define GICR_NSACRn 0x0e00 + +/* Cpu Interface System Registers */ +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 +#define ICC_DIR_EL1 S3_0_C12_C11_1 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 +#define ICC_SEIEN_EL1 S3_0_C12_C13_0 +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + #endif /* __GIC_H__ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 60e872637f..63e4ad5a67 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -32,9 +32,6 @@ struct arch_global_data { unsigned long tbl; unsigned long lastinc; unsigned long long timer_reset_value; -#ifdef CONFIG_IXP425 - unsigned long timestamp; -#endif #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; unsigned long tlb_size; diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h new file mode 100644 index 0000000000..2c7e829994 --- /dev/null +++ b/arch/arm/include/asm/kona-common/clk.h @@ -0,0 +1,29 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */ + +#ifndef __KONA_COMMON_CLK_H +#define __KONA_COMMON_CLK_H + +#include + +struct clk; + +/* Only implement required functions for your specific architecture */ +int clk_init(void); +struct clk *clk_get(const char *id); +int clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +unsigned long clk_get_rate(struct clk *clk); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep); +int clk_bsc_enable(void *base); + +#endif diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h new file mode 100644 index 0000000000..1ff0e55d13 --- /dev/null +++ b/arch/arm/include/asm/kona-common/kona_sdhci.h @@ -0,0 +1,12 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KONA_SDHCI_H +#define __KONA_SDHCI_H + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); + +#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index a78f99079b..04925bca1c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -567,7 +567,6 @@ u32 omap_ddr_clk(void); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); @@ -643,6 +642,7 @@ static inline u8 is_dra7xx(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 +#define DRA752_ES1_1 0x07520110 /* * SRAM scratch space entries diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h deleted file mode 100644 index d4143ecd80..0000000000 --- a/arch/arm/include/asm/omap_gpmc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * (C) Copyright 2013 Andreas Bießmann - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_OMAP_GPMC_H -#define __ASM_OMAP_GPMC_H - -#include - -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ -} -#endif - -enum omap_ecc { - /* 1-bit ECC calculation by Software, Error detection by Software */ - OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ - /* 1-bit ECC calculation by GPMC, Error detection by Software */ - /* ECC layout compatible to legacy ROMCODE. */ - OMAP_ECC_HAM1_CODE_HW, - /* 4-bit ECC calculation by GPMC, Error detection by Software */ - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, - /* 4-bit ECC calculation by GPMC, Error detection by ELM */ - OMAP_ECC_BCH4_CODE_HW, - /* 8-bit ECC calculation by GPMC, Error detection by Software */ - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, - /* 8-bit ECC calculation by GPMC, Error detection by ELM */ - OMAP_ECC_BCH8_CODE_HW, -}; - -#endif /* __ASM_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f41ad8c559..ddc245bfd5 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -12,6 +12,9 @@ /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 struct pl310_regs { u32 pl310_cache_id; @@ -47,6 +50,24 @@ struct pl310_regs { u32 pad9[1]; u32 pl310_clean_inv_line_idx; u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; }; void pl310_inval_all(void); diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h deleted file mode 100644 index 28cf5eaeba..0000000000 --- a/arch/arm/include/asm/sizes.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4178f8cf7e..74ee9a4df9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -66,6 +66,7 @@ static inline void set_sctlr(unsigned int val) } void __asm_flush_dcache_all(void); +void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 321997c332..e035d6acc0 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -5,17 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -lib-y += _ashldi3.o -lib-y += _ashrdi3.o -lib-y += _divsi3.o -lib-y += _lshrdi3.o -lib-y += _modsi3.o -lib-y += _udivsi3.o -lib-y += _umodsi3.o -lib-y += div0.o -endif +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \ + _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o ifdef CONFIG_ARM64 obj-y += crt0_64.o @@ -32,7 +23,6 @@ endif ifndef CONFIG_SYS_GENERIC_BOARD obj-y += board.o endif -obj-y += sections.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTM) += bootm.o @@ -43,7 +33,9 @@ else obj-$(CONFIG_SPL_FRAMEWORK) += spl.o endif +obj-y += sections.o ifdef CONFIG_ARM64 +obj-y += gic_64.o obj-y += interrupts_64.o else obj-y += interrupts.o diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c new file mode 100644 index 0000000000..b0c26e5d68 --- /dev/null +++ b/arch/arm/lib/asm-offsets.c @@ -0,0 +1,248 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#if defined(CONFIG_MB86R0x) +#include +#endif +#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ + || defined(CONFIG_MX51) || defined(CONFIG_MX53) +#include +#endif + +int main(void) +{ + /* + * TODO : Check if each entry in this file is really necessary. + * - struct mb86r0x_ddr2 + * - struct mb86r0x_memc + * - struct esdramc_regs + * - struct max_regs + * - struct aips_regs + * - struct aipi_regs + * - struct clkctl + * - struct dpll + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + +#if defined(CONFIG_MB86R0x) + /* ddr2 controller */ + DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); + DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); + DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); + DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); + DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); + DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); + DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); + DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); + DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); + DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); + DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); + DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); + DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); + DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); + DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); + + /* clock reset generator */ + DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); + DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); + DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); + DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); + DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); + DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); + + /* chip control module */ + DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); + + /* external bus interface */ + DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); + DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); + DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); + DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); + DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); + DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); + DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); + DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); + DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); +#endif + +#if defined(CONFIG_MX25) + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); +#endif + +#if defined(CONFIG_MX27) + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); + + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); +#endif + +#if defined(CONFIG_MX35) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); + DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); + DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); + DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); + DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); + DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); + DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); + DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); + DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); + DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); + DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); + DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); + DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); + DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); + DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); + DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); + DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); + DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); + DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); + DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); +#endif + +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); +#endif + + return 0; +} diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index b770e25d87..92e85c4db5 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -105,8 +106,8 @@ static int display_banner(void) { printf("\n\n%s\n\n", version_string); debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - _TEXT_BASE, - _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE); + (ulong)&_start, + (ulong)&__bss_start, (ulong)&__bss_end); #ifdef CONFIG_MODEM_SUPPORT debug("Modem Support enabled\n"); #endif @@ -197,8 +198,6 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -int print_cpuinfo(void); - void __dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; @@ -250,9 +249,7 @@ init_fnc_t *init_sequence[] = { serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */ -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_DISPLAY_BOARDINFO) checkboard, /* display board info */ #endif @@ -277,13 +274,13 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); - gd->mon_len = _bss_end_ofs; + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_db_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ - gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); + gd->fdt_blob = &_end; #endif /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, @@ -322,7 +319,7 @@ void board_init_f(ulong bootflag) gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; + addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR @@ -455,7 +452,7 @@ void board_init_f(ulong bootflag) gd->relocaddr = addr; gd->start_addr_sp = addr_sp; - gd->reloc_off = addr - _TEXT_BASE; + gd->reloc_off = addr - (ulong)&_start; debug("relocation Offset is: %08lx\n", gd->reloc_off); if (new_fdt) { memcpy(new_fdt, gd->fdt_blob, fdt_size); @@ -520,7 +517,7 @@ void board_init_r(gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); - monitor_flash_len = _end_ofs; + monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start; /* Enable caches */ enable_caches(); @@ -597,6 +594,11 @@ void board_init_r(gd_t *id, ulong dest_addr) mmc_initialize(gd->bd); #endif +#ifdef CONFIG_CMD_SCSI + puts("SCSI: "); + scsi_init(); +#endif + #ifdef CONFIG_HAS_DATAFLASH AT91F_DataflashInit(); dataflash_print_info(); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 2fa7787ebb..8c33345e02 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -71,8 +71,7 @@ static void announce_and_cleanup(int fake) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); #ifdef CONFIG_BOOTSTAGE_FDT - if (flag == BOOTM_STATE_OS_FAKE_GO) - bootstage_fdt_add_report(); + bootstage_fdt_add_report(); #endif #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); @@ -199,6 +198,7 @@ static void do_nonsec_virt_switch(void) #ifdef CONFIG_ARM64 smp_kick_all_cpus(); + flush_dcache_all(); /* flush cache before swtiching to EL2 */ armv8_switch_to_el2(); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 armv8_switch_to_el1(); diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S new file mode 100644 index 0000000000..d56396ea22 --- /dev/null +++ b/arch/arm/lib/gic_64.S @@ -0,0 +1,194 @@ +/* + * GIC Initialization Routines. + * + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + + +/************************************************************************* + * + * void gic_init_secure(DistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure) + /* + * Initialize Distributor + * x0: Distributor Base + */ +#if defined(CONFIG_GICV3) + mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */ + /* EnableGrp1S | ARE_S | ARE_NS */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + add x12, x0, (GICD_IGROUPMODRn + 4) + mov w9, #~0 +0: str w9, [x11], #0x4 + str wzr, [x12], #0x4 /* Config SPIs as Group1NS */ + sub w10, w10, #0x1 + cbnz w10, 0b +#elif defined(CONFIG_GICV2) + mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + mov w9, #~0 /* Config SPIs as Grp1 */ +0: str w9, [x11], #0x4 + sub w10, w10, #0x1 + cbnz w10, 0b +#endif +1: + ret +ENDPROC(gic_init_secure) + + +/************************************************************************* + * For Gicv2: + * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase); + * For Gicv3: + * void gic_init_secure_percpu(ReDistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure_percpu) +#if defined(CONFIG_GICV3) + /* + * Initialize ReDistributor + * x0: ReDistributor Base + */ + mrs x10, mpidr_el1 + lsr x9, x10, #32 + bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */ + mov x9, x0 +1: ldr x11, [x9, GICR_TYPER] + lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */ + cmp w10, w11 + b.eq 2f + add x9, x9, #(2 << 16) + b 1b + + /* x9: ReDistributor Base Address of Current CPU */ +2: mov w10, #~0x2 + ldr w11, [x9, GICR_WAKER] + and w11, w11, w10 /* Clear ProcessorSleep */ + str w11, [x9, GICR_WAKER] + dsb st + isb +3: ldr w10, [x9, GICR_WAKER] + tbnz w10, #2, 3b /* Wait Children be Alive */ + + add x10, x9, #(1 << 16) /* SGI_Base */ + mov w11, #~0 + str w11, [x10, GICR_IGROUPRn] + str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */ + mov w11, #0x1 /* Enable SGI 0 */ + str w11, [x10, GICR_ISENABLERn] + + /* Initialize Cpu Interface */ + mrs x10, ICC_SRE_EL3 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL2 access to ICC_SRE_EL2 */ + msr ICC_SRE_EL3, x10 + isb + + mrs x10, ICC_SRE_EL2 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL1 access to ICC_SRE_EL1 */ + msr ICC_SRE_EL2, x10 + isb + + mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ + msr ICC_IGRPEN1_EL3, x10 + isb + + msr ICC_CTLR_EL3, xzr + isb + + msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ + isb + + mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */ + msr ICC_PMR_EL1, x10 + isb +#elif defined(CONFIG_GICV2) + /* + * Initialize SGIs and PPIs + * x0: Distributor Base + * x1: Cpu Interface Base + */ + mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ + str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ + mov w9, #0x1 /* Enable SGI 0 */ + str w9, [x0, GICD_ISENABLERn] + + /* Initialize Cpu Interface */ + mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */ + /* Enable Ack Group1 Interrupt & */ + /* EnableGrp0 & EnableGrp1 */ + str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */ + + mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ + str w9, [x1, GICC_PMR] +#endif + ret +ENDPROC(gic_init_secure_percpu) + + +/************************************************************************* + * For Gicv2: + * void gic_kick_secondary_cpus(DistributorBase); + * For Gicv3: + * void gic_kick_secondary_cpus(void); + * + *************************************************************************/ +ENTRY(gic_kick_secondary_cpus) +#if defined(CONFIG_GICV3) + mov x9, #(1 << 40) + msr ICC_ASGI1R_EL1, x9 + isb +#elif defined(CONFIG_GICV2) + mov w9, #0x8000 + movk w9, #0x100, lsl #16 + str w9, [x0, GICD_SGIR] +#endif + ret +ENDPROC(gic_kick_secondary_cpus) + + +/************************************************************************* + * For Gicv2: + * void gic_wait_for_interrupt(CpuInterfaceBase); + * For Gicv3: + * void gic_wait_for_interrupt(void); + * + * Wait for SGI 0 from master. + * + *************************************************************************/ +ENTRY(gic_wait_for_interrupt) +0: wfi +#if defined(CONFIG_GICV3) + mrs x9, ICC_IAR1_EL1 + msr ICC_EOIR1_EL1, x9 +#elif defined(CONFIG_GICV2) + ldr w9, [x0, GICC_AIAR] + str w9, [x0, GICC_AEOIR] +#endif + cbnz w9, 0b + ret +ENDPROC(gic_wait_for_interrupt) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 603bf14627..758b01371e 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -153,7 +153,7 @@ void do_prefetch_abort (struct pt_regs *pt_regs) void do_data_abort (struct pt_regs *pt_regs) { - printf ("data abort\n\n MAYBE you should read doc/README.arm-unaligned-accesses\n\n"); + printf ("data abort\n"); show_regs (pt_regs); bad_mode (); } diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 7fba9e2780..5c51cae8ab 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -11,6 +11,7 @@ #include #include #include +#include /* * void relocate_code (addr_moni) @@ -19,6 +20,9 @@ * x0 holds the destination address. */ ENTRY(relocate_code) + stp x29, x30, [sp, #-32]! /* create a stack frame */ + mov x29, sp + str x0, [sp, #16] /* * Copy u-boot from flash to RAM */ @@ -32,6 +36,7 @@ copy_loop: stp x10, x11, [x0], #16 /* copy to target address [x0] */ cmp x1, x2 /* until source end address [x2] */ b.lo copy_loop + str x0, [sp, #24] /* * Fix .rela.dyn relocations @@ -54,5 +59,19 @@ fixnext: b.lo fixloop relocate_done: + switch_el x1, 3f, 2f, 1f + bl hang +3: mrs x0, sctlr_el3 + b 0f +2: mrs x0, sctlr_el2 + b 0f +1: mrs x0, sctlr_el1 +0: tbz w0, #2, 5f /* skip flushing cache if disabled */ + tbz w0, #12, 4f /* invalide i-cache is enabled */ + ic iallu /* i-cache invalidate all */ + isb sy +4: ldp x0, x1, [sp, #16] + bl __asm_flush_dcache_range +5: ldp x29, x30, [sp],#16 ret ENDPROC(relocate_code) diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index e35687c09c..5b30bcb9a5 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -25,3 +25,4 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char _end[0] __attribute__((section(".__end"))); diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 4ab4745edf..28a371c806 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -5,8 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= avr32-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := avr32-linux- +endif +PLATFORM_CPPFLAGS += -DCONFIG_AVR32 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/avr32/cpu/pio2.h b/arch/avr32/cpu/pio2.h deleted file mode 100644 index 9719ea8c43..0000000000 --- a/arch/avr32/cpu/pio2.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Register definitions for Parallel Input/Output Controller - */ -#ifndef __CPU_AT32AP_PIO2_H__ -#define __CPU_AT32AP_PIO2_H__ - -/* PIO2 register offsets */ -#define PIO2_PER 0x0000 -#define PIO2_PDR 0x0004 -#define PIO2_PSR 0x0008 -#define PIO2_OER 0x0010 -#define PIO2_ODR 0x0014 -#define PIO2_OSR 0x0018 -#define PIO2_IFER 0x0020 -#define PIO2_IFDR 0x0024 -#define PIO2_ISFR 0x0028 -#define PIO2_SODR 0x0030 -#define PIO2_CODR 0x0034 -#define PIO2_ODSR 0x0038 -#define PIO2_PDSR 0x003c -#define PIO2_IER 0x0040 -#define PIO2_IDR 0x0044 -#define PIO2_IMR 0x0048 -#define PIO2_ISR 0x004c -#define PIO2_MDER 0x0050 -#define PIO2_MDDR 0x0054 -#define PIO2_MDSR 0x0058 -#define PIO2_PUDR 0x0060 -#define PIO2_PUER 0x0064 -#define PIO2_PUSR 0x0068 -#define PIO2_ASR 0x0070 -#define PIO2_BSR 0x0074 -#define PIO2_ABSR 0x0078 -#define PIO2_OWER 0x00a0 -#define PIO2_OWDR 0x00a4 -#define PIO2_OWSR 0x00a8 - -/* Register access macros */ -#define pio2_readl(base,reg) \ - readl((void *)base + PIO2_##reg) -#define pio2_writel(base,reg,value) \ - writel((value), (void *)base + PIO2_##reg) - -#endif /* __CPU_AT32AP_PIO2_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h b/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h deleted file mode 100644 index 8801bd006c..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ -#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ - -/* Register offsets */ -struct gpio_regs { - u32 GPER; - u32 GPERS; - u32 GPERC; - u32 GPERT; - u32 PMR0; - u32 PMR0S; - u32 PMR0C; - u32 PMR0T; - u32 PMR1; - u32 PMR1S; - u32 PMR1C; - u32 PMR1T; - u32 __reserved0[4]; - u32 ODER; - u32 ODERS; - u32 ODERC; - u32 ODERT; - u32 OVR; - u32 OVRS; - u32 OVRC; - u32 OVRT; - u32 PVR; - u32 __reserved_PVRS; - u32 __reserved_PVRC; - u32 __reserved_PVRT; - u32 PUER; - u32 PUERS; - u32 PUERC; - u32 PUERT; - u32 PDER; - u32 PDERS; - u32 PDERC; - u32 PDERT; - u32 IER; - u32 IERS; - u32 IERC; - u32 IERT; - u32 IMR0; - u32 IMR0S; - u32 IMR0C; - u32 IMR0T; - u32 IMR1; - u32 IMR1S; - u32 IMR1C; - u32 IMR1T; - u32 GFER; - u32 GFERS; - u32 GFERC; - u32 GFERT; - u32 IFR; - u32 __reserved_IFRS; - u32 IFRC; - u32 __reserved_IFRT; - u32 ODMER; - u32 ODMERS; - u32 ODMERC; - u32 ODMERT; - u32 __reserved1[4]; - u32 ODCR0; - u32 ODCR0S; - u32 ODCR0C; - u32 ODCR0T; - u32 ODCR1; - u32 ODCR1S; - u32 ODCR1C; - u32 ODCR1T; - u32 __reserved2[4]; - u32 OSRR0; - u32 OSRR0S; - u32 OSRR0C; - u32 OSRR0T; - u32 __reserved3[8]; - u32 STER; - u32 STERS; - u32 STERC; - u32 STERT; - u32 __reserved4[35]; - u32 VERSION; -}; - -#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/arch/avr32/include/asm/arch-common/portmux-gpio.h b/arch/avr32/include/asm/arch-common/portmux-gpio.h deleted file mode 100644 index fb01a17fc1..0000000000 --- a/arch/avr32/include/asm/arch-common/portmux-gpio.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AVR32_PORTMUX_GPIO_H__ -#define __AVR32_PORTMUX_GPIO_H__ - -#include - -/* Register layout for this specific device */ -#include - -/* Register access macros */ -#define gpio_readl(port, reg) \ - __raw_readl(&((struct gpio_regs *)port)->reg) -#define gpio_writel(gpio, reg, value) \ - __raw_writel(value, &((struct gpio_regs *)port)->reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, - PORTMUX_FUNC_C, - PORTMUX_FUNC_D, -}; - -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (2 << 2) -#define PORTMUX_BUSKEEPER (3 << 2) -#define PORTMUX_DRIVE_MIN (0 << 4) -#define PORTMUX_DRIVE_LOW (1 << 4) -#define PORTMUX_DRIVE_HIGH (2 << 4) -#define PORTMUX_DRIVE_MAX (3 << 4) -#define PORTMUX_OPEN_DRAIN (1 << 6) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void *gpio_pin_to_port(unsigned int pin) -{ - return (void *)GPIO_BASE + (pin >> 5) * 0x200; -} - -static inline void __gpio_set_output_value(void *port, unsigned int pin, - int value) -{ - if (value) - gpio_writel(port, OVRS, 1 << pin); - else - gpio_writel(port, OVRC, 1 << pin); -} - -static inline int __gpio_get_input_value(void *port, unsigned int pin) -{ - return (gpio_readl(port, PVR) >> pin) & 1; -} - -void gpio_set_output_value(unsigned int pin, int value); -int gpio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __gpio_set_output_value(gpio_pin_to_port(pin), - pin & 0x1f, value); - else - gpio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __gpio_get_input_value(gpio_pin_to_port(pin), - pin & 0x1f); - else - return gpio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_GPIO_H__ */ diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 73fa79855f..fcaa44f1d6 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -5,14 +5,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= bfin-uclinux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := bfin-uclinux- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin ifeq ($(CONFIG_BFIN_CPU),) CONFIG_BFIN_CPU := \ $(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \ - $(src)include/configs/$(BOARD).h) + $(srctree)/include/configs/$(BOARD).h) else CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%)) endif @@ -28,10 +30,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -ALL-y += $(obj)u-boot.ldr +ALL-y += u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) -CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o HOSTCFLAGS_NOPED_ADSP := \ $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) .*\' ; then \ echo "$< contains external references!" 1>&2 ; \ @@ -35,7 +36,10 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif -$(obj)init.lds: init.lds.S - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ -$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o - $(LD) $(LDFLAGS) -T $^ -o $@ +CPPFLAGS_init.lds := -ansi + +quiet_cmd_link_init = LD $@ + cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@ +$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o + $(call if_changed,link_init) +targets += init.lds init.o diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h index 1fec7f3d85..ab7fa45075 100644 --- a/arch/blackfin/cpu/initcode.h +++ b/arch/blackfin/cpu/initcode.h @@ -49,7 +49,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('a'); -#ifdef __ADSPBF60x__ +#ifndef __ADSPBF60x__ /* Program the async banks controller. */ #ifdef EBIU_AMGCTL bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); @@ -74,7 +74,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('c'); -#else /* __ADSPBF60x__ */ +#else /* __ADSPBF60x__ */ /* Program the static memory controller. */ # ifdef CONFIG_SMC_GCTL_VAL bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL); @@ -116,7 +116,7 @@ program_async_controller(ADI_BOOT_DATA *bs) bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL); # endif -#endif +#endif /* __ADSPBF60x__ */ serial_putc('d'); } diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index c99cf49833..29a7c232e2 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -190,6 +190,7 @@ ENTRY(_start) call _memcpy_ASM; #endif +.Lnorelocate: /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR * takes care of clearing things for us. @@ -202,7 +203,6 @@ ENTRY(_start) r2.h = __bss_len; call _memset; -.Lnorelocate: /* Setup the actual stack in external memory */ sp.h = HI(CONFIG_STACKBASE); diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 4d6eeab0ec..868c82ea7d 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -42,13 +42,6 @@ # include -extern u_long get_vco(void); -extern u_long get_cclk(void); -extern u_long get_sclk(void); -extern u_long get_sclk0(void); -extern u_long get_sclk1(void); -extern u_long get_dclk(void); - # define bfin_revid() (bfin_read_CHIPID() >> 28) extern int bfin_os_log_check(void); diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index fc84fe43f1..59d3faa29d 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -68,10 +68,21 @@ static inline uint32_t early_get_uart_clk(void) return uclk; } +extern u_long get_vco(void); +extern u_long get_cclk(void); +extern u_long get_sclk(void); + #ifdef CGU_DIV +extern u_long get_sclk0(void); +extern u_long get_sclk1(void); +extern u_long get_dclk(void); # define get_uart_clk get_sclk0 +# define get_i2c_clk get_sclk0 +# define get_spi_clk get_sclk0 #else # define get_uart_clk get_sclk +# define get_i2c_clk get_sclk +# define get_spi_clk get_sclk #endif #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h index 7a43bbb1a3..4c9bc9dc57 100644 --- a/arch/blackfin/include/asm/mach-common/bits/emac.h +++ b/arch/blackfin/include/asm/mach-common/bits/emac.h @@ -217,4 +217,7 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/*default value for EMAC_VLANx reg*/ +#define EMAC_VLANX_DEF_VAL 0xFFFF + #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h deleted file mode 100644 index 17d22ab57f..0000000000 --- a/arch/blackfin/include/asm/mach-common/bits/lockbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Lockbox/Security Masks - */ - -#ifndef __BFIN_PERIPHERAL_LOCKBOX__ -#define __BFIN_PERIPHERAL_LOCKBOX__ - -#ifndef __ASSEMBLY__ - -#include "bootrom.h" - -/* SESR argument structure. Expected to reside at 0xFF900018. */ -typedef struct SESR_args { - unsigned short usFlags; /* security firmware flags */ - unsigned short usIRQMask; /* interrupt mask */ - unsigned long ulMessageSize; /* message length in bytes */ - unsigned long ulSFEntryPoint; /* entry point of secure function */ - unsigned long ulMessagePtr; /* pointer to the buffer containing - the digital signature and message */ - unsigned long ulReserved1; /* reserved */ - unsigned long ulReserved2; /* reserved */ -} tSESR_args; - -/* Secure Entry Service Routine */ -static void (* const sesr)(void) = (void *)_BOOTROM_SESR; - -#endif - -/* SESR flags argument bitfields */ -#define SESR_FLAGS_STAY_AT_NMI 0x0000 -#define SESR_FLAGS_DROP_BELOW_NMI 0x0001 -#define SESR_FLAGS_NO_SF_DMA 0x0000 -#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002 -#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000 -#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100 - -/* Bit masks for SECURE_SYSSWT */ -#define EMUDABL 0x00000001 /* Emulation Disable */ -#define RSTDABL 0x00000002 /* Reset Disable */ -#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */ -#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */ -#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */ -#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */ -#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */ -#define EMUOVR 0x00004000 /* Emulation Override */ -#define OTPSEN 0x00008000 /* OTP Secrets Enable */ -#define L2DABL 0x00070000 /* L2 Memory Disable */ - -/* Bit masks for SECURE_CONTROL */ -#define SECURE0 0x0001 /* SECURE 0 */ -#define SECURE1 0x0002 /* SECURE 1 */ -#define SECURE2 0x0004 /* SECURE 2 */ -#define SECURE3 0x0008 /* SECURE 3 */ - -/* Bit masks for SECURE_STATUS */ -#define SECMODE 0x0003 /* Secured Mode Control State */ -#define NMI 0x0004 /* Non Maskable Interrupt */ -#define AFVALID 0x0008 /* Authentication Firmware Valid */ -#define AFEXIT 0x0010 /* Authentication Firmware Exit */ -#define SECSTAT 0x00e0 /* Secure Status */ - -#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h deleted file mode 100644 index 88e7a5d324..0000000000 --- a/arch/blackfin/include/asm/mach-common/bits/sport.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * SPORT Masks - */ - -#ifndef __BFIN_PERIPHERAL_SPORT__ -#define __BFIN_PERIPHERAL_SPORT__ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /* TX Word Length */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0xF000 /* Multichannel Window Size Field */ -#define WOFF 0x03FF /* Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0xF000 /* Multichannel Frame Delay */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - -#endif diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h new file mode 100644 index 0000000000..922cdbd892 --- /dev/null +++ b/arch/blackfin/include/asm/twi.h @@ -0,0 +1,15 @@ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_TWI_H +#define __ARCH_TWI_H + +#include +#include + +#endif diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile index a5c552f38a..4ba7bf6949 100644 --- a/arch/blackfin/lib/Makefile +++ b/arch/blackfin/lib/Makefile @@ -9,7 +9,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"' +# Unnecessary. +# Use CONFIG_SYS_BOARD instead of BFIN_BOARD_NAME +# and delete this. +ccflags-y += -DBFIN_BOARD_NAME='"$(BOARD)"' obj-y += ins.o obj-y += memcmp.o diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 392d72d232..62342014a4 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -23,6 +23,7 @@ #include #include +#include #include #ifdef CONFIG_CMD_NAND @@ -142,7 +143,8 @@ void init_cplbtables(void) ++i; #if defined(__ADSPBF60x__) icplb_add(0x0, 0x0); - dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID); ++i; #endif diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 9c3e24f2fc..33b3d51af0 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -5,11 +5,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= m68k-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := m68k-elf- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data LDFLAGS_FINAL += --gc-sections diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile index a47fd56739..e0c5db60f4 100644 --- a/arch/m68k/cpu/mcf5227x/Makefile +++ b/arch/m68k/cpu/mcf5227x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk index 2681171458..b5c26e4e5b 100644 --- a/arch/m68k/cpu/mcf5227x/config.mk +++ b/arch/m68k/cpu/mcf5227x/config.mk @@ -7,5 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC diff --git a/arch/m68k/cpu/mcf523x/Makefile b/arch/m68k/cpu/mcf523x/Makefile index a47fd56739..e0c5db60f4 100644 --- a/arch/m68k/cpu/mcf523x/Makefile +++ b/arch/m68k/cpu/mcf523x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk index 620769fb19..c9435ab99b 100644 --- a/arch/m68k/cpu/mcf523x/config.mk +++ b/arch/m68k/cpu/mcf523x/config.mk @@ -7,5 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC diff --git a/arch/m68k/cpu/mcf52x2/Makefile b/arch/m68k/cpu/mcf52x2/Makefile index d9bf9008ec..b92fd864c4 100644 --- a/arch/m68k/cpu/mcf52x2/Makefile +++ b/arch/m68k/cpu/mcf52x2/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = interrupts.o cpu.o speed.o cpu_init.o diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk index d0be46fd9c..34ad99e92c 100644 --- a/arch/m68k/cpu/mcf52x2/config.mk +++ b/arch/m68k/cpu/mcf52x2/config.mk @@ -7,16 +7,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg)) -is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) +cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5208:=$(shell grep CONFIG_M5208 $(srctree)/include/$(cfg)) +is5249:=$(shell grep CONFIG_M5249 $(srctree)/include/$(cfg)) +is5253:=$(shell grep CONFIG_M5253 $(srctree)/include/$(cfg)) +is5271:=$(shell grep CONFIG_M5271 $(srctree)/include/$(cfg)) +is5272:=$(shell grep CONFIG_M5272 $(srctree)/include/$(cfg)) +is5275:=$(shell grep CONFIG_M5275 $(srctree)/include/$(cfg)) +is5282:=$(shell grep CONFIG_M5282 $(srctree)/include/$(cfg)) ifneq (,$(findstring CONFIG_M5208,$(is5208))) PLATFORM_CPPFLAGS += -mcpu=5208 diff --git a/arch/m68k/cpu/mcf532x/Makefile b/arch/m68k/cpu/mcf532x/Makefile index 97aa3f16a9..9c53c50c48 100644 --- a/arch/m68k/cpu/mcf532x/Makefile +++ b/arch/m68k/cpu/mcf532x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y := start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk index be1220365a..af943543a2 100644 --- a/arch/m68k/cpu/mcf532x/config.mk +++ b/arch/m68k/cpu/mcf532x/config.mk @@ -7,11 +7,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg)) -is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg)) +cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5301x:=$(shell grep CONFIG_MCF5301x $(srctree)/include/$(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(srctree)/include/$(cfg)) ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index b506719c8f..9be91ed157 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk index d546b22058..5fd0d4d0e2 100644 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ b/arch/m68k/cpu/mcf5445x/config.mk @@ -9,10 +9,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg)) +cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5441x:=$(shell grep CONFIG_MCF5441x $(srctree)/include/$(cfg)) ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile index 0fa50bfccd..4f82099b6b 100644 --- a/arch/m68k/cpu/mcf547x_8x/Makefile +++ b/arch/m68k/cpu/mcf547x_8x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk index 345f5841ac..825f6ccebe 100644 --- a/arch/m68k/cpu/mcf547x_8x/config.mk +++ b/arch/m68k/cpu/mcf547x_8x/config.mk @@ -7,7 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC ifneq (,$(findstring -linux-,$(shell $(CC) --version))) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index fc545a9ee6..98bbf794fa 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -8,10 +8,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= mb- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := mb- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ - -LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/microblaze/dts/.gitignore b/arch/microblaze/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/microblaze/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile new file mode 100644 index 0000000000..6d4a11f62f --- /dev/null +++ b/arch/microblaze/dts/Makefile @@ -0,0 +1,11 @@ +dtb-y += microblaze-generic.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/board/xilinx/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts similarity index 100% rename from board/xilinx/dts/microblaze-generic.dts rename to arch/microblaze/dts/microblaze-generic.dts diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 59956a8673..fafeeaebd6 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -87,7 +87,7 @@ void board_init_f(ulong not_used) #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (void *)__end; diff --git a/arch/microblaze/lib/time.c b/arch/microblaze/lib/time.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/arch/mips/config.mk b/arch/mips/config.mk index c3f81b5a18..1899f51872 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= mips_4KC- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := mips_4KC- +endif # Handle special prefix in ELDK 4.0 toolchain ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) @@ -50,4 +52,4 @@ PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -pie -OBJCFLAGS += --remove-section=.dynsym +OBJCOPYFLAGS += --remove-section=.dynsym diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index fd0ec65959..a3dac70798 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c @@ -839,104 +839,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 067f871525..332cd62c74 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -11,9 +11,7 @@ # Note: Toolchains with binutils prior to v2.16 # are no longer supported by U-Boot MIPS tree! # -MIPSFLAGS := -march=mips32r2 - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2 PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT ifdef CONFIG_SYS_BIG_ENDIAN PLATFORM_LDFLAGS += -m elf32btsmip @@ -21,4 +19,5 @@ else PLATFORM_LDFLAGS += -m elf32ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ + -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk index d1a8b2c7aa..c55eb7f2ee 100644 --- a/arch/mips/cpu/mips64/config.mk +++ b/arch/mips/cpu/mips64/config.mk @@ -11,9 +11,7 @@ # Note: Toolchains with binutils prior to v2.16 # are no longer supported by U-Boot MIPS tree! # -MIPSFLAGS = -march=mips64 - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64 PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT ifdef CONFIG_SYS_BIG_ENDIAN PLATFORM_LDFLAGS += -m elf64btsmip @@ -21,4 +19,5 @@ else PLATFORM_LDFLAGS += -m elf64ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \ + -T $(srctree)/examples/standalone/mips64.lds diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index d81da21017..b8e53e55c0 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -12,4 +12,5 @@ else PLATFORM_LDFLAGS += -m elf32ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ + -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index d4bb85999b..aebafdbba1 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -27,18 +27,12 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long __s64; -typedef unsigned long __u64; - -#else - #if defined(__GNUC__) __extension__ typedef __signed__ long long __s64; __extension__ typedef unsigned long long __u64; -#endif - +#else +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif #endif /* __ASSEMBLY__ */ @@ -61,19 +55,8 @@ typedef unsigned short u16; typedef __signed int s32; typedef unsigned int u32; -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long s64; -typedef unsigned long u64; - -#else - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) typedef __signed__ long long s64; typedef unsigned long long u64; -#endif - -#endif #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ || defined(CONFIG_64BIT) diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 370592668e..fabeb83f7e 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -8,9 +8,4 @@ obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -lib-y += ashldi3.o -lib-y += ashrdi3.o -lib-y += lshrdi3.o -endif +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk index e93e3a8c28..10248524d1 100644 --- a/arch/nds32/config.mk +++ b/arch/nds32/config.mk @@ -8,9 +8,12 @@ # # SPDX-License-Identifier: GPL-2.0+ -CROSS_COMPILE ?= nds32le-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := nds32le-linux- +endif -CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds +CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \ + -T $(srctree)/examples/standalone/nds32.lds PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax PLATFORM_RELFLAGS += -gdwarf-2 diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index bb3550eb47..206d304d4c 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -9,4 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +# necessary to create built-in.o +obj- := __dummy__.o + extra-y = start.o diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c deleted file mode 100644 index 92ada8ac28..0000000000 --- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include - -#include - -int main(void) -{ -#ifdef CONFIG_FTSMC020 - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); -#endif - BLANK(); -#ifdef CONFIG_FTAHBC020S - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); - OFFSET(FTAHBC020S_CR, ftahbc02s, cr); -#endif - BLANK(); -#ifdef CONFIG_FTPMU010 - OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); -#endif - BLANK(); -#ifdef CONFIG_FTSDMC021 - OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); - OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); - OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); - OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); - OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); - OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); - OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); - OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); -#endif - return 0; -} diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 810326d200..d6484b9cc5 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -32,6 +32,15 @@ #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR + +/* + * for Orca and Emerald + */ +#define BOARD_ID_REG 0x104 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 + /* * parameters for the static memory controller */ @@ -47,6 +56,10 @@ #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) +/* + * for Orca and Emerald + */ +#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 /* @@ -100,14 +113,49 @@ mem_init: * we need to set onboard SDRAM before remap and relocation. */ led 0x01 - write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052 - write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151 + + /* + * for Orca and Emerald + * disable write protection and reset bank size + */ + li $r0, SMC_BANK0_CR_A + lwi $r1, [$r0+#0x00] + ori $r1, $r1, 0x8f0 + xori $r1, $r1, 0x8f0 + /* + * check board + */ + li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG + lwi $r3, [$r3] + li $r4, BOARD_ID_FAMILY_MASK + and $r3, $r3, $r4 + li $r4, BOARD_ID_FAMILY_K7 + xor $r4, $r3, $r4 + beqz $r4, use_flash_16bit_boot + /* + * 32-bit mode + */ +use_flash_32bit_boot: + ori $r1, $r1, 0x50 + li $r2, 0x00151151 + j sdram_b0_cr + /* + * 16-bit mode + */ +use_flash_16bit_boot: + ori $r1, $r1, 0x60 + li $r2, 0x00153153 + /* + * SRAM bank0 config + */ +sdram_b0_cr: + swi $r1, [$r0+#0x00] + swi $r2, [$r0+#0x04] /* * config AHB Controller */ led 0x02 - write32 AHBC_BSR6_A, AHBC_BSR6_D /* * config PMU controller @@ -194,7 +242,16 @@ relo_base: * a FLASH connected to bank0. */ led 0x11 - li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ + /* + * for Orca and Emerald + * read sdram base address automatically + */ + li $r5, AHBC_BSR6_A + lwi $r8, [$r5] + li $r4, 0xfff00000 + and $r4, $r4, $r8 + + li $r5, 0x0 la $r1, relo_base /* get $pc or $lp */ sub $r2, $r0, $r1 @@ -218,6 +275,29 @@ relo_base: write32 SDMC_B1_BSR_A, 0x00001040 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 + /* + * for Orca and Emerald + * extend sdram size from 256MB to 2GB + */ + li $r5, AHBC_BSR6_A + lwi $r6, [$r5] + li $r4, 0xfff0ffff + and $r6 ,$r4 , $r6 + li $r4, 0x000b0000 + or $r6, $r4, $r6 + swi $r6, [$r5] + + /* + * for Orca and Emerald + * extend rom base from 256MB to 2GB + */ + li $r4, AHBC_BSR4_A + lwi $r5, [$r4] + li $r6, 0xffffff + and $r5, $r5, $r6 + li $r6, 0x80000000 + or $r5, $r5, $r6 + swi $r5, [$r4] #endif /* #ifdef CONFIG_MEM_REMAP */ move $lp, $r11 2: diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/lib/asm-offsets.c similarity index 69% rename from arch/nds32/cpu/n1213/ag102/asm-offsets.c rename to arch/nds32/lib/asm-offsets.c index 4769a9521d..39e3480bd5 100644 --- a/arch/nds32/cpu/n1213/ag102/asm-offsets.c +++ b/arch/nds32/lib/asm-offsets.c @@ -15,16 +15,43 @@ int main(void) { + /* + * TODO : Check if each entry in this file is really necessary. + * - struct ftahbc02s + * - struct ftsdmc021 + * - struct andes_pcu + * - struct dwcddr21mctl + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + #ifdef CONFIG_FTSMC020 OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); #endif BLANK(); #ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); OFFSET(FTAHBC020S_CR, ftahbc02s, cr); #endif BLANK(); +#ifdef CONFIG_FTPMU010 + OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); +#endif + BLANK(); +#ifdef CONFIG_FTSDMC021 + OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); + OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); + OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); + OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); + OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); + OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); + OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); + OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); +#endif + BLANK(); #ifdef CONFIG_ANDES_PCU OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ #endif @@ -50,5 +77,6 @@ int main(void) OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ #endif + return 0; } diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 7d546eff69..65a5a40b6d 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -6,7 +6,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= nios2-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := nios2-elf- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index 13015ebc21..9902b9adba 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -5,12 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= or32-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := or32-elf- +endif # r10 used for global object pointer, already set in OR32 GCC but just to be # clear PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 - -LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index f75c3bf187..fb7096e7b5 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= ppc_8xx- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := ppc_8xx- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections @@ -33,5 +35,14 @@ endif # Only test once ifneq ($(CONFIG_SPL_BUILD),y) -ALL-y += checkgcc4 +archprepare: checkgcc4 + +# GCC 3.x is reported to have problems generating the type of relocation +# that U-Boot wants. +# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html +checkgcc4: + @if test $(call cc-version) -lt 0400; then \ + echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ + false; \ + fi endif diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c index 10169912b7..9f5bcd7fc3 100644 --- a/arch/powerpc/cpu/mpc512x/traps.c +++ b/arch/powerpc/cpu/mpc512x/traps.c @@ -27,7 +27,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index 92f956db8d..6b196de355 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -19,9 +19,6 @@ #include #include -#define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 517b5808fe..02c706ec63 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -14,9 +14,6 @@ #include #include -#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index a68f9d6598..3c8b2d904f 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -842,104 +842,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h b/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h deleted file mode 100644 index 6264d189bb..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef I2C_EXPORT_H -#define I2C_EXPORT_H - -/**************************************************** - * - * Copyright Motrola 1999 - * - ****************************************************/ - -/* These are the defined return values for the I2C_do_transaction function. - * Any non-zero value indicates failure. Failure modes can be added for - * more detailed error reporting. - */ -typedef enum _i2c_status -{ - I2C_SUCCESS = 0, - I2C_ERROR, -} I2C_Status; - -/* These are the defined tasks for I2C_do_transaction. - * Modes for SLAVE_RCV and SLAVE_XMIT will be added. - */ -typedef enum _i2c_transaction_mode -{ - I2C_MASTER_RCV = 0, - I2C_MASTER_XMIT = 1, -} I2C_TRANSACTION_MODE; - -typedef enum _i2c_interrupt_mode -{ - I2C_INT_DISABLE = 0, - I2C_INT_ENABLE = 1, -} I2C_INTERRUPT_MODE; - -typedef enum _i2c_stop -{ - I2C_NO_STOP = 0, - I2C_STOP = 1, -} I2C_STOP_MODE; - -typedef enum _i2c_restart -{ - I2C_NO_RESTART = 0, - I2C_RESTART = 1, -} I2C_RESTART_MODE; - -/******************** App. API ******************** - * The application API is for user level application - * to use the functionality provided by I2C driver. - * This is a "generic" I2C interface, it should contain - * nothing specific to the Kahlua implementation. - * Only the generic functions are exported by the library. - * - * Note: Its App.s responsibility to swap the data - * byte. In our API, we just transfer whatever - * we are given - **************************************************/ - - -/* Initialize I2C unit with the following: - * driver's slave address - * interrupt enabled - * optional pointer to application layer print function - * - * These parameters may be added: - * desired clock rate - * digital filter frequency sampling rate - * - * This function must be called before I2C unit can be used. - */ -extern I2C_Status I2C_Initialize( - unsigned char addr, /* driver's I2C slave address */ - I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt - * 0 - disable I2C interrupt - */ - int (*app_print_function)(char *,...)); /* pointer to optional "printf" - * provided by application - */ - -/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV - * are implemented. Both are only in polling mode. - * - * en_int controls interrupt/polling mode - * act is the type of transaction - * addr is the I2C address of the slave device - * len is the length of data to send or receive - * buffer is the address of the data buffer - * stop = I2C_NO_STOP, don't signal STOP at end of transaction - * I2C_STOP, signal STOP at end of transaction - * retry is the timeout retry value, currently ignored - * rsta = I2C_NO_RESTART, this is not continuation of existing transaction - * I2C_RESTART, this is a continuation of existing transaction - */ -extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int, - I2C_TRANSACTION_MODE act, - unsigned char i2c_addr, - unsigned char data_addr, - int len, - char *buffer, - I2C_STOP_MODE stop, - int retry, - I2C_RESTART_MODE rsta); -#endif diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 6f397a44c6..b1fb062a08 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -26,8 +26,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk index dfac710e63..59f152df74 100644 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ b/arch/powerpc/cpu/mpc8260/config.mk @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 5a298f9d05..1432344bcc 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -9,9 +9,6 @@ #include #include -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8260/speed.h b/arch/powerpc/cpu/mpc8260/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/arch/powerpc/cpu/mpc8260/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 1269291c45..324f132bad 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -14,9 +14,6 @@ #include #include -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe65ef..36724e5aa5 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,7 +20,6 @@ #include #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include @@ -120,6 +119,11 @@ disable_addr_trans: mtspr SRR1, r3 rfi + .globl get_svr +get_svr: + mfspr r3, SVR + blr + .globl get_pvr get_pvr: mfspr r3, PVR diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 6ff6a70294..cf18be5528 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,12 +18,32 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x02, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x04, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x05, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x06, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x08, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x09, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0B, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, @@ -32,6 +52,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2F, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x30, {AURORA, AURORA, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, CPRI4, CPRI3, CPRI2, CPRI1}}, @@ -44,18 +67,38 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x34, {AURORA, AURORA, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x39, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3D, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x5C, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x5D, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1} }, {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, + {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1} }, {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, @@ -63,6 +106,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, @@ -75,18 +121,30 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x79, {SRIO2, SRIO2, SRIO2, SRIO2, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, @@ -101,6 +159,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 1e5a43f0e0..8b79c05b1f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -156,7 +156,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum CPU-A003999 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) - puts("Work-around for Erratum DDR-A003473 enabled\n"); + puts("Work-around for Erratum DDR-A003474 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); @@ -229,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A005871 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006475 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006475 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006384 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006384 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 /* This work-around is implemented in PBI, so just check for it */ check_erratum_a4849(svr); @@ -264,6 +272,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) puts("Work-around for Erratum I2C-A004447 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + puts("Work-around for Erratum A006261 enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 72c964cd15..1470f95ff1 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; # see "[PATCH,rs6000] make -mno-spe work as expected" on diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b31efb7610..81aeadd363 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -36,6 +36,54 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 +void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) +{ +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE + u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); + + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port1.xcvrprg, xcvrprg); + + xcvrprg = in_be32(&usb_phy->port2.xcvrprg); + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port2.xcvrprg, xcvrprg); +#else + + u32 temp = 0; + u32 status = in_be32(&usb_phy->status1); + + u32 squelch_prog_rd_0_2 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + u32 squelch_prog_rd_3_5 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + setbits_be32(&usb_phy->config1, + CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); + setbits_be32(&usb_phy->config2, + CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); + + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); + + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); +#endif +} +#endif + + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -625,6 +673,10 @@ skip_l2: { struct ccsr_usb_phy __iomem *usb_phy1 = (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy1); +#endif out_be32(&usb_phy1->usb_enable_override, CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); } @@ -633,6 +685,10 @@ skip_l2: { struct ccsr_usb_phy __iomem *usb_phy2 = (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy2); +#endif out_be32(&usb_phy2->usb_enable_override, CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); } @@ -672,8 +728,14 @@ skip_l2: CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); setbits_be32(&usb_phy->port2.pwrfltcfg, CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy); #endif +#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 25db899e5f..70e09eaed5 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -75,6 +75,8 @@ static const char *serdes_prtcl_str[] = { [XFI_FM2_MAC9] = "XFI_FM2_MAC9", [XFI_FM2_MAC10] = "XFI_FM2_MAC10", [INTERLAKEN] = "INTERLAKEN", + [QSGMII_SW1_A] = "QSGMII_SW1_A", + [QSGMII_SW1_B] = "QSGMII_SW1_B", }; #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c15e83b521..fcfba7ec19 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -10,8 +10,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 35867dffdd..adf09efa27 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -151,7 +151,8 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \ + defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #else diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10c5b..dbbd8e588c 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -17,8 +17,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 32075ce220..68160a9512 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -21,21 +21,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(8, 34, 1, 3), SET_QP_INFO(9, 35, 1, 0), SET_QP_INFO(10, 36, 1, 0), - SET_QP_INFO(11, 37, 1, 1), - SET_QP_INFO(12, 38, 1, 1), - SET_QP_INFO(13, 39, 1, 2), - SET_QP_INFO(14, 40, 1, 2), - SET_QP_INFO(15, 41, 1, 3), - SET_QP_INFO(16, 42, 1, 3), - SET_QP_INFO(17, 43, 1, 0), - SET_QP_INFO(18, 44, 1, 0), - SET_QP_INFO(19, 45, 1, 1), - SET_QP_INFO(20, 46, 1, 1), - SET_QP_INFO(21, 47, 1, 2), - SET_QP_INFO(22, 48, 1, 2), - SET_QP_INFO(23, 49, 1, 3), - SET_QP_INFO(24, 50, 1, 3), - SET_QP_INFO(25, 51, 1, 0), }; #endif @@ -60,11 +45,6 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), - /* SET_NEXUS_LIODN(557), -- not yet implemented */ }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); @@ -77,8 +57,6 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), - SET_FMAN_RX_10G_LIODN(1, 0, 94), - SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif @@ -97,23 +75,9 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); -#ifdef CONFIG_SYS_DPAA_RMAN -struct liodn_id_table rman_liodn_tbl[] = { - /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 678), - SET_RMAN_LIODN(1, 679), - SET_RMAN_LIODN(2, 680), - SET_RMAN_LIODN(3, 681), -}; -int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); -#endif - struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), #endif -#ifdef CONFIG_SYS_DPAA_RMAN - [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), -#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 94814ac13e..d86bb27372 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -8,68 +8,59 @@ #include #include #include -#include "fsl_corenet2_serdes.h" -static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = { - { /* SerDes 1 */ - [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, - [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE3, PCIE4, SATA1}, - [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE2, PCIE2, PCIE2}, - [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5}, - [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1}, - [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, PCIE4, SATA1}, - [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, PCIE4, SATA1}, [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SATA2, SATA1}, - [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, + [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, + [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SATA1}, [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, + [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, PCIE3, QSGMII_SW1_B, SATA1}, + [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B}, + [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE2, PCIE2, PCIE2}, - }, - { - }, - { - }, - { - }, + [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, }; - enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) { - return serdes_cfg_tbl[serdes][cfg][lane]; + return serdes_cfg_tbl[cfg][lane]; } int is_serdes_prtcl_valid(int serdes, u32 prtcl) { int i; - if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes])) + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[serdes][prtcl][i] != NONE) + if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 068e1f26bf..0bfd447381 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -53,8 +53,10 @@ struct liodn_id_table liodn_tbl[] = { SET_USB_LIODN(1, "fsl-usb2-mph", 553), SET_USB_LIODN(2, "fsl-usb2-dr", 554), +#ifdef CONFIG_FSL_SATA_V2 SET_SATA_LIODN(1, 555), SET_SATA_LIODN(2, 556), +#endif SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index f2fbdebec1..07e27deb1f 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -43,7 +43,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = { {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, -#if defined(CONFIG_PPC_T2080) {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, @@ -129,7 +128,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = { XFI_FM1_MAC1, XFI_FM1_MAC2, PCIE4, PCIE4, PCIE4, PCIE4} }, -#elif defined(CONFIG_PPC_T2081) +#if defined(CONFIG_PPC_T2081) {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 3ef6e4ae16..24adbc3078 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -35,7 +35,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc132673a5..acaa0939ab 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,7 +57,14 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; -/* FIXME for non-NAND SPL */ + +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#else #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ .bootpg ADDR(.text) + 0x1000 : { @@ -69,12 +76,6 @@ SECTIONS #else #error unknown NAND controller #endif -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index 69a0b96ead..4c7235fcde 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -mstring -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index 0b7ea3b184..92fb537453 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -29,7 +29,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index d40bdab1e1..f83fd5ecf4 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y += start.o extra-y += traps.o diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ea27d59a6c..e774d1e70a 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -9,9 +9,6 @@ #include #include -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 9869bbd183..f8aa93d611 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -26,9 +26,6 @@ #include #include -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index fe928db039..f8d03cba2d 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -49,7 +49,6 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void update_rdcc(void) { u32 val; @@ -72,7 +71,6 @@ static void update_rdcc(void) } } } -#endif #if defined(CONFIG_440) /* @@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) -#if !defined(CONFIG_NAND_SPL) /*-----------------------------------------------------------------------------+ * sdram_memsize *-----------------------------------------------------------------------------*/ @@ -217,7 +214,6 @@ void board_add_ram_info(int use_default) val = (val & SDRAM_MMODE_DCL_MASK) >> 4; printf(", CL%d)", val); } -#endif /* !CONFIG_NAND_SPL */ #if defined(CONFIG_SPD_EEPROM) @@ -2843,16 +2839,6 @@ static void test(void) *---------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { - /* - * Only run this SDRAM init code once. For NAND booting - * targets like Kilauea, we call initdram() early from the - * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). - * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) - * which calls initdram() again. This time the controller - * mustn't be reconfigured again since we're already running - * from SDRAM. - */ -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val; #if defined(CONFIG_440) @@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type) #endif #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /*------------------------------------------------------------------ | DQS calibration. +-----------------------------------------------------------------*/ DQS_autocalibration(); -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ /* @@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type) set_mcsr(get_mcsr()); #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ - return (CONFIG_SYS_MBYTES_SDRAM << 20); } #endif /* CONFIG_SPD_EEPROM */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #if defined(CONFIG_440) u32 mfdcr_any(u32 dcr) { @@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val) } } #endif /* defined(CONFIG_440) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ inline void ppc4xx_ibm_ddr2_register_dump(void) { diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 82823147fe..67f149deef 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -27,12 +27,6 @@ #include "ecc.h" -/* - * Only compile the DDR auto-calibration code for NOR boot and - * not for NAND boot (NAND SPL and NAND U-Boot - NUB) - */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - #define MAXBXCF 4 #define SDRAM_RXBAS_SHIFT_1M 20 @@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void) return 0; } -#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -u32 DQS_autocalibration(void) -{ - return 0; -} -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index 14b520ff9c..4b792ae2d2 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -14,11 +14,7 @@ obj-y += kgdb.o obj-y += 40x_spd_sdram.o -ifndef CONFIG_NAND_SPL -ifndef CONFIG_NAND_U_BOOT obj-y += 44x_spd_ddr.o -endif -endif obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o obj-y += 4xx_pci.o diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index 71c2a6c729..102f069f9e 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -7,8 +7,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_4xx -mstring -msoft-float -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) +cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is440:=$(shell grep CONFIG_440 $(srctree)/include/$(cfg)) ifneq (,$(findstring CONFIG_440,$(is440))) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 0d99391dfb..6b13528c9a 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -10,8 +10,6 @@ #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index dbc4a6c881..f274c5d564 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -10,7 +10,6 @@ #include #define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 38bbc5a9bc..11b55d5a56 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -31,8 +31,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -184,16 +182,13 @@ .extern ext_bus_cntlr_init -#ifdef CONFIG_NAND_U_BOOT - .extern reconfig_tlb0 -#endif /* * Set up GOT: Global Offset Table * * Use r12 to access the GOT */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -207,22 +202,7 @@ GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT -#endif /* CONFIG_NAND_SPL */ - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SPL_BUILD) - /* - * NAND U-Boot image is started from offset 0 - */ - .text -#if defined(CONFIG_440) - bl reconfig_tlb0 -#endif - GET_GOT - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f - /* NOTREACHED - board_init_f() does not return */ -#endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) /* @@ -257,9 +237,7 @@ */ #if defined(CONFIG_440) -#if !defined(CONFIG_NAND_SPL) .section .bootpg,"ax" -#endif .globl _start_440 /**************************************************************************/ @@ -513,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ * r3 - 1st arg to board_init(): IMMP pointer * r4 - 2nd arg to board_init(): boot flag */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) .text .long 0x27051956 /* U-Boot Magic Number */ .globl version_string @@ -779,9 +757,6 @@ _start: stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else #ifndef CONFIG_SPL_BUILD GET_GOT #endif @@ -789,7 +764,6 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ -#endif #endif /* CONFIG_440 */ @@ -1052,9 +1026,6 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CONFIG_SYS_INIT_DCACHE_CS */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ @@ -1062,13 +1033,11 @@ _start: bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */ -#endif /* CONFIG_NAND_SPL */ - #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */ /*----------------------------------------------------------------------- */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) /* * This code finishes saving the registers to the exception frame * and jumps to the appropriate handler for the exception. @@ -1634,7 +1603,7 @@ __440_msr_continue: blr function_epilog(dcbz_area) #endif /* CONFIG_440 */ -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ /*------------------------------------------------------------------------------- */ /* Function: in8 */ @@ -1983,75 +1952,3 @@ pll_wait: blr function_epilog(mftlb1) #endif /* CONFIG_440 */ - -#if defined(CONFIG_NAND_SPL) -/* - * void nand_boot_relocate(dst, src, bytes) - * - * r3 = Destination address to copy code to (in SDRAM) - * r4 = Source address to copy code from - * r5 = size to copy in bytes - */ -nand_boot_relocate: - mr r6,r3 - mr r7,r4 - mflr r8 - - /* - * Copy SPL from icache into SDRAM - */ - subi r3,r3,4 - subi r4,r4,4 - srwi r5,r5,2 - mtctr r5 -..spl_loop: - lwzu r0,4(r4) - stwu r0,4(r3) - bdnz ..spl_loop - - /* - * Calculate "corrected" link register, so that we "continue" - * in execution in destination range - */ - sub r3,r7,r6 /* r3 = src - dst */ - sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ - mtlr r8 - blr - -nand_boot_common: - /* - * First initialize SDRAM. It has to be available *before* calling - * nand_boot(). - */ - lis r3,CONFIG_SYS_SDRAM_BASE@h - ori r3,r3,CONFIG_SYS_SDRAM_BASE@l - bl initdram - - /* - * Now copy the 4k SPL code into SDRAM and continue execution - * from there. - */ - lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h - ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l - lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h - ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l - lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h - ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l - bl nand_boot_relocate - - /* - * We're running from SDRAM now!!! - * - * It is necessary for 4xx systems to relocate from running at - * the original location (0xfffffxxx) to somewhere else (SDRAM - * preferably). This is because CS0 needs to be reconfigured for - * NAND access. And we can't reconfigure this CS when currently - * "running" from it. - */ - - /* - * Finally call nand_boot() to load main NAND U-Boot image from - * NAND and jump to it. - */ - bl nand_boot /* will not return */ -#endif /* CONFIG_NAND_SPL */ diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index fafc15e2e1..d1e78f6b0c 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -847,104 +847,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 54ce2f053c..df44451091 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -22,6 +22,9 @@ #define FSL_DDR_VER_4_7 47 #define FSL_DDR_VER_5_0 50 +/* IP endianness */ +#define CONFIG_SYS_FSL_IFC_BE + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -151,7 +154,9 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 +#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -382,6 +387,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #elif defined(CONFIG_PPC_P3041) @@ -420,6 +426,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ @@ -503,6 +510,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5040) @@ -534,6 +542,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004699 #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 @@ -552,6 +561,7 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) #define CONFIG_MAX_CPUS 2 @@ -575,6 +585,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 @@ -627,6 +638,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 @@ -656,11 +668,14 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006475 +#define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 @@ -673,6 +688,7 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } @@ -714,10 +730,12 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 @@ -762,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 3cac2d4310..c9982cc8ec 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -15,11 +15,49 @@ static inline bool has_erratum_a006379(void) { u32 svr = get_svr(); if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) return true; return false; } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 +static inline bool has_erratum_a006261(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); + case SVR_P3041: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T4240: + case SVR_T4160: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_P5040: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} +#endif + #endif diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 404ded4580..f60cb0a6de 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -69,13 +69,7 @@ enum srds_prtcl { XFI_FM2_MAC9, XFI_FM2_MAC10, INTERLAKEN, - SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ - SGMII_SW1_DTSEC2, - SGMII_SW1_DTSEC3, - SGMII_SW1_DTSEC4, - SGMII_SW1_DTSEC5, - SGMII_SW1_DTSEC6, - QSGMII_SW1_A, /* SW indicates on L2 swtich */ + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ QSGMII_SW1_B, }; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c82453..4b6f9d018e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1722,6 +1722,9 @@ typedef struct ccsr_gur { u32 rstrqpblsr; /* Reset request preboot loader status */ u8 res11[8]; u32 rstrqmr1; /* Reset request mask */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800 +#endif u8 res12[4]; u32 rstrqsr1; /* Reset request status */ u8 res13[4]; @@ -1759,6 +1762,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -2481,6 +2499,7 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_SDEN 0x00000020 #define SRDS_RSTCTL_SDRST_B 0x00000040 #define SRDS_RSTCTL_PLLRST_B 0x00000080 +#define SRDS_RSTCTL_RSTERR_SHIFT 29 u32 pllcr0; /* PLL Control Register 0 */ #define SRDS_PLLCR0_POFF 0x80000000 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 @@ -2490,6 +2509,7 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 @@ -2497,9 +2517,22 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 +#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0 +#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4 u32 pllcr1; /* PLL Control Register 1 */ -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 - u32 res_0c; /* 0x00c */ +#define SRDS_PLLCR1_BCAP_EN 0x20000000 +#define SRDS_PLLCR1_BCAP_OVD 0x10000000 +#define SRDS_PLLCR1_PLL_FCAP 0x001F8000 +#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15 +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 +#define SRDS_PLLCR1_BYP_CAL 0x02000000 + u32 pllsr2; /* At 0x00c, PLL Status Register 2 */ +#define SRDS_PLLSR2_BCAP_EN 0x00800000 +#define SRDS_PLLSR2_BCAP_EN_SHIFT 23 +#define SRDS_PLLSR2_FCAP 0x003F0000 +#define SRDS_PLLSR2_FCAP_SHIFT 16 +#define SRDS_PLLSR2_DCBIAS 0x000F0000 +#define SRDS_PLLSR2_DCBIAS_SHIFT 16 u32 pllcr3; u32 pllcr4; u8 res_18[0x20-0x18]; @@ -2834,6 +2867,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 +#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -2951,6 +2985,10 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) +#define CONFIG_SYS_FSL_SCFG_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) +#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ diff --git a/arch/powerpc/include/asm/iopin_85xx.h b/arch/powerpc/include/asm/iopin_85xx.h deleted file mode 100644 index 0f07ba355e..0000000000 --- a/arch/powerpc/include/asm/iopin_85xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * MPC85xx I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_85xx_H_ -#define _ASM_IOPIN_85xx_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -extern __inline__ void iopin_set_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_85xx_H_ */ diff --git a/arch/powerpc/include/asm/pnp.h b/arch/powerpc/include/asm/pnp.h deleted file mode 100644 index 22ceba2253..0000000000 --- a/arch/powerpc/include/asm/pnp.h +++ /dev/null @@ -1,643 +0,0 @@ -/* 11/02/95 */ -/*----------------------------------------------------------------------------*/ -/* Plug and Play header definitions */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for PnP on PowerPC Reference Platform */ -/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ -/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ -/* This code has extensions to that specification, namely new short and */ -/* long tag types for platform dependent information */ - -/* Warning: LE notation used throughout this file */ - -/* For enum's: if given in hex then they are bit significant, i.e. */ -/* only one bit is on for each enum */ - -#ifndef _PNP_ -#define _PNP_ - -#ifndef __ASSEMBLY__ -#define MAX_MEM_REGISTERS 9 -#define MAX_IO_PORTS 20 -#define MAX_IRQS 7 -/*#define MAX_DMA_CHANNELS 7*/ - -/* Interrupt controllers */ - -#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ -#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ -#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ -#define PNPinterrupt3 "PNP0003" /* APIC */ -#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ - -/* Timers */ - -#define PNPtimer0 "PNP0100" /* AT Timer */ -#define PNPtimer1 "PNP0101" /* EISA Timer */ -#define PNPtimer2 "PNP0102" /* MCA Timer */ - -/* DMA controllers */ - -#define PNPdma0 "PNP0200" /* AT DMA Controller */ -#define PNPdma1 "PNP0201" /* EISA DMA Controller */ -#define PNPdma2 "PNP0202" /* MCA DMA Controller */ - -/* start of August 15, 1994 additions */ -/* CMOS */ -#define PNPCMOS "IBM0009" /* CMOS */ - -/* L2 Cache */ -#define PNPL2 "IBM0007" /* L2 Cache */ - -/* NVRAM */ -#define PNPNVRAM "IBM0008" /* NVRAM */ - -/* Power Management */ -#define PNPPM "IBM0005" /* Power Management */ -/* end of August 15, 1994 additions */ - -/* Keyboards */ - -#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ -#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ -#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ -#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ -#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ -#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ -#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ -#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ - -/* Parallel port controllers */ - -#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ -#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ -#define PNPepp "IBM001C" /* EPP Parallel Port */ - -/* Serial port controllers */ - -#define PNPserial0 "PNP0500" /* Standard PC Serial port */ -#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ - -/* Disk controllers */ - -#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ -#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ -#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ - -/* Diskette controllers */ - -#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ - -/* Display controllers */ - -#define PNPdisplay0 "PNP0900" /* VGA Compatible */ -#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ -#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ -#define PNPdisplay3 "PNP0903" /* Trident VGA */ -#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ -#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ -#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ -#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ -#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ -#define PNPdisplay9 "PNP0909" /* S3 */ -#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ -#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ -#define PNPdisplayC "PNP090C" /* XGA Compatible */ -#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ -#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ -#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ - -/* Peripheral busses */ - -#define PNPbuses0 "PNP0A00" /* ISA Bus */ -#define PNPbuses1 "PNP0A01" /* EISA Bus */ -#define PNPbuses2 "PNP0A02" /* MCA Bus */ -#define PNPbuses3 "PNP0A03" /* PCI Bus */ -#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ - -/* RTC, BIOS, planar devices */ - -#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ -#define PNPrtc0 "PNP0B00" /* AT RTC */ -#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ -#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ -#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ -#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ - -/* PCMCIA controller */ - -#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ - -/* Mice */ - -#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ -#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ -#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ -#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ -#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ -#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ -#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ -#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ -#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ -#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ -#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ -#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ - -/* Modems */ - -#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ - -/* Network controllers */ - -#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ -#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ -#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ -#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ -#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ -#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ -#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ -#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ - -/* SCSI controllers */ - -#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ -#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ -#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ -#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ -#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ -#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ -#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ - -/* Sound/Video, Multimedia */ - -#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ -#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ -#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ -#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ -#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ -#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ -#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ -#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ - -/* Operator Panel */ -#define PNPopctl "IBM000B" /* Operator's panel */ - -/* Service Processor */ -#define PNPsp "IBM0011" /* IBM Service Processor */ -#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ -#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ - -/* Memory Controller */ -#define PNPmemctl "IBM000A" /* Memory controller */ - -/* Graphics Assist */ -#define PNPg_assist "IBM0014" /* Graphics Assist */ - -/* Miscellaneous Device Controllers */ -#define PNPtablet "IBM0019" /* IBM Tablet Controller */ - -/* PNP Packet Handles */ - -#define S1_Packet 0x0A /* Version resource */ -#define S2_Packet 0x15 /* Logical DEVID (without flags) */ -#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ -#define S3_Packet 0x1C /* Compatible device ID */ -#define S4_Packet 0x22 /* IRQ resource (without flags) */ -#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ -#define S5_Packet 0x2A /* DMA resource */ -#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ -#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ -#define S7_Packet 0x38 /* Depend funct end */ -#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ -#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ -#define S14_Packet 0x71 /* Vendor defined */ -#define S15_Packet 0x78 /* End of resource (w/o checksum) */ -#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ -#define L1_Packet 0x81 /* Memory range */ -#define L1_Shadow 0x20 /* Memory is shadowable */ -#define L1_32bit_mem 0x18 /* 32-bit memory only */ -#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ -#define L1_Decode_Hi 0x04 /* decode supports high address */ -#define L1_Cache 0x02 /* read cacheable, write-through */ -#define L1_Writeable 0x01 /* Memory is writeable */ -#define L2_Packet 0x82 /* ANSI ID string */ -#define L3_Packet 0x83 /* Unicode ID string */ -#define L4_Packet 0x84 /* Vendor defined */ -#define L5_Packet 0x85 /* Large I/O */ -#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ -#define END_TAG 0x78 /* End of resource */ -#define DF_START_TAG 0x30 /* Dependent function start */ -#define DF_START_TAG_priority 0x31 /* Dependent function start */ -#define DF_END_TAG 0x38 /* Dependent function end */ -#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ - -/* Device Base Type Codes */ - -typedef enum _PnP_BASE_TYPE { - Reserved = 0, - MassStorageDevice = 1, - NetworkInterfaceController = 2, - DisplayController = 3, - MultimediaController = 4, - MemoryController = 5, - BridgeController = 6, - CommunicationsDevice = 7, - SystemPeripheral = 8, - InputDevice = 9, - ServiceProcessor = 0x0A, /* 11/2/95 */ - } PnP_BASE_TYPE; - -/* Device Sub Type Codes */ - -typedef enum _PnP_SUB_TYPE { - SCSIController = 0, - IDEController = 1, - FloppyController = 2, - IPIController = 3, - OtherMassStorageController = 0x80, - - EthernetController = 0, - TokenRingController = 1, - FDDIController = 2, - OtherNetworkController = 0x80, - - VGAController= 0, - SVGAController= 1, - XGAController= 2, - OtherDisplayController = 0x80, - - VideoController = 0, - AudioController = 1, - OtherMultimediaController = 0x80, - - RAM = 0, - FLASH = 1, - OtherMemoryDevice = 0x80, - - HostProcessorBridge = 0, - ISABridge = 1, - EISABridge = 2, - MicroChannelBridge = 3, - PCIBridge = 4, - PCMCIABridge = 5, - VMEBridge = 6, - OtherBridgeDevice = 0x80, - - RS232Device = 0, - ATCompatibleParallelPort = 1, - OtherCommunicationsDevice = 0x80, - - ProgrammableInterruptController = 0, - DMAController = 1, - SystemTimer = 2, - RealTimeClock = 3, - L2Cache = 4, - NVRAM = 5, - PowerManagement = 6, - CMOS = 7, - OperatorPanel = 8, - ServiceProcessorClass1 = 9, - ServiceProcessorClass2 = 0xA, - ServiceProcessorClass3 = 0xB, - GraphicAssist = 0xC, - SystemPlanar = 0xF, /* 10/5/95 */ - OtherSystemPeripheral = 0x80, - - KeyboardController = 0, - Digitizer = 1, - MouseController = 2, - TabletController = 3, /* 10/27/95 */ - OtherInputController = 0x80, - - GeneralMemoryController = 0, - } PnP_SUB_TYPE; - -/* Device Interface Type Codes */ - -typedef enum _PnP_INTERFACE { - General = 0, - GeneralSCSI = 0, - GeneralIDE = 0, - ATACompatible = 1, - - GeneralFloppy = 0, - Compatible765 = 1, - NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26E_Floppy = 3, /* Ports 26E and 26F */ - NS15C_Floppy = 4, /* Ports 15C and 15D */ - NS2E_Floppy = 5, /* Ports 2E and 2F */ - CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ - - GeneralIPI = 0, - - GeneralEther = 0, - GeneralToken = 0, - GeneralFDDI = 0, - - GeneralVGA = 0, - GeneralSVGA = 0, - GeneralXGA = 0, - - GeneralVideo = 0, - GeneralAudio = 0, - CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ - - GeneralRAM = 0, - GeneralFLASH = 0, - PCIMemoryController = 0, /* PCI Config Method */ - RS6KMemoryController = 1, /* RS6K Config Method */ - - GeneralHostBridge = 0, - GeneralISABridge = 0, - GeneralEISABridge = 0, - GeneralMCABridge = 0, - GeneralPCIBridge = 0, - PCIBridgeDirect = 0, - PCIBridgeIndirect = 1, - PCIBridgeRS6K = 2, - GeneralPCMCIABridge = 0, - GeneralVMEBridge = 0, - - GeneralRS232 = 0, - COMx = 1, - Compatible16450 = 2, - Compatible16550 = 3, - NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26ESerPort = 5, /* Ports 26E and 26F */ - NS15CSerPort = 6, /* Ports 15C and 15D */ - NS2ESerPort = 7, /* Ports 2E and 2F */ - - GeneralParPort = 0, - LPTx = 1, - NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26EParPort = 3, /* Ports 26E and 26F */ - NS15CParPort = 4, /* Ports 15C and 15D */ - NS2EParPort = 5, /* Ports 2E and 2F */ - - GeneralPIC = 0, - ISA_PIC = 1, - EISA_PIC = 2, - MPIC = 3, - RS6K_PIC = 4, - - GeneralDMA = 0, - ISA_DMA = 1, - EISA_DMA = 2, - - GeneralTimer = 0, - ISA_Timer = 1, - EISA_Timer = 2, - GeneralRTC = 0, - ISA_RTC = 1, - - StoreThruOnly = 1, - StoreInEnabled = 2, - RS6KL2Cache = 3, - - IndirectNVRAM = 0, /* Indirectly addressed */ - DirectNVRAM = 1, /* Memory Mapped */ - IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ - - GeneralPowerManagement = 0, - EPOWPowerManagement = 1, - PowerControl = 2, /* d1378 */ - - GeneralCMOS = 0, - - GeneralOPPanel = 0, - HarddiskLight = 1, - CDROMLight = 2, - PowerLight = 3, - KeyLock = 4, - ANDisplay = 5, /* AlphaNumeric Display */ - SystemStatusLED = 6, /* 3 digit 7 segment LED */ - CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ - - GeneralServiceProcessor = 0, - - TransferData = 1, - IGMC32 = 2, - IGMC64 = 3, - - GeneralSystemPlanar = 0, /* 10/5/95 */ - - } PnP_INTERFACE; - -/* PnP resources */ - -/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ - -typedef struct _SERIAL_ID { - unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ - unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ - unsigned char VendorID2; /* Product number - vendor assigned */ - unsigned char VendorID3; /* Product number - vendor assigned */ - -/* Serial number is to provide uniqueness if more than one board of same */ -/* type is in system. Must be "FFFFFFFF" if feature not supported. */ - - unsigned char Serial0; /* Unique serial number bits (7:0) */ - unsigned char Serial1; /* Unique serial number bits (15:8) */ - unsigned char Serial2; /* Unique serial number bits (23:16) */ - unsigned char Serial3; /* Unique serial number bits (31:24) */ - unsigned char Checksum; - } SERIAL_ID; - -typedef enum _PnPItemName { - Unused = 0, - PnPVersion = 1, - LogicalDevice = 2, - CompatibleDevice = 3, - IRQFormat = 4, - DMAFormat = 5, - StartDepFunc = 6, - EndDepFunc = 7, - IOPort = 8, - FixedIOPort = 9, - Res1 = 10, - Res2 = 11, - Res3 = 12, - SmallVendorItem = 14, - EndTag = 15, - MemoryRange = 1, - ANSIIdentifier = 2, - UnicodeIdentifier = 3, - LargeVendorItem = 4, - MemoryRange32 = 5, - MemoryRangeFixed32 = 6, - } PnPItemName; - -/* Define a bunch of access functions for the bits in the tag field */ - -/* Tag type - 0 = small; 1 = large */ -#define tag_type(t) (((t) & 0x80)>>7) -#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) - -/* Small item name is 4 bits - one of PnPItemName enum above */ -#define tag_small_item_name(t) (((t) & 0x78)>>3) -#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) - -/* Small item count is 3 bits - count of further bytes in packet */ -#define tag_small_count(t) ((t) & 0x07) -#define set_tag_count(t,v) (t = (t & 0x78) | (v)) - -/* Large item name is 7 bits - one of PnPItemName enum above */ -#define tag_large_item_name(t) ((t) & 0x7f) -#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) - -/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ - -typedef union _PnP_TAG_PACKET { - struct _S1_Pack{ /* VERSION PACKET */ - unsigned char Tag; /* small tag = 0x0a */ - unsigned char Version[2]; /* PnP version, Vendor version */ - } S1_Pack; - - struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x15 or 0x16 */ - unsigned char DevId[4]; /* Logical device id */ - unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ - } S2_Pack; - - struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x1c */ - unsigned char CompatId[4]; /* Compatible device id */ - } S3_Pack; - - struct _S4_Pack{ /* IRQ PACKET */ - unsigned char Tag; /* small tag = 0x22 or 0x23 */ - unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ - unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ - } S4_Pack; - - struct _S5_Pack{ /* DMA PACKET */ - unsigned char Tag; /* small tag = 0x2a */ - unsigned char DMAMask; /* bit(0) is channel 0 ... */ - unsigned char DMAInfo; - } S5_Pack; - - struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x30 or 0x31 */ - unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ - } S6_Pack; - - struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x38 */ - } S7_Pack; - - struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ - unsigned char Tag; /* small tag x47 */ - unsigned char IOInfo; /* x0 = decode only bits(9:0); */ -#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ - unsigned char RangeMin[2]; /* Min base address */ - unsigned char RangeMax[2]; /* Max base address */ - unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S8_Pack; - - struct _S9_Pack{ /* FIXED I/O PORT PACKET */ - unsigned char Tag; /* small tag = 0x4b */ - unsigned char Range[2]; /* base address 10 bits */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S9_Pack; - - struct _S14_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* small tag = 0x7m m = 1-7 */ - union _S14_Data{ - unsigned char Data[7]; /* Vendor defined */ - struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; - } S14_Data; - } S14_Pack; - - struct _S15_Pack{ /* END PACKET */ - unsigned char Tag; /* small tag = 0x78 or 0x79 */ - unsigned char Check; /* optional - checksum */ - } S15_Pack; - - struct _L1_Pack{ /* MEMORY RANGE PACKET */ - unsigned char Tag; /* large tag = 0x81 */ - unsigned char Count0; /* x09 */ - unsigned char Count1; /* x00 */ - unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ - } L1_Pack; - - struct _L2_Pack{ /* ANSI ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x82 */ - unsigned char Count0; /* Length of string */ - unsigned char Count1; - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L2_Pack; - - struct _L3_Pack{ /* UNICODE ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x83 */ - unsigned char Count0; /* Length + 2 of string */ - unsigned char Count1; - unsigned char Country0; /* TBD */ - unsigned char Country1; /* TBD */ - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L3_Pack; - - struct _L4_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* large tag = 0x84 */ - unsigned char Count0; - unsigned char Count1; - union _L4_Data{ - unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ - struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; - } L4_Data; - } L4_Pack; - - struct _L5_Pack{ - unsigned char Tag; /* large tag = 0x85 */ - unsigned char Count0; /* Count = 17 */ - unsigned char Count1; - unsigned char Data[17]; - } L5_Pack; - - struct _L6_Pack{ - unsigned char Tag; /* large tag = 0x86 */ - unsigned char Count0; /* Count = 9 */ - unsigned char Count1; - unsigned char Data[9]; - } L6_Pack; - - } PnP_TAG_PACKET; - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _PNP_ */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 831804c5c5..72f30feee6 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1356,7 +1356,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #elif defined(CONFIG_GEMINI) #define _machine _MACH_gemini #define have_of 0 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define _machine _MACH_8260 #define have_of 0 #elif defined(CONFIG_SANDPOINT) diff --git a/arch/powerpc/include/asm/residual.h b/arch/powerpc/include/asm/residual.h deleted file mode 100644 index dc85edbc3c..0000000000 --- a/arch/powerpc/include/asm/residual.h +++ /dev/null @@ -1,331 +0,0 @@ -/* 7/18/95 */ -/*----------------------------------------------------------------------------*/ -/* Residual Data header definitions and prototypes */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for RESIDUAL on PowerPC Reference Platform */ -/* residual.h - Residual data structure passed in r3. */ -/* Load point passed in r4 to boot image. */ -/* For enum's: if given in hex then they are bit significant, */ -/* i.e. only one bit is on for each enum */ -/* Reserved fields must be filled with zeros. */ - -#ifndef _RESIDUAL_ -#define _RESIDUAL_ - -#ifndef __ASSEMBLY__ - -#define MAX_CPUS 32 /* These should be set to the maximum */ -#define MAX_MEMS 64 /* number possible for this system. */ -#define MAX_DEVICES 256 /* Changing these will change the */ -#define AVE_PNP_SIZE 32 /* structure, hence the version of */ -#define MAX_MEM_SEGS 64 /* this header file. */ - -/*----------------------------------------------------------------------------*/ -/* Public structures... */ -/*----------------------------------------------------------------------------*/ - -#include "pnp.h" - -typedef enum _L1CACHE_TYPE { - NoneCAC = 0, - SplitCAC = 1, - CombinedCAC = 2 - } L1CACHE_TYPE; - -typedef enum _TLB_TYPE { - NoneTLB = 0, - SplitTLB = 1, - CombinedTLB = 2 - } TLB_TYPE; - -typedef enum _FIRMWARE_SUPPORT { - Conventional = 0x01, - OpenFirmware = 0x02, - Diagnostics = 0x04, - LowDebug = 0x08, - Multiboot = 0x10, - LowClient = 0x20, - Hex41 = 0x40, - FAT = 0x80, - ISO9660 = 0x0100, - SCSI_InitiatorID_Override = 0x0200, - Tape_Boot = 0x0400, - FW_Boot_Path = 0x0800 - } FIRMWARE_SUPPORT; - -typedef enum _FIRMWARE_SUPPLIERS { - IBMFirmware = 0x00, - MotoFirmware = 0x01, /* 7/18/95 */ - FirmWorks = 0x02, /* 10/5/95 */ - Bull = 0x03, /* 04/03/96 */ - } FIRMWARE_SUPPLIERS; - -typedef enum _ENDIAN_SWITCH_METHODS { - UsePort92 = 0x01, - UsePCIConfigA8 = 0x02, - UseFF001030 = 0x03, - } ENDIAN_SWITCH_METHODS; - -typedef enum _SPREAD_IO_METHODS { - UsePort850 = 0x00, -/*UsePCIConfigA8 = 0x02,*/ - } SPREAD_IO_METHODS; - -typedef struct _VPD { - - /* Box dependent stuff */ - unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ - unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ - unsigned char Reserved[48]; - unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ - unsigned long FirmwareSupports; /* See FirmwareSupport enum */ - unsigned long NvramSize; /* Size of nvram in bytes */ - unsigned long NumSIMMSlots; - unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ - unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ - unsigned long SmpIar; - unsigned long RAMErrLogOffset; /* Heap offset to error log */ - unsigned long Reserved5; - unsigned long Reserved6; - unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ - unsigned long ProcessorBusHz; /* Processor bus clock frequency */ - unsigned long Reserved7; - unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ - unsigned long WordWidth; /* Word width in bits */ - unsigned long PageSize; /* Page size in bytes */ - unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ - unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ - - /* L1 Cache variables */ - unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ - unsigned long CacheAttrib; /* L1CACHE_TYPE */ - unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ - unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ - /* For split L1 Cache: (= combined if combined cache) */ - unsigned long I_CacheSize; - unsigned long I_CacheAssoc; - unsigned long I_CacheLineSize; - unsigned long D_CacheSize; - unsigned long D_CacheAssoc; - unsigned long D_CacheLineSize; - - /* Translation Lookaside Buffer variables */ - unsigned long TLBSize; /* Total number of TLBs on the system */ - unsigned long TLBAttrib; /* Combined I+D or split TLB */ - unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ - /* For split TLB: (= combined if combined TLB) */ - unsigned long I_TLBSize; - unsigned long I_TLBAssoc; - unsigned long D_TLBSize; - unsigned long D_TLBAssoc; - - unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ - } VPD; - -typedef enum _DEVICE_FLAGS { - Enabled = 0x4000, /* 1 - PCI device is enabled */ - Integrated = 0x2000, - Failed = 0x1000, /* 1 - device failed POST code tests */ - Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ - Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ - Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ - Configurable = 0x0100, /* 1 - device is configurable */ - Disableable = 0x80, /* 1 - device can be disabled */ - PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ - ReadOnly = 0x20, /* 1 - device is read only */ - Removable = 0x10, /* 1 - device is removable */ - ConsoleIn = 0x08, - ConsoleOut = 0x04, - Input = 0x02, - Output = 0x01 - } DEVICE_FLAGS; - -typedef enum _BUS_ID { - ISADEVICE = 0x01, - EISADEVICE = 0x02, - PCIDEVICE = 0x04, - PCMCIADEVICE = 0x08, - PNPISADEVICE = 0x10, - MCADEVICE = 0x20, - MXDEVICE = 0x40, /* Devices on mezzanine bus */ - PROCESSORDEVICE = 0x80, /* Devices on processor bus */ - VMEDEVICE = 0x100, - } BUS_ID; - -typedef struct _DEVICE_ID { - unsigned long BusId; /* See BUS_ID enum above */ - unsigned long DevId; /* Big Endian format */ - unsigned long SerialNum; /* For multiple usage of a single - DevId */ - unsigned long Flags; /* See DEVICE_FLAGS enum above */ - unsigned char BaseType; /* See pnp.h for bit definitions */ - unsigned char SubType; /* See pnp.h for bit definitions */ - unsigned char Interface; /* See pnp.h for bit definitions */ - unsigned char Spare; - } DEVICE_ID; - -typedef union _BUS_ACCESS { - struct _PnPAccess{ - unsigned char CSN; - unsigned char LogicalDevNumber; - unsigned short ReadDataPort; - } PnPAccess; - struct _ISAAccess{ - unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ - unsigned char LogicalDevNumber; - unsigned short ISAReserved; - } ISAAccess; - struct _MCAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short MCAReserved; - } MCAAccess; - struct _PCMCIAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short PCMCIAReserved; - } PCMCIAAccess; - struct _EISAAccess{ - unsigned char SlotNumber; - unsigned char FunctionNumber; - unsigned short EISAReserved; - } EISAAccess; - struct _PCIAccess{ - unsigned char BusNumber; - unsigned char DevFuncNumber; - unsigned short PCIReserved; - } PCIAccess; - struct _ProcBusAccess{ - unsigned char BusNumber; - unsigned char BUID; - unsigned short ProcBusReserved; - } ProcBusAccess; - } BUS_ACCESS; - -/* Per logical device information */ -typedef struct _PPC_DEVICE { - DEVICE_ID DeviceId; - BUS_ACCESS BusAccess; - - /* The following three are offsets into the DevicePnPHeap */ - /* All are in PnP compressed format */ - unsigned long AllocatedOffset; /* Allocated resource description */ - unsigned long PossibleOffset; /* Possible resource description */ - unsigned long CompatibleOffset; /* Compatible device identifiers */ - } PPC_DEVICE; - -typedef enum _CPU_STATE { - CPU_GOOD = 0, /* CPU is present, and active */ - CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ - CPU_OFF = 2, /* CPU is present, but inactive */ - CPU_FAILED = 3, /* CPU is present, but failed POST */ - CPU_NOT_PRESENT = 255 /* CPU not present */ - } CPU_STATE; - -typedef struct _PPC_CPU { - unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ - unsigned char CpuNumber; /* CPU Number for this processor */ - unsigned char CpuState; /* CPU State, see CPU_STATE enum */ - unsigned short Reserved; - } PPC_CPU; - -typedef struct _PPC_MEM { - unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ - } PPC_MEM; - -typedef enum _MEM_USAGE { - Other = 0x8000, - ResumeBlock = 0x4000, /* for use by power management */ - SystemROM = 0x2000, /* Flash memory (populated) */ - UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ - IOMemory = 0x0800, - SystemIO = 0x0400, - SystemRegs = 0x0200, - PCIAddr = 0x0100, - PCIConfig = 0x80, - ISAAddr = 0x40, - Unpopulated = 0x20, /* Unpopulated part of System Memory */ - Free = 0x10, /* Free part of System Memory */ - BootImage = 0x08, /* BootImage part of System Memory */ - FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ - FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ - FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ - } MEM_USAGE; - -typedef struct _MEM_MAP { - unsigned long Usage; /* See MEM_USAGE above */ - unsigned long BasePage; /* Page number measured in 4KB pages */ - unsigned long PageCount; /* Page count measured in 4KB pages */ - } MEM_MAP; - -typedef struct _RESIDUAL { - unsigned long ResidualLength; /* Length of Residual */ - unsigned char Version; /* of this data structure */ - unsigned char Revision; /* of this data structure */ - unsigned short EC; /* of this data structure */ - /* VPD */ - VPD VitalProductData; - /* CPU */ - unsigned short MaxNumCpus; /* Max CPUs in this system */ - unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ - PPC_CPU Cpus[MAX_CPUS]; - /* Memory */ - unsigned long TotalMemory; /* Total amount of memory installed */ - unsigned long GoodMemory; /* Total amount of good memory */ - unsigned long ActualNumMemSegs; - MEM_MAP Segs[MAX_MEM_SEGS]; - unsigned long ActualNumMemories; - PPC_MEM Memories[MAX_MEMS]; - /* Devices */ - unsigned long ActualNumDevices; - PPC_DEVICE Devices[MAX_DEVICES]; - unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; - } RESIDUAL; - - -extern RESIDUAL *res; -extern void print_residual_device_info(void); -extern PPC_DEVICE *residual_find_device(unsigned long BusMask, - unsigned char * DevID, int BaseType, - int SubType, int Interface, int n); -extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, - int n); -extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -#endif /* __ASSEMBLY__ */ -#endif /* ndef _RESIDUAL_ */ diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h index 037570993a..441619042d 100644 --- a/arch/powerpc/include/asm/status_led.h +++ b/arch/powerpc/include/asm/status_led.h @@ -11,7 +11,7 @@ #ifndef CONFIG_BOARD_SPECIFIC_LED # if defined(CONFIG_8xx) # include -# elif defined(CONFIG_8260) +# elif defined(CONFIG_MPC8260) # include # elif defined(CONFIG_5xx) # include diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 5916f7ce99..3c28420574 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -35,7 +35,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index a706d3cc70..0f6298269a 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -7,11 +7,7 @@ ## Build a couple of necessary functions into a private libgcc ## if the user asked for it -ifdef USE_PRIVATE_LIBGCC -lib-y += _ashldi3.o -lib-y += _ashrdi3.o -lib-y += _lshrdi3.o -endif +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o MINIMAL= @@ -54,11 +50,11 @@ ifndef CONFIG_SPL_BUILD # Workaround for local bus unaligned access problems # on MPC512x and MPC5200 ifdef CONFIG_MPC512X -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif ifdef CONFIG_MPC5200 -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif endif diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 34bbfca554..f86c6f3e8f 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -277,10 +277,10 @@ static init_fnc_t *init_sequence[] = { serial_init, console_init_f, display_options, -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) prt_8260_rsr, prt_8260_clks, -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ #if defined(CONFIG_MPC83xx) prt_83xx_rsr, #endif @@ -312,17 +312,6 @@ static init_fnc_t *init_sequence[] = { NULL, /* Terminate this list */ }; -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - static int __fixup_cpu(void) { return 0; @@ -343,13 +332,6 @@ int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); * initialized, and stack space is limited to a few kB. */ -#ifdef CONFIG_LOGBUFFER -unsigned long logbuffer_base(void) -{ - return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; -} -#endif - void board_init_f(ulong bootflag) { bd_t *bd; @@ -522,7 +504,7 @@ void board_init_f(ulong bootflag) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif -#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 41fc8f7ff7..33099a492d 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern ulong get_effective_memsize(void); static ulong get_sp (void); extern void ft_fixup_num_cores(void *blob); static void set_clocks_in_mhz (bd_t *kbd); @@ -54,6 +53,13 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); +#ifdef CONFIG_BOOTSTAGE_FDT + bootstage_fdt_add_report(); +#endif +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif + #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 19a56dbe21..01a7708aef 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -159,7 +159,7 @@ kgdb_trap(struct pt_regs *regs) #define SPACE_REQUIRED ((32*4)+(32*8)+(6*4)) -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 /* store floating double indexed */ #define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) /* store floating double multiple */ @@ -190,7 +190,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) *ptr++ = regs->gpr[i]; /* Floating Point Regs */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 STFDM(ptr); ptr += 32*2; #else @@ -213,7 +213,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) /* set the value of the CPU registers */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 /* load floating double */ #define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) /* load floating double indexed */ @@ -252,7 +252,7 @@ kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) regs->gpr[regno] = *ptr; else switch (regno) { -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 #define caseF(n) \ case (n) + 32: LFD(n, *ptr); break; @@ -298,7 +298,7 @@ kgdb_putregs(struct pt_regs *regs, char *buf, int length) regs->gpr[i] = *ptr++; /* Floating Point Regs */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 LFDM(ptr); #endif ptr += 32*2; diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 6142dd4c70..e094ae2d05 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -5,5 +5,16 @@ PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD PLATFORM_LIBS += -lrt +ifdef CONFIG_SANDBOX_SDL +PLATFORM_LIBS += $(shell sdl-config --libs) +PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) +endif + # Support generic board on sandbox __HAVE_ARCH_GENERIC_BOARD := y + +cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ + -Wl,--start-group $(u-boot-main) -Wl,--end-group \ + $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map + +CONFIG_ARCH_DEVICE_TREE := sandbox diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 58c2537762..7d4410c42a 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -8,9 +8,15 @@ # obj-y := cpu.o os.o start.o state.o +obj-$(CONFIG_SANDBOX_SDL) += sdl.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) -$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) +# CFLAGS_REMOVE_os.o cannot be used to drop header include path +quiet_cmd_cc_os.o = CC $(quiet_modtag) $@ +cmd_cc_os.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/os.o: $(src)/os.c FORCE + $(call if_changed_dep,cc_os.o) +$(obj)/sdl.o: $(src)/sdl.c FORCE + $(call if_changed_dep,cc_os.o) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 38019e0b48..3f4005b5d7 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -58,7 +58,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) return (void *)(gd->arch.ram_buf + paddr); } -phys_addr_t map_to_sysmem(void *ptr) +phys_addr_t map_to_sysmem(const void *ptr) { return (u8 *)ptr - gd->arch.ram_buf; } diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 725b505177..57d04a45b2 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -92,6 +92,11 @@ int os_close(int fd) return close(fd); } +int os_unlink(const char *pathname) +{ + return unlink(pathname); +} + void os_exit(int exit_code) { exit(exit_code); @@ -99,21 +104,22 @@ void os_exit(int exit_code) /* Restore tty state when we exit */ static struct termios orig_term; +static bool term_setup; static void os_fd_restore(void) { - tcsetattr(0, TCSANOW, &orig_term); + if (term_setup) + tcsetattr(0, TCSANOW, &orig_term); } /* Put tty into raw mode so and work */ -void os_tty_raw(int fd) +void os_tty_raw(int fd, bool allow_sigs) { - static int setup = 0; struct termios term; - if (setup) + if (term_setup) return; - setup = 1; + term_setup = true; /* If not a tty, don't complain */ if (tcgetattr(fd, &orig_term)) @@ -123,7 +129,7 @@ void os_tty_raw(int fd) term.c_iflag = IGNBRK | IGNPAR; term.c_oflag = OPOST | ONLCR; term.c_cflag = CS8 | CREAD | CLOCAL; - term.c_lflag = 0; + term.c_lflag = allow_sigs ? ISIG : 0; if (tcsetattr(fd, TCSANOW, &term)) return; @@ -143,7 +149,7 @@ void *os_malloc(size_t length) return hdr + 1; } -void *os_free(void *ptr) +void os_free(void *ptr) { struct os_mem_hdr *hdr = ptr; @@ -438,3 +444,93 @@ int os_read_ram_buf(const char *fname) return 0; } + +static int make_exec(char *fname, const void *data, int size) +{ + int fd; + + strcpy(fname, "/tmp/u-boot.jump.XXXXXX"); + fd = mkstemp(fname); + if (fd < 0) + return -ENOENT; + if (write(fd, data, size) < 0) + return -EIO; + close(fd); + if (chmod(fname, 0777)) + return -ENOEXEC; + + return 0; +} + +static int add_args(char ***argvp, const char *add_args[], int count) +{ + char **argv; + int argc; + + for (argv = *argvp, argc = 0; (*argvp)[argc]; argc++) + ; + + argv = malloc((argc + count + 1) * sizeof(char *)); + if (!argv) { + printf("Out of memory for %d argv\n", count); + return -ENOMEM; + } + memcpy(argv, *argvp, argc * sizeof(char *)); + memcpy(argv + argc, add_args, count * sizeof(char *)); + argv[argc + count] = NULL; + + *argvp = argv; + return 0; +} + +int os_jump_to_image(const void *dest, int size) +{ + struct sandbox_state *state = state_get_current(); + char fname[30], mem_fname[30]; + int fd, err; + const char *extra_args[5]; + char **argv = state->argv; +#ifdef DEBUG + int argc, i; +#endif + + err = make_exec(fname, dest, size); + if (err) + return err; + + strcpy(mem_fname, "/tmp/u-boot.mem.XXXXXX"); + fd = mkstemp(mem_fname); + if (fd < 0) + return -ENOENT; + close(fd); + err = os_write_ram_buf(mem_fname); + if (err) + return err; + + os_fd_restore(); + + extra_args[0] = "-j"; + extra_args[1] = fname; + extra_args[2] = "-m"; + extra_args[3] = mem_fname; + extra_args[4] = "--rm_memory"; + err = add_args(&argv, extra_args, + sizeof(extra_args) / sizeof(extra_args[0])); + if (err) + return err; + +#ifdef DEBUG + for (i = 0; argv[i]; i++) + printf("%d %s\n", i, argv[i]); +#endif + + if (state_uninit()) + os_exit(2); + + err = execv(fname, argv); + free(argv); + if (err) + return err; + + return unlink(fname); +} diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c new file mode 100644 index 0000000000..18dc7edf19 --- /dev/null +++ b/arch/sandbox/cpu/sdl.c @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct sdl_info { + SDL_Surface *screen; + int width; + int height; + int depth; + int pitch; + uint frequency; + uint audio_pos; + uint audio_size; + uint8_t *audio_data; + bool audio_active; + bool inited; +} sdl; + +static void sandbox_sdl_poll_events(void) +{ + /* + * We don't want to include common.h in this file since it uses + * system headers. So add a declation here. + */ + extern void reset_cpu(unsigned long addr); + SDL_Event event; + + while (SDL_PollEvent(&event)) { + switch (event.type) { + case SDL_QUIT: + puts("LCD window closed - quitting\n"); + reset_cpu(1); + break; + } + } +} + +static int sandbox_sdl_ensure_init(void) +{ + if (!sdl.inited) { + if (SDL_Init(0) < 0) { + printf("Unable to initialize SDL: %s\n", + SDL_GetError()); + return -EIO; + } + + atexit(SDL_Quit); + + sdl.inited = true; + } + return 0; +} + +int sandbox_sdl_init_display(int width, int height, int log2_bpp) +{ + struct sandbox_state *state = state_get_current(); + int err; + + if (!width || !state->show_lcd) + return 0; + err = sandbox_sdl_ensure_init(); + if (err) + return err; + if (SDL_InitSubSystem(SDL_INIT_VIDEO) < 0) { + printf("Unable to initialize SDL LCD: %s\n", SDL_GetError()); + return -EPERM; + } + SDL_WM_SetCaption("U-Boot", "U-Boot"); + + sdl.width = width; + sdl.height = height; + sdl.depth = 1 << log2_bpp; + sdl.pitch = sdl.width * sdl.depth / 8; + sdl.screen = SDL_SetVideoMode(width, height, 0, 0); + sandbox_sdl_poll_events(); + + return 0; +} + +int sandbox_sdl_sync(void *lcd_base) +{ + SDL_Surface *frame; + + frame = SDL_CreateRGBSurfaceFrom(lcd_base, sdl.width, sdl.height, + sdl.depth, sdl.pitch, + 0x1f << 11, 0x3f << 5, 0x1f << 0, 0); + SDL_BlitSurface(frame, NULL, sdl.screen, NULL); + SDL_FreeSurface(frame); + SDL_UpdateRect(sdl.screen, 0, 0, 0, 0); + sandbox_sdl_poll_events(); + + return 0; +} + +#define NONE (-1) +#define NUM_SDL_CODES (SDLK_UNDO + 1) + +static int16_t sdl_to_keycode[NUM_SDL_CODES] = { + /* 0 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, KEY_BACKSPACE, KEY_TAB, + NONE, NONE, NONE, KEY_ENTER, NONE, + NONE, NONE, NONE, NONE, KEY_POWER, /* use PAUSE as POWER */ + + /* 20 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, KEY_ESC, NONE, NONE, + NONE, NONE, KEY_SPACE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 40 */ + NONE, NONE, NONE, NONE, KEY_COMMA, + KEY_MINUS, KEY_DOT, KEY_SLASH, KEY_0, KEY_1, + KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, + KEY_7, KEY_8, KEY_9, NONE, KEY_SEMICOLON, + + /* 60 */ + NONE, KEY_EQUAL, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 80 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, KEY_BACKSLASH, NONE, NONE, + NONE, KEY_GRAVE, KEY_A, KEY_B, KEY_C, + + /* 100 */ + KEY_D, KEY_E, KEY_F, KEY_G, KEY_H, + KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, + KEY_N, KEY_O, KEY_P, KEY_Q, KEY_R, + KEY_S, KEY_T, KEY_U, KEY_V, KEY_W, + + /* 120 */ + KEY_X, KEY_Y, KEY_Z, NONE, NONE, + NONE, NONE, KEY_DELETE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 140 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 160 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 180 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 200 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 220 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 240 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, KEY_KP0, KEY_KP1, KEY_KP2, KEY_KP3, + + /* 260 */ + KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, KEY_KP8, + KEY_KP9, KEY_KPDOT, KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS, + KEY_KPPLUS, KEY_KPENTER, KEY_KPEQUAL, KEY_UP, KEY_DOWN, + KEY_RIGHT, KEY_LEFT, KEY_INSERT, KEY_HOME, KEY_END, + + /* 280 */ + KEY_PAGEUP, KEY_PAGEDOWN, KEY_F1, KEY_F2, KEY_F3, + KEY_F4, KEY_F5, KEY_F6, KEY_F7, KEY_F8, + KEY_F9, KEY_F10, KEY_F11, KEY_F12, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 300 */ + KEY_NUMLOCK, KEY_CAPSLOCK, KEY_SCROLLLOCK, KEY_RIGHTSHIFT, + KEY_LEFTSHIFT, + KEY_RIGHTCTRL, KEY_LEFTCTRL, KEY_RIGHTALT, KEY_LEFTALT, KEY_RIGHTMETA, + KEY_LEFTMETA, NONE, KEY_FN, NONE, KEY_COMPOSE, + NONE, KEY_PRINT, KEY_SYSRQ, KEY_PAUSE, NONE, + + /* 320 */ + NONE, NONE, NONE, +}; + +int sandbox_sdl_scan_keys(int key[], int max_keys) +{ + Uint8 *keystate; + int i, count; + + sandbox_sdl_poll_events(); + keystate = SDL_GetKeyState(NULL); + for (i = count = 0; i < NUM_SDL_CODES; i++) { + if (count >= max_keys) + break; + else if (keystate[i]) + key[count++] = sdl_to_keycode[i]; + } + + return count; +} + +int sandbox_sdl_key_pressed(int keycode) +{ + int key[8]; /* allow up to 8 keys to be pressed at once */ + int count; + int i; + + count = sandbox_sdl_scan_keys(key, sizeof(key) / sizeof(key[0])); + for (i = 0; i < count; i++) { + if (key[i] == keycode) + return 0; + } + + return -ENOENT; +} + +void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) +{ + int avail; + + avail = sdl.audio_size - sdl.audio_pos; + if (avail < len) + len = avail; + + SDL_MixAudio(stream, sdl.audio_data + sdl.audio_pos, len, + SDL_MIX_MAXVOLUME); + sdl.audio_pos += len; + + /* Loop if we are at the end */ + if (sdl.audio_pos == sdl.audio_size) + sdl.audio_pos = 0; +} + +int sandbox_sdl_sound_init(void) +{ + SDL_AudioSpec wanted; + + if (sandbox_sdl_ensure_init()) + return -1; + + if (sdl.audio_active) + return 0; + + /* + * At present all sandbox sounds crash. This is probably due to + * symbol name conflicts with U-Boot. We can remove the malloc() + * probles with: + * + * #define USE_DL_PREFIX + * + * and get this: + * + * Assertion 'e->pollfd->fd == e->fd' failed at pulse/mainloop.c:676, + * function dispatch_pollfds(). Aborting. + * + * The right solution is probably to make U-Boot's names private or + * link os.c and sdl.c against their libraries before liking with + * U-Boot. TBD. For now sound is disabled. + */ + printf("(Warning: sandbox sound disabled)\n"); + return 0; + + /* Set the audio format */ + wanted.freq = 22050; + wanted.format = AUDIO_S16; + wanted.channels = 1; /* 1 = mono, 2 = stereo */ + wanted.samples = 1024; /* Good low-latency value for callback */ + wanted.callback = sandbox_sdl_fill_audio; + wanted.userdata = NULL; + + sdl.audio_size = sizeof(uint16_t) * wanted.freq; + sdl.audio_data = malloc(sdl.audio_size); + if (!sdl.audio_data) { + printf("%s: Out of memory\n", __func__); + return -1; + } + sdl.audio_pos = 0; + + if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0) { + printf("Unable to initialize SDL audio: %s\n", SDL_GetError()); + goto err; + } + + /* Open the audio device, forcing the desired format */ + if (SDL_OpenAudio(&wanted, NULL) < 0) { + printf("Couldn't open audio: %s\n", SDL_GetError()); + goto err; + } + sdl.audio_active = true; + + return 0; + +err: + free(sdl.audio_data); + return -1; +} + +int sandbox_sdl_sound_start(uint frequency) +{ + if (!sdl.audio_active) + return -1; + sdl.frequency = frequency; + sound_create_square_wave((unsigned short *)sdl.audio_data, + sdl.audio_size, frequency); + sdl.audio_pos = 0; + SDL_PauseAudio(0); + + return 0; +} + +int sandbox_sdl_sound_stop(void) +{ + if (!sdl.audio_active) + return -1; + SDL_PauseAudio(1); + + return 0; +} diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 1df21d49fa..aad3b8b147 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -107,6 +107,16 @@ static int sandbox_cmdline_cb_interactive(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(interactive, 'i', 0, "Enter interactive mode"); +static int sandbox_cmdline_cb_jump(struct sandbox_state *state, + const char *arg) +{ + /* Remember to delete this U-Boot image later */ + state->jumped_fname = arg; + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(jump, 'j', 1, "Jumped from previous U-Boot"); + static int sandbox_cmdline_cb_memory(struct sandbox_state *state, const char *arg) { @@ -126,6 +136,15 @@ static int sandbox_cmdline_cb_memory(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(memory, 'm', 1, "Read/write ram_buf memory contents from file"); +static int sandbox_cmdline_cb_rm_memory(struct sandbox_state *state, + const char *arg) +{ + state->ram_buf_rm = true; + + return 0; +} +SANDBOX_CMDLINE_OPT(rm_memory, 0, "Remove memory file after reading"); + static int sandbox_cmdline_cb_state(struct sandbox_state *state, const char *arg) { @@ -159,6 +178,43 @@ static int sandbox_cmdline_cb_ignore_missing(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(ignore_missing, 'n', 0, "Ignore missing state on read"); +static int sandbox_cmdline_cb_show_lcd(struct sandbox_state *state, + const char *arg) +{ + state->show_lcd = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(show_lcd, 'l', 0, + "Show the sandbox LCD display"); + +static const char *term_args[STATE_TERM_COUNT] = { + "raw-with-sigs", + "raw", + "cooked", +}; + +static int sandbox_cmdline_cb_terminal(struct sandbox_state *state, + const char *arg) +{ + int i; + + for (i = 0; i < STATE_TERM_COUNT; i++) { + if (!strcmp(arg, term_args[i])) { + state->term_raw = i; + return 0; + } + } + + printf("Unknown terminal setting '%s' (", arg); + for (i = 0; i < STATE_TERM_COUNT; i++) + printf("%s%s", i ? ", " : "", term_args[i]); + puts(")\n"); + + return 1; +} +SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1, + "Set terminal to raw/cooked mode"); + int main(int argc, char *argv[]) { struct sandbox_state *state; @@ -176,6 +232,10 @@ int main(int argc, char *argv[]) if (ret) goto err; + /* Remove old memory file if required */ + if (state->ram_buf_rm && state->ram_buf_fname) + os_unlink(state->ram_buf_fname); + /* Do pre- and post-relocation init */ board_init_f(0); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a145808a52..59adad653c 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -365,7 +365,7 @@ int state_uninit(void) state = &main_state; - if (state->write_ram_buf) { + if (state->write_ram_buf && !state->ram_buf_rm) { err = os_write_ram_buf(state->ram_buf_fname); if (err) { printf("Failed to write RAM buffer\n"); @@ -380,6 +380,10 @@ int state_uninit(void) } } + /* Delete this at the last moment so as not to upset gdb too much */ + if (state->jumped_fname) + os_unlink(state->jumped_fname); + if (state->state_fdt) os_free(state->state_fdt); memset(state, '\0', sizeof(*state)); diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile new file mode 100644 index 0000000000..a4c980b235 --- /dev/null +++ b/arch/sandbox/dts/Makefile @@ -0,0 +1,11 @@ +dtb-$(CONFIG_SANDBOX) += sandbox.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts new file mode 100644 index 0000000000..62d803789c --- /dev/null +++ b/arch/sandbox/dts/sandbox.dts @@ -0,0 +1,116 @@ +/dts-v1/; + +/ { + triangle { + compatible = "demo-shape"; + colour = "cyan"; + sides = <3>; + character = <83>; + }; + square { + compatible = "demo-shape"; + colour = "blue"; + sides = <4>; + }; + hexagon { + compatible = "demo-simple"; + colour = "white"; + sides = <6>; + }; + + host@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sandbox,host-emulation"; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* Information for sandbox */ + ro { + reg = <0 0xf000>; + }; + wp-ro { + reg = <0xf000 0x1000>; + }; + rw { + reg = <0x10000 0x10000>; + }; + }; + }; + }; + + lcd { + compatible = "sandbox,lcd-sdl"; + xres = <800>; + yres = <600>; + }; + + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + google,key-rows = <8>; + google,key-columns = <13>; + google,repeat-delay-ms = <240>; + google,repeat-rate-ms = <30>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + +}; diff --git a/arch/sandbox/include/asm/arch-sandbox/sound.h b/arch/sandbox/include/asm/arch-sandbox/sound.h new file mode 100644 index 0000000000..a32e8c802d --- /dev/null +++ b/arch/sandbox/include/asm/arch-sandbox/sound.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SOUND_H +#define __SANDBOX_SOUND_H + +int sound_play(unsigned int msec, unsigned int frequency); + +int sound_init(const void *blob); + +#endif diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index afb9c7842f..95b59da6b4 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -29,7 +29,7 @@ * @param gp GPIO number * @return -1 on error, 0 if GPIO is low, >0 if high */ -int sandbox_gpio_get_value(unsigned gp); +int sandbox_gpio_get_value(struct device *dev, unsigned int offset); /** * Set the simulated value of a GPIO (used only in sandbox test code) @@ -38,7 +38,7 @@ int sandbox_gpio_get_value(unsigned gp); * @param value value to set (0 for low, non-zero for high) * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_value(unsigned gp, int value); +int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value); /** * Return the simulated direction of a GPIO (used only in sandbox test code) @@ -46,7 +46,7 @@ int sandbox_gpio_set_value(unsigned gp, int value); * @param gp GPIO number * @return -1 on error, 0 if GPIO is input, >0 if output */ -int sandbox_gpio_get_direction(unsigned gp); +int sandbox_gpio_get_direction(struct device *dev, unsigned int offset); /** * Set the simulated direction of a GPIO (used only in sandbox test code) @@ -55,11 +55,7 @@ int sandbox_gpio_get_direction(unsigned gp); * @param output 0 to set as input, 1 to set as output * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_direction(unsigned gp, int output); - -/* Display information about each GPIO */ -void gpio_info(void); - -#define gpio_status() gpio_info() +int sandbox_gpio_set_direction(struct device *dev, unsigned int offset, + int output); #endif diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h new file mode 100644 index 0000000000..6edec1acfa --- /dev/null +++ b/arch/sandbox/include/asm/sdl.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SDL_H +#define __SANDBOX_SDL_H + +#include + +#ifdef CONFIG_SANDBOX_SDL + +/** + * sandbox_sdl_init_display() - Set up SDL video ready for use + * + * @width: Window width in pixels + * @height Window height in pixels + * @log2_bpp: Log to base 2 of the number of bits per pixel. So a 32bpp + * display will pass 5, since 2*5 = 32 + * @return 0 if OK, -ENODEV if no device, -EIO if SDL failed to initialize + * and -EPERM if the video failed to come up. + */ +int sandbox_sdl_init_display(int width, int height, int log2_bpp); + +/** + * sandbox_sdl_sync() - Sync current U-Boot LCD frame buffer to SDL + * + * This must be called periodically to update the screen for SDL so that the + * user can see it. + * + * @lcd_base: Base of frame buffer + * @return 0 if screen was updated, -ENODEV is there is no screen. + */ +int sandbox_sdl_sync(void *lcd_base); + +/** + * sandbox_sdl_scan_keys() - scan for pressed keys + * + * Works out which keys are pressed and returns a list + * + * @key: Array to receive keycodes + * @max_keys: Size of array + * @return number of keycodes found, 0 if none, -ENODEV if no keyboard + */ +int sandbox_sdl_scan_keys(int key[], int max_keys); + +/** + * sandbox_sdl_key_pressed() - check if a particular key is pressed + * + * @keycode: Keycode to check (KEY_... - see include/linux/input.h + * @return 0 if pressed, -ENOENT if not pressed. -ENODEV if keybord not + * available, + */ +int sandbox_sdl_key_pressed(int keycode); + +/** + * sandbox_sdl_sound_start() - start playing a sound + * + * @frequency: Frequency of sounds in Hertz + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_start(uint frequency); + +/** + * sandbox_sdl_sound_stop() - stop playing a sound + * + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_stop(void); + +/** + * sandbox_sdl_sound_init() - set up the sound system + * + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_init(void); + +#else +static inline int sandbox_sdl_init_display(int width, int height, + int log2_bpp) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sync(void *lcd_base) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_scan_keys(int key[], int max_keys) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_key_pressed(int keycode) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_start(uint frequency) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_stop(void) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_init(void) +{ + return -ENODEV; +} + +#endif + +#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index e8e4fea1b5..d17a82e90f 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -17,6 +17,29 @@ enum exit_type_id { STATE_EXIT_POWER_OFF, }; +/** + * Selects the behavior of the serial terminal. + * + * If Ctrl-C is processed by U-Boot, then the only way to quit sandbox is with + * the 'reset' command, or equivalent. + * + * If the terminal is cooked, then Ctrl-C will terminate U-Boot, and the + * command line will not be quite such a faithful emulation. + * + * Options are: + * + * raw-with-sigs - Raw, but allow signals (Ctrl-C will quit) + * raw - Terminal is always raw + * cooked - Terminal is always cooked + */ +enum state_terminal_raw { + STATE_TERM_RAW_WITH_SIGS, /* Default */ + STATE_TERM_RAW, + STATE_TERM_COOKED, + + STATE_TERM_COUNT, +}; + struct sandbox_spi_info { const char *spec; const struct sandbox_spi_emu_ops *ops; @@ -30,16 +53,20 @@ struct sandbox_state { enum exit_type_id exit_type; /* How we exited U-Boot */ const char *parse_err; /* Error to report from parsing */ int argc; /* Program arguments */ - char **argv; + char **argv; /* Command line arguments */ + const char *jumped_fname; /* Jumped from previous U_Boot */ uint8_t *ram_buf; /* Emulated RAM buffer */ unsigned int ram_size; /* Size of RAM buffer */ const char *ram_buf_fname; /* Filename to use for RAM buffer */ + bool ram_buf_rm; /* Remove RAM buffer file after read */ bool write_ram_buf; /* Write RAM buffer on exit */ const char *state_fname; /* File containing sandbox state */ void *state_fdt; /* Holds saved state for sandbox */ bool read_state; /* Read sandbox state on startup */ bool write_state; /* Write sandbox state on exit */ bool ignore_missing_state_on_read; /* No error if state missing */ + bool show_lcd; /* Show LCD on start-up */ + enum state_terminal_raw term_raw; /* Terminal raw/cooked */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h index 5707c2710d..d2f1b6566d 100644 --- a/arch/sandbox/include/asm/u-boot-sandbox.h +++ b/arch/sandbox/include/asm/u-boot-sandbox.h @@ -25,4 +25,7 @@ int sandbox_main_loop_init(void); int cleanup_before_linux(void); +/* drivers/video/sandbox_sdl.c */ +int sandbox_lcd_sdl_early_init(void); + #endif /* _U_BOOT_SANDBOX_H_ */ diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 758c0701e5..0578fa3fd8 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= sh4-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := sh4-linux- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) @@ -15,3 +17,4 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) LDFLAGS_FINAL = --gc-sections +PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index 69273b4f38..4904d76d44 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -8,11 +8,10 @@ ENDIANNESS += -EB ifdef CONFIG_SH2A -PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb else # SH2 PLATFORM_CPPFLAGS += -m3e -mb endif PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic) -PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk index abd4b8d2bd..24b5c47859 100644 --- a/arch/sh/cpu/sh3/config.mk +++ b/arch/sh/cpu/sh3/config.mk @@ -12,4 +12,3 @@ # # PLATFORM_CPPFLAGS += -DCONFIG_SH3 -m3 -PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk index 753580beb1..5773d4fec9 100644 --- a/arch/sh/cpu/sh4/config.mk +++ b/arch/sh/cpu/sh4/config.mk @@ -9,4 +9,3 @@ # # PLATFORM_CPPFLAGS += -DCONFIG_SH4 -m4-nofpu -PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 7be37ae984..bf57e18a64 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -1250,8 +1250,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* UBC */ #define CBR0 0xFF200000 diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h index 3af0b0db2f..9d8cb8db44 100644 --- a/arch/sh/include/asm/cpu_sh7723.h +++ b/arch/sh/include/asm/cpu_sh7723.h @@ -178,8 +178,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* UBC */ /* H-UDI */ diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h index 2c2a474d37..88c418a17f 100644 --- a/arch/sh/include/asm/cpu_sh7724.h +++ b/arch/sh/include/asm/cpu_sh7724.h @@ -200,8 +200,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* Ether */ #define EDMR 0xA4600000 diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 5fc9d9d66d..8a84b24af1 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -15,15 +15,5 @@ obj-y += time.o endif obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o - - -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -lib-y += ashiftrt.o -lib-y += ashiftlt.o -lib-y += lshiftrt.o -lib-y += ashldi3.o -lib-y += ashrsi3.o -lib-y += lshrdi3.o -lib-y += movmem.o -endif +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \ + ashldi3.o ashrsi3.o lshrdi3.o movmem.o diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index e94e7cbab5..be59f58190 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -5,8 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= sparc-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := sparc-elf- +endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \ + -T $(srctree)/examples/standalone/sparc.lds PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index c411ded861..ca7d6e86f0 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -757,110 +757,9 @@ static void usb_display_Req(unsigned short req) } #endif -static unsigned char root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_hub_des[] = { - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#define WANT_USB_ROOT_HUB_HUB_DES +#include +#undef WANT_USB_ROOT_HUB_HUB_DES /* * Root Hub Control Pipe (interrupt Pipes are not supported) diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 4a4ad8024a..38cb7c93a5 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -8,13 +8,10 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 PLATFORM_CPPFLAGS += -fno-strict-aliasing -PLATFORM_CPPFLAGS += -Wstrict-prototypes PLATFORM_CPPFLAGS += -mregparm=3 PLATFORM_CPPFLAGS += -fomit-frame-pointer -PF_CPPFLAGS_X86 := $(call cc-option, -ffreestanding) \ - $(call cc-option, -fno-toplevel-reorder, \ +PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) \ - $(call cc-option, -fno-stack-protector) \ $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm @@ -32,6 +29,4 @@ LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) -PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC)) - -export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC)) +CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib diff --git a/arch/x86/dts/.gitignore b/arch/x86/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/x86/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile new file mode 100644 index 0000000000..48265ef6dd --- /dev/null +++ b/arch/x86/dts/Makefile @@ -0,0 +1,12 @@ +dtb-y += link.dtb \ + alex.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/board/chromebook-x86/dts/alex.dts b/arch/x86/dts/alex.dts similarity index 100% rename from board/chromebook-x86/dts/alex.dts rename to arch/x86/dts/alex.dts diff --git a/board/chromebook-x86/dts/link.dts b/arch/x86/dts/link.dts similarity index 100% rename from board/chromebook-x86/dts/link.dts rename to arch/x86/dts/link.dts diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h deleted file mode 100644 index fac2e58502..0000000000 --- a/arch/x86/include/asm/mtrr.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Generic MTRR (Memory Type Range Register) ioctls. - * Taken from the Linux kernel - * - * (C) Copyright 2012 - * Graeme Russ, - * - * Copyright (C) 1997-1999 Richard Gooch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_X86_MTRR_H -#define _ASM_X86_MTRR_H - -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) - -#ifndef __ASSEMBLY__ - -#include -#include -#include - -#define MTRR_IOCTL_BASE 'M' - -struct mtrr_sentry { - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int type; /* Type of region */ -}; - -/* - * Warning: this structure has a different order from i386 - * on x86-64. The 32bit emulation code takes care of that. - * But you need to use this for 64bit, otherwise your X server - * will break. - */ - -#ifdef __i386__ -struct mtrr_gentry { - unsigned int regnum; /* Register number */ - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int type; /* Type of region */ -}; - -#else /* __i386__ */ - -struct mtrr_gentry { - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int regnum; /* Register number */ - unsigned int type; /* Type of region */ -}; -#endif /* !__i386__ */ - -struct mtrr_var_range { - __u32 base_lo; - __u32 base_hi; - __u32 mask_lo; - __u32 mask_hi; -}; - -/* - * In the Intel processor's MTRR interface, the MTRR type is always held in - * an 8 bit field: - */ -typedef __u8 mtrr_type; - -#define MTRR_NUM_FIXED_RANGES 88 -#define MTRR_MAX_VAR_RANGES 256 - -struct mtrr_state_type { - struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES]; - mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES]; - unsigned char enabled; - unsigned char have_fixed; - mtrr_type def_type; -}; - -/* These are the various ioctls */ -#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry) -#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry) -#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry) -#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry) -#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry) -#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry) -#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry) -#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry) -#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry) -#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry) - -/* These are the region types */ -#define MTRR_TYPE_UNCACHABLE 0 -#define MTRR_TYPE_WRCOMB 1 -/*#define MTRR_TYPE_ 2*/ -/*#define MTRR_TYPE_ 3*/ -#define MTRR_TYPE_WRTHROUGH 4 -#define MTRR_TYPE_WRPROT 5 -#define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 - -#ifdef __KERNEL__ - -/* The following functions are for use by other drivers */ -# ifdef CONFIG_MTRR -extern u8 mtrr_type_lookup(u64 addr, u64 end); -extern void mtrr_save_fixed_ranges(void *); -extern void mtrr_save_state(void); -extern int mtrr_add(unsigned long base, unsigned long size, - unsigned int type, bool increment); -extern int mtrr_add_page(unsigned long base, unsigned long size, - unsigned int type, bool increment); -extern int mtrr_del(int reg, unsigned long base, unsigned long size); -extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); -extern void mtrr_ap_init(void); -extern void mtrr_bp_init(void); -extern void set_mtrr_aps_delayed_init(void); -extern void mtrr_aps_init(void); -extern void mtrr_bp_restore(void); -extern int mtrr_trim_uncached_memory(unsigned long end_pfn); -extern int amd_special_default_mtrr(void); -# else -static inline u8 mtrr_type_lookup(u64 addr, u64 end) -{ - /* - * Return no-MTRRs: - */ - return 0xff; -} -#define mtrr_save_fixed_ranges(arg) do {} while (0) -#define mtrr_save_state() do {} while (0) -static inline int mtrr_del(int reg, unsigned long base, unsigned long size) -{ - return -ENODEV; -} -static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) -{ - return -ENODEV; -} -static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) -{ - return 0; -} -static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ -} - -#define mtrr_ap_init() do {} while (0) -#define mtrr_bp_init() do {} while (0) -#define set_mtrr_aps_delayed_init() do {} while (0) -#define mtrr_aps_init() do {} while (0) -#define mtrr_bp_restore() do {} while (0) -# endif - -#ifdef CONFIG_COMPAT -#include - -struct mtrr_sentry32 { - compat_ulong_t base; /* Base address */ - compat_uint_t size; /* Size of region */ - compat_uint_t type; /* Type of region */ -}; - -struct mtrr_gentry32 { - compat_ulong_t regnum; /* Register number */ - compat_uint_t base; /* Base address */ - compat_uint_t size; /* Size of region */ - compat_uint_t type; /* Type of region */ -}; - -#define MTRR_IOCTL_BASE 'M' - -#define MTRRIOC32_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry32) -#define MTRRIOC32_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry32) -#define MTRRIOC32_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry32) -#define MTRRIOC32_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32) -#define MTRRIOC32_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry32) -#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry32) -#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry32) -#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry32) -#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32) -#define MTRRIOC32_KILL_PAGE_ENTRY \ - _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry32) -#endif /* CONFIG_COMPAT */ - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_X86_MTRR_H */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 638f79069c..f7303abccb 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -23,5 +23,6 @@ obj-$(CONFIG_CMD_ZBOOT) += zimage.o LIBGCC := $(notdir $(NORMAL_LIBGCC)) extra-y := $(LIBGCC) -$(obj)$(LIBGCC): $(NORMAL_LIBGCC) - $(OBJCOPY) $< $@ --prefix-symbols=__normal_ +OBJCOPYFLAGS := --prefix-symbols=__normal_ +$(obj)/$(LIBGCC): $(NORMAL_LIBGCC) FORCE + $(call if_changed,objcopy) diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/lib/asm-offsets.c similarity index 100% rename from arch/x86/cpu/coreboot/asm-offsets.c rename to arch/x86/lib/asm-offsets.c diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 582c0ffe24..b5d937feb3 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -92,7 +92,7 @@ int find_fdt(void) { #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (ulong *)&_end; diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds index 5480d1f276..8604696be7 100644 --- a/board/Barix/ipam390/u-boot-spl-ipam390.lds +++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds @@ -49,5 +49,9 @@ SECTIONS } >.sram __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram } diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h new file mode 100644 index 0000000000..15225b0724 --- /dev/null +++ b/board/BuR/common/bur_common.h @@ -0,0 +1,22 @@ +/* + * bur_comon.h + * + * common board information header for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BUR_COMMON_H_ +#define _BUR_COMMON_H_ + +void blink(u32 blinks, u32 intervall, u32 pin); +void pmicsetup(u32 mpupll); +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +int board_eth_init(bd_t *bis); + +#endif diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c new file mode 100644 index 0000000000..4c926ce700 --- /dev/null +++ b/board/BuR/common/common.c @@ -0,0 +1,216 @@ +/* + * common.c + * + * common board functions for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bur_common.h" + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +/* --------------------------------------------------------------------------*/ +void blink(u32 blinks, u32 intervall, u32 pin) +{ + gpio_direction_output(pin, 0); + int val = 0; + + do { + val ^= 0x01; + gpio_set_value(pin, val); + mdelay(intervall); + } while (blinks--); + + gpio_set_value(pin, 0); +} +#ifdef CONFIG_SPL_BUILD +void pmicsetup(u32 mpupll) +{ + int mpu_vdd; + int usb_cur_lim; + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + if (i2c_probe(TPS65217_CHIP_PM)) { + puts("PMIC (0x24) not found! skip further initalization.\n"); + return; + } + + /* Get the frequency which is defined by device fuses */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + printf("detected max. frequency: %d - ", dpll_mpu_opp100.m); + + if (0 != mpupll) { + dpll_mpu_opp100.m = MPUPLL_M_1000; + printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m); + } else { + puts("ok.\n"); + } + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set LDO3 to 1.8V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + /* Set LDO4 to 3.3V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +#endif /* CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +/* describing port offsets of TI's CPSW block */ +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + +#if defined(CONFIG_DRIVER_TI_CPSW) + +int board_eth_init(bd_t *bis) +{ + int rv = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC ... "); + + if (is_valid_ether_addr(mac_addr)) { + printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5] + ); + eth_setenv_enetaddr("ethaddr", mac_addr); + } + } + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) { + printf("Error %d registering CPSW switch\n", rv); + return 0; + } +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + return rv; +} +#endif /* CONFIG_DRIVER_TI_CPSW */ diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile new file mode 100644 index 0000000000..7b04b26ae4 --- /dev/null +++ b/board/BuR/kwb/Makefile @@ -0,0 +1,12 @@ +# +# Makefile +# +# Copyright (C) 2014 Hannes Petermaier - +# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += mux.o +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c new file mode 100644 index 0000000000..804765a8de --- /dev/null +++ b/board/BuR/kwb/board.c @@ -0,0 +1,240 @@ +/* + * board.c + * + * Board functions for B&R KWB Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +/* -------------------------------------------------------------------------*/ +/* -- defines for used GPIO Hardware -- */ +#define KEY (0+4) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) +#define USB2SD_NRST (32+29) +#define USB2SD_PWR (96+13) +/* -------------------------------------------------------------------------*/ +/* -- PSOC Resetcontroller Register defines -- */ + +/* I2C Address of controller */ +#define RSTCTRL_ADDR 0x75 +/* Register for CTRL-word */ +#define RSTCTRL_CTRLREG 0x01 +/* Register for giving some information to VxWorks OS */ +#define RSTCTRL_SCRATCHREG 0x04 + +/* -- defines for RSTCTRL_CTRLREG -- */ +#define RSTCTRL_FORCE_PWR_NEN 0x0404 + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + unsigned int oldspeed; + unsigned short buf; + + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + /* + * enable additional clocks of modules which are accessed later from + * VxWorks OS + */ + u32 *const clk_domains[] = { 0 }; + + u32 *const clk_modules_kwbspecific[] = { + &cmwkup->wkup_adctscctrl, + &cmper->spi1clkctrl, + &cmper->dcan0clkctrl, + &cmper->dcan1clkctrl, + &cmper->epwmss0clkctrl, + &cmper->epwmss1clkctrl, + &cmper->epwmss2clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); + + /* power-OFF LCD-Display */ + gpio_direction_output(LCD_PWR, 0); + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + /* power-ON 3V3 via Resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + buf = RSTCTRL_FORCE_PWR_NEN; + i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); + } + +#if defined(CONFIG_AM335X_USB0) + /* power on USB2SD Controller */ + gpio_direction_output(USB2SD_PWR, 1); + mdelay(1); + /* give a reset Pulse to USB2SD Controller */ + gpio_direction_output(USB2SD_NRST, 0); + mdelay(1); + gpio_set_value(USB2SD_NRST, 1); +#endif + pmicsetup(0); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + const unsigned int ton = 250; + const unsigned int toff = 1000; + unsigned int cnt = 3; + unsigned short buf = 0xAAAA; + unsigned int oldspeed; + + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + + if (gpio_get_value(KEY)) { + do { + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + mdelay(ton); + /* turn off light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x01, 0xFF); + mdelay(toff); + cnt--; + if (!gpio_get_value(KEY) && + gpio_get_value(PUSH_KEY) && 1 == cnt) { + puts("updating from USB ...\n"); + setenv("bootcmd", "run usbupdate"); + break; + } else if (!gpio_get_value(KEY)) { + break; + } + } while (cnt); + } + + switch (cnt) { + case 0: + puts("3 blinks ... entering BOOT mode.\n"); + buf = 0x0000; + break; + case 1: + puts("2 blinks ... entering DIAGNOSE mode.\n"); + buf = 0x0F0F; + break; + case 2: + puts("1 blinks ... entering SERVICE mode.\n"); + buf = 0xB4B4; + break; + case 3: + puts("0 blinks ... entering RUN mode.\n"); + buf = 0x0404; + break; + } + mdelay(ton); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + /* write bootinfo into scratchregister of resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } + /* + * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does + * expect that vectors are there, original u-boot moves them to _start + */ + __asm__("ldr r0,=0x20000"); + __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c new file mode 100644 index 0000000000..1a5ffd5709 --- /dev/null +++ b/board/BuR/kwb/mux.c @@ -0,0 +1,195 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, + /* USB0 DrvBus Receiver disable (from romcode 0x20) */ + {OFFSET(usb0_drvvbus), (MODE(0))}, + /* USB1 DrvBus as GPIO due to HW-Workaround */ + {OFFSET(usb1_drvvbus), (MODE(7))}, + {-1}, +}; +static struct module_pin_mux spi1_pin_mux[] = { + /* SPI1_SCLK */ + {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D0 */ + {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D1 */ + {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_CS0 */ + {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan0_pin_mux[] = { + /* DCAN0 TX */ + {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN0 RX */ + {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan1_pin_mux[] = { + /* DCAN1 TX */ + {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN1 RX */ + {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux gpios[] = { + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, + /* GPIO0_4 (SPI D1) - TA602 */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, + /* GPIO0_7 (PWW0 OUT) - CAN TERM */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_30 (GPMC_WAIT0) - TA601 */ + {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO2_4 (GPMC_nWE) - TST_BAST */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ + {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ + {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ + {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(dcan0_pin_mux); + configure_module_pin_mux(dcan1_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpios); +} diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile new file mode 100644 index 0000000000..ec0d27a7aa --- /dev/null +++ b/board/BuR/tseries/Makefile @@ -0,0 +1,14 @@ +# +# Makefile +# +# Copyright (C) 2013 Hannes Petermaier +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c new file mode 100644 index 0000000000..f0510e599e --- /dev/null +++ b/board/BuR/tseries/board.c @@ -0,0 +1,147 @@ +/* + * board.c + * + * Board functions for B&R LEIT Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* --------------------------------------------------------------------------*/ +/* -- defines for GPIO -- */ +#define ETHLED_ORANGE (96+16) /* GPIO3_16 */ +#define REPSWITCH (0+20) /* GPIO0_20 */ + + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +/* + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + blink(5, 125, ETHLED_ORANGE); + mdelay(1000); + printf("SPL: entering u-boot instead kernel image.\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +#define OSC (V_OSCK/1000000) +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + pmicsetup(1000); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* Basic board specific setup. Pinmux has been handled already. */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + gpio_direction_output(ETHLED_ORANGE, 0); + + if (0 == gpio_get_value(REPSWITCH)) { + printf("\n\n\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" + "!!!!!!! recovery switch activated !!!!!!!\n" + "!!!!!!! running usbupdate !!!!!!!\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n"); + setenv("bootcmd", "sleep 2; run netupdate;"); + } + + printf("turning on display power+backlight ... "); + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1, + 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2, + 0x62, TPS65217_MASK_ALL_BITS); /* 100% */ + printf("ok.\n"); + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c new file mode 100644 index 0000000000..3c76e96926 --- /dev/null +++ b/board/BuR/tseries/mux.c @@ -0,0 +1,225 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; +#endif +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI0_SCLK */ + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D0 */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D1 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_CS0 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + /* + * MII2_CRS is shared with + * NAND_WAIT0 + */ + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ + {-1}, +}; +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif +static struct module_pin_mux gpIOs[] = { + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ + {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO2_0 (GPMC_nCS3) - DCOK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* + * GPIO0_7 (PWW0 OUT) + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) + */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - REP-Switch */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_MMC) + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpIOs); +} diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index 63f7ad9a7a..da39c86258 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 56ba0daa05..752492fc7d 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -20,7 +20,6 @@ #include #include "../include/memory.h" -#include "serial.h" #ifdef CONFIG_DB64360 #include "../db64360/mpsc.h" diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/Marvell/common/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/actux1/Makefile b/board/actux1/Makefile deleted file mode 100644 index 05a8669113..0000000000 --- a/board/actux1/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux1.o diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c deleted file mode 100644 index 03ccd936b4..0000000000 --- a/board/actux1/actux1.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux1_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HwRel */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* Setup GPIOs for PCI INTA */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - ACTUX1_LED1(2); - ACTUX1_LED2(2); - ACTUX1_LED3(0); - ACTUX1_LED4(0); - ACTUX1_LED5(0); - ACTUX1_LED6(0); - ACTUX1_LED7(0); - - ACTUX1_HS(ACTUX1_HS_DCD); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-1 rev."); - putc(ACTUX1_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX1_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - u16 id1, id2; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); - - id2 &= 0xFFF0; /* mask out revision bits */ - - if (id1 == 0x13 && id2 == 0x78e0) { - /* - * LXT971/LXT972 PHY: set LED outputs: - * LED1(green) = Link/ACT, - * LED2 (unused) = LINK, - * LED3(red) = Coll - */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); - } else if (id1 == 0x143 && id2 == 0xbc30) { - /* BCM5241: default values are OK */ - } else - printf("unknown ethernet PHY ID: %x %x\n", id1, id2); -} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h deleted file mode 100644 index 5627f24796..0000000000 --- a/board/actux1/actux1_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX1_HW_H -#define _ACTUX1_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) -#define ACTUX1_HS_DCD 0x01 -#define ACTUX1_HS_DSR 0x02 - -#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_PCI1_INTA 2 -#define CONFIG_SYS_GPIO_PCI2_INTA 3 -#define CONFIG_SYS_GPIO_I2C_SDA 4 -#define CONFIG_SYS_GPIO_I2C_SCL 5 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds deleted file mode 100644 index 4716e4f0e0..0000000000 --- a/board/actux1/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux1/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/actux2/Makefile b/board/actux2/Makefile deleted file mode 100644 index 24cbff1b47..0000000000 --- a/board/actux2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux2.o diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c deleted file mode 100644 index e578cd0996..0000000000 --- a/board/actux2/actux2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include - -#include "actux2_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HW release register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX2_LED1(1); - ACTUX2_LED2(0); - ACTUX2_LED3(0); - ACTUX2_LED4(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-2 rev."); - putc(ACTUX2_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX2_BOARDREL; -} - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE0", 29, 31, 0x175C); -} diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h deleted file mode 100644 index 57c6fa7076..0000000000 --- a/board/actux2/actux2_hw.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX2_HW_H -#define _ACTUX2_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) - -#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_UNUSED4 4 -#define CONFIG_SYS_GPIO_UNUSED5 5 -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_IPAC_INT 8 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds deleted file mode 100644 index f00d7c72b1..0000000000 --- a/board/actux2/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux2/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/actux3/Makefile b/board/actux3/Makefile deleted file mode 100644 index f628f26449..0000000000 --- a/board/actux3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux3.o diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c deleted file mode 100644 index 09c803ccd4..0000000000 --- a/board/actux3/actux3.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "actux3_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: Release/Option register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN); - - /* - * Setup GPIO's for Interrupt inputs - */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* - * Setup GPIO's for 33MHz clock output - */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - /* we need a minimum PCI reset pulse width after enabling the clock */ - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX3_LED1_RT(1); - ACTUX3_LED1_GN(0); - ACTUX3_LED2_RT(0); - ACTUX3_LED2_GN(0); - ACTUX3_LED3_RT(0); - ACTUX3_LED3_GN(0); - ACTUX3_LED4_GN(0); - ACTUX3_LED5_RT(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-3 rev."); - putc(ACTUX3_BOARDREL + 'A' - 1); - - if (i > 0) { - puts (", serial# "); - puts (buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX3_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -void reset_phy(void) -{ - int i; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - /* all LED outputs = Link/Act */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); - - /* - * The Marvell 88E6060 switch comes up with all ports disabled. - * set all ethernet switch ports to forwarding state - */ - for (i = 1; i <= 5; i++) - miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); - -} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h deleted file mode 100644 index f8acb4d060..0000000000 --- a/board/actux3/actux3_hw.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX3_HW_H -#define _ACTUX3_HW_H - -/* 0 = LED off,1 = ON */ -#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) - -#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */ -#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */ -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds deleted file mode 100644 index 2de3ca60b5..0000000000 --- a/board/actux3/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux3/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/actux4/Makefile b/board/actux4/Makefile deleted file mode 100644 index b949b608c6..0000000000 --- a/board/actux4/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux4.o diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c deleted file mode 100644 index 81c545884e..0000000000 --- a/board/actux4/actux4.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux4_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - writel(0xbd113c42, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* led not populated on board*/ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3); - - /* middle LED */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2); - - /* right LED */ - /* weak pulldown = LED weak on */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1); - - /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); - - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); - - /* Setup GPIO's for 33MHz clock output */ - writel(0x011001FF, IXP425_GPIO_GPCLKR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - puts("Board: AcTux-4\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus. - * Flash 1 is an Intel *16 flash using the CFI driver. - */ -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h deleted file mode 100644 index b936376de9..0000000000 --- a/board/actux4/actux4_hw.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX4_HW_H -#define _ACTUX4_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_USBINTA 0 -#define CONFIG_SYS_GPIO_USBINTB 1 -#define CONFIG_SYS_GPIO_USBINTC 2 -#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */ -#define CONFIG_SYS_GPIO_I2C_SCL 4 -#define CONFIG_SYS_GPIO_I2C_SDA 5 -#define CONFIG_SYS_GPIO_PCI_INTB 6 -#define CONFIG_SYS_GPIO_BUTTON1 7 -#define CONFIG_SYS_GPIO_LED1 8 /* Out */ -#define CONFIG_SYS_GPIO_RTCINT 9 -#define CONFIG_SYS_GPIO_LED2 10 /* Out */ -#define CONFIG_SYS_GPIO_PCI_INTA 11 -#define CONFIG_SYS_GPIO_IORST 12 /* Out */ -#define CONFIG_SYS_GPIO_LED3 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index d7e7894831..2022151309 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -7,9 +7,9 @@ # (mem base + reserved) # -UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg +UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.ubl +ALL-y += u-boot.ubl else # as SPL_TEXT_BASE is not page-aligned, we need for some # linkers the -n flag (Do not page align data), to prevent diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index fdfbfc38a9..c0d09adf7c 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -48,5 +48,9 @@ SECTIONS } >.sram __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } } diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index aa126d71bc..5ab9471246 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -16,7 +16,8 @@ void text_base_hook(void); /* nop hook for text_base.S */ -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) static void __early_flash_cmd_reset(void) { /* reset flash before we read env */ @@ -37,7 +38,8 @@ int board_early_init_f(void) "led"); #endif #endif -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) early_flash_cmd_reset(); #endif return 0; diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h new file mode 100644 index 0000000000..9bd044230b --- /dev/null +++ b/board/altera/socfpga/pll_config.h @@ -0,0 +1,118 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +/* PLL configuration data */ +/* Main PLL */ +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +/* + * To tell where is the clock source: + * 0 = MAINPLL + * 1 = PERIPHPLL + */ +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +/* Peripheral PLL */ +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +/* + * To tell where is the clock source: + * 0 = F2S_PERIPH_REF_CLK + * 1 = MAIN_CLK + * 2 = PERIPH_CLK + */ +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +/* SDRAM PLL */ +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz + * This if..else... is not required if generated by tools */ +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) +#else +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#endif /* CONFIG_SOCFPGA_ARRIA5 */ + +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +/* Info for driver */ +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) +#else +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#endif +#define CONFIG_HPS_CLK_EMAC0_HZ (250000000) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (100000000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 576066bef1..a960eb6002 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -12,6 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information */ @@ -20,6 +21,7 @@ int print_cpuinfo(void) puts("CPU : Altera SOCFPGA Platform\n"); return 0; } +#endif /* * Print Board information diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 61bfea3fab..9673118857 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -17,7 +17,6 @@ extern void board_pll_init_f(void); -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val) return; } -#endif phys_size_t initdram(int board_type) { -#if defined(CONFIG_NAND_SPL) - u32 reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; @@ -88,7 +76,6 @@ phys_size_t initdram(int board_type) /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; -#endif return (CONFIG_SYS_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index d74b725ae5..d868582ba9 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -135,45 +135,3 @@ void board_pll_init_f(void) mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU__405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 84bbacf4c5..c8d09636ab 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) /************************************************************************* * * Bamboo has one bank onboard sdram (plus DIMM) @@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0, 0 }; -#endif #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ @@ -440,15 +438,11 @@ int checkboard(void) phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; dram_size = spd_sdram(); return dram_size; -#else - return CONFIG_SYS_MBYTES_SDRAM << 20; -#endif } /*----------------------------------------------------------------------------+ @@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { update_ndfc_ios(gpio_tab); - -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); -#else - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN0 | - SDR0_CUST0_CHIPSELGAT_EN2); -#endif - ndfc_selection_in_fpga(); } else diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 48dbcbe2a1..5c7c839079 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -32,12 +32,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) -#endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) @@ -58,31 +53,3 @@ tlbtab: tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 2b5f1a62cc..79d4babe06 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -379,11 +379,7 @@ int board_early_init_r (void) */ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#else mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#endif /* Remove TLB entry of boot EBC mapping */ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index d83cd6e754..bf00bd6bca 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -31,13 +31,7 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) - tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG) -#endif /* * TLB entries for SDRAM are not needed on this platform. @@ -95,31 +89,3 @@ tlbtab: #endif tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index b31e9db3f9..f876639d35 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -48,11 +48,7 @@ tlbtab: /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ @@ -81,31 +77,3 @@ tlbtab: tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 2c5a21806a..67640d7edf 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -26,14 +26,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); -#if defined(CONFIG_NAND_SPL) -/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133333333 -#endif - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void); ************************************************************************/ phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ - defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_SYS_RAMBOOT) ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); @@ -81,7 +72,7 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ +#endif /* #ifndef CONFIG_SYS_RAMBOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 73c65c56aa..53f9b3419f 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -142,8 +142,7 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -151,8 +150,7 @@ int misc_init_r(void) pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) } #endif -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) /* * On NAND-booting sequoia, we need to patch the chips select numbers * in the dtb (CS0 - NAND, CS3 - NOR) @@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd) return; } } -#endif /* CONFIG_NAND_U_BOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index 389d5e9083..0fb42adc6f 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -183,7 +183,7 @@ cm_remap: /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_TEXT_BASE /* r2 <- past vectors */ + add r2, r0, #64 /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db..4e2d3421d8 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index da5cb0152b..cb2de2f4dd 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -119,11 +119,6 @@ void dram_init_banksize(void) get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); } -int timer_init(void) -{ - return 0; -} - /* * Start timer: * Setup a 32 bit timer, running at 1KHz diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index d42a1730cc..db29879801 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -7,7 +7,7 @@ */ #include -#include +#include #include #include #include @@ -24,6 +24,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -214,6 +215,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif + int board_early_init_f(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile new file mode 100644 index 0000000000..ec82b06990 --- /dev/null +++ b/board/atmel/sama5d3_xplained/Makefile @@ -0,0 +1,15 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# (C) Copyright 2014 +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d3_xplained.o diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c new file mode 100644 index 0000000000..39f2dc6475 --- /dev/null +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +void sama5d3_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d3_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 3, 0); + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +static void sama5d3_xplained_mci0_hw_init(void) +{ + at91_mci_hw_init(); + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ +} +#endif + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d3_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d3_xplained_usb_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3_xplained_mci0_hw_init(); +#endif +#ifdef CONFIG_MACB + at91_gmac_hw_init(); + at91_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_MACB + macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + atmel_mci_init((void *)ATMEL_BASE_MCI0); + + return 0; +} +#endif diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index eff94a48b2..c835c12d02 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -307,6 +307,10 @@ void spl_board_init(void) { #ifdef CONFIG_SYS_USE_MMC sama5d3xek_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3xek_nand_hw_init(); +#elif CONFIG_SYS_USE_SERIALFLASH + at91_spi0_hw_init(1 << 0); #endif } diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index 87e19123b0..bcf7ccfe2a 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index 87e19123b0..bcf7ccfe2a 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index f41eb30723..a556b92e8e 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - obj-y := ../common/tamonten-ng.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index 87e19123b0..bcf7ccfe2a 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bct-brettl2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf518f-ezbrd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf526-ezbrd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf527-ad7160-eval/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf527-ezkit/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk index 5f327a990e..1d46cfcd48 100644 --- a/board/bf527-sdp/config.mk +++ b/board/bf527-sdp/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index ae2ea0b747..ab0fbecab9 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index ad3a7293df..7bb8e9c9ee 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index cfc64fe51d..43a43306bb 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + ret += designware_initialize(EMAC0_MACCFG, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + ret += designware_initialize(EMAC1_MACCFG, 0); } return ret; diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 50490931e0..9d84265029 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -67,10 +67,10 @@ override auto-detection and force activation of the specified panel. To build U-Boot for one of the Nitrogen6x or SabreLite board: make nitrogen6x_config - make u-boot.imx + make Note that 'nitrogen6x' is a placeholder. The complete list of supported -board configurations is shown in tha MAINTAINERS file: +board configurations is shown in the boards.cfg file: nitrogen6q i.MX6Q/6D 1GB nitrogen6dl i.MX6DL 1GB nitrogen6s i.MX6S 512MB diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg index 97ae0c291b..1cdccad772 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg index 82f837e108..516d67e4be 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg index b6f1518ea9..b6642e6901 100644 --- a/board/boundary/nitrogen6x/nitrogen6q.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg index 8d7ff25f7f..fe6dfc1f44 100644 --- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg index 34fb9d0688..ca30cd6c46 100644 --- a/board/boundary/nitrogen6x/nitrogen6s.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg index d61453c665..b1489fb907 100644 --- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 3f4cfa1a29..d9c05b07bf 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -389,7 +389,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_MV_UDC +#ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); #endif diff --git a/board/br4/config.mk b/board/br4/config.mk deleted file mode 100644 index 5c18d5c9e4..0000000000 --- a/board/br4/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile new file mode 100644 index 0000000000..b18785a078 --- /dev/null +++ b/board/broadcom/bcm28155_ap/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += $(BOARD).o diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c new file mode 100644 index 0000000000..940a1c2c50 --- /dev/null +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -0,0 +1,87 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 +#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 +#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 +#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 +#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + printf("Relocation Offset is: %08lx\n", gd->reloc_off); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + clk_init(); + + return 0; +} + +/* + * misc_init_r - miscellaneous platform dependent initializations + */ +int misc_init_r(void) +{ + /* Disable watchdog reset - watchdog unused */ + writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) | + (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) | + (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) | + (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT), + (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET)); + + return 0; +} + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +#ifdef CONFIG_KONA_SDHCI +/* + * mmc_init - Initializes mmc + */ +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + /* Register eMMC - SDIO2 */ + ret = kona_sdhci_init(1, 400000, 0); + if (ret) + return ret; + + /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ + ret = kona_sdhci_init(3, 400000, 0); + return ret; +} +#endif diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk deleted file mode 100644 index 0c05dd03db..0000000000 --- a/board/chromebook-x86/coreboot/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. -# -# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause -# - -HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/cm-bf527/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index c005afb881..beb9834649 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index a43413e976..c35d285070 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 251192839e..8315a57ed9 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 251192839e..8315a57ed9 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h deleted file mode 100644 index 7eb419c1d6..0000000000 --- a/board/cogent/kbm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -extern int cma_kbm_not_implemented; - -/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ - -/* - * note the auxillary port is used to control the mouse - */ - -/* 8542B Commands (Sent to the Command Port) */ -#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ -#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ -#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ -#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ -#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ -#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ -#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ -#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ -#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ -#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ -#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ -#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ - -/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ -#define HT8542_CMD_BYTE_TRANS 0x40 -#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ -#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ -#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ -#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ - -/* Keyboard Commands (Sent to the Data Port) */ -#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ -#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ -#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ -#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ -#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ -#define KBD_CMD_ON 0xF4 /* Enable keyboard */ -#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ -#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ -#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ - -/* Set LED second bit defines */ -#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ -#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ -#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ - -/* Set Mode second byte defines */ -#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ -#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ -#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ -#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ - -/* Keyboard/Mouse ID Codes */ -#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ -#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ -#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ - -/* Keyboard Data Return Defines */ -#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ -#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ -#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ -#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ -#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ -#define KBD_STAT_ACK 0xFA /* Received after all commands */ -#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ -#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ - -/* HT8542B Status Register Bit Defines */ -#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ -#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ -#define HT8542_STAT_SYS 0x04 /* system flag - unused */ -#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ -#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ -#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ -#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ -#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ diff --git a/board/cogent/mb.c b/board/cogent/mb.c index 3eea47d3e8..c0256433ce 100644 --- a/board/cogent/mb.c +++ b/board/cogent/mb.c @@ -14,7 +14,7 @@ /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) #include @@ -186,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ /* ------------------------------------------------------------------------- */ diff --git a/board/cogent/serial.c b/board/cogent/serial.c index f0d6b22cfd..95c8120722 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ - (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)) + (defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE)) #if CONFIG_CONS_INDEX == 1 #define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index b2d3b6b4b2..e6a0b29997 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -16,4 +16,4 @@ obj-y := paz00.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 01019e8eb2..9583149bed 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -47,7 +47,7 @@ static void cpsw_control(int enabled) static struct cpsw_slave_data cpsw_slave = { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }; diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index b3b150a577..d57436445e 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include const struct ctrl_ioregs ioregs = { .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds index 1b609a249a..0984dfe6ea 100644 --- a/board/compulab/cm_t335/u-boot.lds +++ b/board/compulab/cm_t335/u-boot.lds @@ -61,7 +61,12 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Deprecated: this MMU section is used by pxa at present but @@ -92,10 +97,14 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .hash : { *(.hash) } + .got.plt : { *(.got.plt) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index f3bd00dbf1..311eb92d7b 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -7,4 +7,4 @@ obj-y := trimslice.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 2dfcb271d3..9e81bf3f3f 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -79,6 +79,8 @@ static void get_eeprom(struct tricorder_eeprom *eeprom) } else { panic("Could not get board revision\n"); } + } else { + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); } } diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore new file mode 100644 index 0000000000..cd76d660ef --- /dev/null +++ b/board/cray/L1/.gitignore @@ -0,0 +1,2 @@ +bootscript.c +bootscript.image diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h deleted file mode 100644 index 42c34dd910..0000000000 --- a/board/cray/L1/L1.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip - * - * Start Address Length - * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- - * | Failsafe Linux Image | (1M) - * +=======================+ 0xFFD0_0000 - * | (Reserved FlashFiles) | (1M) - * +=======================+ 0xFFE0_0000 - * | Failsafe RootFS | (1M) - * +=======================+ 0xFFF0_0000 - * | | - * | U N U S E D | - * | | - * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) - * | environment settings | (64k) - * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) - * | U-Boot | 0xFFFE_0040 _start of U-Boot - * | | 0xFFFE_FFFC reset vector - branch to _start - * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- - *****************************************************************************/ diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 5f6c690b7c..55402981fd 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -9,8 +9,19 @@ obj-y = L1.o flash.o obj-y += init.o obj-y += bootscript.o -$(obj)bootscript.c: $(obj)bootscript.image - od -t x1 -v -A x $^ | awk -f x2c.awk > $@ +quiet_cmd_awk = AWK $@ + cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@ -$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile - -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@ +$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk + $(call cmd,awk) + +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ + -a 0 -e 0 -n bootscript +$(obj)/bootscript.image: $(src)/bootscript.hush + $(call cmd,mkimage) + +clean-files := bootscript.c bootscript.image \ No newline at end of file diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 44c688d1f0..d4723c733f 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -22,8 +22,6 @@ /*-----------------------------------------------------------------------------#include */ #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/csb272/init.S b/board/csb272/init.S index 5961978c86..bf1d98680d 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/csb472/init.S b/board/csb472/init.S index 1ebc9ead3a..7383a708b0 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 5480d1f276..de21a132b0 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -49,5 +49,9 @@ SECTIONS } >.sram __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } } diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index d49c314490..299226b95f 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -61,5 +61,8 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } } diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 0f71a168bd..74f95011ad 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -31,24 +31,41 @@ DECLARE_GLOBAL_DATA_PTR; +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + int dram_init(void) { - u32 size1, size2; + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } static void setup_iomux_uart(void) diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile deleted file mode 100644 index 8b489362ce..0000000000 --- a/board/dvlhost/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dvlhost.o watchdog.o diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c deleted file mode 100644 index 087070f40d..0000000000 --- a/board/dvlhost/dvlhost.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: LED Latch */ - writel(0xBFFF0002, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* Setup GPIOs used as output */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST); - - /* - * LED latch enable and watchdog enable are tied to the same GPIO, - * so we need to trigger the watchdog if we want to enable the LEDs. - */ -#ifdef CONFIG_HW_WATCHDOG - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN); -#else - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN); -#endif - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB); - - /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x01FF01FF, IXP425_GPIO_GPCLKR); - - /* turn off all LEDs */ - writew(0x0000, DVLHOST_LED_LATCH); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: dLAN 200AV (dvlhost)"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE1", 29, 31, 0x175C); -} diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h deleted file mode 100644 index 545099e9ea..0000000000 --- a/board/dvlhost/dvlhost_hw.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DVLHOST_HW_H -#define _DVLHOST_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */ -#define CONFIG_SYS_GPIO_BTN_WLAN 1 -#define CONFIG_SYS_GPIO_BTN_PAIRING 6 -#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */ -#define CONFIG_SYS_GPIO_BTN_RESET 9 -#define CONFIG_SYS_GPIO_IRQB 10 -#define CONFIG_SYS_GPIO_IRQA 11 -#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */ -#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS - -#endif diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds deleted file mode 100644 index ebcaf447b8..0000000000 --- a/board/dvlhost/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/dvlhost/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/serial/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN (4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN (4); - .data : { - *(.data*) - } - . = ALIGN (4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c deleted file mode 100644 index 02ec35eb1a..0000000000 --- a/board/dvlhost/watchdog.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_HW_WATCHDOG -#include -#include - -void hw_watchdog_reset(void) -{ - unsigned int x; - x = readl(IXP425_GPIO_GPOUTR); - x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER)); - writel(x, IXP425_GPIO_GPOUTR); -} - -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h deleted file mode 100644 index ddc0289b2e..0000000000 --- a/board/esd/common/s1d13806_640_480_8bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_640_320_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index f42510545c..6c2cf215ac 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -23,7 +23,6 @@ #include #include "../../Marvell/include/memory.h" -#include "serial.h" #include "mpsc.h" diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/esd/cpci750/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index cc8030b5e5..1f26fad147 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -27,11 +27,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif /* TLB entries for DDR2 SDRAM are generated dynamically */ @@ -71,31 +67,3 @@ tlbtab: /* TODO: what about high IO space */ tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 88fc5f77b6..e86996c55f 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -229,19 +229,11 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif mtdcr(EBC0_CFGDATA, pbcr); /* diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/etin/debris/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 3081fad21a..83a421708b 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -21,8 +21,6 @@ #include #endif -#include "serial.h" - #include "mpsc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h deleted file mode 100644 index bac9253852..0000000000 --- a/board/evb64260/serial.h +++ /dev/null @@ -1,63 +0,0 @@ -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/fads/fads.h b/board/fads/fads.h index cf6c928dc7..fa49080fb7 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -127,8 +127,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f6b012dbbc..d9c88a074f 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,6 @@ #define CLK_MUX_SEL_MASK 0x4 #define ETH_PHY_CLK_OUT 0x4 -#define PLL_NUM 2 DECLARE_GLOBAL_DATA_PTR; @@ -120,6 +120,7 @@ int configure_vsc3316_3308(void) debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); switch (serdes1_prtcl) { + case 0x29: case 0x2a: case 0x2C: case 0x2D: @@ -151,7 +152,55 @@ int configure_vsc3316_3308(void) } break; + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B: AURORA + * Lanes: C,d: SGMII + * Lanes: E,F,G,H: CPRI + */ + debug("Configuring crossbar for Aurora, SGMII 3 and 4," + " and CPRI. srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* * Configuration: @@ -239,14 +288,191 @@ int configure_vsc3316_3308(void) return 0; } +static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) +{ + u32 rst_err; + + /* Steps For SerDes PLLs reset and reconfiguration + * or PLL power-up procedure + */ + debug("CALIBRATE PLL:%d\n", pll_num); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + + udelay(20); + + /* Check whether PLL has been locked or not */ + rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & + SRDS_RSTCTL_RSTERR; + rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; + debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); + if (rst_err) + return rst_err; + + return rst_err; +} + +static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) +{ + int ret = 0; + u32 fcap, dcbias, bcap, pllcr1, pllcr0; + + if (calibrate_pll(srds_regs, pll_num)) { + /* STEP 1 */ + /* Read fcap, dcbias and bcap value */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + debug("values of bcap:%x, fcap:%x and dcbias:%x\n", + bcap, fcap, dcbias); + if (fcap == 0 && bcap == 1) { + /* Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + if (calibrate_pll(srds_regs, pll_num)) { + /*save the fcap, dcbias and bcap values*/ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32 + (&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + + /* Step 4*/ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + /* change the fcap and dcbias to the saved + * values from Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32 + (&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32 + (&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } else { + goto out; + } + } else { /* Step 5 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + udelay(10); + /* Change the fcap, dcbias, and bcap to the + * values from Step 1 */ + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } + } +out: + return 0; +} + +static int check_serdes_pll_locks(void) +{ + serdes_corenet_t *srds1_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + int i, ret1, ret2; + + debug("\nSerDes1 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret1 = check_pll_locks(srds1_regs, i); + if (ret1) { + printf("SerDes1, PLL:%d didnt lock\n", i); + return ret1; + } + } + debug("\nSerDes2 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret2 = check_pll_locks(srds2_regs, i); + if (ret2) { + printf("SerDes2, PLL:%d didnt lock\n", i); + return ret2; + } + } + + return 0; +} + int config_serdes1_refclks(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 serdes1_prtcl, lane; - unsigned int flag_sgmii_prtcl = 0; - int ret, i; + unsigned int flag_sgmii_aurora_prtcl = 0; + int i; + int ret = 0; serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -257,10 +483,12 @@ int config_serdes1_refclks(void) serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); - /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request */ - for (i = 0; i < PLL_NUM; i++) - clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + /* Reconfigure IDT idt8t49n222a device for CPRI to work * For this SerDes1's Refclk1 and refclk2 need to be set * to 122.88MHz @@ -270,6 +498,25 @@ int config_serdes1_refclks(void) case 0x2C: case 0x2D: case 0x2E: + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: debug("Configuring idt8t49n222a for CPRI SerDes clks:" " for srds_prctl:%x\n", serdes1_prtcl); ret = select_i2c_ch_pca(I2C_CH_IDT); @@ -279,16 +526,16 @@ int config_serdes1_refclks(void) SERDES_REFCLK_122_88, 0); if (ret) { printf("IDT8T49N222A configuration failed.\n"); - return ret; + goto out; } else - printf("IDT8T49N222A configured.\n"); + debug("IDT8T49N222A configured.\n"); } else { - return ret; + goto out; } select_i2c_ch_pca(I2C_CH_DEFAULT); /* Change SerDes1's Refclk1 to 125MHz for on board - * SGMIIs to work + * SGMIIs or Aurora to work */ for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl @@ -300,20 +547,21 @@ int config_serdes1_refclks(void) case SGMII_FM1_DTSEC4: case SGMII_FM1_DTSEC5: case SGMII_FM1_DTSEC6: - flag_sgmii_prtcl++; + case AURORA: + flag_sgmii_aurora_prtcl++; break; default: break; } } - if (flag_sgmii_prtcl) + if (flag_sgmii_aurora_prtcl) QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); /* Steps For SerDes PLLs reset and reconfiguration after * changing SerDes's refclks */ - for (i = 0; i < PLL_NUM; i++) { + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { debug("For PLL%d reset and reconfiguration after" " changing refclks\n", i+1); clrbits_be32(&srds_regs->bank[i].rstctl, @@ -333,16 +581,101 @@ int config_serdes1_refclks(void) printf("WARNING:IDT8T49N222A configuration not" " supported for:%x SerDes1 Protocol.\n", serdes1_prtcl); - return -1; } - return 0; +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; +} + +int config_serdes2_refclks(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + u32 serdes2_prtcl; + int ret = 0; + int i; + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + debug("SERDES2 is not enabled\n"); + return -ENODEV; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request + */ + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + + /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work + * For this SerDes2's Refclk1 need to be set to 100MHz + */ + switch (serdes2_prtcl) { + case 0x9E: + case 0x9A: + case 0xb2: + debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", + serdes2_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, + SERDES_REFCLK_100, + SERDES_REFCLK_156_25, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + goto out; + } else + debug("IDT8T49N222A configured.\n"); + } else { + goto out; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + clrbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + + udelay(10); + } + break; + default: + printf("IDT configuration not supported for:%x S2 Protocol.\n", + serdes2_prtcl); + } + +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; } int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int ret; /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -375,6 +708,35 @@ int board_early_init_r(void) else printf("SerDes1 Refclks have been set.\n"); + /* SerDes2 refclks need to be set again, as default clks + * are not suitable for PCIe SATA to work + * This function will set SerDes2's Refclk1 and refclk2 + * for SerDes2 protocols having PCIe in them + * for PCIe SATA to work + */ + ret = config_serdes2_refclks(); + if (!ret) + printf("SerDes2 Refclks have been set.\n"); + else if (ret == -ENODEV) + printf("SerDes disable, Refclks couldn't change.\n"); + else + printf("SerDes2 Refclk reconfiguring failed.\n"); + +#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A006475) + /* Rechecking the SerDes locks after all SerDes configurations + * are done, As SerDes PLLs may not lock reliably at 5 G VCO + * and at cold temperatures. + * Following sequence ensure the proper locking of SerDes PLLs. + */ + if (SVR_MAJ(get_svr()) == 1) { + if (check_serdes_pll_locks()) + printf("SerDes plls still not locked properly.\n"); + else + printf("SerDes plls have been locked well.\n"); + } +#endif + /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) printf("VSC:failed to configure VSC3316/3308.\n"); diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index db0cf28fff..fcccb8f9b3 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -24,6 +24,10 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {5, 14}, {4, 15}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {5, 14}, + {4, 15}, {2, 12}, {12, 13} }; + #ifdef CONFIG_PPC_B4420 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; @@ -46,6 +50,10 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 11}, {15, 10}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 11}, + {15, 10}, {13, 3}, {12, 12} }; + #ifdef CONFIG_PPC_B4420 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index a8fc845193..12df9a8d9f 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void) serdes2_prtcl); switch (serdes2_prtcl) { + case 0x17: case 0x18: /* * Configuration: @@ -198,6 +199,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); switch (serdes1_prtcl) { + case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Setting phy addresses for FM1_DTSEC5: %x and" @@ -209,6 +211,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); break; #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Setting phy addresses for FM1_DTSEC3: %x and" @@ -228,6 +231,7 @@ int board_eth_init(bd_t *bis) break; } switch (serdes2_prtcl) { + case 0x17: case 0x18: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n"); @@ -240,6 +244,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; + case 0x48: case 0x49: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n"); diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile index 626d48aea7..818484a57d 100644 --- a/board/freescale/c29xpcie/Makefile +++ b/board/freescale/c29xpcie/Makefile @@ -3,8 +3,23 @@ # # SPDX-License-Identifier: GPL-2.0+ +MINIMAL= +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +obj-y += spl_minimal.o tlb.o law.o +else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + obj-y += c29xpcie.o obj-y += cpld.o obj-y += ddr.o obj-y += law.o obj-y += tlb.o +endif diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README index 430f08244a..3bc396b35a 100644 --- a/board/freescale/c29xpcie/README +++ b/board/freescale/c29xpcie/README @@ -62,9 +62,9 @@ Build and program u-boot to NOR flash 2. Program u-boot.bin into NOR flash => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize 3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. @@ -73,9 +73,9 @@ Alternate NOR bank There are four banks in C29XPCIE board, example to change bank booting: 1. Program u-boot.bin into alternate NOR bank => tftp $loadaddr $uboot - => protect off e9f80000 +$filesize - => erase e9f80000 +$filesize - => cp.b $loadaddr e9f80000 $filesize + => protect off e9f40000 +$filesize + => erase e9f40000 +$filesize + => cp.b $loadaddr e9f40000 $filesize 2. Switch to alternate NOR bank => cpld_cmd reset altbank [bank] diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c index 5cbccff633..37722daf5b 100644 --- a/board/freescale/c29xpcie/cpld.c +++ b/board/freescale/c29xpcie/cpld.c @@ -89,6 +89,7 @@ static void cpld_dump_regs(void) } #endif +#ifndef CONFIG_SPL_BUILD int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; @@ -129,3 +130,4 @@ U_BOOT_CMD( "cpld_cmd dump - display the CPLD registers\n" #endif ); +#endif diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c new file mode 100644 index 0000000000..2111711400 --- /dev/null +++ b/board/freescale/c29xpcie/spl.c @@ -0,0 +1,77 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + puts("TPL\n"); +#else + puts("SPL\n"); +#endif + + nand_boot(); +} diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c new file mode 100644 index 0000000000..8f96b67e84 --- /dev/null +++ b/board/freescale/c29xpcie/spl_minimal.c @@ -0,0 +1,63 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot...\n"); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("SPL\n"); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index 84844ee0f5..c5abed0504 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -42,6 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), +#endif #endif SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, @@ -49,7 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_256K, 1), -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_256M, 1), #endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 25f063d3ad..f6a0879753 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -13,7 +13,10 @@ MINIMAL=y endif endif -ifndef MINIMAL +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index f6e2b2bbd6..022f38b117 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -16,6 +16,8 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 +#define ESDHC_DEFAULT_ENVADDR 0x400 + int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; @@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) /* Get the code size from offset 0x48 */ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); +#ifdef CONFIG_ESDHC_HC_BLK_ADDR + /* + * On soc BSC9131, BSC9132: + * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + * code length of these soc specify the memory address in block address + * format. Block length is fixed to 512 bytes as per the SD High + * Capacity specification. + */ + u64 tmp; + + if (mmc->high_capacity) { + tmp = (u64)code_offset * blklen; + tmp += code_len * blklen; + } else + tmp = code_offset + code_len; + + if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) || + (tmp > 0xFFFFFFFFU)) + *env_addr = ESDHC_DEFAULT_ENVADDR; + else + *env_addr = tmp; + + free(tmp_buf); + + return 0; +#endif + *env_addr = code_offset + code_len; free(tmp_buf); diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile deleted file mode 100644 index 77138c6073..0000000000 --- a/board/freescale/m5271evb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = m5271evb.o diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk deleted file mode 100644 index 957f584887..0000000000 --- a/board/freescale/m5271evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c deleted file mode 100644 index 5981a2711a..0000000000 --- a/board/freescale/m5271evb/m5271evb.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: Freescale M5271EVB\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - - int i; - - /* Enable Address lines 23-21 and lower 16bits of data path */ - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | - MCF_GPIO_AD_DATAL); - - /* Set CS2 pin to be SD_CS0 */ - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) - | MCF_GPIO_PAR_CS_PAR_CS2); - - /* Configure SDRAM Control Pin Assignemnt Register */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_11); - asm(" nop"); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(2) - | MCF_SDRAMC_DCR_RC(0x2E)); - asm(" nop"); - - /* - * Initialize DACR0 - * - * CASL: 01 - * CBM: cmd at A20, bank select bits 21 and up - * PS: 32bit port size - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) - | MCF_SDRAMC_DACRn_CASL(1) - | MCF_SDRAMC_DACRn_CBM(3) - | MCF_SDRAMC_DACRn_PS(0)); - asm(" nop"); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M - | MCF_SDRAMC_DMRn_V); - asm(" nop"); - - /* Set IP bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_IP); - asm(" nop"); - - /* Wait at least 20ns to allow banks to precharge */ - for (i = 0; i < 5; i++) - asm(" nop"); - - /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - asm(" nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_MRS); - asm(" nop"); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 2 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; - asm(" nop"); - } - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds deleted file mode 100644 index 3defcd25c1..0000000000 --- a/board/freescale/m5271evb/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk index b306d031b9..07f52e0255 100644 --- a/board/freescale/m54418twr/config.mk +++ b/board/freescale/m54418twr/config.mk @@ -4,6 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 1cca176c38..6da1d4b5f5 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -69,7 +69,12 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c @@ -90,7 +95,7 @@ SECTIONS KEEP(*(.__bss_end)); } - .dynsym _end : { *(.dynsym) } + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index db0bf17363..b32a97ff1a 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -30,24 +30,41 @@ DECLARE_GLOBAL_DATA_PTR; +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + int dram_init(void) { - u32 size1, size2; + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } u32 get_board_rev(void) @@ -343,6 +360,7 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { u32 cpurev; @@ -356,6 +374,7 @@ int print_cpuinfo(void) printf("Reset cause: %s\n", get_reset_cause()); return 0; } +#endif /* * Do not overwrite the console diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg index 6d192a6b4b..16bf473164 100644 --- a/board/freescale/mx6qsabreauto/imximage.cfg +++ b/board/freescale/mx6qsabreauto/imximage.cfg @@ -29,119 +29,101 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 DATA 4 0x020e05a8 0x00000028 DATA 4 0x020e05b0 0x00000028 DATA 4 0x020e0524 0x00000028 DATA 4 0x020e051c 0x00000028 - DATA 4 0x020e0518 0x00000028 DATA 4 0x020e050c 0x00000028 DATA 4 0x020e05b8 0x00000028 DATA 4 0x020e05c0 0x00000028 - -DATA 4 0x020e05ac 0x00000028 -DATA 4 0x020e05b4 0x00000028 -DATA 4 0x020e0528 0x00000028 -DATA 4 0x020e0520 0x00000028 - -DATA 4 0x020e0514 0x00000028 -DATA 4 0x020e0510 0x00000028 -DATA 4 0x020e05bc 0x00000028 -DATA 4 0x020e05c4 0x00000028 - -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 - -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00000030 -DATA 4 0x020e0598 0x00000030 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0774 0x00020000 DATA 4 0x020e0784 0x00000028 DATA 4 0x020e0788 0x00000028 - DATA 4 0x020e0794 0x00000028 DATA 4 0x020e079c 0x00000028 DATA 4 0x020e07a0 0x00000028 DATA 4 0x020e07a4 0x00000028 - DATA 4 0x020e07a8 0x00000028 DATA 4 0x020e0748 0x00000028 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 DATA 4 0x021b0824 0x33333333 DATA 4 0x021b0828 0x33333333 - DATA 4 0x021b481c 0x33333333 DATA 4 0x021b4820 0x33333333 DATA 4 0x021b4824 0x33333333 DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00001740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x8A8F7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x008F0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00020036 -DATA 4 0x021b0040 0x00000047 -DATA 4 0x021b0000 0x841A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x09408030 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 - -/* Calibration values based on ARD and 528MHz */ -DATA 4 0x021b083c 0x434B0358 -DATA 4 0x021b0840 0x033D033C -DATA 4 0x021b483c 0x03520362 -DATA 4 0x021b4840 0x03480318 -DATA 4 0x021b0848 0x41383A3C -DATA 4 0x021b4848 0x3F3C374A -DATA 4 0x021b0850 0x42434444 -DATA 4 0x021b4850 0x4932473A - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x001F001F -DATA 4 0x021b4810 0x001F001F - DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 DATA 4 0x021b0004 0x00025576 - +DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 12d8c5664e..d7d932eeb8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -135,6 +135,16 @@ static void setup_spi(void) imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + iomux_v3_cfg_t const di0_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ @@ -454,6 +464,7 @@ int overwrite_console(void) int board_eth_init(bd_t *bis) { setup_iomux_enet(); + setup_pcie(); return cpu_eth_init(bis); } diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index c4962549a7..aadad3266f 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index d6f05f3cfe..660d1bbc2a 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -18,6 +18,10 @@ obj-y += spl_minimal.o tlb.o law.o else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + obj-y += p1010rdb.o obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA index 158a1b3152..cde246dde2 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -104,9 +104,9 @@ Build and burn u-boot to NOR flash 2. Burn u-boot.bin into NOR flash => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. @@ -115,9 +115,9 @@ Alternate NOR bank ================== 1. Burn u-boot.bin into alternate NOR bank => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize + => protect off eef40000 +$filesize + => erase eef40000 +$filesize + => cp.b $loadaddr eef40000 $filesize 2. Switch to alternate NOR bank => mw.b ffb00009 1 diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB index cf459b339e..c5d1419445 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PB +++ b/board/freescale/p1010rdb/README.P1010RDB-PB @@ -149,11 +149,11 @@ Steps to program images to flash for different boot mode 1. NOR boot => tftp 1000000 u-boot.bin For bank0 - => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board For bank1 - => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize + => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board 2. NAND boot diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c new file mode 100644 index 0000000000..11bd9cfccc --- /dev/null +++ b/board/freescale/p1010rdb/spl.c @@ -0,0 +1,108 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + console_init_f(); + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + +#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("\nTertiary program loader running in sram..."); +#else + puts("\nSecond program loader running in sram..."); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 39a5a0f37b..607957003d 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -16,78 +16,16 @@ DECLARE_GLOBAL_DATA_PTR; - -void sdram_init(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 ddr_ratio; - unsigned long ddr_freq_mhz; - - ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000; - - /* mask off E bit */ - u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - - __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - if (ddr_freq_mhz < 700) { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); - } else { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - } - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - - /* P1014 and it's derivatives support max 16bit DDR width */ - if (svr == SVR_P1014) { - __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); - __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); - /* For CS0_BNDS we divide the start and end address by 2, so we can just - * shift the entire register to achieve the desired result and the mask - * the value so we don't write reserved fields */ - __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); - } - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; @@ -98,9 +36,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -111,6 +46,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a3d36b35d5..af40f979d3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -73,10 +73,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1) + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) #endif }; diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 7f151e38cf..7bd9d296ee 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -21,7 +21,7 @@ static const u32 sysclk_tbl[] = { 99999000, 11111000, 12499800, 13333200 }; -ulong get_effective_memsize(void) +phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; } diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README index 685f5daa99..d382551c4d 100644 --- a/board/freescale/p1023rds/README +++ b/board/freescale/p1023rds/README @@ -62,8 +62,8 @@ To program the image in the boot flash bank: NOR flash boot: => tftp 1000000 u-boot.bin => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 NAND flash boot: => tftp 1000000 u-boot-nand.bin diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README index cb664a5bd7..cd66e5878d 100644 --- a/board/freescale/p1_p2_rdb/README +++ b/board/freescale/p1_p2_rdb/README @@ -20,8 +20,8 @@ Memory Map 0xef00_0000 - 0xef7f_ffff Alternate bank 8MB 0xe800_0000 - 0xefff_ffff Boot bank 8MB -0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB +0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB +0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB Switch settings to boot from the NOR flash banks ------------------------------------------------ @@ -33,16 +33,16 @@ Flashing Images To place a new u-boot image in the alternate flash bank and then boot with that new image temporarily, use this: tftp 1000000 u-boot.bin - erase ef780000 ef7fffff - cp.b 1000000 ef780000 80000 + erase ef740000 ef7fffff + cp.b 1000000 ef740000 c0000 Now to boot from the alternate bank change the SW4[8] from 0 to 1. To program the image in the boot flash bank: tftp 1000000 u-boot.bin protect off all - erase eff80000 ffffffff - cp.b 1000000 eff80000 80000 + erase eff40000 ffffffff + cp.b 1000000 eff40000 c0000 Using the Device Tree Source File --------------------------------- diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 9bb071692d..8d0d850480 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -20,7 +20,7 @@ static const u32 sysclk_tbl[] = { 99999000, 11111000, 12499800, 13333200 }; -ulong get_effective_memsize(void) +phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; } diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 292d0d39cf..9b5539fff3 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -18,8 +18,8 @@ Boot from NOR flash 2. Program image => tftp 1000000 u-boot.bin => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 3. Program RCW => tftp 1000000 rcw.bin @@ -30,8 +30,8 @@ Boot from NOR flash 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin => protect off all - => erase ef000000 ef0fffff - => cp.b 1000000 ef000000 2000 + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 5. Change DIP-switch SW1[1-5] = 10110 @@ -50,11 +50,11 @@ Boot from SDCard 3. Program the PBL image to SDCard => tftp 1000000 pbl_sd.bin => mmcinfo - => mmc write 1000000 8 441 + => mmc write 1000000 8 672 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin - => mmc write 1000000 46a 10 + => mmc write 1000000 690 10 5. Change DIP-switch SW1[1-5] = 01100 diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 93af9eb6a0..19ed21b7df 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -9,3 +9,5 @@ obj-y += ddr.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += eth.o +obj-y += diu.o diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index f8b53b4212..8160ca0bc0 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -118,17 +118,17 @@ Start Address End Address Description Size NOR Flash memory Map on T1040QDS -------------------------------- Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB -0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB -0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB -0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e79d..afa72af26a 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -31,16 +31,18 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {} }; diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c new file mode 100644 index 0000000000..ffd074b0f8 --- /dev/null +++ b/board/freescale/t1040qds/diu.c @@ -0,0 +1,215 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t1040qds.h" +#include "t1040qds_qixis.h" +#include + + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret = 0; + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Route I2C4 to DIU system as HSYNC/VSYNC*/ + sw = QIXIS_READ(brdcfg[5]); + QIXIS_WRITE(brdcfg[5], + ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); + + /*Configure Display ouput port as HDMI*/ + sw = QIXIS_READ(brdcfg[15]); + QIXIS_WRITE(brdcfg[15], + ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) + | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); + + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c new file mode 100644 index 0000000000..3077b4ae2c --- /dev/null +++ b/board/freescale/t1040qds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY connected to + * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board + * PHY or by the standard four-port SGMII riser card (VSC). + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "../common/qixis.h" + +#include "t1040qds_qixis.h" + +#ifdef CONFIG_FMAN_ENET + /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D + * Bank 2 -> Lanes E, F, G, H + */ + + /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII0 0 +#define EMI1_RGMII1 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1040_QDS_MDIO0", + "T1040_QDS_MDIO1", + "T1040_QDS_MDIO2", + "T1040_QDS_MDIO3", + "T1040_QDS_MDIO4", + "T1040_QDS_MDIO5", + "T1040_QDS_MDIO6", + "T1040_QDS_MDIO7", +}; + +struct t1040_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t1040_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void t1040_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval <= 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1040_qds_mdio_reset(struct mii_dev *bus) +{ + struct t1040_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1040_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1040_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1040_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1040_qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1040_qds_mdio_read; + bus->write = t1040_qds_mdio_write; + bus->reset = t1040_qds_mdio_reset; + sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the lane_to_slot[] array. + * + * On the T1040QDS board the mapping is controlled by ?? register. + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL) + >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + QIXIS_WRITE(cms[0], 0x07); + + switch (serdes1_prtcl) { + case 0x60: + case 0x66: + case 0x67: + case 0x69: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + break; + case 0x86: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + case 0x87: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x89: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x8d: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0x8F: + case 0x85: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA5: + lane_to_slot[1] = 7; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA7: + lane_to_slot[1] = 7; + lane_to_slot[7] = 7; + break; + case 0xAA: + lane_to_slot[1] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x40: + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + default: + printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + /* Slot housing a SGMII riser card */ + sprintf(phy, "phy_s%x_%02x", slot, + (fm_info_get_phy_address(port - FM1_DTSEC1)- + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT5: + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + break; + case EMI1_SLOT6: + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + break; + case EMI1_SLOT7: + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC4) + fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); + + if (i == FM1_DTSEC5) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + break; + default: + break; + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +static void set_brdcfg9_for_gtx_clk(void) +{ + u8 brdcfg9; + brdcfg9 = QIXIS_READ(brdcfg[9]); + brdcfg9 |= (1 << 5); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +void t1040_handle_phy_interface_sgmii(int i) +{ + int lane, idx, slot; + idx = i - FM1_DTSEC1; + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + + if (lane < 0) + return; + slot = lane_to_slot[lane]; + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + if (FM1_DTSEC4 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + + mdio_mux[i] = EMI1_SLOT3; + + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 5: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 6: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 7: + if (FM1_DTSEC1 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC2 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + if (FM1_DTSEC3 == i) + fm_info_set_phy_address(i, riser_phy_addr[2]); + + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} +void t1040_handle_phy_interface_rgmii(int i) +{ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : + EMI1_RGMII0; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + set_brdcfg9_for_gtx_clk(); + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + + /* + * Program on board RGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + break; + case PHY_INTERFACE_MODE_SGMII: + t1040_handle_phy_interface_sgmii(i); + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + t1040_handle_phy_interface_rgmii(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index de3ea5c2aa..3dec4473e5 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); #endif } diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h index 79bdedaff3..5041f379de 100644 --- a/board/freescale/t1040qds/t1040qds.h +++ b/board/freescale/t1040qds/t1040qds.h @@ -9,5 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); +int select_i2c_ch_pca9547(u8 ch); #endif diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h index 2ce87959b5..98d2d39e6d 100644 --- a/board/freescale/t1040qds/t1040qds_qixis.h +++ b/board/freescale/t1040qds/t1040qds_qixis.h @@ -13,6 +13,18 @@ #define BRDCFG4_EMISEL_MASK 0xE0 #define BRDCFG4_EMISEL_SHIFT 5 +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_MASK 0xC0 +#define BRDCFG5_IMX_DIU 0x80 + +/* BRDCFG15[3] controls LCD Panel Powerdown*/ +#define BRDCFG15_LCDPD_MASK 0x10 +#define BRDCFG15_LCDPD_ENABLED 0x00 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_MASK 0x03 +#define BRDCFG15_DIUSEL_HDMI 0x00 + /* SYSCLK */ #define QIXIS_SYSCLK_66 0x0 #define QIXIS_SYSCLK_83 0x1 diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 76c0c94b0e..e51fb7a7f4 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -7,6 +7,7 @@ obj-y += t104xrdb.o obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 2cd8219c84..1da52bb0b0 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -161,17 +161,17 @@ Start Address End Address Description Size NOR Flash memory Map --------------------- Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB -0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB -0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB -0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 9009afa3ad..57d0f9cfd8 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp = udimms[0]; - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr + /* Get clk_adjust according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -112,8 +105,8 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); } phys_size_t initdram(int board_type) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index 9276b596ac..09b30b9aac 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -6,7 +6,6 @@ #ifndef __DDR_H__ #define __DDR_H__ - dimm_params_t ddr_raw_timing = { .n_ranks = 2, .rank_density = 2147483648u, @@ -14,22 +13,21 @@ dimm_params_t ddr_raw_timing = { .primary_sdram_width = 64, .ec_sdram_width = 8, .registered_dimm = 0, - .mirrored_dimm = 1, + .mirrored_dimm = 0, .n_row_addr = 15, .n_col_addr = 10, .n_banks_per_sdram_device = 8, .edc_config = 2, /* ECC */ .burst_lengths_bitmask = 0x0c, - .tckmin_x_ps = 1071, - .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ - .taa_ps = 13910, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, .twr_ps = 15000, - .trcd_ps = 13910, + .trcd_ps = 13125, .trrd_ps = 6000, - .trp_ps = 13910, + .trp_ps = 13125, .tras_ps = 34000, - .trc_ps = 48910, + .trc_ps = 48125, .trfc_ps = 260000, .twtr_ps = 7500, .trtp_ps = 7500, @@ -45,9 +43,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -59,14 +54,21 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 */ - {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0}, - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, {} }; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c new file mode 100644 index 0000000000..0188fd4090 --- /dev/null +++ b/board/freescale/t104xrdb/eth.c @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + int phy_addr = 0; + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { +#ifdef CONFIG_T1040RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1040RDB only supports SGMII on DTSEC3 */ + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_SGMII1_PHY_ADDR); +#endif + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h deleted file mode 100644 index 964eaada18..0000000000 --- a/board/freescale/t2080qds/ddr.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - - -#endif diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t208xqds/Makefile similarity index 53% rename from board/freescale/t2080qds/Makefile rename to board/freescale/t208xqds/Makefile index 0b8747b877..947b7f7324 100644 --- a/board/freescale/t2080qds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,8 +4,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_T2080QDS) += t2080qds.o -obj-$(CONFIG_T2080QDS) += eth_t2080qds.o +obj-$(CONFIG_T2080QDS) += t208xqds.o +obj-$(CONFIG_T2080QDS) += eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o +obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t208xqds/ddr.c similarity index 89% rename from board/freescale/t2080qds/ddr.c rename to board/freescale/t208xqds/ddr.c index 5db5d21622..ed1334d985 100644 --- a/board/freescale/t2080qds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (ctrl_num > 2) { + if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } @@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, else pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -49,14 +48,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -69,13 +64,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h new file mode 100644 index 0000000000..9fc879a4ef --- /dev/null +++ b/board/freescale/t208xqds/ddr.h @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; +#endif diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t208xqds/eth_t208xqds.c similarity index 65% rename from board/freescale/t2080qds/eth_t2080qds.c rename to board/freescale/t208xqds/eth_t208xqds.c index 3613f93981..d7a804d22a 100644 --- a/board/freescale/t2080qds/eth_t2080qds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -25,21 +25,31 @@ #include #include "../common/qixis.h" #include "../common/fman.h" -#include "t2080qds_qixis.h" +#include "t208xqds_qixis.h" #define EMI_NONE 0xFFFFFFFF #define EMI1_RGMII1 0 #define EMI1_RGMII2 1 #define EMI1_SLOT1 2 +#if defined(CONFIG_T2080QDS) #define EMI1_SLOT2 6 #define EMI1_SLOT3 3 #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 -#define EMI2 7 +#define EMI2 7 +#elif defined(CONFIG_T2081QDS) +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 +#endif static int mdio_mux[NUM_FM_PORTS]; static const char * const mdio_names[] = { +#if defined(CONFIG_T2080QDS) "T2080QDS_MDIO_RGMII1", "T2080QDS_MDIO_RGMII2", "T2080QDS_MDIO_SLOT1", @@ -48,12 +58,27 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", +#elif defined(CONFIG_T2081QDS) + "T2081QDS_MDIO_RGMII1", + "T2081QDS_MDIO_RGMII2", + "T2081QDS_MDIO_SLOT1", + "T2081QDS_MDIO_SLOT2", + "T2081QDS_MDIO_SLOT3", + "T2081QDS_MDIO_SLOT5", + "T2081QDS_MDIO_SLOT6", + "T2081QDS_MDIO_SLOT7", + "T2081QDS_MDIO_10GC", +#endif }; /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +#if defined(CONFIG_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; +#elif defined(CONFIG_T2081QDS) +static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; +#endif -static const char *T2080qds_mdio_name_for_muxval(u8 muxval) +static const char *t208xqds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; } @@ -61,7 +86,7 @@ static const char *T2080qds_mdio_name_for_muxval(u8 muxval) struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; - const char *name = T2080qds_mdio_name_for_muxval(muxval); + const char *name = t208xqds_mdio_name_for_muxval(muxval); if (!name) { printf("No bus for muxval %x\n", muxval); @@ -78,15 +103,15 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } -struct T2080qds_mdio { +struct t208xqds_mdio { u8 muxval; struct mii_dev *realbus; }; -static void T2080qds_mux_mdio(u8 muxval) +static void t208xqds_mux_mdio(u8 muxval) { u8 brdcfg4; - if (muxval < 7) { + if (muxval < 8) { brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= ~BRDCFG4_EMISEL_MASK; brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); @@ -94,54 +119,54 @@ static void T2080qds_mux_mdio(u8 muxval) } } -static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad, +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, int regnum) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv; - T2080qds_mux_mdio(priv->muxval); + t208xqds_mux_mdio(priv->muxval); return priv->realbus->read(priv->realbus, addr, devad, regnum); } -static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad, +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, int regnum, u16 value) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv; - T2080qds_mux_mdio(priv->muxval); + t208xqds_mux_mdio(priv->muxval); return priv->realbus->write(priv->realbus, addr, devad, regnum, value); } -static int T2080qds_mdio_reset(struct mii_dev *bus) +static int t208xqds_mdio_reset(struct mii_dev *bus) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv; return priv->realbus->reset(priv->realbus); } -static int T2080qds_mdio_init(char *realbusname, u8 muxval) +static int t208xqds_mdio_init(char *realbusname, u8 muxval) { - struct T2080qds_mdio *pmdio; + struct t208xqds_mdio *pmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { - printf("Failed to allocate T2080QDS MDIO bus\n"); + printf("Failed to allocate t208xqds MDIO bus\n"); return -1; } pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { - printf("Failed to allocate T2080QDS private data\n"); + printf("Failed to allocate t208xqds private data\n"); free(bus); return -1; } - bus->read = T2080qds_mdio_read; - bus->write = T2080qds_mdio_write; - bus->reset = T2080qds_mdio_reset; - sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval)); + bus->read = t208xqds_mdio_read; + bus->write = t208xqds_mdio_write; + bus->reset = t208xqds_mdio_reset; + sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); @@ -154,7 +179,6 @@ static int T2080qds_mdio_init(char *realbusname, u8 muxval) pmdio->muxval = muxval; bus->priv = pmdio; - return mdio_register(bus); } @@ -173,13 +197,20 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); switch (port) { +#if defined(CONFIG_T2080QDS) case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC9: case FM1_DTSEC10: - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } break; case FM1_DTSEC5: case FM1_DTSEC6: @@ -193,6 +224,36 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; +#elif defined(CONFIG_T2081QDS) + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } else if (mdio_mux[port] == EMI1_SLOT5) { + sprintf(alias, "phy_sgmii_s5_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + } else if (mdio_mux[port] == EMI1_SLOT6) { + sprintf(alias, "phy_sgmii_s6_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + } else if (mdio_mux[port] == EMI1_SLOT7) { + sprintf(alias, "phy_sgmii_s7_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + } + break; +#endif default: break; } @@ -226,8 +287,8 @@ void fdt_fixup_board_enet(void *fdt) } /* - * This function reads RCW to check if Serdes1{E,F,G,H} is configured - * as slot 1/2/3 and update the lane_to_slot[] array accordingly + * This function reads RCW to check if Serdes1{A:H} is configured + * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly */ static void initialize_lane_to_slot(void) { @@ -238,6 +299,7 @@ static void initialize_lane_to_slot(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; switch (srds_s1) { +#if defined(CONFIG_T2080QDS) case 0x51: case 0x5f: case 0x65: @@ -264,6 +326,31 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; +#elif defined(CONFIG_T2081QDS) + case 0x6b: + lane_to_slot[4] = 1; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xca: + case 0xcb: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xf2: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 4; + lane_to_slot[6] = 3; + lane_to_slot[7] = 7; + break; +#endif default: break; } @@ -305,14 +392,20 @@ int board_eth_init(bd_t *bis) fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); +#if defined(CONFIG_T2080QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); +#endif + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); +#if defined(CONFIG_T2081QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); +#endif + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); @@ -327,21 +420,21 @@ int board_eth_init(bd_t *bis) case 0x95: case 0xa2: case 0x94: - /* SGMII in Slot3 */ + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x51: case 0x5f: case 0x65: - /* XAUI/HiGig in Slot3 */ + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; @@ -365,15 +458,17 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0x6c: case 0x6d: - /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x71: /* SGMII in Slot3 */ @@ -406,6 +501,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; +#if defined(CONFIG_T2080QDS) case 0xd9: case 0xd3: case 0xcb: @@ -417,8 +513,28 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; +#elif defined(CONFIG_T2081QDS) + case 0xca: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + /* SGMII in Slot5 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot6 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; +#endif + case 0xf2: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; default: - puts("Invalid SerDes1 protocol for T2080QDS\n"); break; } @@ -448,7 +564,29 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; - }; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#if defined(CONFIG_T2081QDS) + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 6: + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 7: + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#endif + } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t208xqds/law.c similarity index 100% rename from board/freescale/t2080qds/law.c rename to board/freescale/t208xqds/law.c diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t208xqds/pci.c similarity index 100% rename from board/freescale/t2080qds/pci.c rename to board/freescale/t208xqds/pci.c diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg similarity index 100% rename from board/freescale/t2080qds/t2080_rcw.cfg rename to board/freescale/t208xqds/t2080_rcw.cfg diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg new file mode 100644 index 0000000000..a2d5ecf4ad --- /dev/null +++ b/board/freescale/t208xqds/t2081_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg similarity index 100% rename from board/freescale/t2080qds/t2080_pbi.cfg rename to board/freescale/t208xqds/t208x_pbi.cfg diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t208xqds/t208xqds.c similarity index 67% rename from board/freescale/t2080qds/t2080qds.c rename to board/freescale/t208xqds/t208xqds.c index cac32fe73c..9cfc0bd7c3 100644 --- a/board/freescale/t2080qds/t2080qds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -20,8 +20,8 @@ #include "../common/qixis.h" #include "../common/vsc3316_3308.h" -#include "t2080qds.h" -#include "t2080qds_qixis.h" +#include "t208xqds.h" +#include "t208xqds_qixis.h" DECLARE_GLOBAL_DATA_PTR; @@ -40,6 +40,11 @@ int checkboard(void) printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -51,6 +56,7 @@ int checkboard(void) puts("NAND\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); @@ -83,27 +89,42 @@ int select_i2c_ch_pca9547(u8 ch) int brd_mux_lane_to_slot(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; + u32 srds_prtcl_s1; srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & +#if defined(CONFIG_T2080QDS) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; +#endif switch (srds_prtcl_s1) { case 0: /* SerDes1 is not enabled */ break; +#if defined(CONFIG_T2080QDS) case 0x1c: - case 0x95: case 0xa2: - case 0x94: /* SD1(A:D) => SLOT3 SGMII * SD1(G:H) => SLOT1 SGMII */ - QIXIS_WRITE(brdcfg[12], 0x58); + QIXIS_WRITE(brdcfg[12], 0x1a); + break; + case 0x94: + case 0x95: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:H) => SLOT1 SGMII@1.25bps + */ + case 0x96: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C) => SFP Module, SGMII@3.125bps + * SD1(D) => SFP Module, SGMII@1.25bps + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x3a); break; case 0x51: /* SD1(A:D) => SLOT3 XAUI @@ -134,12 +155,117 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0xda); break; + case 0x6e: + /* SD1(A:B) => SFP Module, XFI + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xd9); + break; + case 0xda: + /* SD1(A:H) => SLOT3 PCIe3 x8 + */ + QIXIS_WRITE(brdcfg[12], 0x0); + break; + case 0xc8: + /* SD1(A) => SLOT3 PCIe3 x1 + * SD1(B) => SFP Module, SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x79); + break; + case 0xab: + /* SD1(A:D) => SLOT3 PCIe3 x4 + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; +#elif defined(CONFIG_T2081QDS) + case 0x51: + /* SD1(A:D) => SLOT2 XAUI + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6b: + /* SD1(A:D) => XFI SFP Module + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6c: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0x6d: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xaa: + case 0xab: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(F:H) => SLOT1 SGMI4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xf8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xca: + case 0xcb: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B) => SLOT7 SGMII + * SD1(C) => SLOT6 SGMII + * SD1(D) => SLOT5 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0xde: + case 0xdf: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x25); + break; + case 0xf2: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B:D) => SLOT7 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x81); + QIXIS_WRITE(brdcfg[13], 0xa5); + break; +#endif default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", srds_prtcl_s1); return -1; } +#ifdef CONFIG_T2080QDS switch (srds_prtcl_s2) { case 0: /* SerDes2 is not enabled */ @@ -147,7 +273,7 @@ int brd_mux_lane_to_slot(void) case 0x01: case 0x02: /* SD2(A:H) => SLOT4 PCIe1 */ - QIXIS_WRITE(brdcfg[13], 0x20); + QIXIS_WRITE(brdcfg[13], 0x10); break; case 0x15: case 0x16: @@ -164,7 +290,7 @@ int brd_mux_lane_to_slot(void) * SD2(E:F) => SLOT5 Aurora * SD2(G:H) => SATA1,SATA2 */ - QIXIS_WRITE(brdcfg[13], 0x70); + QIXIS_WRITE(brdcfg[13], 0x78); break; case 0x1f: /* @@ -180,13 +306,22 @@ int brd_mux_lane_to_slot(void) * SD2(A:D) => SLOT4 SRIO2 * SD2(E:H) => SLOT5 SRIO1 */ - QIXIS_WRITE(brdcfg[13], 0x50); + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x36: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:F) => Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); break; default: printf("WARNING: unsupported for SerDes2 Protocol %d\n", srds_prtcl_s2); return -1; } +#endif return 0; } diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t208xqds/t208xqds.h similarity index 100% rename from board/freescale/t2080qds/t2080qds.h rename to board/freescale/t208xqds/t208xqds.h diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h similarity index 90% rename from board/freescale/t2080qds/t2080qds_qixis.h rename to board/freescale/t208xqds/t208xqds_qixis.h index fc83da707f..bdcdc12f59 100644 --- a/board/freescale/t2080qds/t2080qds_qixis.h +++ b/board/freescale/t208xqds/t208xqds_qixis.h @@ -4,10 +4,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __T2080QDS_QIXIS_H__ -#define __T2080QDS_QIXIS_H__ +#ifndef __T208xQDS_QIXIS_H__ +#define __T208xQDS_QIXIS_H__ -/* Definitions of QIXIS Registers for T2080QDS */ +/* Definitions of QIXIS Registers for T208xQDS */ #define QIXIS_SRDS1CLK_122 0x5a #define QIXIS_SRDS1CLK_125 0x5e @@ -35,6 +35,8 @@ #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ +#define BRDCFG9_SFP_TX_EN 0x10 + #define BRDCFG12_SD3EN_MASK 0x20 #define BRDCFG12_SD3MX_MASK 0x08 #define BRDCFG12_SD3MX_SLOT5 0x08 diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t208xqds/tlb.c similarity index 100% rename from board/freescale/t2080qds/tlb.c rename to board/freescale/t208xqds/tlb.c diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile new file mode 100644 index 0000000000..092c9ff0dc --- /dev/null +++ b/board/freescale/t208xrdb/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T2080RDB) += t208xrdb.o +obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o +obj-$(CONFIG_T2080RDB) += cpld.o +obj-$(CONFIG_PCI) += pci.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README new file mode 100644 index 0000000000..0012c6cb40 --- /dev/null +++ b/board/freescale/t208xrdb/README @@ -0,0 +1,208 @@ +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. +It can work in two mode: standalone mode and PCIe endpoint mode. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080PCIe-RDB board Overview +---------------------------- + - SERDES Configuration + - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) + - SerDes-2 Lane G-H: to SATA1 & SATA2 + - Ethernet + - Two on-board 10M/100M/1G RGMII ethernet ports + - Two on-board 10Gbps XFI fiber ports + - Two on-board 10Gbps Base-T copper ports + - DDR Memory + - Supports 72bit 4GB DDR3-LP SODIMM + - PCIe + - One PCIe x4 gold-finger + - One PCIe x4 connector + - One PCIe x2 end-point device (C293 Crypto co-processor) + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 512MB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - SATA + - Two SATA 2.0 onnectors on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one TF-card connector on-board + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +System Memory map +----------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T2080PCIe-RDB Ethernet Port Map +------------------------------- +Label In Uboot In Linux FMan Address Comments PHY +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) + + +T2080PCIe-RDB Default DIP-Switch setting +---------------------------------------- +SW1[1:8] = '00010011' +SW2[1:8] = '10111111' +SW3[1:8] = '11100001' + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080RDB + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank and alternate bank on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '011' + + To change boot source to vbank0: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '111' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080RDB_NAND_config + $ make u-boot.pbl + b. program u-boot.pbl to NAND flash + => tftp 1000000 u-boot.pbl + => nand erase 0 d0000 + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080RDB_SPIFLASH_config + $ make u-boot.pbl + b. program u-boot.pbl to SPI flash + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf erase 0 d0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080RDB_SDCARD_config + $ make u-boot.pbl + b. program u-boot.pbl to TF card + => tftp 1000000 u-boot.pbl + => mmc write 1000000 8 1650 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +How to update the ucode of Cortina CS4315/CS4340 10G PHY +-------------------------------------------------------- +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080PCIe-RDB User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c new file mode 100644 index 0000000000..4aa126be54 --- /dev/null +++ b/board/freescale/t208xrdb/cpld.c @@ -0,0 +1,71 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale T2080RDB board-specific CPLD controlling supports. + */ + +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" +); diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h new file mode 100644 index 0000000000..4cee4e55cf --- /dev/null +++ b/board/freescale/t208xrdb/cpld.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CPLD register set of T2080RDB board-specific. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - Chip ID1 register */ + u8 chip_id2; /* 0x01 - Chip ID2 register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl; /* 0x10 - Reset control Register */ + u8 flash_csr; /* 0x11 - Flash control and status register */ + u8 thermal_csr; /* 0x12 - Thermal control and status register */ + u8 led_csr; /* 0x13 - LED control and status register */ + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ + u8 misc_csr; /* 0x15 - Misc control and status register */ + u8 boot_or; /* 0x16 - Boot config override register */ + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ +} cpld_data_t; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c new file mode 100644 index 0000000000..01e917398f --- /dev/null +++ b/board/freescale/t208xrdb/ddr.c @@ -0,0 +1,112 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h new file mode 100644 index 0000000000..b6d406219e --- /dev/null +++ b/board/freescale/t208xrdb/ddr.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c new file mode 100644 index 0000000000..cbbc625831 --- /dev/null +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -0,0 +1,106 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x66: + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); + fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); + break; + default: + printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c new file mode 100644 index 0000000000..eb82431e22 --- /dev/null +++ b/board/freescale/t208xrdb/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c new file mode 100644 index 0000000000..ba7041af95 --- /dev/null +++ b/board/freescale/t208xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg new file mode 100644 index 0000000000..e200d926fb --- /dev/null +++ b/board/freescale/t208xrdb/t2080_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg new file mode 100644 index 0000000000..cd62cc8641 --- /dev/null +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T2080RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x66_0x16 +#Core/DDR: 1533Mhz/1600MT/s +120c0017 15000000 00000000 00000000 +66160002 00008400 ec104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c new file mode 100644 index 0000000000..f3fec2aa6e --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -0,0 +1,124 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t208xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", ~reg & 0x7); + } +#endif + + puts("SERDES Reference Clocks:\n"); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h new file mode 100644 index 0000000000..13380d02a3 --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c new file mode 100644 index 0000000000..085d9f5c6a --- /dev/null +++ b/board/freescale/t208xrdb/tlb.c @@ -0,0 +1,151 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 699ea7f010..4ee74c0198 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; void setup_iomux_ddr(void) { static const iomux_v3_cfg_t ddr_pads[] = { - VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A14__DDR_A_14, VF610_PAD_DDR_A13__DDR_A_13, diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk index 309c879489..731a53905f 100644 --- a/board/gaisler/gr_cpci_ax2000/config.mk +++ b/board/gaisler/gr_cpci_ax2000/config.mk @@ -17,5 +17,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x60000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk index d57efae158..6e01f07c0c 100644 --- a/board/gaisler/gr_ep2s60/config.mk +++ b/board/gaisler/gr_ep2s60/config.mk @@ -15,5 +15,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk index e87320be99..e4a66cbcf1 100644 --- a/board/gaisler/gr_xc3s_1500/config.mk +++ b/board/gaisler/gr_xc3s_1500/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk index df26f82c9c..d1f61dac76 100644 --- a/board/gaisler/grsim/config.mk +++ b/board/gaisler/grsim/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk index 99f9a68725..f98b23b800 100644 --- a/board/gaisler/grsim_leon2/config.mk +++ b/board/gaisler/grsim_leon2/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # RUN U-BOOT FROM RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile new file mode 100644 index 0000000000..e8dab89c65 --- /dev/null +++ b/board/gateworks/gw_ventana/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Gateworks Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := gw_ventana.o gsc.o + diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README new file mode 100644 index 0000000000..9e697d6199 --- /dev/null +++ b/board/gateworks/gw_ventana/README @@ -0,0 +1,55 @@ +U-Boot for the Gateworks Ventana Product Family boards + +This file contains information for the port of U-Boot to the Gateworks +Ventana Product family boards. + +1. Boot source, boot from NAND +------------------------------ + +The i.MX6 BOOT ROM expects some structures that provide details of NAND layout +and bad block information (referred to as 'bootstreams') which are replicated +multiple times in NAND. The number of replications is configurable through +board strapping options and eFUSE settings. The Freescale 'kobs-ng' +application from the Freescale LTIB BSP, which runs under Linux, must be used +to program the bootstream in order to setup the replicated headers correctly. + +The Gateworks Ventana boards with NAND flash have been factory programmed +such that their eFUSE settings expect 2 copies of the boostream (this is +specified by providing kobs-ng with the --search_exponent=1 argument). Once in +Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +with: + +kobs-ng init -v -x --search_exponent=1 u-boot.imx + +The kobs-ng application uses an imximage (u-boot.imx) which contains the +Image Vector Table (IVT) and Device Configuration Data (DCD) structures that +the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware +Configuration Block (FCB) and Discovered Bad Block Table (DBBT). + +This information is taken from: + http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH + +More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. + +2. Build +-------- + +There are several Gateworks Ventana boards that share a simliar design but +vary based on CPU, Memory configuration, and subloaded devices. Although +the subloaded devices are handled dynamically in the bootloader using +factory configured EEPROM data to modify the device-tree, the CPU choice +(IMX6Q vs IMX6DL) and memory configurations are currently compile-time +options. + +The following Gateworks Ventana configurations exist: + gwventanaq1gspi: MX6Q,1GB,SPI FLASH + gwventanaq : MX6Q,512MB,NAND FLASH + gwventanaq1g : MX6Q,1GB,NAND FLASH + gwventanadl : MX6DL,512MB,NAND FLASH + gwventanadl1g : MX6DL,1GB,NAND FLASH + +To build U-Boot for the MX6Q,1GB,NAND FLASH for example: + + make gwventanaq1g_config + make + diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg new file mode 100644 index 0000000000..a8118a258e --- /dev/null +++ b/board/gateworks/gw_ventana/clocks.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c new file mode 100644 index 0000000000..37966abba9 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "gsc.h" + +#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_read(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + return ret; +} + +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_write(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(1); + return ret; +} + +#ifdef CONFIG_CMD_GSC +static void read_hwmon(const char *name, uint reg, uint size, uint low, + uint high) +{ + unsigned char buf[3]; + uint ui; + + printf("%-8s:", name); + memset(buf, 0, sizeof(buf)); + if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { + puts("fRD\n"); + } else { + ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); + if (ui == 0xffffff) + printf("invalid"); + else if (ui < low) + printf("%d Failed - Low", ui); + else if (ui > high) + printf("%d Failed - High", ui); + else + printf("%d", ui); + } + puts("\n"); +} + +int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *model = getenv("model"); + + i2c_set_bus_num(0); + read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); + read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); + read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); + read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); + read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); + read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); + read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); + read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); + + switch (model[3]) { + case '1': /* GW51xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + break; + case '2': /* GW52xx */ + case '3': /* GW53xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + case '4': /* GW54xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + } + return 0; +} + +U_BOOT_CMD(gsc, 1, 1, do_gsc, + "GSC test", + "" +); + +#endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h new file mode 100644 index 0000000000..da970c39d6 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASSEMBLY__ + +/* i2c slave addresses */ +#define GSC_SC_ADDR 0x20 +#define GSC_RTC_ADDR 0x68 +#define GSC_HWMON_ADDR 0x29 +#define GSC_EEPROM_ADDR 0x51 + +/* System Controller registers */ +enum { + GSC_SC_CTRL0 = 0x00, + GSC_SC_CTRL1 = 0x01, + GSC_SC_STATUS = 0x0a, + GSC_SC_FWVER = 0x0e, +}; + +/* System Controller Control1 bits */ +enum { + GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ +}; + +/* System Controller Interrupt bits */ +enum { + GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ + GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ + GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ + GSC_SC_IRQ_GPIO = 4, /* GPIO change */ + GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ + GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ + GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ +}; + +/* Hardware Monitor registers */ +enum { + GSC_HWMON_TEMP = 0x00, + GSC_HWMON_VIN = 0x02, + GSC_HWMON_VDD_3P3 = 0x05, + GSC_HWMON_VBATT = 0x08, + GSC_HWMON_VDD_5P0 = 0x0b, + GSC_HWMON_VDD_CORE = 0x0e, + GSC_HWMON_VDD_HIGH = 0x14, + GSC_HWMON_VDD_DDR = 0x17, + GSC_HWMON_VDD_SOC = 0x11, + GSC_HWMON_VDD_1P8 = 0x1d, + GSC_HWMON_VDD_2P5 = 0x23, + GSC_HWMON_VDD_1P0 = 0x20, +}; + +/* + * I2C transactions to the GSC are done via these functions which + * perform retries in the case of a busy GSC NAK'ing the transaction + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +#endif + diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c new file mode 100644 index 0000000000..c130e2c1ed --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -0,0 +1,1263 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gsc.h" +#include "ventana_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO's common to all baseboards */ +#define GP_PHY_RST IMX_GPIO_NR(1, 30) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_RS232_EN IMX_GPIO_NR(2, 11) +#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) + +/* I2C bus numbers */ +#define I2C_GSC 0 +#define I2C_PMIC 1 + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +/* + * EEPROM board info struct populated by read_eeprom so that we only have to + * read it once. + */ +static struct ventana_board_info ventana_info; + +enum { + GW54proto, /* original GW5400-A prototype */ + GW51xx, + GW52xx, + GW53xx, + GW54xx, + GW_UNKNOWN, +}; + +int board_type; + +/* UART1: Function varies per baseboard */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* UART2: Serial Console */ +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1: GSC */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3: Misc/Expansion */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* MMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +/* ENET */ +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* PHY nRST */ + MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* NAND */ +iomux_v3_cfg_t const nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* toggle PHY_RST# */ + gpio_direction_output(GP_PHY_RST, 0); + mdelay(2); + gpio_set_value(GP_PHY_RST, 1); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */ +}; + +int board_ehci_hcd_init(int port) +{ + struct ventana_board_info *info = &ventana_info; + + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB HUB (present on GW54xx/GW53xx) */ + switch (info->model[3]) { + case '3': /* GW53xx */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09| + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 9), 1); + break; + case '4': /* GW54xx */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 16), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 16), 1); + break; + } + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + return 0; + gpio_set_value(GP_USB_OTG_PWR, on); + return 0; +} +#endif /* CONFIG_USB_EHCI_MX6 */ + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Card Detect */ + gpio_direction_input(GP_SD3_CD); + return !gpio_get_value(GP_SD3_CD); +} + +int board_mmc_init(bd_t *bis) +{ + /* Only one USDHC controller on Ventana */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +/* configure eth0 PHY board-specific LED behavior */ +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* Marvel 88E1510 */ + if (phydev->phy_id == 0x1410dd1) { + /* + * Page 3, Register 16: LED[2:0] Function Control Register + * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link + * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity + */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + val = phy_read(phydev, MDIO_DEVAD_NONE, 16); + val &= 0xff00; + val |= 0x0017; + phy_write(phydev, MDIO_DEVAD_NONE, 16, val); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + cpu_eth_init(bis); +#endif + +#ifdef CONFIG_CI_UDC + /* For otg ethernet*/ + usb_eth_initialize(bis); +#endif + + return 0; +} + +/* read ventana EEPROM, check for validity, and return baseboard type */ +static int +read_eeprom(void) +{ + int i; + int chksum; + char baseboard; + int type; + struct ventana_board_info *info = &ventana_info; + unsigned char *buf = (unsigned char *)&ventana_info; + + memset(info, 0, sizeof(ventana_info)); + + /* + * On a board with a missing/depleted backup battery for GSC, the + * board may be ready to probe the GSC before its firmware is + * running. We will wait here indefinately for the GSC/EEPROM. + */ + while (1) { + if (0 == i2c_set_bus_num(I2C_GSC) && + 0 == i2c_probe(GSC_EEPROM_ADDR)) + break; + mdelay(1); + } + + /* read eeprom config section */ + if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) { + puts("EEPROM: Failed to read EEPROM\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* sanity checks */ + if (info->model[0] != 'G' || info->model[1] != 'W') { + puts("EEPROM: Invalid Model in EEPROM\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + if ((info->chksum[0] != chksum>>8) || + (info->chksum[1] != (chksum&0xff))) { + puts("EEPROM: Failed EEPROM checksum\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* original GW5400-A prototype */ + baseboard = info->model[3]; + if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) + baseboard = '0'; + + switch (baseboard) { + case '0': /* original GW5400-A prototype */ + type = GW54proto; + break; + case '1': + type = GW51xx; + break; + case '2': + type = GW52xx; + break; + case '3': + type = GW53xx; + break; + case '4': + type = GW54xx; + break; + default: + printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); + type = GW_UNKNOWN; + break; + } + return type; +} + +/* + * Baseboard specific GPIO + */ + +/* common to add baseboards */ +static iomux_v3_cfg_t const gw_gpio_pads[] = { + /* MSATA_EN */ + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS232_EN# */ + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* prototype */ +static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS485_EN */ + MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_EN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCICK_SSON */ + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* GPS_SHDN */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_PWR */ + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPS_SHDN */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* USBOTG_SEL */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_PWR */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPS_SHDN */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_EN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* MIPI_DIO */ + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS485_EN */ + MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCICK_SSON */ + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * each baseboard has 4 user configurable Digital IO lines which can + * be pinmuxed as a GPIO or in some cases a PWM + */ +struct dio_cfg { + iomux_v3_cfg_t gpio_padmux; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux; + unsigned pwm_param; +}; + +struct ventana { + /* pinmux */ + iomux_v3_cfg_t const *gpio_pads; + int num_pads; + /* DIO pinmux/val */ + struct dio_cfg dio_cfg[4]; + /* various gpios (0 if non-existent) */ + int leds[3]; + int pcie_rst; + int mezz_pwren; + int mezz_irq; + int rs485en; + int gps_shdn; + int vidin_en; + int dioi2c_en; + int pcie_sson; + int usb_sel; +}; + +struct ventana gpio_cfg[] = { + /* GW5400proto */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), + MX6_PAD_GPIO_9__PWM1_OUT, 1 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), + MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), + MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(4, 7), + .mezz_irq = IMX_GPIO_NR(4, 9), + .rs485en = IMX_GPIO_NR(3, 24), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, + + /* GW51xx */ + { + .gpio_pads = gw51xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18), + MX6_PAD_SD1_CMD__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 2), + .vidin_en = IMX_GPIO_NR(5, 20), + }, + + /* GW52xx */ + { + .gpio_pads = gw52xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .usb_sel = IMX_GPIO_NR(1, 2), + }, + + /* GW53xx */ + { + .gpio_pads = gw53xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + }, + + /* GW54xx */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), + MX6_PAD_GPIO_9__PWM1_OUT, 1 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), + MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), + MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs485en = IMX_GPIO_NR(7, 1), + .vidin_en = IMX_GPIO_NR(3, 31), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, +}; + +/* setup GPIO pinmux and default configuration per baseboard */ +static void setup_board_gpio(int board) +{ + struct ventana_board_info *info = &ventana_info; + const char *s; + char arg[10]; + size_t len; + int i; + int quiet = simple_strtol(getenv("quiet"), NULL, 10); + + if (board >= GW_UNKNOWN) + return; + + /* RS232_EN# */ + gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + + /* MSATA Enable */ + if (is_cpu_type(MXC_CPU_MX6Q) && + test_bit(EECONFIG_SATA, info->config)) { + gpio_direction_output(GP_MSATA_SEL, + (hwconfig("msata")) ? 1 : 0); + } else { + gpio_direction_output(GP_MSATA_SEL, 0); + } + + /* + * assert PCI_RST# (released by OS when clock is valid) + * TODO: figure out why leaving this de-asserted from PCI scan on boot + * causes linux pcie driver to hang during enumeration + */ + gpio_direction_output(gpio_cfg[board].pcie_rst, 0); + + /* turn off (active-high) user LED's */ + for (i = 0; i < 4; i++) { + if (gpio_cfg[board].leds[i]) + gpio_direction_output(gpio_cfg[board].leds[i], 1); + } + + /* Expansion Mezzanine IO */ + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + gpio_direction_input(gpio_cfg[board].mezz_irq); + + /* RS485 Transmit Enable */ + if (gpio_cfg[board].rs485en) + gpio_direction_output(gpio_cfg[board].rs485en, 0); + + /* GPS_SHDN */ + if (gpio_cfg[board].gps_shdn) + gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + + /* Analog video codec power enable */ + if (gpio_cfg[board].vidin_en) + gpio_direction_output(gpio_cfg[board].vidin_en, 1); + + /* DIOI2C_DIS# */ + if (gpio_cfg[board].dioi2c_en) + gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + + /* PCICK_SSON: disable spread-spectrum clock */ + if (gpio_cfg[board].pcie_sson) + gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + + /* USBOTG Select (PCISKT or FrontPanel) */ + if (gpio_cfg[board].usb_sel) + gpio_direction_output(gpio_cfg[board].usb_sel, 0); + + /* + * Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; + unsigned ctrl = DIO_PAD_CTRL; + + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) + ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + if (!quiet) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + } + imx_iomux_v3_setup_pad(cfg->gpio_padmux | + MUX_PAD_CTRL(ctrl)); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + if (!quiet) + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux | + MUX_PAD_CTRL(ctrl)); + } + } + + if (!quiet) { + if (is_cpu_type(MXC_CPU_MX6Q) && + (test_bit(EECONFIG_SATA, info->config))) { + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } +} + +#if defined(CONFIG_CMD_PCI) +int imx6_pcie_toggle_reset(void) +{ + if (board_type < GW_UNKNOWN) { + gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0); + mdelay(50); + gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1); + } + return 0; +} +#endif /* CONFIG_CMD_PCI */ + +#ifdef CONFIG_SERIAL_TAG +/* + * called when setting up ATAGS before booting kernel + * populate serialnum from the following (in order of priority): + * serial# env var + * eeprom + */ +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial) { + serialnr->high = 0; + serialnr->low = simple_strtoul(serial, NULL, 10); + } else if (ventana_info.model[0]) { + serialnr->high = 0; + serialnr->low = ventana_info.serial; + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +/* + * Board Support + */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); + gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + CONFIG_DDR_MB*1024*1024); + + return 0; +} + +int board_init(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUXC_GPR1_OTG_ID_MASK, + IOMUXC_GPR1_OTG_ID_GPIO1); + + /* address of linux boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + /* read Gateworks EEPROM into global struct (used later) */ + board_type = read_eeprom(); + + /* board-specifc GPIO iomux */ + if (board_type < GW_UNKNOWN) { + imx_iomux_v3_setup_multiple_pads(gw_gpio_pads, + ARRAY_SIZE(gw_gpio_pads)); + imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads, + gpio_cfg[board_type].num_pads); + } + + return 0; +} + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +/* + * called during late init (after relocation and after board_init()) + * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and + * EEPROM read. + */ +int checkboard(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char buf[4]; + const char *p; + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + p = getenv("quiet"); + if (p) + quiet = simple_strtol(p, NULL, 10); + else + setenv("quiet", "0"); + + puts("\nGateworks Corporation Copyright 2014\n"); + if (info->model[0]) { + printf("Model: %s\n", info->model); + printf("MFGDate: %02x-%02x-%02x%02x\n", + info->mfgdate[0], info->mfgdate[1], + info->mfgdate[2], info->mfgdate[3]); + printf("Serial:%d\n", info->serial); + } else { + puts("Invalid EEPROM - board will not function fully\n"); + } + if (quiet) + return 0; + + /* Display GSC firmware revision/CRC/status */ + i2c_set_bus_num(I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { + printf("GSC: v%d", buf[0]); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { + printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ + printf(" 0x%02x", buf[0]); /* irq status */ + } + puts("\n"); + } + /* Display RTC */ + if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { + printf("RTC: %d\n", + buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); + } + + return 0; +} +#endif + +#ifdef CONFIG_CMD_BMODE +/* + * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +/* late init */ +int misc_init_r(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char reg; + + /* set env vars based on EEPROM data */ + if (ventana_info.model[0]) { + char str[16], fdt[36]; + char *p; + const char *cputype = ""; + int i; + + /* + * FDT name will be prefixed with CPU type. Three versions + * will be created each increasingly generic and bootloader + * env scripts will try loading each from most specific to + * least. + */ + if (is_cpu_type(MXC_CPU_MX6Q)) + cputype = "imx6q"; + else if (is_cpu_type(MXC_CPU_MX6DL)) + cputype = "imx6dl"; + memset(str, 0, sizeof(str)); + for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) + str[i] = tolower(info->model[i]); + if (!getenv("model")) + setenv("model", str); + if (!getenv("fdt_file")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file", fdt); + } + p = strchr(str, '-'); + if (p) { + *p++ = 0; + + setenv("model_base", str); + if (!getenv("fdt_file1")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); + } + str[4] = 'x'; + str[5] = 'x'; + str[6] = 0; + if (!getenv("fdt_file2")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); + } + } + + /* initialize env from EEPROM */ + if (test_bit(EECONFIG_ETH0, info->config) && + !getenv("ethaddr")) { + eth_setenv_enetaddr("ethaddr", info->mac0); + } + if (test_bit(EECONFIG_ETH1, info->config) && + !getenv("eth1addr")) { + eth_setenv_enetaddr("eth1addr", info->mac1); + } + + /* board serial-number */ + sprintf(str, "%6d", info->serial); + setenv("serial#", str); + } + + /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */ + if ((board_type == GW54xx || board_type == GW54proto) && + !pmic_init(I2C_PMIC)) { + struct pmic *p = pmic_get("PFUZE100_PMIC"); + u32 reg; + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* setup baseboard specific GPIO pinmux and config */ + setup_board_gpio(board_type); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + /* + * The Gateworks System Controller implements a boot + * watchdog (always enabled) as a workaround for IMX6 boot related + * errata such as: + * ERR005768 - no fix + * ERR006282 - fixed in silicon r1.3 + * ERR007117 - fixed in silicon r1.3 + * ERR007220 - fixed in silicon r1.3 + * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf + * + * Disable the boot watchdog and display/clear the timeout flag if set + */ + i2c_set_bus_num(I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { + reg |= (1 << GSC_SC_CTRL1_WDDIS); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + puts("Error: could not disable GSC Watchdog\n"); + } else { + puts("Error: could not disable GSC Watchdog\n"); + } + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { + if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ + puts("GSC boot watchdog timeout detected"); + reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ + gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); + } + } + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) + +/* FDT aliases associated with EEPROM config bits */ +const char *fdt_aliases[] = { + "ethernet0", + "ethernet1", + "hdmi_out", + "ahci0", + "pcie", + "ssi0", + "ssi1", + "lcd0", + "lvds0", + "lvds1", + "usb0", + "usb1", + "mmc0", + "mmc1", + "mmc2", + "mmc3", + "uart0", + "uart1", + "uart2", + "uart3", + "uart4", + "ipu0", + "ipu1", + "can0", + "mipi_dsi", + "mipi_csi", + "tzasc0", + "tzasc1", + "i2c0", + "i2c1", + "i2c2", + "vpu", + "csi0", + "csi1", + "caam", + NULL, + NULL, + NULL, + NULL, + NULL, + "spi0", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + NULL, + NULL, + "pps", + NULL, + NULL, + NULL, + "hdmi_in", + "cvbs_out", + "cvbs_in", + "nand", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +/* + * called prior to booting kernel or by 'fdt boardsetup' command + * + * unless 'fdt_noauto' env var is set we will update the following in the DTB: + * - mtd partitions based on mtdparts/mtdids env + * - system-serial (board serial num from EEPROM) + * - board (full model from EEPROM) + * - peripherals removed from DTB if not loaded on board (per EEPROM config) + */ +void ft_board_setup(void *blob, bd_t *bd) +{ + int bit; + struct ventana_board_info *info = &ventana_info; + struct node_info nodes[] = { + { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + const char *model = getenv("model"); + + if (getenv("fdt_noauto")) { + puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); + return; + } + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + if (!model) { + puts("invalid board info: Leaving FDT fully enabled\n"); + return; + } + printf(" Adjusting FDT per EEPROM for %s...\n", model); + + /* board serial number */ + fdt_setprop(blob, 0, "system-serial", getenv("serial#"), + strlen(getenv("serial#") + 1)); + + /* board (model contains model from device-tree) */ + fdt_setprop(blob, 0, "board", info->model, + strlen((const char *)info->model) + 1); + + /* + * Peripheral Config: + * remove nodes by alias path if EEPROM config tells us the + * peripheral is not loaded on the board. + */ + for (bit = 0; bit < 64; bit++) { + if (!test_bit(bit, info->config)) + fdt_del_node_and_alias(blob, fdt_aliases[bit]); + } +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ + diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg new file mode 100644 index 0000000000..27f09745c1 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.cfg @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd, nand, sata + */ +#ifdef CONFIG_SPI_FLASH +BOOT_FROM spi +#else +BOOT_FROM nand +#endif + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* Memory configuration (size is overridden via eeprom config) */ +#include "../../boundary/nitrogen6x/ddr-setup.cfg" +#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024 + #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024 + #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512 + #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" +#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512 + #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" +#else + #error "Unsupported CPU/Memory configuration" +#endif +#include "clocks.cfg" diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h new file mode 100644 index 0000000000..d310bfd994 --- /dev/null +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _VENTANA_EEPROM_ +#define _VENTANA_EEPROM_ + +struct ventana_board_info { + u8 mac0[6]; /* 0x00: MAC1 */ + u8 mac1[6]; /* 0x06: MAC2 */ + u8 res0[12]; /* 0x0C: reserved */ + u32 serial; /* 0x18: Serial Number (read only) */ + u8 res1[4]; /* 0x1C: reserved */ + u8 mfgdate[4]; /* 0x20: MFG date (read only) */ + u8 res2[7]; /* 0x24 */ + /* sdram config */ + u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ + u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ + u8 sdram_width; /* 0x2D: enum (32,64) bit */ + /* cpu config */ + u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ + u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ + u8 model[16]; /* 0x30: model string */ + /* FLASH config */ + u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ + u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ + + /* Config1: SoC Peripherals */ + u8 config[8]; /* 0x42: loading options */ + + u8 res3[4]; /* 0x4A */ + + u8 chksum[2]; /* 0x4E */ +}; + +/* config bits */ +enum { + EECONFIG_ETH0, + EECONFIG_ETH1, + EECONFIG_HDMI_OUT, + EECONFIG_SATA, + EECONFIG_PCIE, + EECONFIG_SSI0, + EECONFIG_SSI1, + EECONFIG_LCD, + EECONFIG_LVDS0, + EECONFIG_LVDS1, + EECONFIG_USB0, + EECONFIG_USB1, + EECONFIG_SD0, + EECONFIG_SD1, + EECONFIG_SD2, + EECONFIG_SD3, + EECONFIG_UART0, + EECONFIG_UART1, + EECONFIG_UART2, + EECONFIG_UART3, + EECONFIG_UART4, + EECONFIG_IPU0, + EECONFIG_IPU1, + EECONFIG_FLEXCAN, + EECONFIG_MIPI_DSI, + EECONFIG_MIPI_CSI, + EECONFIG_TZASC0, + EECONFIG_TZASC1, + EECONFIG_I2C0, + EECONFIG_I2C1, + EECONFIG_I2C2, + EECONFIG_VPU, + EECONFIG_CSI0, + EECONFIG_CSI1, + EECONFIG_CAAM, + EECONFIG_MEZZ, + EECONFIG_RES1, + EECONFIG_RES2, + EECONFIG_RES3, + EECONFIG_RES4, + EECONFIG_ESPCI0, + EECONFIG_ESPCI1, + EECONFIG_ESPCI2, + EECONFIG_ESPCI3, + EECONFIG_ESPCI4, + EECONFIG_ESPCI5, + EECONFIG_RES5, + EECONFIG_RES6, + EECONFIG_GPS, + EECONFIG_SPIFL0, + EECONFIG_SPIFL1, + EECONFIG_GSPBATT, + EECONFIG_HDMI_IN, + EECONFIG_VID_OUT, + EECONFIG_VID_IN, + EECONFIG_NAND, + EECONFIG_RES8, + EECONFIG_RES9, + EECONFIG_RES10, + EECONFIG_RES11, + EECONFIG_RES12, + EECONFIG_RES13, + EECONFIG_RES14, + EECONFIG_RES15, +}; + +#endif diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h deleted file mode 100644 index 7c95b566f9..0000000000 --- a/board/genietv/genietv.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ diff --git a/board/h2200/Makefile b/board/h2200/Makefile index d4fa15344c..e516e916b4 100644 --- a/board/h2200/Makefile +++ b/board/h2200/Makefile @@ -10,5 +10,5 @@ obj-y := h2200.o extra-y := h2200-header.bin -$(obj)h2200-header.bin: $(obj)h2200-header.o +$(obj)/h2200-header.bin: $(obj)/h2200-header.o $(OBJCOPY) -O binary $< $@ diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/hidden_dragon/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 4b272c780e..a1b67494f6 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #define HB_AHCI_BASE 0xffe08000 @@ -51,17 +51,23 @@ int board_eth_init(bd_t *bis) return rc; } -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) { - char envbuffer[16]; - u32 boot_choice; u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); if (reg & PWRDOM_STAT_SATA) { ahci_init(HB_AHCI_BASE); scsi_scan(1); } +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char envbuffer[16]; + u32 boot_choice; boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; sprintf(envbuffer, "bootcmd%d", boot_choice); diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index 703dbeccfd..17c122cf50 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -325,8 +325,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ - /* SYS_nRESWARM */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ diff --git a/board/hymod/config.mk b/board/hymod/config.mk index abcd2d50ac..2eeea50377 100644 --- a/board/hymod/config.mk +++ b/board/hymod/config.mk @@ -9,6 +9,6 @@ # HYMOD boards # -PLATFORM_CPPFLAGS += -I$(TOPDIR) +PLATFORM_CPPFLAGS += -I$(srctree) -OBJCFLAGS = --remove-section=.ppcenv +OBJCOPYFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h index 3ab3794901..7024d8a807 100644 --- a/board/hymod/hymod.h +++ b/board/hymod/hymod.h @@ -8,7 +8,7 @@ #ifndef _HYMOD_H_ #define _HYMOD_H_ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 #include #endif diff --git a/board/idmr/Makefile b/board/idmr/Makefile deleted file mode 100644 index 67c2384c79..0000000000 --- a/board/idmr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = idmr.o flash.o diff --git a/board/idmr/config.mk b/board/idmr/config.mk deleted file mode 100644 index 840a37e856..0000000000 --- a/board/idmr/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xff800000 diff --git a/board/idmr/flash.c b/board/idmr/flash.c deleted file mode 100644 index 52eb105c32..0000000000 --- a/board/idmr/flash.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE 0x800000 -#define EN29LV640 0x227e227e - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (EN29LV640 & FLASH_TYPEMASK): - printf ("EN29LV640 (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (EN29LV640 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + 0x10000 * j; - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - printf("Waiting 10 ms..."); - udelay (10000); - -/* for (i = 0; i < 10 * 1000 * 1000; ++i) - asm(" nop"); -*/ - - printf("done\n"); - if (iflag) - enable_interrupts (); - - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c deleted file mode 100644 index 73660d802d..0000000000 --- a/board/idmr/idmr.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: iDMR\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - int i; - - /* - * After reset, CS0 is configured to cover entire address space. We - * need to configure it to its proper values, so that writes to - * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do - * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). - */ - - /* Flash chipselect, CS0 */ - /* ;CSAR0: Flash at 0xFF800000 */ - mbar_writeShort(0x0080, 0xFF80); - - /* CSCR0: Flash 6 waits, 16bit */ - mbar_writeShort(0x008A, 0x1980); - - /* CSMR0: Flash 8MB, R/W, valid */ - mbar_writeLong(0x0084, 0x007F0001); - - - /* - * SDRAM configuration proper - */ - - /* - * Address/Data Pin Assignment Reg.: enable address lines 23-21; do - * not enable data pins D[15:0], as we have 16 bit port to SDRAM - */ - mbar_writeByte(MCF_GPIO_PAR_AD, - MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | - MCF_GPIO_AD_ADDR21); - - /* No need to configure BS pins - reset values are OK */ - - /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */ - mbar_writeByte(MCF_GPIO_PAR_CS, 0x00); - - /* SDRAM Control Pin Assignment Reg. */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, - MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */ - MCF_GPIO_SDRAM_SDWE | - MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | - MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_01); - - /* - * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 - * iterations will do, but we do 10 just to be safe. - */ - for (i = 0; i < 10; ++i) - asm(" nop"); - - - /* 1. Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */ - MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */ - - - /* - * 2. Initialize DACR0 - * - * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1) - * CBM: cmd at A20, bank select bits 21 and up - * PS: 16 bit - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | - MCF_SDRAMC_DACRn_BA(0x00) | - MCF_SDRAMC_DACRn_CASL(0x03) | - MCF_SDRAMC_DACRn_CBM(0x03) | - MCF_SDRAMC_DACRn_PS(0x03)); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M | - MCF_SDRAMC_DMRn_V); - - - /* 3. Set IP bit in DACR to initiate PALL command */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_IP); - - /* Write to this block to initiate precharge */ - *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; - - /* - * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We - * wait a wee longer, just to be safe. - */ - for (i = 0; i < 5; ++i) - asm(" nop"); - - - /* 4. Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_RE); - - /* - * Wait for at least 8 auto refresh cycles to occur, i.e. at least - * 781 bus cycles. - */ - for (i = 0; i < 1000; ++i) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_MRS); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 3 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds deleted file mode 100644 index 4071f70d45..0000000000 --- a/board/idmr/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h deleted file mode 100644 index f16f450d01..0000000000 --- a/board/inka4x0/hyb25d512160bf-5.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/ip04/config.mk b/board/ip04/config.mk index ae2ea0b747..ab0fbecab9 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 089a835e0c..9f8fcf2c1c 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -116,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 7a7500b342..3b2b1f15b8 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index cbfc7d2175..51a3cfe647 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -189,6 +189,31 @@ int wait_for_fpga_config(void) return 0; } +#if defined(KM_PCIE_RESET_MPP7) + +#define KM_PEX_RST_GPIO_PIN 7 +int fpga_reset(void) +{ + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe reset through GPIO7: "); + /* apply PCIe reset via GPIO */ + kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); + udelay(1000*10); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); + + printf(" done\n"); + + return 0; +} + +#else + #define PRST1 0x4 #define PCIE_RST 0x10 #define TRAFFIC_RST 0x04 @@ -219,6 +244,7 @@ int fpga_reset(void) return 0; } +#endif /* the FPGA was configured, we configure the BOCO2 so that the EEPROM * is available from the Bobcat SPI bus */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5620737bf0..35402c800b 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, +#if defined(KM_PCIE_RESET_MPP7) + MPP7_GPO, +#else MPP7_PEX_RST_OUTn, +#endif #if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ @@ -102,7 +106,7 @@ static const u32 kwmpp_config[] = { /* * Wait for startup OK from mgcoge3ne */ -int startup_allowed(void) +static int startup_allowed(void) { unsigned char buf; @@ -164,7 +168,6 @@ static int initialize_unit_leds(void) return 0; } -#if defined(CONFIG_BOOTCOUNT_LIMIT) static void set_bootcount_addr(void) { uchar buf[32]; @@ -173,7 +176,6 @@ static void set_bootcount_addr(void) sprintf((char *)buf, "0x%x", bootcountaddr); setenv("bootcountaddr", (char *)buf); } -#endif int misc_init_r(void) { @@ -210,9 +212,7 @@ int misc_init_r(void) initialize_unit_leds(); set_km_env(); -#if defined(CONFIG_BOOTCOUNT_LIMIT) set_bootcount_addr(); -#endif return 0; } @@ -322,15 +322,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) + if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile index 3e69ee2f15..c57ca08e14 100644 --- a/board/keymile/kmp204x/Makefile +++ b/board/keymile/kmp204x/Makefile @@ -8,5 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \ +obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \ ../common/common.o ../common/ivm.o diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index f02642aece..95a19cdb2c 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -33,12 +33,51 @@ int checkboard(void) return 0; } -/* TODO: implement the I2C deblocking function */ -int i2c_make_abort(void) +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines + * For I2C only the low state is activly driven and high state is pulled-up + * by a resistor. Therefore the deblock GPIOs are used + * -> as an active output to drive a low state + * -> as an open-drain input to have a pulled-up high state + */ + +/* QRIO GPIOs used for deblocking */ +#define DEBLOCK_PORT1 GPIO_A +#define DEBLOCK_SCL1 20 +#define DEBLOCK_SDA1 21 + +/* By default deblock GPIOs are floating */ +static void i2c_deblock_gpio_cfg(void) { - return 1; + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); + + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); } +void set_sda(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); +} + +int get_scl(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); +} + + #define ZL30158_RST 8 #define ZL30343_RST 9 @@ -62,6 +101,7 @@ int board_early_init_f(void) int board_early_init_r(void) { + int ret = 0; /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); @@ -69,7 +109,11 @@ int board_early_init_r(void) set_liodns(); setup_portals(); - return 0; + ret = trigger_fpga_config(); + if (ret) + printf("error triggering PCIe FPGA config\n"); + + return ret; } unsigned long get_board_sys_clk(unsigned long dummy) @@ -77,80 +121,12 @@ unsigned long get_board_sys_clk(unsigned long dummy) return 66666666; } -#define WDMASK_OFF 0x16 - -static void qrio_wdmask(u8 bit, bool wden) +int misc_init_f(void) { - u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); - wdmask = in_be16(qrio_base + WDMASK_OFF); - - if (wden) - wdmask |= (1 << bit); - else - wdmask &= ~(1 << bit); - - out_be16(qrio_base + WDMASK_OFF, wdmask); -} - -#define PRST_OFF 0x1a - -void qrio_prst(u8 bit, bool en, bool wden) -{ - u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - qrio_wdmask(bit, wden); - - prst = in_be16(qrio_base + PRST_OFF); - - if (en) - prst &= ~(1 << bit); - else - prst |= (1 << bit); - - out_be16(qrio_base + PRST_OFF, prst); -} - -#define PRSTCFG_OFF 0x1c - -void qrio_prstcfg(u8 bit, u8 mode) -{ - u32 prstcfg; - u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - prstcfg = in_be32(qrio_base + PRSTCFG_OFF); - - for (i = 0; i < 2; i++) { - if (mode & (1< #include #include +#include #include "kmp204x.h" +#define PROM_SEL_L 11 +/* control the PROM_SEL_L signal*/ +static void toggle_fpga_eeprom_bus(bool cpu_own) +{ + qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); +} + +#define CONF_SEL_L 10 +#define FPGA_PROG_L 19 +#define FPGA_DONE 18 +#define FPGA_INIT_L 17 + +int trigger_fpga_config(void) +{ + int ret = 0, init_l; + /* approx 10ms */ + u32 timeout = 10000; + + /* make sure the FPGA_can access the EEPROM */ + toggle_fpga_eeprom_bus(false); + + /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ + qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); + + /* trigger the config start */ + qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); + + /* small delay for INIT_L line */ + udelay(10); + + /* wait for FPGA_INIT to be asserted */ + do { + init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); + if (timeout-- == 0) { + printf("FPGA_INIT timeout\n"); + ret = -EFAULT; + break; + } + udelay(10); + } while (init_l); + + /* deassert FPGA_PROG, config should start */ + qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); + + return ret; +} + +/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ +static int wait_for_fpga_config(void) +{ + int ret = 0, done; + /* approx 5 s */ + u32 timeout = 500000; + + printf("PCIe FPGA config:"); + do { + done = qrio_get_gpio(GPIO_A, FPGA_DONE); + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + ret = -EFAULT; + goto err_out; + } + udelay(10); + } while (!done); + + printf(" done\n"); + +err_out: + /* deactive CONF_SEL and give the CPU conf EEPROM access */ + qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); + toggle_fpga_eeprom_bus(true); + + return ret; +} + #define PCIE_SW_RST 14 +#define PEXHC_SW_RST 13 #define HOOPER_SW_RST 12 void pci_init_board(void) { + /* first wait for the PCIe FPGA to be configured + * it has been triggered earlier in board_early_init_r */ + int ret = wait_for_fpga_config(); + if (ret) + printf("error finishing PCIe FPGA config\n"); + qrio_prst(PCIE_SW_RST, false, false); + qrio_prst(PEXHC_SW_RST, false, false); qrio_prst(HOOPER_SW_RST, false, false); /* Hooper is not direcly PCIe capable */ mdelay(50); + fsl_pcie_init_board(0); } diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c new file mode 100644 index 0000000000..49f9aa2546 --- /dev/null +++ b/board/keymile/kmp204x/qrio.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../common/common.h" +#include "kmp204x.h" + +/* QRIO GPIO register offsets */ +#define DIRECT_OFF 0x18 +#define GPRT_OFF 0x1c + +int qrio_get_gpio(u8 port_off, u8 gpio_nr) +{ + u32 gprt; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + + return (gprt >> gpio_nr) & 1U; +} + +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) +{ + u32 gprt, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + if (value) + gprt |= mask; + else + gprt &= ~mask; + + out_be32(qrio_base + port_off + GPRT_OFF, gprt); +} + +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct |= mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); + + qrio_set_gpio(port_off, gpio_nr, value); +} + +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct &= ~mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + if (val == 0) + /* set to output -> GPIO drives low */ + direct |= mask; + else + /* set to input -> GPIO floating */ + direct &= ~mask; + + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +#define WDMASK_OFF 0x16 + +static void qrio_wdmask(u8 bit, bool wden) +{ + u16 wdmask; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + wdmask = in_be16(qrio_base + WDMASK_OFF); + + if (wden) + wdmask |= (1 << bit); + else + wdmask &= ~(1 << bit); + + out_be16(qrio_base + WDMASK_OFF, wdmask); +} + +#define PRST_OFF 0x1a + +void qrio_prst(u8 bit, bool en, bool wden) +{ + u16 prst; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + qrio_wdmask(bit, wden); + + prst = in_be16(qrio_base + PRST_OFF); + + if (en) + prst &= ~(1 << bit); + else + prst |= (1 << bit); + + out_be16(qrio_base + PRST_OFF, prst); +} + +#define PRSTCFG_OFF 0x1c + +void qrio_prstcfg(u8 bit, u8 mode) +{ + u32 prstcfg; + u8 i; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + prstcfg = in_be32(qrio_base + PRSTCFG_OFF); + + for (i = 0; i < 2; i++) { + if (mode & (1</dev/null) + +MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script + +$(obj)/bootscript.img: $(src)/bootscript + $(call cmd,mkimage) diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile index c6c0933956..c056ebaf78 100644 --- a/board/matrix_vision/mvblx/Makefile +++ b/board/matrix_vision/mvblx/Makefile @@ -8,4 +8,4 @@ obj-y += mvblx.o fpga.o obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o -CFLAGS += -Werror +ccflags-y += -Werror diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore new file mode 100644 index 0000000000..469f1bc4c1 --- /dev/null +++ b/board/matrix_vision/mvsmr/.gitignore @@ -0,0 +1 @@ +bootscript.img diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index b6a4f6754b..a9c794e21a 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -12,5 +12,11 @@ obj-y := mvsmr.o fpga.o extra-y := bootscript.img -$(obj)bootscript.img: bootscript - @mkimage -T script -C none -n mvSMR_Script -d $< $@ +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script + +$(obj)/bootscript.img: $(src)/bootscript + $(call cmd,mkimage) diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk index 0f004e0ee0..354d918474 100644 --- a/board/micronas/vct/config.mk +++ b/board/micronas/vct/config.mk @@ -8,8 +8,6 @@ # vct_xxx boards with MIPS 4Kc CPU core # -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE = 0x87000000 endif diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 6bbb527dab..5590be1962 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -640,118 +640,9 @@ static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} static void usb_display_Req(unsigned short req) {} #endif -static unsigned char root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - - -static unsigned char root_hub_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - +#define WANT_USB_ROOT_HUB_HUB_DES +#include +#undef WANT_USB_ROOT_HUB_HUB_DES /* * Root Hub Control Pipe (interrupt Pipes are not supported) diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 642f17c35b..2ea2e29c3b 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 95fed34fcc..292393ec43 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index b889cf94af..cca9c0c880 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -197,13 +197,10 @@ #define REFCNT_266 0 /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* use r0 to relocate DATA read/write to flash rather than memory ! */ - ldr r0, _TEXT_BASE + ldr r0, =CONFIG_SYS_TEXT_BASE ldr r13, =BWSCON /* enable minimal access to PLD */ diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index 4a230dd596..0d2f0a54c5 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -22,8 +22,6 @@ struct emu_hal_params_rx51 { u32 param4; }; -int print_cpuinfo(void); - /* * IEN - Input Enable * IDIS - Input Disable diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index e3fcf2bdff..e3b2651570 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -1,4 +1,4 @@ # Copyright (c) 2011 The Chromium OS Authors. # SPDX-License-Identifier: GPL-2.0+ -include common.mk +include $(src)/common.mk diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 1972527e7d..3b18e28cc4 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -48,17 +48,6 @@ const struct tegra_sysinfo sysinfo = { CONFIG_TEGRA_BOARD_STRING }; -#ifndef CONFIG_SPL_BUILD -/* - * Routine: timer_init - * Description: init the timestamp and lastinc value - */ -int timer_init(void) -{ - return 0; -} -#endif - void __pin_mux_usb(void) { } @@ -78,12 +67,14 @@ void __gpio_early_init_uart(void) void gpio_early_init_uart(void) __attribute__((weak, alias("__gpio_early_init_uart"))); +#if defined(CONFIG_TEGRA_NAND) void __pin_mux_nand(void) { funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); } void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); +#endif void __pin_mux_display(void) { diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 8c05a1517c..9dcd5e42af 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -132,8 +132,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* VI pinmux */ VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), @@ -145,8 +145,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux */ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), @@ -224,8 +224,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* SYSCLK pinmux */ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), @@ -252,8 +252,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB pinmux */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile new file mode 100644 index 0000000000..5fac5ab1f8 --- /dev/null +++ b/board/nvidia/venice2/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += as3722_init.o +obj-y += venice2.o diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c new file mode 100644 index 0000000000..960fea7ee7 --- /dev/null +++ b/board/nvidia/venice2/as3722_init.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "as3722_init.h" + +/* AS3722-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + debug("%s entry\n", __func__); + + /* Don't need to set up VDD_CORE - already done - by OTP */ + + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); + /* + * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); + /* + * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); + /* + * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.2V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +} diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h new file mode 100644 index 0000000000..2a9e7cdf87 --- /dev/null +++ b/board/nvidia/venice2/as3722_init.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* AS3722-PMIC-specific early init regs */ + +#define AS3722_I2C_ADDR 0x80 + +#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ +#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ +#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ +#define AS3722_SDCONTROL_REG 0x4D + +#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ +#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ +#define AS3722_LDCONTROL_REG 0x4E + +#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) +#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) + +#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) + +#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) +#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) + +#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) +#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) + +#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) +#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h new file mode 100644 index 0000000000..b3d68d589a --- /dev/null +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_VENICE2_H_ +#define _PINMUX_CONFIG_VENICE2_H_ + +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define USB_PINMUX CEC_PINMUX + +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + +static struct pingroup_config tegra124_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), + + /* EC KBC/SPI */ + DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), + + /* I2C3 (TPM) pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTD pinmux (UART4 on Servo board, unused) */ + DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 (Winbond 'boot ROM') */ + DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT), + + /* Touch IRQ */ + DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + + /* Misc */ + DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */ + DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTB, GPS */ + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UARTC (WIFI/BT) */ + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* I2C4 (HDMI_DDC) pinmux */ + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* Unused, marked SNN_ on schematic, TRISTATE 'em */ + DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pingroup_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT), +}; + +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pingroup_config tegra124_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT), + + /* EN_VDD_BL */ + DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT), + + /* MODEM */ + DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + + /* BOOT_SEL0-3 */ + DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), + + /* TS_SHDN_L */ + DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT), +}; + +static struct padctrl_config venice2_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; +#endif /* PINMUX_CONFIG_VENICE2_H */ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c new file mode 100644 index 0000000000..1ed2fd788e --- /dev/null +++ b/board/nvidia/venice2/venice2.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pinmux-config-venice2.h" +#include + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_table(tegra124_pinmux_set_nontristate, + ARRAY_SIZE(tegra124_pinmux_set_nontristate)); + + pinmux_config_table(tegra124_pinmux_common, + ARRAY_SIZE(tegra124_pinmux_common)); + + pinmux_config_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl)); +} diff --git a/board/overo/overo.c b/board/overo/overo.c index 9ac35d2f4e..1192d02e91 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "overo.h" diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 1e761284e4..b90d5d0ec1 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -10,7 +10,7 @@ # # Check the U-Boot Image with a SHA1 checksum -ALL-y += $(obj)u-boot.sha1 +ALL-y += u-boot.sha1 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 7e5e07ff23..1071662ea9 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -176,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RGMII, }, }; diff --git a/board/pr1/config.mk b/board/pr1/config.mk deleted file mode 100644 index 5c18d5c9e4..0000000000 --- a/board/pr1/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/prodrive/p3mx/ppc_error_no.h b/board/prodrive/p3mx/ppc_error_no.h deleted file mode 100644 index 58a68b5d89..0000000000 --- a/board/prodrive/p3mx/ppc_error_no.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus - */ -#ifndef _MV_PPC_ERRNO_H -#define _MV_PPC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ -#define EDEADLOCK 58 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -/* Should never be seen by user programs */ -#define ERESTARTSYS 512 -#define ERESTARTNOINTR 513 -#define ERESTARTNOHAND 514 /* restart if no handler.. */ -#define ENOIOCTLCMD 515 /* No ioctl command */ - -#define _LAST_ERRNO 515 - -#endif diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c index 89040a899e..5b7b989860 100644 --- a/board/prodrive/p3mx/serial.c +++ b/board/prodrive/p3mx/serial.c @@ -23,7 +23,6 @@ #include #include "../../Marvell/include/memory.h" -#include "serial.h" #include "mpsc.h" diff --git a/board/prodrive/p3mx/serial.h b/board/prodrive/p3mx/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/prodrive/p3mx/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index fb4acf3641..2804d9133d 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -76,7 +76,7 @@ int board_init(void) { /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x66, PGCR); + outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); outw((inw(HIZCRA) & ~0x02), HIZCRA); debug_led(1 << 0); @@ -97,7 +97,7 @@ int board_init(void) /* USB host */ outw((inw(PBCR) & ~0x300) | 0x100, PBCR); outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & 0x100000, MSTPCR2); + outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); outw(0x0600, UPONCR0); debug_led(1 << 3); diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S index eeebdd245f..e4c40c8616 100644 --- a/board/renesas/ecovec/lowlevel_init.S +++ b/board/renesas/ecovec/lowlevel_init.S @@ -20,7 +20,7 @@ lowlevel_init: - /* jump to 0xA0020000 if bit 1 of PVDR_A */ + /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ mov.l PVDR_A, r1 mov.l PVDR_D, r2 mov.b @r1, r0 diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index a63438343e..ec3ac89593 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 3cedeef8ae..3aaffa803c 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index c9f2747007..15aa4acd11 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 22bd6b197e..7d2bb8c4a2 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o +obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_BOARD_COMMON) += board.o diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index cd873bc56d..de154e0f64 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -22,16 +22,24 @@ #include #include #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; +int __exynos_early_init_f(void) +{ + return 0; +} +int exynos_early_init_f(void) + __attribute__((weak, alias("__exynos_early_init_f"))); -static struct local_info local; +int __exynos_power_init(void) +{ + return 0; +} +int exynos_power_init(void) + __attribute__((weak, alias("__exynos_power_init"))); #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ @@ -140,155 +148,21 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif - return err; -} -#endif - -struct cros_ec_dev *board_get_cros_ec_dev(void) -{ - return local.cros_ec_dev; -} - -#ifdef CONFIG_CROS_EC -static int board_init_cros_ec_devices(const void *blob) -{ - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ - - return 0; + return exynos_early_init_f(); } #endif #if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - int power_init_board(void) { - int ret = 0; - set_ps_hold_ctrl(); -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); -#endif - - return ret; + return exynos_power_init(); } #endif #ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_SMC911X static int decode_sromc(const void *blob, struct fdt_sromc *config) { int err; @@ -312,6 +186,7 @@ static int decode_sromc(const void *blob, struct fdt_sromc *config) } return 0; } +#endif int board_eth_init(bd_t *bis) { @@ -369,27 +244,47 @@ int board_mmc_init(bd_t *bis) { int ret; +#ifdef CONFIG_SDHCI + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); + if (ret) + debug("mmc init failed\n"); +#endif +#ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); if (ret) debug("dwmmc init failed\n"); +#endif return ret; } #endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Board: %s\n", board_name ? board_name : "unknown"); + + return 0; +} #endif +#endif /* CONFIG_OF_CONTROL */ #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { stdio_print_current_devices(); - if (local.cros_ec_err) { + if (cros_ec_get_error()) { /* Force console on */ gd->flags &= ~GD_FLG_SILENT; printf("cros-ec communications failure %d\n", - local.cros_ec_err); + cros_ec_get_error()); puts("\nPlease reset with Power+Refresh\n\n"); panic("Cannot init cros-ec device"); return -1; @@ -401,7 +296,7 @@ int board_late_init(void) int arch_early_init_r(void) { #ifdef CONFIG_CROS_EC - if (board_init_cros_ec_devices(gd->fdt_blob)) { + if (cros_ec_board_init()) { printf("%s: Failed to init EC\n", __func__); return 0; } @@ -409,3 +304,21 @@ int arch_early_init_r(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt new file mode 100644 index 0000000000..d6ee8a228a --- /dev/null +++ b/board/samsung/common/dfu_sample_env.txt @@ -0,0 +1,9 @@ +mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0 +rootfstype=ext4 +loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage +mmcdev=0 +mmcbootpart=2 +mmcrootpart=5 +console=console=ttySAC2,115200n8 +bootcmd=run mmcboot +dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2 diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 8e3b73ecf7..b22f9e07bb 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -42,7 +42,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram .bss : { diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c new file mode 100644 index 0000000000..3ff4289780 --- /dev/null +++ b/board/samsung/common/misc.c @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void) +{ + char info[64]; + + snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f, + (s5p_cpu_rev & 0xf0) >> 0x04); + setenv("soc_rev", info); + + snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id); + setenv("soc_id", info); + +#ifdef CONFIG_REVISION_TAG + snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev()); + setenv("board_rev", info); +#endif +#ifdef CONFIG_OF_LIBFDT + snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb", + CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD); + setenv("fdtfile", info); +#endif +} +#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ + +#ifdef CONFIG_LCD_MENU +static int power_key_pressed(u32 reg) +{ + struct pmic *pmic; + u32 status; + u32 mask; + + pmic = pmic_get(KEY_PWR_PMIC_NAME); + if (!pmic) { + printf("%s: Not found\n", KEY_PWR_PMIC_NAME); + return 0; + } + + if (pmic_probe(pmic)) + return 0; + + if (reg == KEY_PWR_STATUS_REG) + mask = KEY_PWR_STATUS_MASK; + else + mask = KEY_PWR_INTERRUPT_MASK; + + if (pmic_reg_read(pmic, reg, &status)) + return 0; + + return !!(status & mask); +} + +static int key_pressed(int key) +{ + int value; + + switch (key) { + case KEY_POWER: + value = power_key_pressed(KEY_PWR_INTERRUPT_REG); + break; + case KEY_VOLUMEUP: + value = !gpio_get_value(KEY_VOL_UP_GPIO); + break; + case KEY_VOLUMEDOWN: + value = !gpio_get_value(KEY_VOL_DOWN_GPIO); + break; + default: + value = 0; + break; + } + + return value; +} + +static int check_keys(void) +{ + int keys = 0; + + if (key_pressed(KEY_POWER)) + keys += KEY_POWER; + if (key_pressed(KEY_VOLUMEUP)) + keys += KEY_VOLUMEUP; + if (key_pressed(KEY_VOLUMEDOWN)) + keys += KEY_VOLUMEDOWN; + + return keys; +} + +/* + * 0 BOOT_MODE_INFO + * 1 BOOT_MODE_THOR + * 2 BOOT_MODE_UMS + * 3 BOOT_MODE_DFU + * 4 BOOT_MODE_EXIT + */ +static char * +mode_name[BOOT_MODE_EXIT + 1] = { + "DEVICE", + "THOR", + "UMS", + "DFU", + "EXIT" +}; + +static char * +mode_info[BOOT_MODE_EXIT + 1] = { + "info", + "downloader", + "mass storage", + "firmware update", + "and run normal boot" +}; + +#define MODE_CMD_ARGC 4 + +static char * +mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = { + {"", "", "", ""}, + {"thor", "0", "mmc", "0"}, + {"ums", "0", "mmc", "0"}, + {"dfu", "0", "mmc", "0"}, + {"", "", "", ""}, +}; + +static void display_board_info(void) +{ +#ifdef CONFIG_GENERIC_MMC + struct mmc *mmc = find_mmc_device(0); +#endif + vidinfo_t *vid = &panel_info; + + lcd_position_cursor(4, 4); + + lcd_printf("%s\n\t", U_BOOT_VERSION); + lcd_puts("\n\t\tBoard Info:\n"); +#ifdef CONFIG_SYS_BOARD + lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD); +#endif +#ifdef CONFIG_REVISION_TAG + lcd_printf("\tBoard rev: %u\n", get_board_rev()); +#endif + lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS); + lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M); + +#ifdef CONFIG_GENERIC_MMC + if (mmc) { + if (!mmc->capacity) + mmc_init(mmc); + + lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M); + } +#endif + if (vid) + lcd_printf("\tDisplay resolution: %u x % u\n", + vid->vl_col, vid->vl_row); + + lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix); +} + +static int mode_leave_menu(int mode) +{ + char *exit_option; + char *exit_boot = "boot"; + char *exit_back = "back"; + cmd_tbl_t *cmd; + int cmd_result; + int cmd_repeatable; + int leave; + + lcd_clear(); + + switch (mode) { + case BOOT_MODE_EXIT: + return 1; + case BOOT_MODE_INFO: + display_board_info(); + exit_option = exit_back; + leave = 0; + break; + default: + cmd = find_cmd(mode_cmd[mode][0]); + if (cmd) { + printf("Enter: %s %s\n", mode_name[mode], + mode_info[mode]); + lcd_printf("\n\n\t%s %s\n", mode_name[mode], + mode_info[mode]); + lcd_puts("\n\tDo not turn off device before finish!\n"); + + cmd_result = cmd_process(0, MODE_CMD_ARGC, + *(mode_cmd + mode), + &cmd_repeatable, NULL); + + if (cmd_result == CMD_RET_SUCCESS) { + printf("Command finished\n"); + lcd_clear(); + lcd_printf("\n\n\t%s finished\n", + mode_name[mode]); + + exit_option = exit_boot; + leave = 1; + } else { + printf("Command error\n"); + lcd_clear(); + lcd_printf("\n\n\t%s command error\n", + mode_name[mode]); + + exit_option = exit_back; + leave = 0; + } + } else { + lcd_puts("\n\n\tThis mode is not supported.\n"); + exit_option = exit_back; + leave = 0; + } + } + + lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option); + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + /* Wait for PWR key */ + while (!key_pressed(KEY_POWER)) + mdelay(1); + + lcd_clear(); + return leave; +} + +static void display_download_menu(int mode) +{ + char *selection[BOOT_MODE_EXIT + 1]; + int i; + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + selection[i] = "[ ]"; + + selection[mode] = "[=>]"; + + lcd_clear(); + lcd_printf("\n\t\tDownload Mode Menu\n"); + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + lcd_printf("\t%s %s - %s\n\n", selection[i], + mode_name[i], + mode_info[i]); +} + +static void download_menu(void) +{ + int mode = 0; + int last_mode = 0; + int run; + int key; + + display_download_menu(mode); + + while (1) { + run = 0; + + if (mode != last_mode) + display_download_menu(mode); + + last_mode = mode; + mdelay(100); + + key = check_keys(); + switch (key) { + case KEY_POWER: + run = 1; + break; + case KEY_VOLUMEUP: + if (mode > 0) + mode--; + break; + case KEY_VOLUMEDOWN: + if (mode < BOOT_MODE_EXIT) + mode++; + break; + default: + break; + } + + if (run) { + if (mode_leave_menu(mode)) + break; + + display_download_menu(mode); + } + } + + lcd_clear(); +} + +static void display_mode_info(void) +{ + lcd_position_cursor(4, 4); + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_puts("\nDownload Mode Menu\n"); +#ifdef CONFIG_SYS_BOARD + lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD); +#endif + lcd_printf("Press POWER KEY to display MENU options."); +} + +static int boot_menu(void) +{ + int key = 0; + int timeout = 10; + + display_mode_info(); + + while (timeout--) { + lcd_printf("\rNormal boot will start in: %d seconds.", timeout); + mdelay(1000); + + key = key_pressed(KEY_POWER); + if (key) + break; + } + + lcd_clear(); + + /* If PWR pressed - show download menu */ + if (key) { + printf("Power pressed - go to download menu\n"); + download_menu(); + printf("Download mode exit.\n"); + } + + return 0; +} + +void check_boot_mode(void) +{ + int pwr_key; + + pwr_key = power_key_pressed(KEY_PWR_STATUS_REG); + if (!pwr_key) + return; + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + if (key_pressed(KEY_VOLUMEUP)) + boot_menu(); + else if (key_pressed(KEY_VOLUMEDOWN)) + mode_leave_menu(BOOT_MODE_THOR); +} + +void keys_init(void) +{ + /* Set direction to input */ + gpio_direction_input(KEY_VOL_UP_GPIO); + gpio_direction_input(KEY_VOL_DOWN_GPIO); +} +#endif /* CONFIG_LCD_MENU */ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void) +{ + int x, y; + ulong addr; + + addr = panel_info.logo_addr; + if (!addr) { + error("There is no logo data."); + return; + } + + if (panel_info.vl_width >= panel_info.logo_width) { + x = ((panel_info.vl_width - panel_info.logo_width) >> 1); + x += panel_info.logo_x_offset; /* For X center align */ + } else { + x = 0; + printf("Warning: image width is bigger than display width\n"); + } + + if (panel_info.vl_height >= panel_info.logo_height) { + y = ((panel_info.vl_height - panel_info.logo_height) >> 1); + y += panel_info.logo_y_offset; /* For Y center align */ + } else { + y = 0; + printf("Warning: image height is bigger than display height\n"); + } + + bmp_display(addr, x, y); +} +#endif /* CONFIG_CMD_BMP */ diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 366f648d32..61b9ece038 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -13,10 +13,17 @@ #include #include #include +#include + DECLARE_GLOBAL_DATA_PTR; static struct s5pc110_gpio *s5pc110_gpio; +u32 get_board_rev(void) +{ + return 0; +} + int board_init(void) { /* Set Initial global variables */ @@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = { .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, }; #endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif + return 0; +} +#endif diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 726211a336..d52bc09f8d 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -22,9 +22,6 @@ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r11, lr diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index e8818bf9b1..1add9fe626 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -4,16 +4,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o + +hostprogs-y := tools/mkorigenspl +always := $(hostprogs-y) + +# omit -O2 option to suppress +# warning: dereferencing type-punned pointer will break strict-aliasing rules +# +# TODO: +# Fix the root cause in tools/mkorigenspl.c and delete the following work-around +$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS)) +else obj-y += origen.o endif - -ifdef CONFIG_SPL_BUILD -all: $(OBJTREE)/tools/mk$(BOARD)spl -endif - -# Fix ME after we implement hostprogs-y. -ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl -endif diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 15f77cacbd..d502f02d3d 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -11,129 +11,35 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; -int board_init(void) +u32 get_board_rev(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } -static int board_uart_init(void) +int exynos_init(void) { - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - return 0; } +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} + +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) +{ + return 0; +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) +int exynos_early_init_f(void) { - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ - PHYS_SDRAM_4_SIZE); -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: ORIGEN\n"); return 0; } #endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); - } - - err = s5p_mmc_init(2, 4); - return err; -} -#endif diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkorigenspl.c similarity index 100% rename from board/samsung/origen/tools/mkv310_image.c rename to board/samsung/origen/tools/mkorigenspl.c diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S index c7b78fd103..5de04f10e9 100644 --- a/board/samsung/smdk2410/lowlevel_init.S +++ b/board/samsung/smdk2410/lowlevel_init.S @@ -110,16 +110,13 @@ #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* memory control configuration */ /* make r0 relative the current location so that it */ /* reads SMRDATA out of FLASH rather than memory ! */ ldr r0, =SMRDATA - ldr r1, _TEXT_BASE + ldr r1, =CONFIG_SYS_TEXT_BASE sub r0, r0, r1 ldr r1, =BWSCON /* Bus Width Status Controller */ add r2, r0, #13*4 diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 5fb8664936..379a45cc23 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -45,21 +44,6 @@ int exynos_init(void) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S deleted file mode 100644 index 9003e2d007..0000000000 --- a/board/samsung/smdk5250/lowlevel_init.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Lowlevel setup for SMDK5250 board based on S5PC520 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - - .globl lowlevel_init -lowlevel_init: - - /* use iRAM stack in bl2 */ - ldr sp, =CONFIG_IRAM_STACK - stmdb r13!, {ip,lr} - - /* check reset status */ - ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET) - ldr r1, [r0] - - /* AFTR wakeup reset */ - ldr r2, =S5P_CHECK_DIDLE - cmp r1, r2 - beq exit_wakeup - - /* LPA wakeup reset */ - ldr r2, =S5P_CHECK_LPA - cmp r1, r2 - beq exit_wakeup - - /* Sleep wakeup reset */ - ldr r2, =S5P_CHECK_SLEEP - cmp r1, r2 - beq wakeup_reset - - /* - * If U-boot is already running in RAM, no need to relocate U-Boot. - * Memory controller must be configured before relocating U-Boot - * in ram. - */ - ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ - bic r1, pc, r0 /* pc <- current addr of code */ - /* r1 <- unmasked bits of pc */ - ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ - bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ - cmp r1, r2 /* compare r1, r2 */ - beq 1f /* r0 == r1 then skip sdram init */ - - /* init system clock */ - bl system_clock_init - - /* Memory initialize */ - bl mem_ctrl_init - -1: - bl arch_cpu_init - bl tzpc_init - ldmia r13!, {ip,pc} - -wakeup_reset: - bl system_clock_init - bl mem_ctrl_init - bl arch_cpu_init - bl tzpc_init - -exit_wakeup: - /* Load return address and jump to kernel */ - ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET) - - /* r1 = physical address of exynos5_cpu_resume function*/ - ldr r1, [r0] - - /* Jump to kernel */ - mov pc, r1 - nop - nop diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 943c29a698..28a6d9e718 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,22 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_USB_EHCI_EXYNOS -static int board_usb_vbus_init(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); - - /* VBUS turn ON time */ - mdelay(3); - - return 0; -} -#endif - #ifdef CONFIG_SOUND_MAX98095 static void board_enable_audio_codec(void) { @@ -56,9 +40,6 @@ static void board_enable_audio_codec(void) int exynos_init(void) { -#ifdef CONFIG_USB_EHCI_EXYNOS - board_usb_vbus_init(); -#endif #ifdef CONFIG_SOUND_MAX98095 board_enable_audio_codec(); #endif @@ -166,6 +147,131 @@ void board_i2c_init(const void *blob) } } +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif /* CONFIG_POWER_MAX77686 */ + +int exynos_power_init(void) +{ + int ret = 0; + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); +#endif + return ret; +} +#endif /* CONFIG_POWER */ + #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 3ad2ad0e56..e4606ecd2a 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -142,18 +142,3 @@ int board_get_revision(void) { return 0; } - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 4df0974af5..65e6b7a73a 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -17,9 +17,6 @@ * r5 has zero always */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r9, lr diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index dbc621bd61..de0da167be 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -4,16 +4,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o + +hostprogs-y := tools/mksmdkv310spl +always := $(hostprogs-y) +else obj-y += smdkv310.o endif - -ifdef CONFIG_SPL_BUILD -all: $(OBJTREE)/tools/mk$(BOARD)spl -endif - -# Fix ME after we implement hostprogs-y. -ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl -endif diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mksmdkv310spl.c similarity index 100% rename from board/samsung/smdkv310/tools/mkv310_image.c rename to board/samsung/smdkv310/tools/mksmdkv310spl.c diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 640a193dc2..7c79e7b73a 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -12,20 +12,18 @@ #include #include #include -#include #include #include -#include #include #include #include #include #include #include -#include #include #include #include +#include #include #include @@ -45,10 +43,8 @@ u32 get_board_rev(void) static void check_hw_revision(void); struct s3c_plat_otg_data s5pc210_otg_data; -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; - check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); @@ -280,7 +276,7 @@ static int pmic_init_max8997(void) return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg, ret; struct power_battery *pb; @@ -349,28 +345,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - static unsigned int get_hw_revision(void) { struct exynos4_gpio_part1 *gpio = @@ -403,55 +377,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int err; - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio->k0, 2, 1); - s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; -} -#endif #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) @@ -598,38 +523,22 @@ static void board_power_init(void) writel(0, (unsigned int)&pwr->arm_core1_configuration); } -static void board_uart_init(void) +static void exynos_uart_init(void) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i; - - /* - * UART2 GPIOs - * GPA1CON[0] = UART_2_RXD(2) - * GPA1CON[1] = UART_2_TXD(2) - * GPA1CON[2] = I2C_3_SDA (3) - * GPA1CON[3] = I2C_3_SCL (3) - */ - - for (i = 0; i < 4; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); - } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); s5p_gpio_direction_output(&gpio2->y4, 7, 1); } -int board_early_init_f(void) +int exynos_early_init_f(void) { wdt_stop(); pmic_reset(); board_clock_init(); - board_uart_init(); + exynos_uart_init(); board_power_init(); return 0; @@ -647,7 +556,7 @@ void exynos_reset_lcd(void) s5p_gpio_direction_output(&gpio2->y4, 5, 1); } -static int lcd_power(void) +int lcd_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -670,46 +579,7 @@ static int lcd_power(void) return 0; } -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&s6e8ax0_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -732,57 +602,13 @@ static int mipi_power(void) return 0; } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 1, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1, - vid->resolution = HD_RESOLUTION, - vid->rgb_mode = MODE_RGB_P, - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - mipi_lcd_device.reverse_panel = 1; - - strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); - s6e8ax0_platform_data.lcd_power = lcd_power; - s6e8ax0_platform_data.mipi_power = mipi_power; - s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; - s6e8ax0_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - exynos_set_dsim_platform_data(&s6e8ax0_platform_data); - setenv("lcdinfo", "lcd=s6e8ax0"); +#endif } diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index be15357e69..f558ef97a9 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -8,15 +8,9 @@ #include #include -#include -#include -#include -#include -#include -#include -#include #include #include +#include #include #include #include @@ -68,19 +62,6 @@ static void check_hw_revision(void) board_rev = modelrev << 8; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS2\n"); - return 0; -} -#endif - -static void show_hw_revision(void) -{ - printf("HW Revision:\t0x%04x\n", board_rev); -} - u32 get_board_rev(void) { return board_rev; @@ -144,47 +125,51 @@ static void board_init_i2c(void) int get_soft_i2c_scl_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */ + return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */ else - return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */ + return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */ } int get_soft_i2c_sda_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */ + return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */ else - return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */ + return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */ } #endif -int board_early_init_f(void) +int exynos_early_init_f(void) { - check_hw_revision(); board_external_gpio_init(); - gd->flags |= GD_FLG_DISABLE_CONSOLE; - return 0; } static int pmic_init_max77686(void); -int board_init(void) +int exynos_init(void) { struct exynos4_power *pwr = (struct exynos4_power *)samsung_get_base_power(); - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + check_hw_revision(); + printf("HW Revision:\t0x%04x\n", board_rev); - /* workaround: clear INFORM4..5 */ - writel(0, (unsigned int)&pwr->inform4); - writel(0, (unsigned int)&pwr->inform5); + /* + * First bootloader on the TRATS2 platform uses + * INFORM4 and INFORM5 registers for recovery + * + * To indicate correct boot chain - those two + * registers must be cleared out + */ + writel(0, &pwr->inform4); + writel(0, &pwr->inform5); return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg; struct power_battery *pb; @@ -250,90 +235,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - u32 size_mb; - - size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; - - gd->ram_size = size_mb << 20; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - -int board_mmc_init(bd_t *bis) -{ - int err0, err2 = 0; - - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio2->k0, 2, 1); - s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); - - /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - - err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - if (err0) - debug("SDMMC0 not configured\n"); - else - err0 = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err2) - debug("SDMMC2 not configured\n"); - else - err2 = s5p_mmc_init(2, 4); - } - - return err0 & err2; -} - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -481,46 +382,7 @@ static int pmic_init_max77686(void) */ #ifdef CONFIG_LCD -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim dsim_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&dsim_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { struct pmic *p = pmic_get("MAX77686_PMIC"); @@ -558,71 +420,13 @@ void exynos_reset_lcd(void) s5p_gpio_set_value(&gpio1->f2, 1, 1); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - .mipi_enabled = 1, - - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 25, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; - - vid->power_on_delay = 30; - - mipi_lcd_device.reverse_panel = 1; - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - - strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); - dsim_platform_data.mipi_power = mipi_power; - dsim_platform_data.phy_enable = set_mipi_phy_ctrl; - dsim_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); - +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - - exynos_set_dsim_platform_data(&dsim_platform_data); +#endif } #endif /* LCD */ - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - setenv("model", "GT-I8800"); - setenv("board", "TRATS2"); - - show_hw_revision(); - - return 0; -} -#endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 3feef3f777..f9d71b617d 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -13,15 +13,17 @@ #include #include #include -#include #include #include -#include #include #include +#include #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -41,7 +43,7 @@ static int get_hwrev(void) static void init_pmic_lcd(void); -int power_init_board(void) +int exynos_power_init(void) { int ret; @@ -58,22 +60,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -} - static unsigned short get_adc_value(int channel) { struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); @@ -158,71 +144,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tUniversal C210\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err; - - switch (get_hwrev()) { - case 0: - /* - * Set the low to enable LDO_EN - * But when you use the test board for eMMC booting - * you should set it HIGH since it removes the inverter - */ - /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); - break; - default: - /* - * Default reset state is High and there's no inverter - * But set it as HIGH to ensure - */ - /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); - break; - } - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; - -} -#endif - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -270,7 +191,20 @@ struct s3c_plat_otg_data s5pc210_otg_data = { }; #endif -int board_early_init_f(void) +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} + +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) +{ + return 0; +} +#endif + +int exynos_early_init_f(void) { wdt_stop(); @@ -411,6 +345,11 @@ void exynos_cfg_lcd_gpio(void) spi_init(); } +int mipi_power(void) +{ + return 0; +} + void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); @@ -435,39 +374,6 @@ void exynos_lcd_power_on(void) pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 480, - .vl_row = 800, - .vl_width = 480, - .vl_height = 800, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - - .vl_bpix = 5, /* Bits per pixel */ - - /* LD9040 LCD Panel */ - .vl_hspw = 2, - .vl_hbpd = 16, - .vl_hfpd = 16, - - .vl_vspw = 2, - .vl_vbpd = 8, - .vl_vfpd = 8, - .vl_cmd_allow_len = 0xf, - - .win_id = 0, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 10000, - .reset_delay = 10000, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 0, -}; - void exynos_cfg_ldo(void) { ld9040_cfg_ldo(); @@ -478,12 +384,44 @@ void exynos_enable_ldo(unsigned int onoff) ld9040_enable_ldo(onoff); } -void init_panel_info(vidinfo_t *vid) +int exynos_init(void) { - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; + gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; + gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; + gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; + + switch (get_hwrev()) { + case 0: + /* + * Set the low to enable LDO_EN + * But when you use the test board for eMMC booting + * you should set it HIGH since it removes the inverter + */ + /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ + s5p_gpio_direction_output(&gpio1->e3, 6, 0); + break; + default: + /* + * Default reset state is High and there's no inverter + * But set it as HIGH to ensure + */ + /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ + s5p_gpio_direction_output(&gpio1->e1, 3, 1); + break; + } + +#ifdef CONFIG_SOFT_SPI + soft_spi_init(); +#endif + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + + return 0; +} + +void exynos_lcd_misc_init(vidinfo_t *vid) +{ #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif @@ -494,20 +432,3 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=ld9040"); } - -int board_init(void) -{ - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - -#ifdef CONFIG_SOFT_SPI - soft_spi_init(); -#endif - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - - return 0; -} diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 65dcce804b..e4d4e021bc 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -4,8 +4,10 @@ */ #include - +#include +#include #include +#include /* * Pointer to initial global data area @@ -14,6 +16,11 @@ */ gd_t *gd; +/* Add a simple GPIO device */ +U_BOOT_DEVICE(gpio_sandbox) = { + .name = "gpio_sandbox", +}; + void flush_cache(unsigned long start, unsigned long size) { } @@ -23,13 +30,54 @@ unsigned long timer_read_counter(void) return os_get_nsec() / 1000; } -int timer_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_VIDEO_SANDBOX_SDL + int ret; + + ret = sandbox_lcd_sdl_early_init(); + if (ret) { + puts("Could not init sandbox LCD emulation\n"); + return ret; + } +#endif + + return 0; +} +#endif + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (cros_ec_board_init()) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (cros_ec_get_error()) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + cros_ec_get_error()); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile index f890008be2..ce29b4100e 100644 --- a/board/sandburst/karef/Makefile +++ b/board/sandburst/karef/Makefile @@ -10,11 +10,7 @@ # # TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f karef.o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging +ccflags-y += -DBUILDUSER='"$(shell whoami)"' obj-y = karef.o ../common/flash.o ../common/sb_common.o extra-y += init.o diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile index 37d91a51a3..2c1028bd2b 100644 --- a/board/sandburst/metrobox/Makefile +++ b/board/sandburst/metrobox/Makefile @@ -9,11 +9,7 @@ # # TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f metrobox.o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging +ccflags-y += -DBUILDUSER='"$(shell whoami)"' obj-y = metrobox.o ../common/flash.o ../common/sb_common.o extra-y += init.o diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/sandpoint/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/sc3/init.S b/board/sc3/init.S index 46323d2688..097aa4a5e7 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 6c316faa8f..38ac93d795 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -198,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_MII, }, }; @@ -242,6 +242,25 @@ int board_eth_init(bd_t *bis) n += rv; return n; } + +static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c index 5c22999bb8..f2314b5d3e 100644 --- a/board/siemens/dxr2/mux.c +++ b/board/siemens/dxr2/mux.c @@ -221,6 +221,8 @@ static struct module_pin_mux gpios_pin_mux[] = { {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, + /* nRST for SMSC LAN9303 switch - GPIO2_24 */ + {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ {-1}, }; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index ef3d6cc158..98083d52cd 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -181,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 25ab54d9a2..e0ada3f6a5 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -143,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile new file mode 100644 index 0000000000..c8b4f9a280 --- /dev/null +++ b/board/silica/pengwyn/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c new file mode 100644 index 0000000000..ee88b6f399 --- /dev/null +++ b/board/silica/pengwyn/board.c @@ -0,0 +1,207 @@ +/* + * board.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) + +/* DDR3 RAM timings */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128MJT187E_RD_DQS, + .datawdsratio0 = MT41K128MJT187E_WR_DQS, + .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, + .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128MJT187E_RATIO, + .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd1csratio = MT41K128MJT187E_RATIO, + .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd2csratio = MT41K128MJT187E_RATIO, + .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128MJT187E_EMIF_SDCFG, + .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, + .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, + .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, + .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, + .zq_config = MT41K128MJT187E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_266 = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_303 = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_400 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* + * The pengwyn board uses the TPS650250 PMIC without I2C + * interface and will output the following fixed voltages: + * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) + * VLDO1=1V8 (IO) VLDO2=1V8(IO) + * Vcore=1V1 is fixed, generated by TPS62231 + */ + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* 720MHz cpu, this might change on newer board revisions */ + dpll_mpu_opp100.m = MPUPLL_M_720; + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + /* future configs can return other clock settings */ + return &dpll_ddr_303; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(303, &ddr3_ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif /* if CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return n; + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* if CONFIG_DRIVER_TI_CPSW */ diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h new file mode 100644 index 0000000000..05addf6bb2 --- /dev/null +++ b/board/silica/pengwyn/board.h @@ -0,0 +1,15 @@ +/* + * board.h + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); + +#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c new file mode 100644 index 0000000000..c8be440a20 --- /dev/null +++ b/board/silica/pengwyn/mux.c @@ -0,0 +1,98 @@ +/* + * mux.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "board.h" + +/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ + +/* I2C pins C16(scl)/C17(sda) */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ + {-1}, +}; + +/* MMC0 pins */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +/* MII pins */ +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +/* NAND pins */ +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux() +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c index 8b309b49de..2e2fb2a5b7 100644 --- a/board/solidrun/hummingboard/hummingboard.c +++ b/board/solidrun/hummingboard/hummingboard.c @@ -156,11 +156,7 @@ int board_eth_init(bd_t *bis) setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } #endif diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 08dc09f06d..b0ba320481 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -5,7 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +else obj-y := spr_misc.o obj-y += spr_lowlevel_init.o endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index e25aba2f28..6b6bd9f29d 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 70f9aa16ea..a4c6a8edb0 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index f6b1fdd0e6..ab732a724c 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index e996a0e381..8472002f74 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile index f9053feec3..18d3dd2e6f 100644 --- a/board/spear/x600/Makefile +++ b/board/spear/x600/Makefile @@ -5,6 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +else obj-y := fpga.o x600.o endif diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 044d2049ef..b8edfcd071 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,31 +67,32 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); + phy_reset(phydev); /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++; diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile index 6867a70b7c..f0605e2bcd 100644 --- a/board/st-ericsson/snowball/Makefile +++ b/board/st-ericsson/snowball/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D__RELEASE -D__STN_8500 +ccflags-y += -D__RELEASE -D__STN_8500 obj-y := snowball.o diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile index b9dfbe9359..d6c4280475 100644 --- a/board/st-ericsson/u8500/Makefile +++ b/board/st-ericsson/u8500/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D__RELEASE -D__STN_8500 +ccflags-y += -D__RELEASE -D__STN_8500 obj-y := u8500_href.o gpio.o diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile new file mode 100644 index 0000000000..f0965f7841 --- /dev/null +++ b/board/synopsys/axs101/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += axs101.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c new file mode 100644 index 0000000000..d1271ffcca --- /dev/null +++ b/board/synopsys/axs101/axs101.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 25000000; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(ARC_DWGMAC_BASE, + PHY_INTERFACE_MODE_RGMII) >= 0) + return 1; + + return 0; +} diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c new file mode 100644 index 0000000000..c7f90c4400 --- /dev/null +++ b/board/synopsys/axs101/nand.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define BUS_WIDTH 8 /* AXI data bus width in bytes */ + +/* DMA buffer descriptor bits & masks */ +#define BD_STAT_OWN (1 << 31) +#define BD_STAT_BD_FIRST (1 << 3) +#define BD_STAT_BD_LAST (1 << 2) +#define BD_SIZES_BUFFER1_MASK 0xfff + +#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) + +/* Controller command flags */ +#define B_WFR (1 << 19) /* 1b - Wait for ready */ +#define B_LC (1 << 18) /* 1b - Last cycle */ +#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ + +/* NAND cycle types */ +#define B_CT_ADDRESS (0x0 << 16) /* Address operation */ +#define B_CT_COMMAND (0x1 << 16) /* Command operation */ +#define B_CT_WRITE (0x2 << 16) /* Write operation */ +#define B_CT_READ (0x3 << 16) /* Write operation */ + +enum nand_isr_t { + NAND_ISR_DATAREQUIRED = 0, + NAND_ISR_TXUNDERFLOW, + NAND_ISR_TXOVERFLOW, + NAND_ISR_DATAAVAILABLE, + NAND_ISR_RXUNDERFLOW, + NAND_ISR_RXOVERFLOW, + NAND_ISR_TXDMACOMPLETE, + NAND_ISR_RXDMACOMPLETE, + NAND_ISR_DESCRIPTORUNAVAILABLE, + NAND_ISR_CMDDONE, + NAND_ISR_CMDAVAILABLE, + NAND_ISR_CMDERROR, + NAND_ISR_DATATRANSFEROVER, + NAND_ISR_NONE +}; + +enum nand_regs_t { + AC_FIFO = 0, /* address and command fifo */ + IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */ + INT_STATUS = 0x118, /* interrupt status register */ + INT_CLR_STATUS = 0x120, /* interrupt clear status register */ +}; + +struct nand_bd { + uint32_t status; /* DES0 */ + uint32_t sizes; /* DES1 */ + uint32_t buffer_ptr0; /* DES2 */ + uint32_t buffer_ptr1; /* DES3 */ +}; + +#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r) +#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r) + +static struct nand_bd *bd; /* DMA buffer descriptors */ + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static uint32_t nand_flag_is_set(uint32_t flag) +{ + uint32_t reg = NAND_REG_READ(INT_STATUS); + + if (reg & (1 << NAND_ISR_CMDERROR)) + return 0; + + if (reg & (1 << flag)) { + NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag); + return 1; + } + + return 0; +} + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + + /* Issue "write" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store data + * @len: number of bytes to read + */ +static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + + /* Issue "read" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char axs101_nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + + axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * axs101_nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 axs101_nand_read_word(struct mtd_info *mtd) +{ + u16 word; + + axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * axs101_nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, + unsigned int ctrl) +{ + if (cmd == NAND_CMD_NONE) + return; + + cmd = cmd & 0xff; + + switch (ctrl & (NAND_ALE | NAND_CLE)) { + /* Address */ + case NAND_ALE: + cmd |= B_CT_ADDRESS; + break; + + /* Command */ + case NAND_CLE: + cmd |= B_CT_COMMAND | B_WFR; + + break; + + default: + debug("%s: unknown ctrl %#x\n", __func__, ctrl); + } + + NAND_REG_WRITE(AC_FIFO, cmd | B_LC); + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; +} + +int board_nand_init(struct nand_chip *nand) +{ + bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN, + sizeof(struct nand_bd)); + + /* Set buffer descriptor address in IDMAC */ + NAND_REG_WRITE(IDMAC_BDADDR, bd); + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = axs101_nand_hwcontrol; + nand->read_byte = axs101_nand_read_byte; + nand->read_word = axs101_nand_read_word; + nand->write_buf = axs101_nand_write_buf; + nand->read_buf = axs101_nand_read_buf; + + return 0; +} diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/tcm-bf518/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index 973d357559..7f9138b09b 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 2a30ab8981..947305b58d 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -46,23 +46,42 @@ NAND The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In this example to program the NAND we assume that an SD card has been inserted with the files to write in the first SD slot and that mtdparts -have been configured correctly for the board. As a time saving measure we -load MLO into memory in one location, copy it into the three locatations -that the ROM checks for additional valid copies, then load U-Boot into -memory. We then write that whole section of memory to NAND. +have been configured correctly for the board. All images are first loaded +into memory, then written to NAND. -U-Boot # mmc rescan -U-Boot # env default -f -a -U-Boot # nand erase.chip -U-Boot # saveenv -U-Boot # load mmc 0 81000000 MLO -U-Boot # cp.b 81000000 81020000 20000 -U-Boot # cp.b 81000000 81040000 20000 -U-Boot # cp.b 81000000 81060000 20000 -U-Boot # load mmc 0 81080000 u-boot.img -U-Boot # nand write 81000000 0 260000 -U-Boot # load mmc 0 ${loadaddr} uImage -U-Boot # nand write ${loadaddr} kernel 500000 +Step-1: Building u-boot for NAND boot + Set following CONFIGxx options for NAND device. + CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page + CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page + CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block + CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) + +Step-2: Flashing NAND via MMC/SD + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card + U-Boot # mmc rescan + # erase flash + U-Boot # nand erase.chip + U-Boot # env default -f -a + U-Boot # saveenv + # flash MLO. Redundant copies of MLO are kept for failsafe + U-Boot # load mmc 0 0x82000000 MLO + U-Boot # nand write 0x82000000 0x00000 0x20000 + U-Boot # nand write 0x82000000 0x20000 0x20000 + U-Boot # nand write 0x82000000 0x40000 0x20000 + U-Boot # nand write 0x82000000 0x60000 0x20000 + # flash u-boot.img + U-Boot # load mmc 0 0x82000000 u-boot.img + U-Boot # nand write 0x82000000 0x80000 0x60000 + # flash kernel image + U-Boot # load mmc 0 0x82000000 uImage + U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} + # flash filesystem image + U-Boot # load mmc 0 0x82000000 filesystem.img + U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 + +Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. + The device should boot from images flashed on NAND device. NOR === diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57217688d6..554398f346 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -544,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; @@ -573,8 +573,22 @@ static struct cpsw_platform_data cpsw_data = { }; #endif -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; @@ -602,6 +616,21 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_DRIVER_TI_CPSW + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index 6a734b30ac..a9e3d34df9 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -77,7 +77,12 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Deprecated: this MMU section is used by pxa at present but @@ -108,11 +113,12 @@ SECTIONS KEEP(*(.__bss_end)); } - .dynsym _end : { *(.dynsym) } + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } .hash : { *(.hash*) } + .gnu.hash : { *(.gnu.hash) } .plt : { *(.plt*) } .interp : { *(.interp*) } .gnu : { *(.gnu*) } diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index ed87cd97b0..d7449770a3 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,9 +19,13 @@ #include #include #include "board.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + /* * Read header information from EEPROM into global structure. */ @@ -188,7 +192,7 @@ const struct ctrl_ioregs ioregs_ddr3 = { .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0043, + .emif_sdram_config_ext = 0x0143, }; const struct emif_regs ddr3_emif_regs_400Mhz = { @@ -200,7 +204,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E084008, + .emif_ddr_phy_ctlr_1 = 0x0E004008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00400040, .emif_ddr_ext_phy_ctrl_3 = 0x00400040, @@ -346,14 +350,14 @@ static void enable_vtt_regulator(void) u32 temp; /* enable module */ - writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL); + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); - /* enable output for GPIO0_22 */ - writel(GPIO_SETDATAOUT(GPIO_22), - AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT); - temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE); - temp = temp & ~(GPIO_OE_ENABLE(GPIO_22)); - writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE); + /* enable output for GPIO5_7 */ + writel(GPIO_SETDATAOUT(7), + AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); } void sdram_init(void) @@ -402,3 +406,97 @@ int board_late_init(void) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + /* Additional controls can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 16, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("ethaddr")) { + puts(" not set. Validating first E-fuse MAC\n"); + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + if (board_is_eposevm()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 16; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 810b1941db..77c53d2e90 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -11,6 +11,41 @@ #include #include "board.h" +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ + {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, @@ -33,8 +68,18 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; -static struct module_pin_mux gpio0_22_pin_mux[] = { - {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */ +static struct module_pin_mux gpio5_7_pin_mux[] = { + {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ + {-1}, +}; + +static struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ {-1}, }; @@ -47,9 +92,15 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mdio_pin_mux); - if (board_is_gpevm()) - configure_module_pin_mux(gpio0_22_pin_mux); + if (board_is_gpevm()) { + configure_module_pin_mux(gpio5_7_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + } else if (board_is_eposevm()) { + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(qspi_pin_mux); + } } void enable_i2c0_pin_mux(void) diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README new file mode 100644 index 0000000000..533da01a34 --- /dev/null +++ b/board/ti/dra7xx/README @@ -0,0 +1,26 @@ +Summary +======= + +This document covers various features of the 'dra7xx_evm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} dra7xx/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} dra7xx/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 +U-Boot # mmc rst-function 1 1 diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 1b60b8f672..c6c4fd1743 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -12,6 +12,7 @@ */ #include #include +#include #include #include #include @@ -80,7 +81,7 @@ int board_init(void) int board_late_init(void) { - omap_sata_init(); + init_sata(0); return 0; } @@ -148,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 2, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 3, }, }; @@ -215,6 +216,21 @@ int board_eth_init(bd_t *bis) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S index cad0a5acd8..e05a1c7b55 100644 --- a/board/ti/omap5912osk/lowlevel_init.S +++ b/board/ti/omap5912osk/lowlevel_init.S @@ -18,10 +18,6 @@ #include <./configs/omap1510.h> #endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - .globl lowlevel_init lowlevel_init: diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README new file mode 100644 index 0000000000..970e2eceb7 --- /dev/null +++ b/board/ti/omap5_uevm/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'omap5_uevm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} omap5uevm/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index af854dac1a..3eaa5ac398 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -15,6 +15,7 @@ #include "mux_data.h" #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) +#include #include #include #include @@ -70,7 +71,7 @@ int board_init(void) int board_late_init(void) { - omap_sata_init(); + init_sata(0); return 0; } @@ -157,19 +158,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 31ce363b63..de7ce9fe0b 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -55,238 +55,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ - -}; - #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index cda09a9125..5ab6db98ac 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -284,36 +284,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index fb83eac9be..53c7080979 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 79270a9e94..1e9ef9e38b 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -73,26 +73,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 4394dbaa48..9a9efe7a54 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 140ad7103a..54b3dfb82c 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -132,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x50, .sliver_reg_ofs = 0x700, - .phy_id = 1, + .phy_addr = 1, }, { .slave_reg_ofs = 0x90, .sliver_reg_ofs = 0x740, - .phy_id = 0, + .phy_addr = 0, }, }; diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index b6fdde4d1b..5dbf94e44e 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -54,7 +54,12 @@ SECTIONS . = ALIGN(0x800); - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -63,7 +68,7 @@ SECTIONS __bss_end = .; } - .dynsym _end : { *(.dynsym) } + .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/board/w7o/init.S b/board/w7o/init.S index 54eda3299f..dfde149956 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/w7o/post1.S b/board/w7o/post1.S index 7a411a4920..aae5387212 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -13,8 +13,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 72e9bb2e97..f1951dc5ef 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -25,6 +25,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +57,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const usdhc1_pads[] = { +static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore deleted file mode 100644 index 739c63eb7e..0000000000 --- a/board/xilinx/ppc405-generic/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -config.mk -dts -Makefile -microblaze-generic.c -xparameters.h diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore deleted file mode 100644 index 739c63eb7e..0000000000 --- a/board/xilinx/ppc440-generic/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -config.mk -dts -Makefile -microblaze-generic.c -xparameters.h diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 2bc7d4cacf..131addeea4 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -6,12 +6,10 @@ # obj-y := board.o - -ifneq ($(wildcard ps7_init.c),) -ifneq ($(wildcard ps7_init.h),) obj-$(CONFIG_SPL_BUILD) += ps7_init.o + +ifneq ($(wildcard ps7_init.h),) ifeq ($(CONFIG_SPL_BUILD),y) $(shell touch xil_io.h) endif endif -endif diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 9a45fe1139..6f48253c1a 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include #include @@ -59,7 +61,8 @@ int board_init(void) } #endif - /* temporary hack to clear pending irqs before Linux as it + /* + * temporary hack to clear pending irqs before Linux as it * will hang Linux */ writel(0x26d, 0xe0001014); @@ -155,8 +158,27 @@ int board_mmc_init(bd_t *bd) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#ifdef CONFIG_OF_CONTROL + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("ZYNQ DRAM: Can't get memory node\n"); + return -1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("ZYNQ DRAM: Can't get base address or size\n"); + return -1; + } + gd->ram_size = size; +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif zynq_ddrc_init(); return 0; diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c new file mode 100644 index 0000000000..c47da09b9e --- /dev/null +++ b/board/xilinx/zynq/ps7_init.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +__weak void ps7_init(void) +{ + puts("Please copy ps7_init.c/h from hw project\n"); +} diff --git a/boards.cfg b/boards.cfg index 711f58b4f3..eefa6a68a2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -43,6 +43,10 @@ # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers ########################################################################################################### +Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng +Active arc arc700 - synopsys - axs101 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4-be - Alexey Brodkin Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij Active arm arm1136 mx31 - - imx31_phycore - - Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk @@ -59,11 +63,11 @@ Active arm arm720t - armltd integrator Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang -Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas Bießmann +Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann -Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig +Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig -Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard +Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard Active arm arm920t imx - - scb9328 - Torsten Koschorrek Active arm arm920t ks8695 - - cm4008 - Greg Ungerer @@ -136,12 +140,12 @@ Active arm arm926ejs at91 eukrea cpu9260 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev +Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher +Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher +Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig -Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher -Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher -Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher -Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher +Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara @@ -168,10 +172,11 @@ Active arm arm926ejs kirkwood d-link - Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov Active arm arm926ejs kirkwood karo tk71 tk71 - - Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp -Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp @@ -202,15 +207,15 @@ Active arm arm926ejs mx25 syteco zmx25 Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes :Eric Jarrige Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher -Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala +Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut -Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut -Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador +Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut +Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam -Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut -Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut +Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut +Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team :Alessandro Rubini @@ -218,7 +223,7 @@ Active arm arm926ejs nomadik st nhk8815 Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD Active arm arm926ejs pantheon Marvell - dkb - Lei Wen -Active arm arm926ejs spear spear - x600 x600 Stefan Roese +Active arm arm926ejs spear spear - x600 - Stefan Roese Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand - Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty - @@ -247,13 +252,18 @@ Active arm arm946es - armltd integrator Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel -Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg +Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier Active arm armv7 am33xx siemens rut rut - Roger Meier +Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini @@ -268,14 +278,17 @@ Active arm armv7 am33xx ti am335x Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter Active arm armv7 am33xx ti ti816x ti816x_evm - - +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen +Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger Active arm armv7 exynos samsung arndale arndale - Inderpal Singh Active arm armv7 exynos samsung origen origen - Chander Kashyap Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde -Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde +Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap Active arm armv7 exynos samsung trats trats - Lukasz Majewski Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek @@ -291,10 +304,11 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson @@ -308,8 +322,12 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam -Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese -Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton +Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey +Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey +Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey +Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat @@ -346,23 +364,23 @@ Active arm armv7 omap5 ti dra7xx Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu :Tetsuyuki Kobayashi -Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu -Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu +Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu +Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang -Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki -Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki -Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki -Active arm armv7 zynq xilinx zynq zynq_zc770_XM010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki -Active arm armv7 zynq xilinx zynq zynq_zc770_XM012 zynq_zc770:ZC770_XM012 Michal Simek :Jagannadha Sutradharudu Teki -Active arm armv7 zynq xilinx zynq zynq_zc770_XM013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_XM010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zc770_XM011 zynq_zc770:ZC770_XM011 Michal Simek +Active arm armv7 zynq xilinx zynq zynq_zc770_XM012 zynq_zc770:ZC770_XM012 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_XM013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_afx_nor zynq_afx:AFX_NOR Michal Simek Active arm armv7 zynq xilinx zynq zynq_afx_qspi zynq_afx:AFX_QSPI Michal Simek Active arm armv7 zynq xilinx zynq zynq_afx_nand zynq_afx:AFX_NAND Michal Simek @@ -381,10 +399,10 @@ Active arm armv7 zynq xilinx zynq Active arm armv7 zynq xilinx zynq zynq_zc70x_RSA zynq_zc70x:CMD_ZYNQ_RSA Michal Simek Active arm armv7 zynq xilinx zynq zynq_zed_RSA zynq_zed:CMD_ZYNQ_RSA Michal Simek Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren +Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel -Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren @@ -392,16 +410,9 @@ Active arm armv7:arm720t tegra20 nvidia seaboard Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach +Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - actux2 - Michael Schwingen -Active arm ixp - - - actux3 - Michael Schwingen -Active arm ixp - - - actux4 - Michael Schwingen -Active arm ixp - - - dvlhost - Michael Schwingen -Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen -Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen -Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen -Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen Active arm pxa - - - balloon3 - Marek Vasut Active arm pxa - - - h2200 - Lukasz Dalek Active arm pxa - - - palmld - Marek Vasut @@ -418,7 +429,6 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich Active arm pxa - toradex - colibri_pxa270 - Marek Vasut Active arm sa1100 - - - jornada - Kristoffer Ericson -Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen @@ -430,45 +440,36 @@ Active avr32 at32ap at32ap700x in-circuit - Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May :Alex Raimondi Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald -Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang :Chong Huang -Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-sdp - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf533-stamp - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang +Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang +Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf527-sdp - Sonic Zhang +Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf533-stamp - Sonic Zhang Active blackfin blackfin - - - bf537-minotaur - Martin Strubel -Active blackfin blackfin - - - bf537-pnav - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf537-pnav - Sonic Zhang Active blackfin blackfin - - - bf537-srv1 - Martin Strubel -Active blackfin blackfin - - - bf537-stamp - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf537-stamp - Sonic Zhang +Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin :Valentin Yakovenkov -Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang Active blackfin blackfin - - - blackstamp - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews Active blackfin blackfin - - - blackvme - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews Active blackfin blackfin - - - br4 - Dimitar Penev -Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule Active blackfin blackfin - - - ip04 - Brent Kandetzki Active blackfin blackfin - - - pr1 - Dimitar Penev -Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards -Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards -Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang :Blackfin Team +Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew -Active m68k mcf52x2 - - - idmr - - Active m68k mcf52x2 - - cobra5272 cobra5272 - - Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig @@ -477,7 +478,6 @@ Active m68k mcf52x2 - freescale m5208evbe Active m68k mcf52x2 - freescale m5249evb M5249EVB - - Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser -Active m68k mcf52x2 - freescale m5271evb M5271EVB - - Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - Active m68k mcf52x2 - freescale m5275evb M5275EVB - - Active m68k mcf52x2 - freescale m5282evb M5282EVB - - @@ -517,8 +517,8 @@ Active m68k mcf547x_8x - freescale m548xevb Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - -Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton -Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton +Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton +Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - @@ -594,7 +594,7 @@ Active powerpc mpc5xxx - - icecube Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B - Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - -Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 - +Active powerpc mpc5xxx - - mcc200 mcc200 - - Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 - Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - @@ -637,19 +637,17 @@ Active powerpc mpc5xxx - intercontrol digsy_mtc Active powerpc mpc5xxx - manroland - hmi1001 - - Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher -Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz -Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz -Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl +Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl Active powerpc mpc5xxx - tqc tqm5200 aev - - Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B - Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - -Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher +Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 - Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP - Active powerpc mpc5xxx - tqc tqm5200 TB5200 - - Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B - -Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: - +Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 - @@ -657,17 +655,14 @@ Active powerpc mpc5xxx - tqc tqm5200 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc824x - - - utx8245 - Greg Allen Active powerpc mpc824x - - a3000 A3000 - - -Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner +Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk Active powerpc mpc824x - - eXalion eXalion - Torsten Demke -Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson Active powerpc mpc824x - - mvblue MVBLUE - - Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson -Active powerpc mpc824x - etin - debris - Sangmoon Kim -Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim Active powerpc mpc8260 - - - atc - Wolfgang Denk Active powerpc mpc8260 - - - ep8260 - Frank Panno Active powerpc mpc8260 - - - ep82xxm - - @@ -676,16 +671,12 @@ Active powerpc mpc8260 - - - Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp Active powerpc mpc8260 - - - sacsng - Jerry Van Baren Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen -Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk +Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk -Active powerpc mpc8260 - - cpu87 CPU87 CPU87 - +Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - -Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen -Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger -Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen -Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk @@ -696,29 +687,10 @@ Active powerpc mpc8260 - - pm826 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk -Active powerpc mpc8260 - - pm828 PM828 PM828 - +Active powerpc mpc8260 - - pm828 PM828 - - Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - -Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen -Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen -Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck @@ -736,21 +708,21 @@ Active powerpc mpc8260 - tqc tqm8260 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk Active powerpc mpc8260 - tqc tqm8272 TQM8272 - - Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok -Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker +Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt -Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt +Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND - -Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu +Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski -Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu +Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu @@ -769,10 +741,7 @@ Active powerpc mpc83xx - freescale mpc8360emds Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov -Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu +Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck @@ -783,12 +752,10 @@ Active powerpc mpc83xx - keymile km83xx Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck -Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz -Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid Active powerpc mpc83xx - tqc tqm834x TQM834x - - -Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker +Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker @@ -796,12 +763,12 @@ Active powerpc mpc85xx - - sbc8548 Active powerpc mpc85xx - - socrates socrates - - Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal @@ -815,48 +782,49 @@ Active powerpc mpc85xx - freescale bsc9132qds Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu +Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu Active powerpc mpc85xx - freescale corenet_ds P3041DS - - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS - - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS - - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5040DS - - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala -Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala +Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - -Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS - +Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - -Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala +Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - -Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS - +Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - -Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS - +Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - - Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - @@ -895,8 +863,8 @@ Active powerpc mpc85xx - freescale p1022ds Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi -Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB - -Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang +Active powerpc mpc85xx - freescale p1023rdb P1023RDB - - +Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - @@ -981,42 +949,53 @@ Active powerpc mpc85xx - freescale p2020ds Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal +Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal +Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal -Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal -Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal -Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach +Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek -Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek +Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek Active powerpc mpc85xx - xes - xpedite520x - - Active powerpc mpc85xx - xes - xpedite537x - - Active powerpc mpc85xx - xes - xpedite550x - - Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - -Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala +Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala Active powerpc mpc86xx - xes - xpedite517x - - Active powerpc mpc8xx - - - hermes - Wolfgang Denk @@ -1026,10 +1005,6 @@ Active powerpc mpc8xx - - - Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - - svm_sc8xx - John Zhan Active powerpc mpc8xx - - - v37 - - -Active powerpc mpc8xx - - adder Adder - Yuli Barcohen -Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen -Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen -Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark Active powerpc mpc8xx - - fads MPC86xADS - - @@ -1048,7 +1023,7 @@ Active powerpc mpc8xx - - ivm Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 - Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 - -Active powerpc mpc8xx - - netta NETTA NETTA - +Active powerpc mpc8xx - - netta NETTA - - Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 - Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 - @@ -1062,7 +1037,7 @@ Active powerpc mpc8xx - - netvia Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk Active powerpc mpc8xx - - rbc823 RBC823 - - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW - +Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - @@ -1122,7 +1097,6 @@ Active powerpc ppc4xx - - w7o Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen Active powerpc ppc4xx - amcc - acadia - Stefan Roese Active powerpc ppc4xx - amcc - bamboo - Stefan Roese -Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri Active powerpc ppc4xx - amcc - bubinga - - Active powerpc ppc4xx - amcc - ebony - Stefan Roese Active powerpc ppc4xx - amcc - katmai - Stefan Roese @@ -1133,28 +1107,19 @@ Active powerpc ppc4xx - amcc - Active powerpc ppc4xx - amcc - taihu - John Otken Active powerpc ppc4xx - amcc - taishan - Stefan Roese Active powerpc ppc4xx - amcc - yucca - - -Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese -Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese -Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese -Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese -Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese -Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese -Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese -Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese -Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - @@ -1204,8 +1169,6 @@ Active powerpc ppc4xx - mpl mip405 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter Active powerpc ppc4xx - prodrive - alpr - Stefan Roese Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese -Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com> -Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com> Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic - Michal Simek Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic - Michal Simek @@ -1238,11 +1201,57 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +# The following were moved to "Orphan" in March, 2014 +Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards +Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz +Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz +Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso +Orphan powerpc mpc824x - etin - debris - Sangmoon Kim +Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim +Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen +Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen +Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen +Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen +Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen +Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov +Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz +Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz +Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen +Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen +Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri +Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff +Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer +Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer +# The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski Orphan arm pxa - - - lubbock - (dead address) Kyle Harris -Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 - -Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man +Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - Orphan powerpc mpc824x - - mousse MOUSSE - - Orphan powerpc mpc8260 - - - rsdproto - - Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - diff --git a/common/Makefile b/common/Makefile index 780c697ab5..6203982e7a 100644 --- a/common/Makefile +++ b/common/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o obj-$(CONFIG_CMD_DATE) += cmd_date.o +obj-$(CONFIG_CMD_DEMO) += cmd_demo.o obj-$(CONFIG_CMD_SOUND) += cmd_sound.o ifdef CONFIG_4xx obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o @@ -81,9 +82,8 @@ obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o obj-$(CONFIG_CMD_FAT) += cmd_fat.o -obj-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o +obj-$(CONFIG_CMD_FDC) += cmd_fdc.o obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o -obj-$(CONFIG_CMD_FDOS) += cmd_fdos.o obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o obj-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA @@ -159,6 +159,9 @@ obj-$(CONFIG_CMD_UBI) += cmd_ubi.o obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o +ifdef CONFIG_LZMA +obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o +endif ifdef CONFIG_CMD_USB obj-y += cmd_usb.o obj-y += usb.o usb_hub.o @@ -199,6 +202,13 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o +ifdef CONFIG_SPL_USB_HOST_SUPPORT +obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o +obj-$(CONFIG_USB_STORAGE) += usb_storage.o +endif +ifdef CONFIG_SPL_SATA_SUPPORT +obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o +endif ifneq ($(CONFIG_SPL_NET_SUPPORT),y) obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o @@ -224,6 +234,7 @@ obj-$(SPD) += ddr_spd.o obj-$(CONFIG_HWCONFIG) += hwconfig.o obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o obj-y += console.o +obj-$(CONFIG_CROS_EC) += cros_ec.o obj-y += dlmalloc.o obj-y += image.o obj-$(CONFIG_OF_LIBFDT) += image-fdt.o @@ -232,11 +243,4 @@ obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o obj-y += memsize.o obj-y += stdio.o -$(obj)env_embedded.o: $(src)env_embedded.c - $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell $(obj)../tools/envcrc) \ - -c -o $@ $(src)env_embedded.c - -# SEE README.arm-unaligned-accesses -$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/common/board_f.c b/common/board_f.c index aa70c3e57d..f285bad538 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -149,13 +149,9 @@ static int display_text_info(void) #ifndef CONFIG_SANDBOX ulong bss_start, bss_end; -#ifdef CONFIG_SYS_SYM_OFFSETS - bss_start = _bss_start_ofs + _TEXT_BASE; - bss_end = _bss_end_ofs + _TEXT_BASE; -#else bss_start = (ulong)&__bss_start; bss_end = (ulong)&__bss_end; -#endif + debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", CONFIG_SYS_TEXT_BASE, bss_start, bss_end); #endif @@ -223,17 +219,6 @@ static int show_dram_config(void) return 0; } -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - void __dram_init_banksize(void) { #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) @@ -279,8 +264,8 @@ static int zero_global_data(void) static int setup_mon_len(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - gd->mon_len = _bss_end_ofs; +#ifdef __ARM__ + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #elif defined(CONFIG_SANDBOX) gd->mon_len = (ulong)&_end - (ulong)_init; #else @@ -297,45 +282,39 @@ __weak int arch_cpu_init(void) #ifdef CONFIG_OF_HOSTFILE -#define CHECK(x) err = (x); if (err) goto failed; - -/* Create an empty device tree blob */ -static int make_empty_fdt(void *fdt) -{ - int err; - - CHECK(fdt_create(fdt, 256)); - CHECK(fdt_finish_reservemap(fdt)); - CHECK(fdt_begin_node(fdt, "")); - CHECK(fdt_end_node(fdt)); - CHECK(fdt_finish(fdt)); - - return 0; -failed: - printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); - return -EACCES; -} - static int read_fdt_from_file(void) { struct sandbox_state *state = state_get_current(); + const char *fname = state->fdt_fname; void *blob; - int size; + ssize_t size; int err; + int fd; blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); if (!state->fdt_fname) { - err = make_empty_fdt(blob); + err = fdt_create_empty_tree(blob, 256); if (!err) goto done; - return err; + printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); + return -EINVAL; } - err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX); - if (err) - return err; - size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0); - if (size < 0) + + size = os_get_filesize(fname); + if (size < 0) { + printf("Failed to file FDT file '%s'\n", fname); + return -ENOENT; + } + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Failed to open FDT file '%s'\n", fname); + return -EACCES; + } + if (os_read(fd, blob, size) != size) { + os_close(fd); return -EIO; + } + os_close(fd); done: gd->fdt_blob = blob; @@ -360,14 +339,10 @@ static int setup_fdt(void) { #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ -# ifdef CONFIG_SYS_SYM_OFFSETS - gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); -# else gd->fdt_blob = (ulong *)&_end; -# endif #elif defined(CONFIG_OF_HOSTFILE) if (read_fdt_from_file()) { puts("Failed to read control FDT\n"); @@ -661,7 +636,7 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif -#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif @@ -877,19 +852,17 @@ static init_fnc_t init_sequence_f[] = { #endif display_options, /* say that we are here */ display_text_info, /* show debugging info if required */ -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) prt_8260_rsr, prt_8260_clks, -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ #if defined(CONFIG_MPC83xx) prt_83xx_rsr, #endif #ifdef CONFIG_PPC checkcpu, #endif -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ diff --git a/common/board_r.c b/common/board_r.c index 86ca1cbbd4..8629a656c2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -18,6 +18,7 @@ #ifdef CONFIG_HAS_DATAFLASH #include #endif +#include #include #include #if defined(CONFIG_CMD_IDE) @@ -51,7 +52,9 @@ #ifdef CONFIG_X86 #include #endif +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -128,8 +131,8 @@ __weak int fixup_cpu(void) static int initr_reloc_global_data(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - monitor_flash_len = _end_ofs; +#ifdef __ARM__ + monitor_flash_len = _end - __image_copy_start; #elif !defined(CONFIG_SANDBOX) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; #endif @@ -263,6 +266,33 @@ static int initr_malloc(void) return 0; } +#ifdef CONFIG_DM +static int initr_dm(void) +{ + int ret; + + ret = dm_init(); + if (ret) { + debug("dm_init() failed: %d\n", ret); + return ret; + } + ret = dm_scan_platdata(); + if (ret) { + debug("dm_scan_platdata() failed: %d\n", ret); + return ret; + } +#ifdef CONFIG_OF_CONTROL + ret = dm_scan_fdt(gd->fdt_blob); + if (ret) { + debug("dm_scan_fdt() failed: %d\n", ret); + return ret; + } +#endif + + return 0; +} +#endif + __weak int power_init_board(void) { return 0; @@ -761,6 +791,9 @@ init_fnc_t init_sequence_r[] = { initr_barrier, initr_malloc, bootstage_relocate, +#ifdef CONFIG_DM + initr_dm, +#endif #ifdef CONFIG_ARCH_EARLY_INIT_R arch_early_init_r, #endif @@ -903,9 +936,19 @@ init_fnc_t init_sequence_r[] = { void board_init_r(gd_t *new_gd, ulong dest_addr) { +#ifdef CONFIG_NEEDS_MANUAL_RELOC + int i; +#endif + #ifndef CONFIG_X86 gd = new_gd; #endif + +#ifdef CONFIG_NEEDS_MANUAL_RELOC + for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++) + init_sequence_r[i] += gd->reloc_off; +#endif + if (initcall_run_list(init_sequence_r)) hang(); diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 713de1464c..238cadb1e1 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -88,7 +88,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \ - defined(CONFIG_8260) || defined(CONFIG_E500) + defined(CONFIG_MPC8260) || defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); @@ -517,6 +517,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_ARC700) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("mem start", bd->bi_memstart); + print_lnum("mem size", bd->bi_memsize); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf("ip_addr = %s\n", getenv("ipaddr")); +#endif + printf("baudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a59ee95a69..9751edc907 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -514,8 +514,8 @@ static int do_bootm_standalone(int flag, int argc, char * const argv[], setenv_hex("filesize", images->os.image_len); return 0; } - appl = (int (*)(int, char * const []))(ulong)ntohl(images->ep); - (*appl)(argc, argv); + appl = (int (*)(int, char * const []))images->ep; + appl(argc, argv); return 0; } diff --git a/common/cmd_demo.c b/common/cmd_demo.c new file mode 100644 index 0000000000..a3bba7fdf3 --- /dev/null +++ b/common/cmd_demo.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct device *demo_dev; + +static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ch = 0; + + if (argc) + ch = *argv[0]; + + return demo_hello(demo_dev, ch); +} + +static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int status; + int ret; + + ret = demo_status(demo_dev, &status); + if (ret) + return ret; + + printf("Status: %d\n", status); + + return 0; +} + +int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct device *dev; + int i, ret; + + puts("Demo uclass entries:\n"); + + for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev); + dev; + ret = uclass_next_device(&dev)) { + printf("entry %d - instance %08x, ops %08x, platdata %08x\n", + i++, map_to_sysmem(dev), + map_to_sysmem(dev->driver->ops), + map_to_sysmem(dev_get_platdata(dev))); + } + + return cmd_process_error(cmdtp, ret); +} + +static cmd_tbl_t demo_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, do_demo_list, "", ""), + U_BOOT_CMD_MKENT(hello, 2, 1, do_demo_hello, "", ""), + U_BOOT_CMD_MKENT(status, 1, 1, do_demo_status, "", ""), +}; + +static int do_demo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *demo_cmd; + int devnum = 0; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + demo_cmd = find_cmd_tbl(argv[1], demo_commands, + ARRAY_SIZE(demo_commands)); + argc -= 2; + argv += 2; + if (!demo_cmd || argc > demo_cmd->maxargs) + return CMD_RET_USAGE; + + if (argc) { + devnum = simple_strtoul(argv[0], NULL, 10); + ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); + if (ret) + return cmd_process_error(cmdtp, ret); + argc--; + argv++; + } + + ret = demo_cmd->cmd(demo_cmd, flag, argc, argv); + + return cmd_process_error(demo_cmd, ret); +} + +U_BOOT_CMD( + demo, 4, 1, do_demo, + "Driver model (dm) demo operations", + "list List available demo devices\n" + "demo hello [] Say hello\n" + "demo status Get demo device status" +); diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index 39248054f8..fad462fb34 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -389,8 +389,13 @@ void eeprom_init (void) #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_init_f (); #endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \ + defined(CONFIG_SYS_I2C) +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif #endif } diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index 8289d25b06..68b047ba6a 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -79,8 +79,8 @@ int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, /* get the address in hexadecimal format (string to int) */ ram_address = simple_strtoul(argv[3], NULL, 16); - /* get the filesize in base 10 format */ - file_size = simple_strtoul(argv[5], NULL, 10); + /* get the filesize in hexadecimal format */ + file_size = simple_strtoul(argv[5], NULL, 16); /* set the device as block device */ ext4fs_set_blk_dev(dev_desc, &info); diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 98b3c4c001..1cfb656bc0 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -627,72 +627,6 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) return true; } -#if defined(CONFIG_CMD_FDOS) - -/* Low level functions for the Floppy-DOS layer */ - -/************************************************************************** -* int fdc_fdos_init -* initialize the FDC layer -* -*/ -int fdc_fdos_init (int drive) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - /* setup FDC and scan for drives */ - if (fdc_setup(drive, pCMD, pFG) == false) { - printf("\n** Error in setup FDC **\n"); - return false; - } - if (fdc_check_drive(pCMD, pFG) == false) { - printf("\n** Error in check_drives **\n"); - return false; - } - if((pCMD->flags&(1<flags&(0x10<drive=drive; - - /* read first block */ - pCMD->blnr=0; - return true; -} -/************************************************************************** -* int fdc_fdos_seek -* parameter is a block number -*/ -int fdc_fdos_seek (int where) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - pCMD -> blnr = where ; - return (fdc_seek (pCMD, pFG)); -} -/************************************************************************** -* int fdc_fdos_read -* the length is in block number -*/ -int fdc_fdos_read (void *buffer, int len) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - return (fdc_read_data (buffer, len, pCMD, pFG)); -} -#endif - -#if defined(CONFIG_CMD_FDC) /**************************************************************************** * main routine do_fdcboot */ @@ -812,4 +746,3 @@ U_BOOT_CMD( "boot from floppy device", "loadAddr drive" ); -#endif diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index 47eee89221..778aa5f098 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -8,7 +8,7 @@ #include #include - +#include #include #ifndef name_to_gpio @@ -22,25 +22,115 @@ enum gpio_cmd { GPIO_TOGGLE, }; -static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int gpio; - enum gpio_cmd sub_cmd; - ulong value; - const char *str_cmd, *str_gpio; +#if defined(CONFIG_DM_GPIO) && !defined(gpio_status) +static const char * const gpio_function[] = { + "input", + "output", + "unknown", +}; -#ifdef gpio_status - if (argc == 2 && !strcmp(argv[1], "status")) { - gpio_status(); - return 0; +static void show_gpio(struct device *dev, const char *bank_name, int offset) +{ + struct dm_gpio_ops *ops = gpio_get_ops(dev); + char buf[80]; + int ret; + + *buf = '\0'; + if (ops->get_state) { + ret = ops->get_state(dev, offset, buf, sizeof(buf)); + if (ret) { + puts(""); + return; + } + } else { + int func = GPIOF_UNKNOWN; + int ret; + + if (ops->get_function) { + ret = ops->get_function(dev, offset); + if (ret >= 0 && ret < ARRAY_SIZE(gpio_function)) + func = ret; + } + sprintf(buf, "%s%u: %8s %d", bank_name, offset, + gpio_function[func], ops->get_value(dev, offset)); } + + puts(buf); + puts("\n"); +} + +static int do_gpio_status(const char *gpio_name) +{ + struct device *dev; + int newline = 0; + int ret; + + if (gpio_name && !*gpio_name) + gpio_name = NULL; + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + const char *bank_name; + int num_bits; + + bank_name = gpio_get_bank_info(dev, &num_bits); + + if (!gpio_name || !bank_name || + !strncmp(gpio_name, bank_name, strlen(bank_name))) { + const char *p = NULL; + int offset; + + if (bank_name) { + if (newline) + putc('\n'); + printf("Bank %s:\n", bank_name); + } + newline = 1; + if (gpio_name && bank_name) { + p = gpio_name + strlen(bank_name); + offset = simple_strtoul(p, NULL, 10); + show_gpio(dev, bank_name, offset); + } else { + for (offset = 0; offset < num_bits; offset++) + show_gpio(dev, bank_name, offset); + } + } + } + + return ret; +} #endif - if (argc != 3) +static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int gpio; + enum gpio_cmd sub_cmd; + ulong value; + const char *str_cmd, *str_gpio = NULL; +#ifdef CONFIG_DM_GPIO + int ret; +#endif + + if (argc < 2) show_usage: return CMD_RET_USAGE; str_cmd = argv[1]; - str_gpio = argv[2]; + if (argc > 2) + str_gpio = argv[2]; + if (!strcmp(str_cmd, "status")) { + /* Support deprecated gpio_status() */ +#ifdef gpio_status + gpio_status(); + return 0; +#elif defined(CONFIG_DM_GPIO) + return cmd_process_error(cmdtp, do_gpio_status(str_gpio)); +#else + goto show_usage; +#endif + } + + if (!str_gpio) + goto show_usage; /* parse the behavior */ switch (*str_cmd) { @@ -51,11 +141,23 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) default: goto show_usage; } +#if defined(CONFIG_DM_GPIO) + /* + * TODO(sjg@chromium.org): For now we must fit into the existing GPIO + * framework, so we look up the name here and convert it to a GPIO number. + * Once all GPIO drivers are converted to driver model, we can change the + * code here to use the GPIO uclass interface instead of the numbered + * GPIO compatibility layer. + */ + ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio); + if (ret) + return cmd_process_error(cmdtp, ret); +#else /* turn the gpio name into a gpio number */ gpio = name_to_gpio(str_gpio); if (gpio < 0) goto show_usage; - +#endif /* grab the pin before we tweak it */ if (gpio_request(gpio, "cmd_gpio")) { printf("gpio: requesting pin %u failed\n", gpio); @@ -84,6 +186,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD(gpio, 3, 0, do_gpio, - "input/set/clear/toggle gpio pins", + "query and control gpio pins", " \n" - " - input/set/clear/toggle the specified pin"); + " - input/set/clear/toggle the specified pin\n" + "gpio status [ | ]"); diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index 1f12e6deb6..e38422d792 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -29,30 +29,53 @@ * * @return - zero on successful expand and env is set */ -static char extract_env(const char *str, char **env) +static int extract_env(const char *str, char **env) { + int ret = -1; char *e, *s; +#ifdef CONFIG_RANDOM_UUID + char uuid_str[UUID_STR_LEN + 1]; +#endif if (!str || strlen(str) < 4) return -1; - if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) { - s = strdup(str); - if (s == NULL) - return -1; - memset(s + strlen(s) - 1, '\0', 1); - memmove(s, s + 2, strlen(s) - 1); + if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}'))) + return -1; + + s = strdup(str); + if (s == NULL) + return -1; + + memset(s + strlen(s) - 1, '\0', 1); + memmove(s, s + 2, strlen(s) - 1); + + e = getenv(s); + if (e == NULL) { +#ifdef CONFIG_RANDOM_UUID + debug("%s unset. ", str); + gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD); + setenv(s, uuid_str); + e = getenv(s); - free(s); - if (e == NULL) { - printf("Environmental '%s' not set\n", str); - return -1; /* env not set */ + if (e) { + debug("Set to random.\n"); + ret = 0; + } else { + debug("Can't get random UUID.\n"); } - *env = e; - return 0; +#else + debug("%s unset.\n", str); +#endif + } else { + debug("%s get from environment.\n", str); + ret = 0; } - return -1; + *env = e; + free(s); + + return ret; } /** @@ -299,8 +322,16 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; } - if (gpt_default(blk_dev_desc, argv[4])) + puts("Writing GPT: "); + + ret = gpt_default(blk_dev_desc, argv[4]); + if (!ret) { + puts("success!\n"); + return CMD_RET_SUCCESS; + } else { + puts("error!\n"); return CMD_RET_FAILURE; + } } else { return CMD_RET_USAGE; } diff --git a/common/cmd_immap.c b/common/cmd_immap.c index bdf53a4dbb..1414f9ad55 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -12,13 +12,13 @@ #include #include -#if defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) #if defined(CONFIG_8xx) #include #include #include -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #include #include #include @@ -40,7 +40,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile sysconf8xx_t *sc = &immap->im_siu_conf; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile sysconf8260_t *sc = &immap->im_siu_conf; #endif @@ -50,7 +50,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf ("BCR = %08x\n", sc->sc_bcr); printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); @@ -72,7 +72,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile memctl8xx_t *memctl = &immap->im_memctl; int nbanks = 8; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile memctl8260_t *memctl = &immap->im_memctl; int nbanks = 12; #endif @@ -92,19 +92,19 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("MAR = %08x", memctl->memc_mar); #if defined(CONFIG_8xx) printf (" MCR = %08x\n", memctl->memc_mcr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) putc ('\n'); #endif printf ("MAMR = %08x MBMR = %08x", memctl->memc_mamr, memctl->memc_mbmr); #if defined(CONFIG_8xx) printf ("\nMSTAT = %04x\n", memctl->memc_mstat); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf (" MCMR = %08x\n", memctl->memc_mcmr); #endif printf ("MPTPR = %04x MDR = %08x\n", memctl->memc_mptpr, memctl->memc_mdr); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) printf ("PSDMR = %08x LSDMR = %08x\n", memctl->memc_psdmr, memctl->memc_lsdmr); printf ("PURT = %02x PSRT = %02x\n", @@ -123,7 +123,7 @@ do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 int do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -139,7 +139,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile car8xx_t *car = &immap->im_clkrst; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile car8260_t *car = &immap->im_clkrst; #endif @@ -147,7 +147,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("SCCR = %08x\n", car->car_sccr); printf ("PLPRCR= %08x\n", car->car_plprcr); printf ("RSR = %08x\n", car->car_rsr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf ("SCCR = %08x\n", car->car_sccr); printf ("SCMR = %08x\n", car->car_scmr); printf ("RSR = %08x\n", car->car_rsr); @@ -207,7 +207,7 @@ static void binary (char *label, uint value, int nbits) #define PB_NB_ODR 16 #define PC_NBITS 12 #define PD_NBITS 13 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define PA_NBITS 32 #define PA_NB_ODR 32 #define PB_NBITS 28 @@ -224,7 +224,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile iop8xx_t *iop = &immap->im_ioport; volatile ushort *l, *r; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile iop8260_t *iop = &immap->im_ioport; volatile uint *l, *r; #endif @@ -240,7 +240,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) l = &iop->iop_padir; R = &immap->im_cpm.cp_pbdir; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) l = &iop->iop_pdira; R = &iop->iop_pdirb; #endif @@ -248,7 +248,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) binary ("PB_DIR", *R++, PB_NBITS); binary ("PA_PAR", *l++, PA_NBITS); binary ("PB_PAR", *R++, PB_NBITS); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) binary ("PA_SOR", *l++, PA_NBITS); binary ("PB_SOR", *R++, PB_NBITS); #endif @@ -266,7 +266,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) l = &iop->iop_pcdir; r = &iop->iop_pddir; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) l = &iop->iop_pdirc; r = &iop->iop_pdird; #endif @@ -278,7 +278,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) binary ("PC_SO ", *l++, PC_NBITS); binary (" ", 0, 0); r++; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) binary ("PC_SOR", *l++, PC_NBITS); binary ("PD_SOR", *r++, PD_NBITS); binary ("PC_ODR", *l++, PC_NBITS); @@ -436,7 +436,7 @@ static void prbrg (int n, uint val) #if defined(CONFIG_8xx) ulong clock = gd->cpu_clk; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) ulong clock = gd->arch.brg_clk; #endif @@ -489,7 +489,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile cpm8xx_t *cp = &immap->im_cpm; volatile uint *p = &cp->cp_brgc1; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile uint *p = &immap->im_brgc1; #endif int i = 1; @@ -497,7 +497,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) while (i <= 4) prbrg (i++, *p++); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) p = &immap->im_brgc5; while (i <= 8) prbrg (i++, *p++); @@ -514,7 +514,7 @@ do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) volatile i2c8xx_t *i2c = &immap->im_i2c; volatile cpm8xx_t *cp = &immap->im_cpm; volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile i2c8260_t *i2c = &immap->im_i2c; volatile iic_t *iip; uint dpaddr; @@ -614,7 +614,7 @@ U_BOOT_CMD( "" ); -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 U_BOOT_CMD( icinfo, 1, 1, do_icinfo, "print Interrupt Controller registers", diff --git a/common/cmd_itest.c b/common/cmd_itest.c index 29f8076f82..ae2527bfec 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -71,6 +71,19 @@ static char * evalstr(char *s) /* if the parameter starts with a * then assume a string pointer else its a literal */ if (s[0] == '*') { return (char *)simple_strtoul(&s[1], NULL, 16); + } else if (s[0] == '$') { + int i = 2; + + if (s[1] != '{') + return NULL; + + while (s[i] != '}') { + if (s[i] == 0) + return NULL; + i++; + } + s[i] = 0; + return getenv((const char *)&s[2]); } else { return s; } diff --git a/common/cmd_log.c b/common/cmd_log.c index 8164bdf488..38d0f5edfd 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -52,7 +52,7 @@ static char *lbuf; unsigned long __logbuffer_base(void) { - return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN; + return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; } unsigned long logbuffer_base(void) __attribute__((weak, alias("__logbuffer_base"))); diff --git a/common/cmd_lzmadec.c b/common/cmd_lzmadec.c new file mode 100644 index 0000000000..7b0b3fdd90 --- /dev/null +++ b/common/cmd_lzmadec.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2013 Patrice Bouchand + * lzma uncompress command in Uboot + * + * made from existing cmd_unzip.c file of Uboot + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include + +static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long src, dst; + unsigned long src_len = ~0UL, dst_len = ~0UL; + int ret; + + switch (argc) { + case 4: + dst_len = simple_strtoul(argv[3], NULL, 16); + /* fall through */ + case 3: + src = simple_strtoul(argv[1], NULL, 16); + dst = simple_strtoul(argv[2], NULL, 16); + break; + default: + return CMD_RET_USAGE; + } + + ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len, + map_sysmem(src, 0), dst_len); + + if (ret != SZ_OK) + return 1; + printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len); + setenv_hex("filesize", src_len); + + return 0; +} + +U_BOOT_CMD( + lzmadec, 4, 1, do_lzmadec, + "lzma uncompress a memory region", + "srcaddr dstaddr [dstsize]" +); diff --git a/common/cmd_mem.c b/common/cmd_mem.c index c3aab3d4b5..5b03c2d5b1 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -41,7 +41,7 @@ static ulong base_address = 0; /* Memory Display * * Syntax: - * md{.b, .w, .l} {addr} {len} + * md{.b, .w, .l, .q} {addr} {len} */ #define DISP_LINE_LEN 16 static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -155,7 +155,12 @@ static int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong addr, writeval, count; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 writeval; +#else + ulong writeval; +#endif + ulong addr, count; int size; void *buf; ulong bytes; @@ -175,7 +180,11 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Get the value to write. */ +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + writeval = simple_strtoull(argv[2], NULL, 16); +#else writeval = simple_strtoul(argv[2], NULL, 16); +#endif /* Count ? */ if (argc == 4) { @@ -188,11 +197,15 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) buf = map_sysmem(addr, bytes); while (count-- > 0) { if (size == 4) - *((ulong *)buf) = (ulong)writeval; + *((u32 *)buf) = (u32)writeval; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)buf) = (u64)writeval; +#endif else if (size == 2) - *((ushort *)buf) = (ushort)writeval; + *((u16 *)buf) = (u16)writeval; else - *((u_char *)buf) = (u_char)writeval; + *((u8 *)buf) = (u8)writeval; buf += size; } unmap_sysmem(buf); @@ -262,6 +275,11 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int rcode = 0; const char *type; const void *buf1, *buf2, *base; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 word1, word2; +#else + ulong word1, word2; +#endif if (argc != 4) return CMD_RET_USAGE; @@ -270,7 +288,9 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ if ((size = cmd_get_data_size(argv[0], 4)) < 0) return 1; - type = size == 4 ? "word" : size == 2 ? "halfword" : "byte"; + type = size == 8 ? "double word" : + size == 4 ? "word" : + size == 2 ? "halfword" : "byte"; addr1 = simple_strtoul(argv[1], NULL, 16); addr1 += base_address; @@ -298,23 +318,32 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) base = buf1 = map_sysmem(addr1, bytes); buf2 = map_sysmem(addr2, bytes); for (ngood = 0; ngood < count; ++ngood) { - ulong word1, word2; if (size == 4) { - word1 = *(ulong *)buf1; - word2 = *(ulong *)buf2; + word1 = *(u32 *)buf1; + word2 = *(u32 *)buf2; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + } else if (size == 8) { + word1 = *(u64 *)buf1; + word2 = *(u64 *)buf2; +#endif } else if (size == 2) { - word1 = *(ushort *)buf1; - word2 = *(ushort *)buf2; + word1 = *(u16 *)buf1; + word2 = *(u16 *)buf2; } else { - word1 = *(u_char *)buf1; - word2 = *(u_char *)buf2; + word1 = *(u8 *)buf1; + word2 = *(u8 *)buf2; } if (word1 != word2) { ulong offset = buf1 - base; - +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n", + type, (void *)(addr1 + offset), size, word1, + type, (void *)(addr2 + offset), size, word2); +#else printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n", type, (ulong)(addr1 + offset), size, word1, type, (ulong)(addr2 + offset), size, word2); +#endif rcode = 1; break; } @@ -433,11 +462,15 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) src = map_sysmem(addr, bytes); while (count-- > 0) { if (size == 4) - *((ulong *)buf) = *((ulong *)src); + *((u32 *)buf) = *((u32 *)src); +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)buf) = *((u64 *)src); +#endif else if (size == 2) - *((ushort *)buf) = *((ushort *)src); + *((u16 *)buf) = *((u16 *)src); else - *((u_char *)buf) = *((u_char *)src); + *((u8 *)buf) = *((u8 *)src); src += size; buf += size; @@ -467,9 +500,12 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, { ulong addr, length, i, bytes; int size; - volatile uint *longp; - volatile ushort *shortp; - volatile u_char *cp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + volatile u64 *llp; +#endif + volatile u32 *longp; + volatile u16 *shortp; + volatile u8 *cp; const void *buf; if (argc < 3) @@ -497,24 +533,41 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, * If we have only one object, just run infinite loops. */ if (length == 1) { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + llp = (u64 *)buf; + for (;;) + i = *llp; + } +#endif if (size == 4) { - longp = (uint *)buf; + longp = (u32 *)buf; for (;;) i = *longp; } if (size == 2) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; for (;;) i = *shortp; } - cp = (u_char *)buf; + cp = (u8 *)buf; for (;;) i = *cp; } +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + for (;;) { + llp = (u64 *)buf; + i = length; + while (i-- > 0) + *llp++; + } + } +#endif if (size == 4) { for (;;) { - longp = (uint *)buf; + longp = (u32 *)buf; i = length; while (i-- > 0) *longp++; @@ -522,14 +575,14 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, } if (size == 2) { for (;;) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; i = length; while (i-- > 0) *shortp++; } } for (;;) { - cp = (u_char *)buf; + cp = (u8 *)buf; i = length; while (i-- > 0) *cp++; @@ -542,11 +595,17 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, #ifdef CONFIG_LOOPW int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong addr, length, i, data, bytes; + ulong addr, length, i, bytes; int size; - volatile uint *longp; - volatile ushort *shortp; - volatile u_char *cp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + volatile u64 *llp; + u64 data; +#else + ulong data; +#endif + volatile u32 *longp; + volatile u16 *shortp; + volatile u8 *cp; void *buf; if (argc < 4) @@ -568,7 +627,11 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) length = simple_strtoul(argv[2], NULL, 16); /* data to write */ +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + data = simple_strtoull(argv[3], NULL, 16); +#else data = simple_strtoul(argv[3], NULL, 16); +#endif bytes = size * length; buf = map_sysmem(addr, bytes); @@ -577,24 +640,41 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * If we have only one object, just run infinite loops. */ if (length == 1) { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + llp = (u64 *)buf; + for (;;) + *llp = data; + } +#endif if (size == 4) { - longp = (uint *)buf; + longp = (u32 *)buf; for (;;) *longp = data; - } + } if (size == 2) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; for (;;) *shortp = data; } - cp = (u_char *)buf; + cp = (u8 *)buf; for (;;) *cp = data; } +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + for (;;) { + llp = (u64 *)buf; + i = length; + while (i-- > 0) + *llp++ = data; + } + } +#endif if (size == 4) { for (;;) { - longp = (uint *)buf; + longp = (u32 *)buf; i = length; while (i-- > 0) *longp++ = data; @@ -602,14 +682,14 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (size == 2) { for (;;) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; i = length; while (i-- > 0) *shortp++ = data; } } for (;;) { - cp = (u_char *)buf; + cp = (u8 *)buf; i = length; while (i-- > 0) *cp++ = data; @@ -746,7 +826,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -767,7 +848,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, printf("\nFAILURE: Address bit stuck low or" " shorted @ 0x%.8lx: expected 0x%.8lx," " actual 0x%.8lx\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -807,7 +889,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE (read/write) @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -827,7 +910,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != anti_pattern) { printf("\nFAILURE (read/write): @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset, anti_pattern, temp); + start_addr + offset*sizeof(vu_long), + anti_pattern, temp); errs++; if (ctrlc()) return -1; @@ -885,7 +969,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr, printf("\nMem error @ 0x%08X: " "found %08lX, expected %08lX\n", - (uint)(uintptr_t)(start_addr + offset), + (uint)(uintptr_t)(start_addr + offset*sizeof(vu_long)), readback, val); errs++; if (ctrlc()) @@ -994,13 +1078,18 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, /* Modify memory. * * Syntax: - * mm{.b, .w, .l} {addr} - * nm{.b, .w, .l} {addr} + * mm{.b, .w, .l, .q} {addr} + * nm{.b, .w, .l, .q} {addr} */ static int mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) { - ulong addr, i; + ulong addr; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 i; +#else + ulong i; +#endif int nbytes, size; void *ptr = NULL; @@ -1050,11 +1139,15 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) ptr = map_sysmem(addr, size); printf("%08lx:", addr); if (size == 4) - printf(" %08x", *((uint *)ptr)); + printf(" %08x", *((u32 *)ptr)); +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + printf(" %016llx", *((u64 *)ptr)); +#endif else if (size == 2) - printf(" %04x", *((ushort *)ptr)); + printf(" %04x", *((u16 *)ptr)); else - printf(" %02x", *((u_char *)ptr)); + printf(" %02x", *((u8 *)ptr)); nbytes = readline (" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { @@ -1075,7 +1168,11 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) #endif else { char *endp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + i = simple_strtoull(console_buffer, &endp, 16); +#else i = simple_strtoul(console_buffer, &endp, 16); +#endif nbytes = endp - console_buffer; if (nbytes) { #ifdef CONFIG_BOOT_RETRY_TIME @@ -1084,11 +1181,15 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) reset_cmd_timeout(); #endif if (size == 4) - *((uint *)ptr) = i; + *((u32 *)ptr) = i; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)ptr) = i; +#endif else if (size == 2) - *((ushort *)ptr) = i; + *((u16 *)ptr) = i; else - *((u_char *)ptr) = i; + *((u8 *)ptr) = i; if (incrflag) addr += size; } @@ -1132,39 +1233,63 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( md, 3, 1, do_mem_md, "memory display", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address [# of objects]" +#else "[.b, .w, .l] address [# of objects]" +#endif ); U_BOOT_CMD( mm, 2, 1, do_mem_mm, "memory modify (auto-incrementing address)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address" +#else "[.b, .w, .l] address" +#endif ); U_BOOT_CMD( nm, 2, 1, do_mem_nm, "memory modify (constant address)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address" +#else "[.b, .w, .l] address" +#endif ); U_BOOT_CMD( mw, 4, 1, do_mem_mw, "memory write (fill)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address value [count]" +#else "[.b, .w, .l] address value [count]" +#endif ); U_BOOT_CMD( cp, 4, 1, do_mem_cp, "memory copy", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] source target count" +#else "[.b, .w, .l] source target count" +#endif ); U_BOOT_CMD( cmp, 4, 1, do_mem_cmp, "memory compare", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] addr1 addr2 count" +#else "[.b, .w, .l] addr1 addr2 count" +#endif ); #ifdef CONFIG_CMD_CRC32 @@ -1216,14 +1341,22 @@ U_BOOT_CMD( U_BOOT_CMD( loop, 3, 1, do_mem_loop, "infinite loop on address range", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address number_of_objects" +#else "[.b, .w, .l] address number_of_objects" +#endif ); #ifdef CONFIG_LOOPW U_BOOT_CMD( loopw, 4, 1, do_mem_loopw, "infinite write loop on address range", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address number_of_objects data_to_write" +#else "[.b, .w, .l] address number_of_objects data_to_write" +#endif ); #endif /* CONFIG_LOOPW */ @@ -1239,13 +1372,21 @@ U_BOOT_CMD( U_BOOT_CMD( mdc, 4, 1, do_mem_mdc, "memory display cyclic", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address count delay(ms)" +#else "[.b, .w, .l] address count delay(ms)" +#endif ); U_BOOT_CMD( mwc, 4, 1, do_mem_mwc, "memory write cyclic", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address value delay(ms)" +#else "[.b, .w, .l] address value delay(ms)" +#endif ); #endif /* CONFIG_MX_CYCLIC */ diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index da5fef9db9..c1916c9b56 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -79,7 +79,7 @@ enum mmc_state { }; static void print_mmcinfo(struct mmc *mmc) { - printf("Device: %s\n", mmc->name); + printf("Device: %s\n", mmc->cfg->name); printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24); printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff); printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff, @@ -131,36 +131,6 @@ U_BOOT_CMD( "- display info of the current MMC device" ); -#ifdef CONFIG_SUPPORT_EMMC_BOOT -static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - err = mmc_boot_part_access(mmc, ack, part_num, access); - - if ((err == 0) && (access != 0)) { - printf("\t\t\t!!!Notice!!!\n"); - - printf("!You must close EMMC boot Partition"); - printf("after all images are written\n"); - - printf("!EMMC boot partition has continuity"); - printf("at image writing time.\n"); - - printf("!So, do not close the boot partition"); - printf("before all images are written.\n"); - return 0; - } else if ((err == 0) && (access == 0)) - return 0; - else if ((err != 0) && (access != 0)) { - printf("EMMC boot partition-%d OPEN Failed.\n", part_num); - return 1; - } else { - printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); - return 1; - } -} -#endif - static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -195,7 +165,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; else return 0; - } else if (strncmp(argv[1], "part", 4) == 0) { + } else if (strcmp(argv[1], "part") == 0) { block_dev_desc_t *mmc_dev; struct mmc *mmc; @@ -273,15 +243,16 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if ((strcmp(argv[1], "open") == 0) || - (strcmp(argv[1], "close") == 0)) { + } else if (strcmp(argv[1], "partconf") == 0) { int dev; struct mmc *mmc; - u8 part_num, access = 0; + u8 ack, part_num, access; - if (argc == 4) { + if (argc == 6) { dev = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); + ack = simple_strtoul(argv[3], NULL, 10); + part_num = simple_strtoul(argv[4], NULL, 10); + access = simple_strtoul(argv[5], NULL, 10); } else { return CMD_RET_USAGE; } @@ -293,32 +264,53 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (IS_SD(mmc)) { - printf("SD device cannot be opened/closed\n"); + puts("PARTITION_CONFIG only exists on eMMC\n"); return 1; } - if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { - printf("Invalid boot partition number:\n"); - printf("Boot partition number cannot be <= 0\n"); - printf("EMMC44 supports only 2 boot partitions\n"); - return 1; - } - - if (strcmp(argv[1], "open") == 0) - access = part_num; /* enable R/W access to boot part*/ - else - access = 0; /* No access to boot partition */ - /* acknowledge to be sent during boot operation */ - return boot_part_access(mmc, 1, part_num, access); - - } else if (strcmp(argv[1], "bootpart") == 0) { + return mmc_set_part_conf(mmc, ack, part_num, access); + } else if (strcmp(argv[1], "bootbus") == 0) { int dev; - dev = simple_strtoul(argv[2], NULL, 10); + struct mmc *mmc; + u8 width, reset, mode; - u32 bootsize = simple_strtoul(argv[3], NULL, 10); - u32 rpmbsize = simple_strtoul(argv[4], NULL, 10); - struct mmc *mmc = find_mmc_device(dev); + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + width = simple_strtoul(argv[3], NULL, 10); + reset = simple_strtoul(argv[4], NULL, 10); + mode = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return 1; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_boot_bus_width(mmc, width, reset, mode); + } else if (strcmp(argv[1], "bootpart-resize") == 0) { + int dev; + struct mmc *mmc; + u32 bootsize, rpmbsize; + + if (argc == 5) { + dev = simple_strtoul(argv[2], NULL, 10); + bootsize = simple_strtoul(argv[3], NULL, 10); + rpmbsize = simple_strtoul(argv[4], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); if (!mmc) { printf("no mmc device at slot %x\n", dev); return 1; @@ -338,6 +330,40 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("EMMC boot partition Size change Failed.\n"); return 1; } + } else if (strcmp(argv[1], "rst-function") == 0) { + /* + * Set the RST_n_ENABLE bit of RST_n_FUNCTION + * The only valid values are 0x0, 0x1 and 0x2 and writing + * a value of 0x1 or 0x2 sets the value permanently. + */ + int dev; + struct mmc *mmc; + u8 enable; + + if (argc == 4) { + dev = simple_strtoul(argv[2], NULL, 10); + enable = simple_strtoul(argv[3], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + if (enable > 2 || enable < 0) { + puts("Invalid RST_n_ENABLE value\n"); + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + puts("RST_n_FUNCTION only exists on eMMC\n"); + return 1; + } + + return mmc_set_rst_n_function(mmc, enable); #endif /* CONFIG_SUPPORT_EMMC_BOOT */ } @@ -438,12 +464,15 @@ U_BOOT_CMD( "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc open \n" - " - Enable boot_part for booting and enable R/W access of boot_part\n" - "mmc close \n" - " - Enable boot_part for booting and disable access to boot_part\n" - "mmc bootpart \n" - " - change sizes of boot and RPMB partitions of specified device\n" + "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + " - Set the BOOT_BUS_WIDTH field of the specified device\n" + "mmc bootpart-resize \n" + " - Change sizes of boot and RPMB partitions of specified device\n" + "mmc partconf dev boot_ack boot_partition partition_access\n" + " - Change the bits of the PARTITION_CONFIG field of the specified device\n" + "mmc rst-function dev value\n" + " - Change the RST_n_FUNCTION field of the specified device\n" + " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" #endif "mmc setdsr - set DSR register value\n" ); diff --git a/common/cmd_mmc_spi.c b/common/cmd_mmc_spi.c index 98cd788c76..a2138b8650 100644 --- a/common/cmd_mmc_spi.c +++ b/common/cmd_mmc_spi.c @@ -72,7 +72,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Failed to create MMC Device\n"); return 1; } - printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev, + printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev, bus, cs, speed, mode); mmc_init(mmc); return 0; diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 5bcc324675..c53601cf74 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -1008,6 +1008,9 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, if (argc == 2) { size = simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1 && chk) { + puts("## Error: external checksum format must pass size\n"); + return CMD_RET_FAILURE; } else { char *s = addr; diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 6f93335517..67808aa377 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -18,6 +18,7 @@ #include #include +#include #include static const char *otp_strerror(uint32_t err) diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index c27ec354cc..348332874b 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "menu.h" @@ -44,6 +45,7 @@ static char *from_env(const char *envvar) return ret; } +#ifdef CONFIG_CMD_NET /* * Convert an ethaddr from the environment to the format used by pxelinux * filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to @@ -74,6 +76,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len) return 1; } +#endif /* * Returns the directory the file specified in the bootfile env variable is @@ -119,6 +122,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, static int (*do_getfile)(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr); +#ifdef CONFIG_CMD_NET static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) { char *tftp_argv[] = {"tftp", NULL, NULL, NULL}; @@ -131,6 +135,7 @@ static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) return 1; } +#endif static char *fs_argv[5]; @@ -160,6 +165,19 @@ static int do_get_fat(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) return -ENOENT; } +static int do_get_any(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) +{ +#ifdef CONFIG_CMD_FS_GENERIC + fs_argv[0] = "load"; + fs_argv[3] = file_addr; + fs_argv[4] = (void *)file_path; + + if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY)) + return 1; +#endif + return -ENOENT; +} + /* * As in pxelinux, paths to files referenced from files we retrieve are * relative to the location of bootfile. get_relfile takes such a path and @@ -235,6 +253,8 @@ static int get_pxe_file(cmd_tbl_t *cmdtp, const char *file_path, void *file_addr return 1; } +#ifdef CONFIG_CMD_NET + #define PXELINUX_DIR "pxelinux.cfg/" /* @@ -383,6 +403,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } +#endif /* * Wrapper to make it easier to store the file at file_path in the location @@ -445,6 +466,7 @@ struct pxe_label { char *append; char *initrd; char *fdt; + char *fdtdir; int ipappend; int attempted; int localboot; @@ -517,6 +539,9 @@ static void label_destroy(struct pxe_label *label) if (label->fdt) free(label->fdt); + if (label->fdtdir) + free(label->fdtdir); + free(label); } @@ -629,6 +654,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) len += strlen(ip_str); } +#ifdef CONFIG_CMD_NET if (label->ipappend & 0x2) { int err; strcpy(mac_str, " BOOTIF="); @@ -637,6 +663,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) mac_str[0] = '\0'; len += strlen(mac_str); } +#endif if (label->append) len += strlen(label->append); @@ -675,13 +702,70 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) bootm_argv[3] = getenv("fdt_addr_r"); /* if fdt label is defined then get fdt from server */ - if (bootm_argv[3] && label->fdt) { - if (get_relfile_envaddr(cmdtp, label->fdt, "fdt_addr_r") < 0) { - printf("Skipping %s for failure retrieving fdt\n", - label->name); - return 1; + if (bootm_argv[3]) { + char *fdtfile = NULL; + char *fdtfilefree = NULL; + + if (label->fdt) { + fdtfile = label->fdt; + } else if (label->fdtdir) { + char *f1, *f2, *f3, *f4, *slash; + + f1 = getenv("fdtfile"); + if (f1) { + f2 = ""; + f3 = ""; + f4 = ""; + } else { + /* + * For complex cases where this code doesn't + * generate the correct filename, the board + * code should set $fdtfile during early boot, + * or the boot scripts should set $fdtfile + * before invoking "pxe" or "sysboot". + */ + f1 = getenv("soc"); + f2 = "-"; + f3 = getenv("board"); + f4 = ".dtb"; + } + + len = strlen(label->fdtdir); + if (!len) + slash = "./"; + else if (label->fdtdir[len - 1] != '/') + slash = "/"; + else + slash = ""; + + len = strlen(label->fdtdir) + strlen(slash) + + strlen(f1) + strlen(f2) + strlen(f3) + + strlen(f4) + 1; + fdtfilefree = malloc(len); + if (!fdtfilefree) { + printf("malloc fail (FDT filename)\n"); + return 1; + } + + snprintf(fdtfilefree, len, "%s%s%s%s%s%s", + label->fdtdir, slash, f1, f2, f3, f4); + fdtfile = fdtfilefree; } - } else + + if (fdtfile) { + int err = get_relfile_envaddr(cmdtp, fdtfile, "fdt_addr_r"); + free(fdtfilefree); + if (err < 0) { + printf("Skipping %s for failure retrieving fdt\n", + label->name); + return 1; + } + } else { + bootm_argv[3] = NULL; + } + } + + if (!bootm_argv[3]) bootm_argv[3] = getenv("fdt_addr"); if (bootm_argv[3]) @@ -716,6 +800,7 @@ enum token_type { T_PROMPT, T_INCLUDE, T_FDT, + T_FDTDIR, T_ONTIMEOUT, T_IPAPPEND, T_INVALID @@ -745,7 +830,10 @@ static const struct token keywords[] = { {"append", T_APPEND}, {"initrd", T_INITRD}, {"include", T_INCLUDE}, + {"devicetree", T_FDT}, {"fdt", T_FDT}, + {"devicetreedir", T_FDTDIR}, + {"fdtdir", T_FDTDIR}, {"ontimeout", T_ONTIMEOUT,}, {"ipappend", T_IPAPPEND,}, {NULL, T_INVALID} @@ -1134,6 +1222,11 @@ static int parse_label(char **c, struct pxe_menu *cfg) err = parse_sliteral(c, &label->fdt); break; + case T_FDTDIR: + if (!label->fdtdir) + err = parse_sliteral(c, &label->fdtdir); + break; + case T_LOCALBOOT: label->localboot = 1; err = parse_integer(c, &label->localboot_val); @@ -1419,6 +1512,7 @@ static void handle_pxe_menu(cmd_tbl_t *cmdtp, struct pxe_menu *cfg) boot_unattempted_labels(cmdtp, cfg); } +#ifdef CONFIG_CMD_NET /* * Boots a system using a pxe file * @@ -1495,6 +1589,7 @@ U_BOOT_CMD( "get - try to retrieve a pxe file using tftp\npxe " "boot [pxefile_addr_r] - boot from the pxe file at pxefile_addr_r\n" ); +#endif /* * Boots a system using a local disk syslinux/extlinux file @@ -1539,6 +1634,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) do_getfile = do_get_ext2; else if (strstr(argv[3], "fat")) do_getfile = do_get_fat; + else if (strstr(argv[3], "any")) + do_getfile = do_get_any; else { printf("Invalid filesystem: %s\n", argv[3]); return 1; @@ -1576,7 +1673,7 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sysboot, 7, 1, do_sysboot, "command to get and boot from syslinux files", - "[-p] [addr] [filename]\n" - " - load and parse syslinux menu file 'filename' from ext2 or fat\n" - " filesystem on 'dev' on 'interface' to address 'addr'" + "[-p] [addr] [filename]\n" + " - load and parse syslinux menu file 'filename' from ext2, fat\n" + " or any filesystem on 'dev' on 'interface' to address 'addr'" ); diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 7b97dc9332..b3f7687aee 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -168,7 +168,9 @@ removable: scsi_curr_dev = -1; printf("Found %d device(s).\n", scsi_max_devs); +#ifndef CONFIG_SPL_BUILD setenv_ulong("scsidevs", scsi_max_devs); +#endif } int scsi_get_disk_count(void) diff --git a/common/cmd_test.c b/common/cmd_test.c index bacc368406..c93fe78231 100644 --- a/common/cmd_test.c +++ b/common/cmd_test.c @@ -16,11 +16,54 @@ #include #include +#include + +#define OP_INVALID 0 +#define OP_NOT 1 +#define OP_OR 2 +#define OP_AND 3 +#define OP_STR_EMPTY 4 +#define OP_STR_NEMPTY 5 +#define OP_STR_EQ 6 +#define OP_STR_NEQ 7 +#define OP_STR_LT 8 +#define OP_STR_GT 9 +#define OP_INT_EQ 10 +#define OP_INT_NEQ 11 +#define OP_INT_LT 12 +#define OP_INT_LE 13 +#define OP_INT_GT 14 +#define OP_INT_GE 15 +#define OP_FILE_EXISTS 16 + +const struct { + int arg; + const char *str; + int op; + int adv; +} op_adv[] = { + {1, "=", OP_STR_EQ, 3}, + {1, "!=", OP_STR_NEQ, 3}, + {1, "<", OP_STR_LT, 3}, + {1, ">", OP_STR_GT, 3}, + {1, "-eq", OP_INT_EQ, 3}, + {1, "-ne", OP_INT_NEQ, 3}, + {1, "-lt", OP_INT_LT, 3}, + {1, "-le", OP_INT_LE, 3}, + {1, "-gt", OP_INT_GT, 3}, + {1, "-ge", OP_INT_GE, 3}, + {0, "!", OP_NOT, 1}, + {0, "-o", OP_OR, 1}, + {0, "-a", OP_AND, 1}, + {0, "-z", OP_STR_EMPTY, 2}, + {0, "-n", OP_STR_NEMPTY, 2}, + {0, "-e", OP_FILE_EXISTS, 4}, +}; static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char * const *ap; - int left, adv, expr, last_expr, neg, last_cmp; + int i, op, left, adv, expr, last_expr, last_unop, last_binop; /* args? */ if (argc < 3) @@ -35,101 +78,112 @@ static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif - last_expr = 0; - left = argc - 1; ap = argv + 1; - if (left > 0 && strcmp(ap[0], "!") == 0) { - neg = 1; - ap++; - left--; - } else - neg = 0; - - expr = -1; - last_cmp = -1; + left = argc - 1; + ap = argv + 1; + expr = 0; + last_unop = OP_INVALID; + last_binop = OP_INVALID; last_expr = -1; while (left > 0) { - - if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0) - adv = 1; - else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0) - adv = 2; - else - adv = 3; - + for (i = 0; i < ARRAY_SIZE(op_adv); i++) { + if (left <= op_adv[i].arg) + continue; + if (!strcmp(ap[op_adv[i].arg], op_adv[i].str)) { + op = op_adv[i].op; + adv = op_adv[i].adv; + break; + } + } + if (i == ARRAY_SIZE(op_adv)) { + expr = 1; + break; + } if (left < adv) { expr = 1; break; } - if (adv == 1) { - if (strcmp(ap[0], "-o") == 0) { - last_expr = expr; - last_cmp = 0; - } else if (strcmp(ap[0], "-a") == 0) { - last_expr = expr; - last_cmp = 1; - } else { - expr = 1; - break; - } + switch (op) { + case OP_STR_EMPTY: + expr = strlen(ap[1]) == 0 ? 1 : 0; + break; + case OP_STR_NEMPTY: + expr = strlen(ap[1]) == 0 ? 0 : 1; + break; + case OP_STR_EQ: + expr = strcmp(ap[0], ap[2]) == 0; + break; + case OP_STR_NEQ: + expr = strcmp(ap[0], ap[2]) != 0; + break; + case OP_STR_LT: + expr = strcmp(ap[0], ap[2]) < 0; + break; + case OP_STR_GT: + expr = strcmp(ap[0], ap[2]) > 0; + break; + case OP_INT_EQ: + expr = simple_strtol(ap[0], NULL, 10) == + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_NEQ: + expr = simple_strtol(ap[0], NULL, 10) != + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_LT: + expr = simple_strtol(ap[0], NULL, 10) < + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_LE: + expr = simple_strtol(ap[0], NULL, 10) <= + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_GT: + expr = simple_strtol(ap[0], NULL, 10) > + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_GE: + expr = simple_strtol(ap[0], NULL, 10) >= + simple_strtol(ap[2], NULL, 10); + break; + case OP_FILE_EXISTS: + expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY); + break; } - if (adv == 2) { - if (strcmp(ap[0], "-z") == 0) - expr = strlen(ap[1]) == 0 ? 1 : 0; - else if (strcmp(ap[0], "-n") == 0) - expr = strlen(ap[1]) == 0 ? 0 : 1; - else { - expr = 1; - break; + switch (op) { + case OP_OR: + last_expr = expr; + last_binop = OP_OR; + break; + case OP_AND: + last_expr = expr; + last_binop = OP_AND; + break; + case OP_NOT: + if (last_unop == OP_NOT) + last_unop = OP_INVALID; + else + last_unop = OP_NOT; + break; + default: + if (last_unop == OP_NOT) { + expr = !expr; + last_unop = OP_INVALID; } - if (last_cmp == 0) + if (last_binop == OP_OR) expr = last_expr || expr; - else if (last_cmp == 1) + else if (last_binop == OP_AND) expr = last_expr && expr; - last_cmp = -1; - } + last_binop = OP_INVALID; - if (adv == 3) { - if (strcmp(ap[1], "=") == 0) - expr = strcmp(ap[0], ap[2]) == 0; - else if (strcmp(ap[1], "!=") == 0) - expr = strcmp(ap[0], ap[2]) != 0; - else if (strcmp(ap[1], ">") == 0) - expr = strcmp(ap[0], ap[2]) > 0; - else if (strcmp(ap[1], "<") == 0) - expr = strcmp(ap[0], ap[2]) < 0; - else if (strcmp(ap[1], "-eq") == 0) - expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-ne") == 0) - expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-lt") == 0) - expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-le") == 0) - expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-gt") == 0) - expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-ge") == 0) - expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10); - else { - expr = 1; - break; - } - - if (last_cmp == 0) - expr = last_expr || expr; - else if (last_cmp == 1) - expr = last_expr && expr; - last_cmp = -1; + break; } ap += adv; left -= adv; } - if (neg) - expr = !expr; - expr = !expr; debug (": returns %d\n", expr); diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 122ba7e171..7c4d950e96 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -123,6 +123,27 @@ static int ubi_info(int layout) return 0; } +static int ubi_check_volumename(const struct ubi_volume *vol, char *name) +{ + return strcmp(vol->name, name); +} + +static int ubi_check(char *name) +{ + int i; + + for (i = 0; i < (ubi->vtbl_slots + 1); i++) { + if (!ubi->volumes[i]) + continue; /* Empty record */ + + if (!ubi_check_volumename(ubi->volumes[i], name)) + return 0; + } + + return -EEXIST; +} + + static int verify_mkvol_req(const struct ubi_device *ubi, const struct ubi_mkvol_req *req) { @@ -558,6 +579,14 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ubi_info(layout); } + if (strcmp(argv[1], "check") == 0) { + if (argc > 2) + return ubi_check(argv[2]); + + printf("Error, no volume name passed\n"); + return 1; + } + if (strncmp(argv[1], "create", 6) == 0) { int dynamic = 1; /* default: dynamic volume */ @@ -663,6 +692,8 @@ U_BOOT_CMD( " header offset)\n" "ubi info [l[ayout]]" " - Display volume and ubi layout information\n" + "ubi check volumename" + " - check if volumename exists\n" "ubi create[vol] volume [size] [type]" " - create volume name with size\n" "ubi write[vol] address volume size" diff --git a/common/cmd_ubifs.c b/common/cmd_ubifs.c index d9af023d70..fdc8bfe46a 100644 --- a/common/cmd_ubifs.c +++ b/common/cmd_ubifs.c @@ -21,15 +21,6 @@ static int ubifs_initialized; static int ubifs_mounted; -extern struct super_block *ubifs_sb; - -/* Prototypes */ -int ubifs_init(void); -int ubifs_mount(char *vol_name); -void ubifs_umount(struct ubifs_info *c); -int ubifs_ls(char *dir_name); -int ubifs_load(char *filename, u32 addr, u32 size); - int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *vol_name; diff --git a/common/command.c b/common/command.c index 597ab4cb4d..746b7e3f0e 100644 --- a/common/command.c +++ b/common/command.c @@ -421,6 +421,10 @@ int cmd_get_data_size(char* arg, int default_size) return 2; case 'l': return 4; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + case 'q': + return 8; +#endif case 's': return -2; default: @@ -538,3 +542,13 @@ enum command_ret_t cmd_process(int flag, int argc, char * const argv[], rc = cmd_usage(cmdtp); return rc; } + +int cmd_process_error(cmd_tbl_t *cmdtp, int err) +{ + if (err) { + printf("Command '%s' failed: Error %d\n", cmdtp->name, err); + return 1; + } + + return 0; +} diff --git a/common/cros_ec.c b/common/cros_ec.c new file mode 100644 index 0000000000..b8ce1b581a --- /dev/null +++ b/common/cros_ec.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + */ + +#include +#include +DECLARE_GLOBAL_DATA_PTR; + +struct local_info { + struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ + int cros_ec_err; /* Error for cros_ec, 0 if ok */ +}; + +static struct local_info local; + +struct cros_ec_dev *board_get_cros_ec_dev(void) +{ + return local.cros_ec_dev; +} + +static int board_init_cros_ec_devices(const void *blob) +{ + local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); + if (local.cros_ec_err) + return -1; /* Will report in board_late_init() */ + + return 0; +} + +int cros_ec_board_init(void) +{ + return board_init_cros_ec_devices(gd->fdt_blob); +} + +int cros_ec_get_error(void) +{ + return local.cros_ec_err; +} diff --git a/common/env_sf.c b/common/env_sf.c index 9f806fb090..be270f21bc 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -299,13 +299,16 @@ int saveenv(void) void env_relocate_spec(void) { - char buf[CONFIG_ENV_SIZE]; int ret; + char *buf = NULL; + buf = (char *)malloc(CONFIG_ENV_SIZE); env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); if (!env_flash) { set_default_env("!spi_flash_probe() failed"); + if (buf) + free(buf); return; } @@ -321,6 +324,8 @@ void env_relocate_spec(void) gd->env_valid = 1; out: spi_flash_free(env_flash); + if (buf) + free(buf); env_flash = NULL; } #endif diff --git a/common/hush.c b/common/hush.c index 3f3a79c508..df10267d64 100644 --- a/common/hush.c +++ b/common/hush.c @@ -221,6 +221,8 @@ struct child_prog { pid_t pid; /* 0 if exited */ #endif char **argv; /* program name and arguments */ + /* was quoted when parsed; copy of struct o_string.nonnull field */ + int *argv_nonnull; #ifdef __U_BOOT__ int argc; /* number of program arguments */ #endif @@ -467,7 +469,7 @@ static int process_command_subs(o_string *dest, struct p_context *ctx, struct in static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch); #endif static char *lookup_param(char *src); -static char *make_string(char **inp); +static char *make_string(char **inp, int *nonnull); static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input); #ifndef __U_BOOT__ static int parse_string(o_string *dest, struct p_context *ctx, const char *src); @@ -1613,7 +1615,8 @@ static int run_pipe_real(struct pipe *pi) if (child->sp) { char * str = NULL; - str = make_string((child->argv + i)); + str = make_string(child->argv + i, + child->argv_nonnull + i); parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); free(str); return last_return_code; @@ -1940,7 +1943,8 @@ static int free_pipe(struct pipe *pi, int indent) for (a = 0; a < child->argc; a++) { free(child->argv[a]); } - free(child->argv); + free(child->argv); + free(child->argv_nonnull); child->argc = 0; #endif child->argv=NULL; @@ -2470,8 +2474,14 @@ static int done_word(o_string *dest, struct p_context *ctx) argc = ++child->argc; child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); if (child->argv == NULL) return 1; + child->argv_nonnull = realloc(child->argv_nonnull, + (argc+1)*sizeof(*child->argv_nonnull)); + if (child->argv_nonnull == NULL) + return 1; child->argv[argc-1]=str; + child->argv_nonnull[argc-1] = dest->nonnull; child->argv[argc]=NULL; + child->argv_nonnull[argc] = 0; for (s = dest->data; s && *s; s++,str++) { if (*s == '\\') s++; *str = *s; @@ -2537,6 +2547,7 @@ static int done_command(struct p_context *ctx) prog->redirects = NULL; #endif prog->argv = NULL; + prog->argv_nonnull = NULL; #ifndef __U_BOOT__ prog->is_stopped = 0; #endif @@ -3585,8 +3596,12 @@ static char **make_list_in(char **inp, char *name) return list; } -/* Make new string for parser */ -static char * make_string(char ** inp) +/* + * Make new string for parser + * inp - array of argument strings to flatten + * nonnull - indicates argument was quoted when originally parsed + */ +static char *make_string(char **inp, int *nonnull) { char *p; char *str = NULL; @@ -3600,13 +3615,17 @@ static char * make_string(char ** inp) noeval = 1; for (n = 0; inp[n]; n++) { p = insert_var_value_sub(inp[n], noeval); - str = xrealloc(str, (len + strlen(p))); + str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); if (n) { strcat(str, " "); } else { *str = '\0'; } + if (nonnull[n]) + strcat(str, "'"); strcat(str, p); + if (nonnull[n]) + strcat(str, "'"); len = strlen(str) + 3; if (p != inp[n]) free(p); } diff --git a/common/image-fdt.c b/common/image-fdt.c index 6f9ce7d37c..a54a919a5b 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -463,7 +463,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, return -1; } arch_fixup_memory_node(blob); - if (IMAAGE_OF_BOARD_SETUP) + if (IMAGE_OF_BOARD_SETUP) ft_board_setup(blob, gd->bd); fdt_fixup_ethernet(blob); diff --git a/common/image-fit.c b/common/image-fit.c index cf4b67e3e8..b94a3fe86d 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1500,7 +1500,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, } bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK); if (fit_uname) { - /* get ramdisk component image node offset */ + /* get FIT component image node offset */ bootstage_mark(bootstage_id + BOOTSTAGE_SUB_UNIT_NAME); noffset = fit_image_get_node(fit, fit_uname); } else { diff --git a/common/image.c b/common/image.c index ae95c3f18a..9c6bec5b76 100644 --- a/common/image.c +++ b/common/image.c @@ -82,6 +82,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, { IH_ARCH_ARM64, "arm64", "AArch64", }, + { IH_ARCH_ARC, "arc", "ARC", }, { -1, "", "", }, }; diff --git a/common/lcd.c b/common/lcd.c index 56bf067fb5..19b86b7c55 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -26,8 +26,10 @@ #endif #include #include - +#include #include +#include +#include #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) @@ -63,6 +65,10 @@ # endif #endif +#ifdef CONFIG_SANDBOX +#include +#endif + #ifndef CONFIG_LCD_ALIGNMENT #define CONFIG_LCD_ALIGNMENT PAGE_SIZE #endif @@ -144,6 +150,13 @@ void lcd_sync(void) if (lcd_flush_dcache) flush_dcache_range((u32)lcd_base, (u32)(lcd_base + lcd_get_size(&line_length))); +#elif defined(CONFIG_SANDBOX) && defined(CONFIG_VIDEO_SANDBOX_SDL) + static ulong last_sync; + + if (get_timer(last_sync) > 10) { + sandbox_sdl_sync(lcd_base); + last_sync = get_timer(0); + } #endif } @@ -403,7 +416,7 @@ int drv_lcd_init(void) struct stdio_dev lcddev; int rc; - lcd_base = (void *) gd->fb_base; + lcd_base = map_sysmem(gd->fb_base, 0); lcd_init(lcd_base); /* LCD initialization */ @@ -494,8 +507,8 @@ static int lcd_init(void *lcdbase) * by setting up gd->fb_base. Check for this condition and fixup * 'lcd_base' address. */ - if ((unsigned long)lcdbase != gd->fb_base) - lcd_base = (void *)gd->fb_base; + if (map_to_sysmem(lcdbase) != gd->fb_base) + lcd_base = map_sysmem(gd->fb_base, 0); debug("[LCD] Using LCD frambuffer at %p\n", lcd_base); @@ -777,9 +790,9 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, int x, y; int decode = 1; - width = le32_to_cpu(bmp->header.width); - height = le32_to_cpu(bmp->header.height); - bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); + width = get_unaligned_le32(&bmp->header.width); + height = get_unaligned_le32(&bmp->header.height); + bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset); x = 0; y = height - 1; @@ -886,7 +899,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) ushort *cmap_base = NULL; ushort i, j; uchar *fb; - bmp_image_t *bmp=(bmp_image_t *)bmp_image; + bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0); uchar *bmap; ushort padded_width; unsigned long width, height, byte_width; @@ -900,9 +913,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - width = le32_to_cpu(bmp->header.width); - height = le32_to_cpu(bmp->header.height); - bmp_bpix = le16_to_cpu(bmp->header.bit_count); + width = get_unaligned_le32(&bmp->header.width); + height = get_unaligned_le32(&bmp->header.height); + bmp_bpix = get_unaligned_le16(&bmp->header.bit_count); + colors = 1 << bmp_bpix; bpix = NBITS(panel_info.vl_bpix); @@ -917,9 +931,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) /* We support displaying 8bpp BMPs on 16bpp LCDs */ if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", - bpix, - le16_to_cpu(bmp->header.bit_count)); - + bpix, get_unaligned_le16(&bmp->header.bit_count)); return 1; } @@ -956,7 +968,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } } #endif - /* * BMP format for Monochrome assumes that the state of a * pixel is described on a per Bit basis, not per Byte. @@ -987,15 +998,16 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) if ((y + height) > panel_info.vl_row) height = panel_info.vl_row - y; - bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); - fb = (uchar *) (lcd_base + + bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset); + fb = (uchar *)(lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); switch (bmp_bpix) { case 1: /* pass through */ case 8: #ifdef CONFIG_LCD_BMP_RLE8 - if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) { + u32 compression = get_unaligned_le32(&bmp->header.compression); + if (compression == BMP_BI_RLE8) { if (bpix != 16) { /* TODO implement render code for bpix != 16 */ printf("Error: only support 16 bpix"); diff --git a/common/memsize.c b/common/memsize.c index 73b92c8a00..589400d3b1 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -5,7 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include + +DECLARE_GLOBAL_DATA_PTR; + #ifdef __PPC__ /* * At least on G2 PowerPC cores, sequential accesses to non-existent @@ -76,3 +79,14 @@ long get_ram_size(long *base, long maxsize) return (maxsize); } + +phys_size_t __weak get_effective_memsize(void) +{ +#ifndef CONFIG_VERY_BIG_RAM + return gd->ram_size; +#else + /* limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +#endif +} diff --git a/common/spl/Makefile b/common/spl/Makefile index 5c0637b750..64569c2cc6 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -16,4 +16,7 @@ obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o +obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o +obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o endif diff --git a/common/spl/spl.c b/common/spl/spl.c index da31457d5f..774fdad252 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -204,6 +204,16 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case BOOT_DEVICE_USBETH: spl_net_load_image("usb_ether"); break; +#endif +#ifdef CONFIG_SPL_USB_SUPPORT + case BOOT_DEVICE_USB: + spl_usb_load_image(); + break; +#endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case BOOT_DEVICE_SATA: + spl_sata_load_image(); + break; #endif default: debug("SPL: Un-supported Boot Device\n"); diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c new file mode 100644 index 0000000000..1e532d5963 --- /dev/null +++ b/common/spl/spl_fat.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * FAT Image Functions copied from spl_mmc.c + */ + +#include +#include +#include +#include +#include + +static int fat_registered; + +#ifdef CONFIG_SPL_FAT_SUPPORT +static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition) +{ + int err = 0; + + if (fat_registered) + return err; + + err = fat_register_device(block_dev, partition); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: fat register err - %d\n", __func__, err); +#endif + hang(); + } + + fat_registered = 1; + + return err; +} + +int spl_load_image_fat(block_dev_desc_t *block_dev, + int partition, + const char *filename) +{ + int err; + struct image_header *header; + + err = spl_register_fat_device(block_dev, partition); + if (err) + goto end; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = file_fat_read(filename, header, sizeof(struct image_header)); + if (err <= 0) + goto end; + + spl_parse_image_header(header); + + err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); + +end: +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + if (err <= 0) + printf("%s: error reading image %s, err - %d\n", + __func__, filename, err); +#endif + + return (err <= 0); +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition) +{ + int err; + + err = spl_register_fat_device(block_dev, partition); + if (err) + return err; + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME, + (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); + if (err <= 0) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: error reading image %s, err - %d\n", + __func__, CONFIG_SPL_FAT_LOAD_ARGS_NAME, err); +#endif + return -1; + } + + return spl_load_image_fat(block_dev, partition, + CONFIG_SPL_FAT_LOAD_KERNEL_NAME); +} +#endif +#endif diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index e18ee64889..edbdd03c0d 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -10,9 +10,9 @@ #include #include #include -#include #include #include +#include #include #include @@ -100,54 +100,6 @@ static int mmc_load_fpga_image_fat(struct mmc *mmc) } #endif -#ifdef CONFIG_SPL_FAT_SUPPORT -static int mmc_load_image_fat(struct mmc *mmc, const char *filename) -{ - int err; - struct image_header *header; - - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - - sizeof(struct image_header)); - - err = file_fat_read(filename, header, sizeof(struct image_header)); - if (err <= 0) - goto end; - - spl_parse_image_header(header); - - err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); - -end: -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - if (err <= 0) - printf("spl: error reading image %s, err - %d\n", - filename, err); -#endif - - return (err <= 0); -} - -#ifdef CONFIG_SPL_OS_BOOT -static int mmc_load_image_fat_os(struct mmc *mmc) -{ - int err; - - err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME, - (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); - if (err <= 0) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: error reading image %s, err - %d\n", - CONFIG_SPL_FAT_LOAD_ARGS_NAME, err); -#endif - return -1; - } - - return mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_KERNEL_NAME); -} -#endif - -#endif - void spl_mmc_load_image(void) { struct mmc *mmc; @@ -172,34 +124,54 @@ void spl_mmc_load_image(void) hang(); } - boot_mode = spl_boot_mode(); + boot_mode = spl_boot_mode(); if (boot_mode == MMCSD_MODE_RAW) { debug("boot mode - RAW\n"); #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) #endif err = mmc_load_image_raw(mmc, - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #ifdef CONFIG_SPL_FAT_SUPPORT } else if (boot_mode == MMCSD_MODE_FAT) { debug("boot mode - FAT\n"); - err = fat_register_device(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: fat register err - %d\n", err); -#endif - hang(); - } #ifdef CONFIG_SPL_FPGA_SUPPORT mmc_load_fpga_image_fat(mmc); #endif #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || mmc_load_image_fat_os(mmc)) + if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev, + CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION)) #endif - err = mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + err = spl_load_image_fat(&mmc->block_dev, + CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION, + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); +#endif +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + + if (mmc_switch_part(0, part)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("MMC partition switch failed\n"); +#endif + hang(); + } + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) +#endif + err = mmc_load_image_raw(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif } else { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c new file mode 100644 index 0000000000..2e7adca0ca --- /dev/null +++ b/common/spl/spl_sata.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2013 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_usb.c + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_sata_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: sata init failed: err - %d\n", err); +#endif + hang(); + } else { + /* try to recognize storage devices immediately */ + stor_dev = scsi_get_dev(0); + } + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION, + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + if (err) { + puts("Error loading sata device\n"); + hang(); + } +} diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c new file mode 100644 index 0000000000..53a9043795 --- /dev/null +++ b/common/spl/spl_usb.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_mmc.c + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_STORAGE +static int usb_stor_curr_dev = -1; /* current device */ +#endif + +void spl_usb_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + usb_stop(); + err = usb_init(); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: usb init failed: err - %d\n", __func__, err); +#endif + hang(); + } + +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + usb_stor_curr_dev = usb_stor_scan(1); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); +#endif + + debug("boot mode - FAT\n"); + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION, + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + + if (err) { + puts("Error loading USB device\n"); + hang(); + } +} diff --git a/config.mk b/config.mk index b824bb3469..05864aabb5 100644 --- a/config.mk +++ b/config.mk @@ -6,381 +6,59 @@ # ######################################################################### -# Set shell to bash if possible, otherwise fall back to sh -SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi; fi) - -export SHELL - -ifeq ($(CURDIR),$(SRCTREE)) -dir := -else -dir := $(subst $(SRCTREE)/,,$(CURDIR)) -endif - -ifneq ($(OBJTREE),$(SRCTREE)) -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) -else -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) -endif -else -obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) -endif -src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) - -$(shell mkdir -p $(obj)) -else -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) -else -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) - -endif -$(shell mkdir -p $(obj)) -else -obj := -endif -src := -endif - -# clean the slate ... -PLATFORM_RELFLAGS = -PLATFORM_CPPFLAGS = -PLATFORM_LDFLAGS = - +# This file is included from ./Makefile and spl/Makefile. +# Clean the state to avoid the same flags added twice. +# +# (Tegra needs different flags for SPL. +# That's the reason why this file must be included from spl/Makefile too. +# If we did not have Tegra SoCs, build system would be much simpler...) +PLATFORM_RELFLAGS := +PLATFORM_CPPFLAGS := +PLATFORM_LDFLAGS := +LDFLAGS := +LDFLAGS_FINAL := +OBJCOPYFLAGS := ######################################################################### -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \ - $(HOSTCPPFLAGS) -HOSTSTRIP = strip - -# -# Mac OS X / Darwin's C preprocessor is Apple specific. It -# generates numerous errors and warnings. We want to bypass it -# and use GNU C's cpp. To do this we pass the -traditional-cpp -# option to the compiler. Note that the -traditional-cpp flag -# DOES NOT have the same semantics as GNU C's flag, all it does -# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. -# -# Apple's linker is similar, thanks to the new 2 stage linking -# multiple symbol definitions are treated as errors, hence the -# -multiply_defined suppress option to turn off this error. -# - -ifeq ($(HOSTOS),darwin) -# get major and minor product version (e.g. '10' and '6' for Snow Leopard) -DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') -DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') - -os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ - $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) - -# Snow Leopards build environment has no longer restrictions as described above -HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") -HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") -HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") -else -HOSTCC = gcc -endif - -ifeq ($(HOSTOS),cygwin) -HOSTCFLAGS += -ansi -endif - -# We build some files with extra pedantic flags to try to minimize things -# that won't build on some weird host compiler -- though there are lots of -# exceptions for files that aren't complaint. - -HOSTCFLAGS_NOPED = $(filter-out -pedantic,$(HOSTCFLAGS)) -HOSTCFLAGS += -pedantic - -######################################################################### -# -# Option checker, gcc version (courtesy linux kernel) to ensure -# only supported compiler options are used -# -CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk -CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o - --include $(CC_OPTIONS_CACHE_FILE) - -cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \ - if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \ - > /dev/null 2>&1; then \ - echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \ - echo "$(1)"; fi) - -ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y) -cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2)) -else -cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\ - $(if $(call cc-option-sys,$1),$1,$2))) -endif - -# cc-version -# Usage gcc-ver := $(call cc-version) -cc-version = $(shell $(SHELL) $(SRCTREE)/scripts/gcc-version.sh $(CC)) -binutils-version = $(shell $(SHELL) $(SRCTREE)/scripts/binutils-version.sh $(AS)) -dtc-version = $(shell $(SHELL) $(SRCTREE)/scripts/dtc-version.sh $(DTC)) - -# -# Include the make variables (CC, etc...) -# -AS = $(CROSS_COMPILE)as - -# Always use GNU ld -LD = $(shell if $(CROSS_COMPILE)ld.bfd -v > /dev/null 2>&1; \ - then echo "$(CROSS_COMPILE)ld.bfd"; else echo "$(CROSS_COMPILE)ld"; fi;) - -CC = $(CROSS_COMPILE)gcc -CPP = $(CC) -E -AR = $(CROSS_COMPILE)ar -NM = $(CROSS_COMPILE)nm -LDR = $(CROSS_COMPILE)ldr -STRIP = $(CROSS_COMPILE)strip -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -RANLIB = $(CROSS_COMPILE)RANLIB -DTC = dtc -CHECK = sparse - -######################################################################### - -# Load generated board configuration -ifeq ($(CONFIG_TPL_BUILD),y) -# Include TPL autoconf -sinclude $(OBJTREE)/include/tpl-autoconf.mk -else -ifeq ($(CONFIG_SPL_BUILD),y) -# Include SPL autoconf -sinclude $(OBJTREE)/include/spl-autoconf.mk -else -# Include normal autoconf -sinclude $(OBJTREE)/include/autoconf.mk -endif -endif -sinclude $(OBJTREE)/include/config.mk - # Some architecture config.mk files need to know what CPUDIR is set to, # so calculate CPUDIR before including ARCH/SOC/CPU config.mk files. # Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains # CPU-specific code. CPUDIR=arch/$(ARCH)/cpu/$(CPU) -ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) +ifneq ($(srctree)/$(CPUDIR),$(wildcard $(srctree)/$(CPUDIR))) CPUDIR=arch/$(ARCH)/cpu endif -sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules -sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules +sinclude $(srctree)/arch/$(ARCH)/config.mk # include architecture dependend rules +sinclude $(srctree)/$(CPUDIR)/config.mk # include CPU specific rules ifdef SOC -sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules +sinclude $(srctree)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules endif +ifneq ($(BOARD),) ifdef VENDOR BOARDDIR = $(VENDOR)/$(BOARD) else BOARDDIR = $(BOARD) endif +endif ifdef BOARD -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +sinclude $(srctree)/board/$(BOARDDIR)/config.mk # include board specific rules endif ######################################################################### -# We don't actually use $(ARFLAGS) anywhere anymore, so catch people -# who are porting old code to latest mainline but not updating $(AR). -ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR) -RELFLAGS= $(PLATFORM_RELFLAGS) -DBGFLAGS= -g # -DDEBUG -OPTFLAGS= -Os #-fomit-frame-pointer +RELFLAGS := $(PLATFORM_RELFLAGS) -OBJCFLAGS += --gap-fill=0xff +OBJCOPYFLAGS += --gap-fill=0xff -gccincdir := $(shell $(CC) -print-file-name=include) - -CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ - -# Enable garbage collection of un-used sections for SPL -ifeq ($(CONFIG_SPL_BUILD),y) -CPPFLAGS += -ffunction-sections -fdata-sections -LDFLAGS_FINAL += --gc-sections -endif - -# TODO(sjg@chromium.org): Is this correct on Mac OS? - -# MXSImage needs LibSSL -ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) -HOSTLIBS += -lssl -lcrypto -# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register -# the mxsimage support within tools/mxsimage.c . -HOSTCFLAGS += -DCONFIG_MXS -endif - -ifdef CONFIG_FIT_SIGNATURE -HOSTLIBS += -lssl -lcrypto - -# This affects include/image.h, but including the board config file -# is tricky, so manually define this options here. -HOSTCFLAGS += -DCONFIG_FIT_SIGNATURE -endif - -ifneq ($(CONFIG_SYS_TEXT_BASE),) -CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -endif - -ifeq ($(CONFIG_SPL_BUILD),y) -CPPFLAGS += -DCONFIG_SPL_BUILD -ifeq ($(CONFIG_TPL_BUILD),y) -CPPFLAGS += -DCONFIG_TPL_BUILD -endif -endif - -# Does this architecture support generic board init? -ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) -ifneq ($(CONFIG_SYS_GENERIC_BOARD),) -CHECK_GENERIC_BOARD = $(error Your architecture does not support generic board. \ -Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) -endif -endif - -# Sandbox needs the base flags and includes, so keep them around -BASE_CPPFLAGS := $(CPPFLAGS) - -ifneq ($(OBJTREE),$(SRCTREE)) -BASE_INCLUDE_DIRS := $(OBJTREE)/include -endif - -BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include - -CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS)) -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) - -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes - -ifdef BUILD_TAG -CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' -endif - -CFLAGS_SSP := $(call cc-option,-fno-stack-protector) -CFLAGS += $(CFLAGS_SSP) -# Some toolchains enable security related warning flags by default, -# but they don't make much sense in the u-boot world, so disable them. -CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \ - $(call cc-option,-Wno-format-security) -CFLAGS += $(CFLAGS_WARN) - -# Report stack usage if supported -CFLAGS_STACK := $(call cc-option,-fstack-usage) -CFLAGS += $(CFLAGS_STACK) - -BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%)) - -ifeq ($(findstring examples/,$(BCURDIR)),) -ifeq ($(CONFIG_SPL_BUILD),) -ifdef FTRACE -CFLAGS += -finstrument-functions -DFTRACE -endif -endif -endif - -# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g -# option to the assembler. -AFLAGS_DEBUG := - -# turn jbsr into jsr for m68k -ifeq ($(ARCH),m68k) -ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) -AFLAGS_DEBUG := -Wa,-gstabs,-S -endif -endif - -AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) +PLATFORM_CPPFLAGS += $(RELFLAGS) +PLATFORM_CPPFLAGS += -pipe LDFLAGS += $(PLATFORM_LDFLAGS) LDFLAGS_FINAL += -Bstatic -LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) -ifneq ($(CONFIG_SYS_TEXT_BASE),) -LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) -endif - -LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) -ifneq ($(CONFIG_SPL_TEXT_BASE),) -LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) -endif - -# Linus' kernel sanity checking tool -CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ - -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) - -# Location of a usable BFD library, where we define "usable" as -# "built for ${HOST}, supports ${TARGET}". Sensible values are -# - When cross-compiling: the root of the cross-environment -# - Linux/ppc (native): /usr -# - NetBSD/ppc (native): you lose ... (must extract these from the -# binutils build directory, plus the native and U-Boot include -# files don't like each other) -# -# So far, this is used only by tools/gdb/Makefile. - -ifeq ($(HOSTOS),darwin) -BFD_ROOT_DIR = /usr/local/tools -else -ifeq ($(HOSTARCH),$(ARCH)) -# native -BFD_ROOT_DIR = /usr -else -#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 -#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 -BFD_ROOT_DIR = /opt/powerpc -endif -endif - -######################################################################### - -export HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \ - AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE -export CONFIG_SYS_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS - -######################################################################### - -# Allow boards to use custom optimize flags on a per dir/file basis -ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) -ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) -EXTRA_CPPFLAGS = $(CPPFLAGS_$(BCURDIR)/$(@F)) $(CPPFLAGS_$(BCURDIR)) -ALL_CFLAGS += $(EXTRA_CPPFLAGS) - -# The _DEP version uses the $< file target (for dependency generation) -# See rules.mk -EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \ - $(CPPFLAGS_$(BCURDIR)) -$(obj)%.s: %.S - $(CPP) $(ALL_AFLAGS) -o $@ $< -$(obj)%.o: %.S - $(CC) $(ALL_AFLAGS) -o $@ $< -c -$(obj)%.o: %.c -ifneq ($(CHECKSRC),0) - $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $< -endif - $(CC) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.i: %.c - $(CPP) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.s: %.c - $(CC) $(ALL_CFLAGS) -o $@ $< -c -S - -######################################################################### - -# If the list of objects to link is empty, just create an empty built-in.o -cmd_link_o_target = $(if $(strip $1),\ - $(LD) $(LDFLAGS) -r -o $@ $1,\ - rm -f $@; $(AR) rcs $@ ) - -######################################################################### +export PLATFORM_CPPFLAGS +export RELFLAGS +export LDFLAGS_FINAL +export CONFIG_STANDALONE_LOAD_ADDR diff --git a/disk/Makefile b/disk/Makefile index 48abec8328..6970cecc71 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DET_DEBUG -DDEBUG +#ccflags-y += -DET_DEBUG -DDEBUG obj-$(CONFIG_PARTITIONS) += part.o obj-$(CONFIG_MAC_PARTITION) += part_mac.o diff --git a/disk/part.c b/disk/part.c index 6941033d8d..b8c6aac801 100644 --- a/disk/part.c +++ b/disk/part.c @@ -452,23 +452,6 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, int part; disk_partition_t tmpinfo; - /* - * For now, we have a special case for sandbox, since there is no - * real block device support. - */ - if (0 == strcmp(ifname, "host")) { - *dev_desc = NULL; - info->start = info->size = info->blksz = 0; - info->bootable = 0; - strcpy((char *)info->type, BOOT_PART_TYPE); - strcpy((char *)info->name, "Sandbox host"); -#ifdef CONFIG_PARTITION_UUIDS - info->uuid[0] = 0; -#endif - - return 0; - } - /* If no dev_part_str, use bootdevice environment variable */ if (!dev_part_str || !strlen(dev_part_str) || !strcmp(dev_part_str, "-")) diff --git a/disk/part_efi.c b/disk/part_efi.c index 9c33ae7a31..216a2920c2 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -63,26 +63,6 @@ static char *print_efiname(gpt_entry *pte) return name; } -static void uuid_string(unsigned char *uuid, char *str) -{ - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, - 12, 13, 14, 15}; - int i; - - for (i = 0; i < 16; i++) { - sprintf(str, "%02x", uuid[le[i]]); - str += 2; - switch (i) { - case 3: - case 5: - case 7: - case 9: - *str++ = '-'; - break; - } - } -} - static efi_guid_t system_guid = PARTITION_SYSTEM_GUID; static inline int is_bootable(gpt_entry *p) @@ -103,6 +83,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) gpt_entry *gpt_pte = NULL; int i = 0; char uuid[37]; + unsigned char *uuid_bin; if (!dev_desc) { printf("%s: Invalid Argument(s)\n", __func__); @@ -119,8 +100,8 @@ void print_part_efi(block_dev_desc_t * dev_desc) printf("Part\tStart LBA\tEnd LBA\t\tName\n"); printf("\tAttributes\n"); - printf("\tType UUID\n"); - printf("\tPartition UUID\n"); + printf("\tType GUID\n"); + printf("\tPartition GUID\n"); for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { /* Stop at the first non valid PTE */ @@ -132,10 +113,12 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_cpu(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw); - uuid_string(gpt_pte[i].partition_type_guid.b, uuid); + uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); printf("\ttype:\t%s\n", uuid); - uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); - printf("\tuuid:\t%s\n", uuid); + uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); + printf("\tguid:\t%s\n", uuid); } /* Remember to free pte */ @@ -182,7 +165,8 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->type, "U-Boot"); info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS - uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); + uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid, + UUID_STR_FORMAT_GUID); #endif debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__, @@ -213,10 +197,10 @@ int test_part_efi(block_dev_desc_t * dev_desc) */ static int set_protective_mbr(block_dev_desc_t *dev_desc) { - legacy_mbr *p_mbr; - /* Setup the Protective MBR */ - p_mbr = calloc(1, sizeof(p_mbr)); + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1); + memset(p_mbr, 0, sizeof(*p_mbr)); + if (p_mbr == NULL) { printf("%s: calloc failed!\n", __func__); return -1; @@ -231,65 +215,9 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) { printf("** Can't write to device %d **\n", dev_desc->dev); - free(p_mbr); return -1; } - free(p_mbr); - return 0; -} - -/** - * string_uuid(); Convert UUID stored as string to bytes - * - * @param uuid - UUID represented as string - * @param dst - GUID buffer - * - * @return return 0 on successful conversion - */ -static int string_uuid(char *uuid, u8 *dst) -{ - efi_guid_t guid; - u16 b, c, d; - u64 e; - u32 a; - u8 *p; - u8 i; - - const u8 uuid_str_len = 36; - - /* The UUID is written in text: */ - /* 1 9 14 19 24 */ - /* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */ - - debug("%s: uuid: %s\n", __func__, uuid); - - if (strlen(uuid) != uuid_str_len) - return -1; - - for (i = 0; i < uuid_str_len; i++) { - if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) { - if (uuid[i] != '-') - return -1; - } else { - if (!isxdigit(uuid[i])) - return -1; - } - } - - a = (u32)simple_strtoul(uuid, NULL, 16); - b = (u16)simple_strtoul(uuid + 9, NULL, 16); - c = (u16)simple_strtoul(uuid + 14, NULL, 16); - d = (u16)simple_strtoul(uuid + 19, NULL, 16); - e = (u64)simple_strtoull(uuid + 24, NULL, 16); - - p = (u8 *) &e; - guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF, - *(p + 5), *(p + 4), *(p + 3), - *(p + 2), *(p + 1) , *p); - - memcpy(dst, guid.b, sizeof(efi_guid_t)); - return 0; } @@ -360,6 +288,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, size_t efiname_len, dosname_len; #ifdef CONFIG_PARTITION_UUIDS char *str_uuid; + unsigned char *bin_uuid; #endif for (i = 0; i < parts; i++) { @@ -393,7 +322,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, #ifdef CONFIG_PARTITION_UUIDS str_uuid = partitions[i].uuid; - if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) { + bin_uuid = gpt_e[i].unique_partition_guid.b; + + if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid); return -1; @@ -440,7 +371,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_h->header_crc32 = 0; gpt_h->partition_entry_array_crc32 = 0; - if (string_uuid(str_guid, gpt_h->disk_guid.b)) + if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b, UUID_STR_FORMAT_GUID)) return -1; return 0; diff --git a/doc/DocBook/.gitignore b/doc/DocBook/.gitignore index 90c1b112a1..720f245ceb 100644 --- a/doc/DocBook/.gitignore +++ b/doc/DocBook/.gitignore @@ -1,4 +1,3 @@ -*/ *.xml *.ps *.pdf diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 29b79d7cd1..9b4a9b6762 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -1,14 +1,12 @@ ### # This makefile is used to generate the kernel documentation, # primarily based on in-line comments in various source files. -# See doc/kernel-doc-nano-HOWTO.txt for instruction in how +# See Documentation/kernel-doc-nano-HOWTO.txt for instruction in how # to document the SRC - and how to read it. # To add a new book the only step required is to add the book to the # list of DOCBOOKS. -include $(TOPDIR)/config.mk - -DOCBOOKS := fs.xml linker_lists.xml stdio.xml +DOCBOOKS := linker_lists.xml stdio.xml ### # The build process is as follows (targets): @@ -26,9 +24,9 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs -BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS)) +BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) xmldocs: $(BOOKS) sgmldocs: xmldocs @@ -53,10 +51,10 @@ installmandocs: mandocs ### #External programs used -KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc -DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc +KERNELDOC = $(srctree)/scripts/kernel-doc +DOCPROC = $(objtree)/scripts/docproc -XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl +XMLTOFLAGS = -m $(srctree)/doc/DocBook/stylesheet.xsl XMLTOFLAGS += --skip-validation ### @@ -66,28 +64,36 @@ XMLTOFLAGS += --skip-validation # appropriate parameters. # The following rules are used to generate the .xml documentation # required to generate the final targets. (ps, pdf, html). -%.xml: %.tmpl - $(DOCPROC) doc $< >$@ +quiet_cmd_docproc = DOCPROC $@ + cmd_docproc = SRCTREE=$(srctree)/ $(DOCPROC) doc $< >$@ +define rule_docproc + set -e; \ + $(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))';) \ + $(cmd_$(1)); \ + ( \ + echo 'cmd_$@ := $(cmd_$(1))'; \ + echo $@: `SRCTREE=$(srctree) $(DOCPROC) depend $<`; \ + ) > $(dir $@).$(notdir $@).cmd +endef -ifeq ($@, "cleandocs") -sinclude $(obj).depend -$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS)) - rm -f $(obj).depend ; \ - touch $(obj).depend ; \ - for file in $^ ; do \ - xmlfile=`echo "$${file}" | \ - sed "s/tmpl$$/xml/"` ; \ - echo -n "$${xmlfile}: ">> $(obj).depend ; \ - $(DOCPROC) depend $$file >> $(obj).depend ; \ - echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \ - $(obj).depend ; \ - done +%.xml: %.tmpl FORCE + $(call if_changed_rule,docproc) + +### +#Read in all saved dependency files +cmd_files := $(wildcard $(foreach f,$(BOOKS),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + include $(cmd_files) endif ### # Changes in kernel-doc force a rebuild of all documentation $(BOOKS): $(KERNELDOC) +# Tell kbuild to always build the programs +always := $(hostprogs-y) + notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \ exit 1 db2xtemplate = db2TYPE -o $(dir $@) $< @@ -113,37 +119,34 @@ endif quiet_cmd_db2ps = PS $@ cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template)) %.ps : %.xml - $(call cmd_db2ps) + $(call cmd,db2ps) quiet_cmd_db2pdf = PDF $@ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template)) %.pdf : %.xml - $(call cmd_db2pdf) + $(call cmd,db2pdf) index = index.html -main_idx = $(index) +main_idx = doc/DocBook/$(index) build_main_index = rm -rf $(main_idx); \ echo '

U-Boot Bootloader HTML Documentation

' >> $(main_idx) && \ - echo '

U-Boot Version: $(U_BOOT_VERSION)

' >> $(main_idx) && \ + echo '

U-Boot Version: $(UBOOTVERSION)

' >> $(main_idx) && \ cat $(HTML) >> $(main_idx) -# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html -# docs instead of xhtml with xmlto. -# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338 quiet_cmd_db2html = HTML $@ - cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \ + cmd_db2html = xmlto xhtml $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \ echo ' \ - $(patsubst %.html,%,$(notdir $@))

' > $@ + $(patsubst %.html,%,$(notdir $@))

' > $@ %.html: %.xml @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) @rm -rf $@ $(patsubst %.html,%,$@) - $(call cmd_db2html) + $(call cmd,db2html) @if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \ - cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi + cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi quiet_cmd_db2man = MAN $@ cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi @@ -151,8 +154,8 @@ quiet_cmd_db2man = MAN $@ @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) - $(Q)mkdir -p $(obj)man - $(call cmd_db2man) + $(Q)mkdir -p $(obj)/man + $(call cmd,db2man) @touch $@ ### @@ -164,7 +167,7 @@ quiet_cmd_fig2eps = FIG2EPS $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2eps) + $(call cmd,fig2eps) quiet_cmd_fig2png = FIG2PNG $@ cmd_fig2png = fig2dev -Lpng $< $@ @@ -173,7 +176,7 @@ quiet_cmd_fig2png = FIG2PNG $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2png) + $(call cmd,fig2png) ### # Rule to convert a .c file to inline XML documentation @@ -219,9 +222,8 @@ clean-files := $(DOCBOOKS) \ clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man cleandocs: - @rm -f $(obj).depend - @$(Q)rm -f $(call objectify, $(clean-files)) - @$(Q)rm -rf $(call objectify, $(clean-dirs)) + $(Q)rm -f $(call objectify, $(clean-files)) + $(Q)rm -rf $(call objectify, $(clean-dirs)) # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable se we can use it in if_changed and friends. diff --git a/doc/DocBook/stylesheet.xsl b/doc/DocBook/stylesheet.xsl index 8adce568b6..85b2527519 100644 --- a/doc/DocBook/stylesheet.xsl +++ b/doc/DocBook/stylesheet.xsl @@ -7,5 +7,4 @@ 2 1 -../docbook.css diff --git a/doc/README.ARC b/doc/README.ARC new file mode 100644 index 0000000000..5f414fb2fa --- /dev/null +++ b/doc/README.ARC @@ -0,0 +1,27 @@ +Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs +that SoC designers can optimize for a wide range of uses, from deeply embedded +to high-performance host applications. + +More information on ARC cores avaialble here: +http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx + +Designers can differentiate their products by using patented configuration +technology to tailor each ARC processor instance to meet specific performance, +power and area requirements. + +The DesignWare ARC processors are also extendable, allowing designers to add +their own custom instructions that dramatically increase performance. + +Synopsys' ARC processors have been used by over 170 customers worldwide who +collectively ship more than 1 billion ARC-based chips annually. + +All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent +performance and code density for embedded and host SoC applications. + +The RISC microprocessors are synthesizable and can be implemented in any foundry +or process, and are supported by a complete suite of development tools. + +The ARC GNU toolchain with support for all ARC Processors can be downloaded +from here (available pre-built toolchains as well): + +https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases diff --git a/doc/README.SPL b/doc/README.SPL index 312a6a612e..57a39a489b 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -13,7 +13,7 @@ can be reused. No code duplication or symlinking is necessary anymore. How it works ------------ -There is a new directory TOPDIR/spl which contains only a Makefile. +There is a new directory $(srctree)/spl which contains only a Makefile. The object files are built separately for SPL and placed in this directory. The final binaries which are generated are u-boot-spl, u-boot-spl.bin and u-boot-spl.map. @@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o) CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o) +CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc) CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) diff --git a/doc/README.TPL b/doc/README.TPL index 1df03b958e..980debe777 100644 --- a/doc/README.TPL +++ b/doc/README.TPL @@ -19,7 +19,7 @@ board can be reused. No code duplication or symlinking is necessary anymore. How it works ------------ -There has been a directory TOPDIR/spl which contains only a Makefile. The +There has been a directory $(srctree)/spl which contains only a Makefile. The Makefile is shared by SPL and TPL. The object files are built separately for SPL/TPL and placed in the diff --git a/doc/README.arm-unaligned-accesses b/doc/README.arm-unaligned-accesses deleted file mode 100644 index c37d135852..0000000000 --- a/doc/README.arm-unaligned-accesses +++ /dev/null @@ -1,122 +0,0 @@ -If you are reading this because of a data abort: the following MIGHT -be relevant to your abort, if it was caused by an alignment violation. -In order to determine this, use the PC from the abort dump along with -an objdump -s -S of the u-boot ELF binary to locate the function where -the abort happened; then compare this function with the examples below. -If they match, then you've been hit with a compiler generated unaligned -access, and you should rewrite your code or add -mno-unaligned-access -to the command line of the offending file. - -Note that the PC shown in the abort message is relocated. In order to -be able to match it to an address in the ELF binary dump, you will need -to know the relocation offset. If your target defines CONFIG_CMD_BDI -and if you can get to the prompt and enter commands before the abort -happens, then command "bdinfo" will give you the offset. Otherwise you -will need to try a build with DEBUG set, which will display the offset, -or use a debugger and set a breakpoint at relocate_code() to see the -offset (passed as an argument). - -* - -Since U-Boot runs on a variety of hardware, some only able to perform -unaligned accesses with a strong penalty, some unable to perform them -at all, the policy regarding unaligned accesses is to not perform any, -unless absolutely necessary because of hardware or standards. - -Also, on hardware which permits it, the core is configured to throw -data abort exceptions on unaligned accesses in order to catch these -unallowed accesses as early as possible. - -Until version 4.7, the gcc default for performing unaligned accesses -(-mno-unaligned-access) is to emulate unaligned accesses using aligned -loads and stores plus shifts and masks. Emulated unaligned accesses -will not be caught by hardware. These accesses may be costly and may -be actually unnecessary. In order to catch these accesses and remove -or optimize them, option -munaligned-access is explicitly set for all -versions of gcc which support it. - -From gcc 4.7 onward starting at armv7 architectures, the default for -performing unaligned accesses is to use unaligned native loads and -stores (-munaligned-access), because the cost of unaligned accesses -has dropped on armv7 and beyond. This should not affect U-Boot's -policy of controlling unaligned accesses, however the compiler may -generate uncontrolled unaligned accesses on its own in at least one -known case: when declaring a local initialized char array, e.g. - -function foo() -{ - char buffer[] = "initial value"; -/* or */ - char buffer[] = { 'i', 'n', 'i', 't', 0 }; - ... -} - -Under -munaligned-accesses with optimizations on, this declaration -causes the compiler to generate native loads from the literal string -and native stores to the buffer, and the literal string alignment -cannot be controlled. If it is misaligned, then the core will throw -a data abort exception. - -Quite probably the same might happen for 16-bit array initializations -where the constant is aligned on a boundary which is a multiple of 2 -but not of 4: - -function foo() -{ - u16 buffer[] = { 1, 2, 3 }; - ... -} - -The long term solution to this issue is to add an option to gcc to -allow controlling the general alignment of data, including constant -initialization values. - -However this will only apply to the version of gcc which will have such -an option. For other versions, there are four workarounds: - -a) Enforce as a rule that array initializations as described above - are forbidden. This is generally not acceptable as they are valid, - and usual, C constructs. The only case where they could be rejected - is when they actually equate to a const char* declaration, i.e. the - array is initialized and never modified in the function's scope. - -b) Drop the requirement on unaligned accesses at least for ARMv7, - i.e. do not throw a data abort exception upon unaligned accesses. - But that will allow adding badly aligned code to U-Boot, only for - it to fail when re-used with a stricter target, possibly once the - bad code is already in mainline. - -c) Relax the -munaligned-access rule globally. This will prevent native - unaligned accesses of course, but that will also hide any bug caused - by a bad unaligned access, making it much harder to diagnose it. It - is actually what already happens when building ARM targets with a - pre-4.7 gcc, and it may actually already hide some bugs yet unseen - until the target gets compiled with -munaligned-access. - -d) Relax the -munaligned-access rule only for for files susceptible to - the local initialized array issue and for armv7 architectures and - beyond. This minimizes the quantity of code which can hide unwanted - misaligned accesses. - -The option retained is d). - -Considering that actual occurrences of the issue are rare (as of this -writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized -local char array which cannot actually be replaced with a const char*), -contributors should not be required to systematically try and detect -the issue in their patches. - -Detecting files susceptible to the issue can be automated through a -filter installed as a hook in .git which recognizes local char array -initializations. Automation should err on the false positive side, for -instance flagging non-local arrays as if they were local if they cannot -be told apart. - -In any case, detection shall not prevent committing the patch, but -shall pre-populate the commit message with a note to the effect that -this patch contains an initialized local char or 16-bit array and thus -should be protected from the gcc 4.7 issue. - -Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be -added to CFLAGS for the affected file(s), or if the array is a pseudo -const char*, it should be replaced by an actual one. diff --git a/doc/README.b4860qds b/doc/README.b4860qds index 48ece4b835..3da77d9f0f 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -227,17 +227,17 @@ Start Address End Address Description Size NOR Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB -0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB -0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB -0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB -0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB -0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB +0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB +0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB +0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB +0xED300000 0xEDEFFFFF rootfs (current bank) 12MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB 0xEC000000 0xEC01FFFF RCW (current bank) 128KB diff --git a/doc/README.commands b/doc/README.commands index 9eb367104f..afd5577b0a 100644 --- a/doc/README.commands +++ b/doc/README.commands @@ -28,7 +28,7 @@ these symbols when linking full U-Boot even though they are not referenced in the source code as such. If a new board is defined do not forget to define the command section -by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these +by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these 3 lines: .u_boot_list : { diff --git a/doc/README.designware_eth b/doc/README.designware_eth deleted file mode 100644 index 25ec6bd969..0000000000 --- a/doc/README.designware_eth +++ /dev/null @@ -1,25 +0,0 @@ -This driver supports Designware Ethernet Controller provided by Synopsis. - -The driver is enabled by CONFIG_DESIGNWARE_ETH. - -The driver has been developed and tested on SPEAr platforms. By default, the -MDIO interface works at 100/Full. #defining the below options in board -configuration file changes this behavior. - -Call an subroutine from respective board/.../board.c -designware_initialize(u32 id, ulong base_addr, u32 phy_addr); - -The various options suported by the driver are -1. CONFIG_DW_ALTDESCRIPTOR - Define this to use the Alternate/Enhanced Descriptor configurations. -1. CONFIG_DW_AUTONEG - Define this to autonegotiate with the host before proceeding with mac - level configuration. This obviates the definitions of CONFIG_DW_SPEED10M - and CONFIG_DW_DUPLEXHALF. -2. CONFIG_DW_SPEED10M - Define this to change the default behavior from 100Mbps to 10Mbps. -3. CONFIG_DW_DUPLEXHALF - Define this to change the default behavior from Full Duplex to Half. -4. CONFIG_DW_SEARCH_PHY - Define this to search the phy address. This would overwrite the value - passed as 3rd arg from designware_initialize routine. diff --git a/doc/README.gpt b/doc/README.gpt index 5c133f3321..f822894709 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -132,8 +132,8 @@ of the Primary. ---------------------- Offset Size Description - 0 16 B Partition type GUID - 16 16 B Unique partition GUID + 0 16 B Partition type GUID (Big Endian) + 16 16 B Unique partition GUID in (Big Endian) 32 8 B First LBA (Little Endian) 40 8 B Last LBA (inclusive) 48 8 B Attribute flags [+] @@ -160,6 +160,9 @@ To restore GUID partition table one needs to: Fields 'name', 'size' and 'uuid' are mandatory for every partition. The field 'start' is optional. + option: CONFIG_RANDOM_UUID + If any partition "UUID" no exists then it is randomly generated. + 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT' 2. From u-boot prompt type: @@ -168,11 +171,20 @@ To restore GUID partition table one needs to: Useful info: ============ -Two programs, namely: 'fdisk' and 'parted' are recommended to work with GPT -recovery. Parted is able to handle GUID partitions. Unfortunately the 'fdisk' -hasn't got such ability. +Two programs, namely: 'gdisk' and 'parted' are recommended to work with GPT +recovery. Both are able to handle GUID partitions. Please, pay attention at -l switch for parted. "uuid" program is recommended to generate UUID string. Moreover it can decode (-d switch) passed in UUID string. It can be used to generate partitions UUID passed to u-boot environment variables. +If optional CONFIG_RANDOM_UUID is defined then for any partition which environment +uuid is unset, uuid is randomly generated and stored in correspond environment +variable. + +note: +Each string block of UUID generated by program "uuid" is in big endian and it is +also stored in big endian in disk GPT. +Partitions layout can be printed by typing "mmc part". Note that each partition +GUID has different byte order than UUID generated before, this is because first +three blocks of GUID string are in Little Endian. diff --git a/doc/README.kwbimage b/doc/README.kwbimage index 8ed708c356..13f6f92f68 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -42,7 +42,7 @@ Board specific configuration file specifications: kwbimage.cfg. The name can be set as part of the full path to the file using CONFIG_SYS_KWD_CONFIG (probably in include/configs/.h). The path should look like: - $(SRCTREE)/$(CONFIG_BOARDDIR)/.cfg + $(CONFIG_BOARDDIR)/.cfg 2. This file can have empty lines and lines starting with "#" as first character to put comments 3. This file can have configuration command lines as mentioned below, diff --git a/doc/README.malta b/doc/README.malta index a495d02455..c8db8a0c39 100644 --- a/doc/README.malta +++ b/doc/README.malta @@ -9,7 +9,7 @@ How to flash using a MIPS Navigator Probe: - Within Navigator Console run the following commands: - source /path/to/u-boot/board/malta/flash-malta-boot.tcl + source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl reset flash-boot /path/to/u-boot/u-boot.bin diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2aed855993..7d670339dd 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,15 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -mx1ads arm arm920t - 2014-01-13 -mini2440 arm arm920t - 2014-01-13 Gabriel Huau +idmr m68k mcf52x2 - 2014-01-28 +M5271EVB m68k mcf52x2 - 2014-01-28 +dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen +actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen +actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen +actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen +actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen +mx1ads arm arm920t e570aca9 2014-01-13 +mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau omap730p2 arm arm926ejs 79c5c08d 2013-11-11 pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese diff --git a/doc/README.unaligned-memory-access.txt b/doc/README.unaligned-memory-access.txt new file mode 100644 index 0000000000..00529f5dac --- /dev/null +++ b/doc/README.unaligned-memory-access.txt @@ -0,0 +1,240 @@ +Editors note: This document is _heavily_ cribbed from the Linux Kernel, with +really only the section about "Alignment vs. Networking" removed. + +UNALIGNED MEMORY ACCESSES +========================= + +Linux runs on a wide variety of architectures which have varying behaviour +when it comes to memory access. This document presents some details about +unaligned accesses, why you need to write code that doesn't cause them, +and how to write such code! + + +The definition of an unaligned access +===================================== + +Unaligned memory accesses occur when you try to read N bytes of data starting +from an address that is not evenly divisible by N (i.e. addr % N != 0). +For example, reading 4 bytes of data from address 0x10004 is fine, but +reading 4 bytes of data from address 0x10005 would be an unaligned memory +access. + +The above may seem a little vague, as memory access can happen in different +ways. The context here is at the machine code level: certain instructions read +or write a number of bytes to or from memory (e.g. movb, movw, movl in x86 +assembly). As will become clear, it is relatively easy to spot C statements +which will compile to multiple-byte memory access instructions, namely when +dealing with types such as u16, u32 and u64. + + +Natural alignment +================= + +The rule mentioned above forms what we refer to as natural alignment: +When accessing N bytes of memory, the base memory address must be evenly +divisible by N, i.e. addr % N == 0. + +When writing code, assume the target architecture has natural alignment +requirements. + +In reality, only a few architectures require natural alignment on all sizes +of memory access. However, we must consider ALL supported architectures; +writing code that satisfies natural alignment requirements is the easiest way +to achieve full portability. + + +Why unaligned access is bad +=========================== + +The effects of performing an unaligned memory access vary from architecture +to architecture. It would be easy to write a whole document on the differences +here; a summary of the common scenarios is presented below: + + - Some architectures are able to perform unaligned memory accesses + transparently, but there is usually a significant performance cost. + - Some architectures raise processor exceptions when unaligned accesses + happen. The exception handler is able to correct the unaligned access, + at significant cost to performance. + - Some architectures raise processor exceptions when unaligned accesses + happen, but the exceptions do not contain enough information for the + unaligned access to be corrected. + - Some architectures are not capable of unaligned memory access, but will + silently perform a different memory access to the one that was requested, + resulting in a subtle code bug that is hard to detect! + +It should be obvious from the above that if your code causes unaligned +memory accesses to happen, your code will not work correctly on certain +platforms and will cause performance problems on others. + + +Code that does not cause unaligned access +========================================= + +At first, the concepts above may seem a little hard to relate to actual +coding practice. After all, you don't have a great deal of control over +memory addresses of certain variables, etc. + +Fortunately things are not too complex, as in most cases, the compiler +ensures that things will work for you. For example, take the following +structure: + + struct foo { + u16 field1; + u32 field2; + u8 field3; + }; + +Let us assume that an instance of the above structure resides in memory +starting at address 0x10000. With a basic level of understanding, it would +not be unreasonable to expect that accessing field2 would cause an unaligned +access. You'd be expecting field2 to be located at offset 2 bytes into the +structure, i.e. address 0x10002, but that address is not evenly divisible +by 4 (remember, we're reading a 4 byte value here). + +Fortunately, the compiler understands the alignment constraints, so in the +above case it would insert 2 bytes of padding in between field1 and field2. +Therefore, for standard structure types you can always rely on the compiler +to pad structures so that accesses to fields are suitably aligned (assuming +you do not cast the field to a type of different length). + +Similarly, you can also rely on the compiler to align variables and function +parameters to a naturally aligned scheme, based on the size of the type of +the variable. + +At this point, it should be clear that accessing a single byte (u8 or char) +will never cause an unaligned access, because all memory addresses are evenly +divisible by one. + +On a related topic, with the above considerations in mind you may observe +that you could reorder the fields in the structure in order to place fields +where padding would otherwise be inserted, and hence reduce the overall +resident memory size of structure instances. The optimal layout of the +above example is: + + struct foo { + u32 field2; + u16 field1; + u8 field3; + }; + +For a natural alignment scheme, the compiler would only have to add a single +byte of padding at the end of the structure. This padding is added in order +to satisfy alignment constraints for arrays of these structures. + +Another point worth mentioning is the use of __attribute__((packed)) on a +structure type. This GCC-specific attribute tells the compiler never to +insert any padding within structures, useful when you want to use a C struct +to represent some data that comes in a fixed arrangement 'off the wire'. + +You might be inclined to believe that usage of this attribute can easily +lead to unaligned accesses when accessing fields that do not satisfy +architectural alignment requirements. However, again, the compiler is aware +of the alignment constraints and will generate extra instructions to perform +the memory access in a way that does not cause unaligned access. Of course, +the extra instructions obviously cause a loss in performance compared to the +non-packed case, so the packed attribute should only be used when avoiding +structure padding is of importance. + + +Code that causes unaligned access +================================= + +With the above in mind, let's move onto a real life example of a function +that can cause an unaligned memory access. The following function taken +from the Linux Kernel's include/linux/etherdevice.h is an optimized routine +to compare two ethernet MAC addresses for equality. + +bool ether_addr_equal(const u8 *addr1, const u8 *addr2) +{ +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) | + ((*(const u16 *)(addr1 + 4)) ^ (*(const u16 *)(addr2 + 4))); + + return fold == 0; +#else + const u16 *a = (const u16 *)addr1; + const u16 *b = (const u16 *)addr2; + return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0; +#endif +} + +In the above function, when the hardware has efficient unaligned access +capability, there is no issue with this code. But when the hardware isn't +able to access memory on arbitrary boundaries, the reference to a[0] causes +2 bytes (16 bits) to be read from memory starting at address addr1. + +Think about what would happen if addr1 was an odd address such as 0x10003. +(Hint: it'd be an unaligned access.) + +Despite the potential unaligned access problems with the above function, it +is included in the kernel anyway but is understood to only work normally on +16-bit-aligned addresses. It is up to the caller to ensure this alignment or +not use this function at all. This alignment-unsafe function is still useful +as it is a decent optimization for the cases when you can ensure alignment, +which is true almost all of the time in ethernet networking context. + + +Here is another example of some code that could cause unaligned accesses: + void myfunc(u8 *data, u32 value) + { + [...] + *((u32 *) data) = cpu_to_le32(value); + [...] + } + +This code will cause unaligned accesses every time the data parameter points +to an address that is not evenly divisible by 4. + +In summary, the 2 main scenarios where you may run into unaligned access +problems involve: + 1. Casting variables to types of different lengths + 2. Pointer arithmetic followed by access to at least 2 bytes of data + + +Avoiding unaligned accesses +=========================== + +The easiest way to avoid unaligned access is to use the get_unaligned() and +put_unaligned() macros provided by the header file. + +Going back to an earlier example of code that potentially causes unaligned +access: + + void myfunc(u8 *data, u32 value) + { + [...] + *((u32 *) data) = cpu_to_le32(value); + [...] + } + +To avoid the unaligned memory access, you would rewrite it as follows: + + void myfunc(u8 *data, u32 value) + { + [...] + value = cpu_to_le32(value); + put_unaligned(value, (u32 *) data); + [...] + } + +The get_unaligned() macro works similarly. Assuming 'data' is a pointer to +memory and you wish to avoid unaligned access, its usage is as follows: + + u32 value = get_unaligned((u32 *) data); + +These macros work for memory accesses of any length (not just 32 bits as +in the examples above). Be aware that when compared to standard access of +aligned memory, using these macros to access unaligned memory can be costly in +terms of performance. + +If use of such macros is not convenient, another option is to use memcpy(), +where the source or destination (or both) are of type u8* or unsigned char*. +Due to the byte-wise nature of this operation, unaligned accesses are avoided. + +-- +In the Linux Kernel, +Authors: Daniel Drake , + Johannes Berg +With help from: Alan Cox, Avuton Olrich, Heikki Orsila, Jan Engelhardt, +Kyle McMartin, Kyle Moffett, Randy Dunlap, Robert Hancock, Uli Kunitz, +Vadim Lobanov diff --git a/doc/README.usb b/doc/README.usb index 65fb2886d9..bc768a3854 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -127,8 +127,14 @@ To enable USB Host Ethernet in U-Boot, your platform must of course support USB with CONFIG_CMD_USB enabled and working. You will need to add some config settings to your board header file: +#define CONFIG_CMD_USB /* the 'usb' interactive command */ #define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */ -#define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */ + +and one or more of the following for individual adapter hardware: + +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX As with built-in networking, you will also want to enable some network commands, for example: @@ -148,7 +154,10 @@ settings should start you off: You can also set the default IP address of your board and the server as well as the default file to load when a 'bootp' command is issued. -All of these can be obtained from the bootp server if not set. +However note that encoding these individual network settings into a +common exectuable is discouraged, as it leads to potential conflicts, +and all the parameters can either get stored in the board's external +environment, or get obtained from the bootp server if not set. #define CONFIG_IPADDR 10.0.0.2 (replace with your value) #define CONFIG_SERVERIP 10.0.0.1 (replace with your value) diff --git a/doc/SPI/README.ti_qspi_am43x_test b/doc/SPI/README.ti_qspi_am43x_test new file mode 100644 index 0000000000..8fbf10b57a --- /dev/null +++ b/doc/SPI/README.ti_qspi_am43x_test @@ -0,0 +1,76 @@ +Testing details- +---------------- + +This doc simply illustrated the testing details of qspi flash +driver with Macronix M25L51235 flash device. + +The test includes +- probing the flash device +- erasing the flash device +- Writing to flash +- Reading the contents of the flash. + +Test Log +-------- + +Hit any key to stop autoboot: 0 +U-Boot# sf probe 0 +SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 +U-Boot# sf erase 0 0x80000 +SF: 524288 bytes @ 0x0 Erased: OK +U-Boot# mw 81000000 0xdededede 0x40000 +U-Boot# sf write 81000000 0 0x40000 +SF: 262144 bytes @ 0x0 Written: OK +U-Boot# sf read 82000000 0 0x40000 +SF: 262144 bytes @ 0x0 Read: OK +U-Boot# md 0x82000000 +82000000: dededede dededede dededede dededede ................ +82000010: dededede dededede dededede dededede ................ +82000020: dededede dededede dededede dededede ................ +82000030: dededede dededede dededede dededede ................ +82000040: dededede dededede dededede dededede ................ +82000050: dededede dededede dededede dededede ................ +82000060: dededede dededede dededede dededede ................ +82000070: dededede dededede dededede dededede ................ +82000080: dededede dededede dededede dededede ................ +82000090: dededede dededede dededede dededede ................ +820000a0: dededede dededede dededede dededede ................ +820000b0: dededede dededede dededede dededede ................ +820000c0: dededede dededede dededede dededede ................ +820000d0: dededede dededede dededede dededede ................ +820000e0: dededede dededede dededede dededede ................ +820000f0: dededede dededede dededede dededede ................ +U-Boot# md 0x82010000 +82010000: dededede dededede dededede dededede ................ +82010010: dededede dededede dededede dededede ................ +82010020: dededede dededede dededede dededede ................ +82010030: dededede dededede dededede dededede ................ +82010040: dededede dededede dededede dededede ................ +82010050: dededede dededede dededede dededede ................ +82010060: dededede dededede dededede dededede ................ +82010070: dededede dededede dededede dededede ................ +82010080: dededede dededede dededede dededede ................ +82010090: dededede dededede dededede dededede ................ +820100a0: dededede dededede dededede dededede ................ +820100b0: dededede dededede dededede dededede ................ +820100c0: dededede dededede dededede dededede ................ +820100d0: dededede dededede dededede dededede ................ +820100e0: dededede dededede dededede dededede ................ +820100f0: dededede dededede dededede dededede ................ +U-Boot# md 0x82030000 +82030000: dededede dededede dededede dededede ................ +82030010: dededede dededede dededede dededede ................ +82030020: dededede dededede dededede dededede ................ +82030030: dededede dededede dededede dededede ................ +82030040: dededede dededede dededede dededede ................ +82030050: dededede dededede dededede dededede ................ +82030060: dededede dededede dededede dededede ................ +82030070: dededede dededede dededede dededede ................ +82030080: dededede dededede dededede dededede ................ +82030090: dededede dededede dededede dededede ................ +820300a0: dededede dededede dededede dededede ................ +820300b0: dededede dededede dededede dededede ................ +820300c0: dededede dededede dededede dededede ................ +820300d0: dededede dededede dededede dededede ................ +820300e0: dededede dededede dededede dededede ................ +820300f0: dededede dededede dededede dededede ................ diff --git a/doc/device-tree-bindings/video/exynos_mipi_dsi.txt b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt new file mode 100644 index 0000000000..4938ea01ec --- /dev/null +++ b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt @@ -0,0 +1,82 @@ +Exynos MIPI-DSIM Controller +========================= + +Required properties: +SOC specific: + compatible: should be "samsung,exynos-mipi-dsi" + reg: Base address of MIPI-DSIM IP. + +Board specific: + samsung,dsim-config-e-interface: interface to be used (RGB interface + for main display or CPU interface for main or sub display). + samsung,dsim-config-e-virtual-ch: virtual channel number that main + or sub display uses. + samsung,dsim-config-e-pixel-format: pixel stream format for main + or sub display. + samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode. + in Non-burst mode, RGB data area is filled with RGB data and + NULL packets, according to input bandwidth of RGB interface. + samsung,dsim-config-e-no-data-lane: data lane count used by Master. + samsung,dsim-config-e-byte-clk: select byte clock source. + It must be DSIM_PLL_OUT_DIV8. + DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. + samsung,dsim-config-hfp: HFP disable mode. + If set, DSI master ignores HFP area in VIDEO mode. + In command mode, this variable is ignored. + samsung,dsim-config-p: P value for PMS setting. + samsung,dsim-config-m: M value for PMS setting. + samsung,dsim-config-s: S value for PMS setting. + samsung,dsim-config-pll-stable-time: the PLL Timer for stability + of the ganerated clock. + samsung,dsim-config-esc-clk: escape clock frequency for getting + the escape clock prescaler value. + samsung,dsim-config-stop-holding-cnt: the interval value between + transmitting read packet (or write "set_tear_on" command) + and BTA request. After transmitting read packet or write + "set_tear_on" command, BTA requests to D-PHY automatically. + This counter value specifies the interval between them. + samsung,dsim-config-bta-timeout: the timer for BTA. This register + specifies time out from BTA request to change the direction + with respect to Tx escape clock. + samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout. + this register specifies time out on how long RxValid deasserts, + after RxLpdt asserts with respect to Tx escape clock. + - RxValid specifies Rx data valid indicator. + - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode + - RxValid and RxLpdt specifies signal from D-PHY. + samsung,dsim-device-name: name of the device. + samsung,dsim-device-id: unique device id. + samsung,dsim-device-bus_id: bus id for identifing connected bus + and this bus id should be same as id of mipi_dsim_device. + +Optional properties: + samsung,dsim-device-reverse-panel: reverse panel. + +Example: + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; diff --git a/doc/device-tree-bindings/video/sandbox-fb.txt b/doc/device-tree-bindings/video/sandbox-fb.txt new file mode 100644 index 0000000000..eb91b30e3f --- /dev/null +++ b/doc/device-tree-bindings/video/sandbox-fb.txt @@ -0,0 +1,13 @@ +Sandbox LCD +=========== + +This uses the displaymode.txt binding except that only xres and yres are +required properties. + +Example: + + lcd { + compatible = "sandbox,lcd-sdl"; + xres = <800>; + yres = <600>; + }; diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt new file mode 100644 index 0000000000..e0b395a618 --- /dev/null +++ b/doc/driver-model/README.txt @@ -0,0 +1,368 @@ +Driver Model +============ + +This README contains high-level information about driver model, a unified +way of declaring and accessing drivers in U-Boot. The original work was done +by: + + Marek Vasut + Pavel Herrmann + Viktor KÅ™ivák + Tomas Hlavacek + +This has been both simplified and extended into the current implementation +by: + + Simon Glass + + +Terminology +----------- + +Uclass - a group of devices which operate in the same way. A uclass provides + a way of accessing invidual devices within the group, but always + using the same interface. For example a GPIO uclass provides + operations for get/set value. An I2C uclass may have 10 I2C ports, + 4 with one driver, and 6 with another. + +Driver - some code which talks to a peripheral and presents a higher-level + interface to it. + +Device - an instance of a driver, tied to a particular port or peripheral. + + +How to try it +------------- + +Build U-Boot sandbox and run it: + + make sandbox_config + make + ./u-boot + + (type 'reset' to exit U-Boot) + + +There is a uclass called 'demo'. This uclass handles +saying hello, and reporting its status. There are two drivers in this +uclass: + + - simple: Just prints a message for hello, doesn't implement status + - shape: Prints shapes and reports number of characters printed as status + +The demo class is pretty simple, but not trivial. The intention is that it +can be used for testing, so it will implement all driver model features and +provide good code coverage of them. It does have multiple drivers, it +handles parameter data and platdata (data which tells the driver how +to operate on a particular platform) and it uses private driver data. + +To try it, see the example session below: + +=>demo hello 1 +Hello '@' from 07981110: red 4 +=>demo status 2 +Status: 0 +=>demo hello 2 +g +r@ +e@@ +e@@@ +n@@@@ +g@@@@@ +=>demo status 2 +Status: 21 +=>demo hello 4 ^ + y^^^ + e^^^^^ +l^^^^^^^ +l^^^^^^^ + o^^^^^ + w^^^ +=>demo status 4 +Status: 36 +=> + + +Running the tests +----------------- + +The intent with driver model is that the core portion has 100% test coverage +in sandbox, and every uclass has its own test. As a move towards this, tests +are provided in test/dm. To run them, try: + + ./test/dm/test-dm.sh + +You should see something like this: + + <...U-Boot banner...> + Running 12 driver model tests + Test: dm_test_autobind + Test: dm_test_autoprobe + Test: dm_test_children + Test: dm_test_fdt + Test: dm_test_gpio + sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved + Test: dm_test_leak + Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c + Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c + Test: dm_test_lifecycle + Test: dm_test_operations + Test: dm_test_ordering + Test: dm_test_platdata + Test: dm_test_remove + Test: dm_test_uclass + Failures: 0 + +(You can add '#define DEBUG' as suggested to check for memory leaks) + + +What is going on? +----------------- + +Let's start at the top. The demo command is in common/cmd_demo.c. It does +the usual command procesing and then: + + struct device *demo_dev; + + ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); + +UCLASS_DEMO means the class of devices which implement 'demo'. Other +classes might be MMC, or GPIO, hashing or serial. The idea is that the +devices in the class all share a particular way of working. The class +presents a unified view of all these devices to U-Boot. + +This function looks up a device for the demo uclass. Given a device +number we can find the device because all devices have registered with +the UCLASS_DEMO uclass. + +The device is automatically activated ready for use by uclass_get_device(). + +Now that we have the device we can do things like: + + return demo_hello(demo_dev, ch); + +This function is in the demo uclass. It takes care of calling the 'hello' +method of the relevant driver. Bearing in mind that there are two drivers, +this particular device may use one or other of them. + +The code for demo_hello() is in drivers/demo/demo-uclass.c: + +int demo_hello(struct device *dev, int ch) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->hello) + return -ENOSYS; + + return ops->hello(dev, ch); +} + +As you can see it just calls the relevant driver method. One of these is +in drivers/demo/demo-simple.c: + +static int simple_hello(struct device *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + + printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), + pdata->colour, pdata->sides); + + return 0; +} + + +So that is a trip from top (command execution) to bottom (driver action) +but it leaves a lot of topics to address. + + +Declaring Drivers +----------------- + +A driver declaration looks something like this (see +drivers/demo/demo-shape.c): + +static const struct demo_ops shape_ops = { + .hello = shape_hello, + .status = shape_status, +}; + +U_BOOT_DRIVER(demo_shape_drv) = { + .name = "demo_shape_drv", + .id = UCLASS_DEMO, + .ops = &shape_ops, + .priv_data_size = sizeof(struct shape_data), +}; + + +This driver has two methods (hello and status) and requires a bit of +private data (accessible through dev_get_priv(dev) once the driver has +been probed). It is a member of UCLASS_DEMO so will register itself +there. + +In U_BOOT_DRIVER it is also possible to specify special methods for bind +and unbind, and these are called at appropriate times. For many drivers +it is hoped that only 'probe' and 'remove' will be needed. + +The U_BOOT_DRIVER macro creates a data structure accessible from C, +so driver model can find the drivers that are available. + +The methods a device can provide are documented in the device.h header. +Briefly, they are: + + bind - make the driver model aware of a device (bind it to its driver) + unbind - make the driver model forget the device + ofdata_to_platdata - convert device tree data to platdata - see later + probe - make a device ready for use + remove - remove a device so it cannot be used until probed again + +The sequence to get a device to work is bind, ofdata_to_platdata (if using +device tree) and probe. + + +Platform Data +------------- + +Where does the platform data come from? See demo-pdata.c which +sets up a table of driver names and their associated platform data. +The data can be interpreted by the drivers however they like - it is +basically a communication scheme between the board-specific code and +the generic drivers, which are intended to work on any board. + +Drivers can acceess their data via dev->info->platdata. Here is +the declaration for the platform data, which would normally appear +in the board file. + + static const struct dm_demo_cdata red_square = { + .colour = "red", + .sides = 4. + }; + static const struct driver_info info[] = { + { + .name = "demo_shape_drv", + .platdata = &red_square, + }, + }; + + demo1 = driver_bind(root, &info[0]); + + +Device Tree +----------- + +While platdata is useful, a more flexible way of providing device data is +by using device tree. With device tree we replace the above code with the +following device tree fragment: + + red-square { + compatible = "demo-shape"; + colour = "red"; + sides = <4>; + }; + + +The easiest way to make this work it to add a few members to the driver: + + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), + .ofdata_to_platdata = testfdt_ofdata_to_platdata, + .probe = testfdt_drv_probe, + +The 'auto_alloc' feature allowed space for the platdata to be allocated +and zeroed before the driver's ofdata_to_platdata method is called. This +method reads the information out of the device tree and puts it in +dev->platdata. Then the probe method is called to set up the device. + +Note that both methods are optional. If you provide an ofdata_to_platdata +method then it wlil be called first (after bind). If you provide a probe +method it will be called next. + +If you don't want to have the platdata automatically allocated then you +can leave out platdata_auto_alloc_size. In this case you can use malloc +in your ofdata_to_platdata (or probe) method to allocate the required memory, +and you should free it in the remove method. + + +Declaring Uclasses +------------------ + +The demo uclass is declared like this: + +U_BOOT_CLASS(demo) = { + .id = UCLASS_DEMO, +}; + +It is also possible to specify special methods for probe, etc. The uclass +numbering comes from include/dm/uclass.h. To add a new uclass, add to the +end of the enum there, then declare your uclass as above. + + +Data Structures +--------------- + +Driver model uses a doubly-linked list as the basic data structure. Some +nodes have several lists running through them. Creating a more efficient +data structure might be worthwhile in some rare cases, once we understand +what the bottlenecks are. + + +Changes since v1 +---------------- + +For the record, this implementation uses a very similar approach to the +original patches, but makes at least the following changes: + +- Tried to agressively remove boilerplate, so that for most drivers there +is little or no 'driver model' code to write. +- Moved some data from code into data structure - e.g. store a pointer to +the driver operations structure in the driver, rather than passing it +to the driver bind function. +- Rename some structures to make them more similar to Linux (struct device +instead of struct instance, struct platdata, etc.) +- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that +this concept relates to a class of drivers (or a subsystem). We shouldn't +use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems +better than 'core'. +- Remove 'struct driver_instance' and just use a single 'struct device'. +This removes a level of indirection that doesn't seem necessary. +- Built in device tree support, to avoid the need for platdata +- Removed the concept of driver relocation, and just make it possible for +the new driver (created after relocation) to access the old driver data. +I feel that relocation is a very special case and will only apply to a few +drivers, many of which can/will just re-init anyway. So the overhead of +dealing with this might not be worth it. +- Implemented a GPIO system, trying to keep it simple + + +Things to punt for later +------------------------ + +- SPL support - this will have to be present before many drivers can be +converted, but it seems like we can add it once we are happy with the +core implementation. +- Pre-relocation support - similar story + +That is not to say that no thinking has gone into these - in fact there +is quite a lot there. However, getting these right is non-trivial and +there is a high cost associated with going down the wrong path. + +For SPL, it may be possible to fit in a simplified driver model with only +bind and probe methods, to reduce size. + +For pre-relocation we can simply call the driver model init function. Then +post relocation we throw that away and re-init driver model again. For drivers +which require some sort of continuity between pre- and post-relocation +devices, we can provide access to the pre-relocation device pointers. + +Uclasses are statically numbered at compile time. It would be possible to +change this to dynamic numbering, but then we would require some sort of +lookup service, perhaps searching by name. This is slightly less efficient +so has been left out for now. One small advantage of dynamic numbering might +be fewer merge conflicts in uclass-id.h. + + +Simon Glass +sjg@chromium.org +April 2013 +Updated 7-May-13 +Updated 14-Jun-13 +Updated 18-Oct-13 +Updated 5-Nov-13 diff --git a/doc/driver-model/UDM-block.txt b/doc/driver-model/UDM-block.txt deleted file mode 100644 index 0437d9bb9c..0000000000 --- a/doc/driver-model/UDM-block.txt +++ /dev/null @@ -1,278 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Block device subsystem analysis -=============================== - -Pavel Herrmann -2012-03-08 - -I) Overview ------------ - - U-Boot currently implements several distinct APIs for block devices - some - drivers use the SATA API, some drivers use the IDE API, sym53c8xx and - AHCI use the SCSI API, mg_disk has a separate API, and systemace also has a - separate API. There are also MMC and USB APIs used outside of drivers/block, - those will be detailed in their specific documents. - - Block devices are described by block_dev_desc structure, that holds, among - other things, the read/write/erase callbacks. Block device structures are - stored in any way depending on the API, but can be accessed by - - block_dev_desc_t * $api_get_dev(int dev) - - function, as seen in disk/part.c. - - 1) SATA interface - ----------------- - - The SATA interface drivers implement the following functions: - - int init_sata(int dev) - int scan_sata(int dev) - ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer) - ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer) - - Block devices are kept in sata_dev_desc[], which is prefilled with values - common to all SATA devices in cmd_sata.c, and then modified in init_sata - function in the drivers. Callbacks of the block device use SATA API - directly. The sata_get_dev function is defined in cmd_sata.c. - - 2) SCSI interface - ----------------- - - The SCSI interface drivers implement the following functions: - - void scsi_print_error(ccb *pccb) - int scsi_exec(ccb *pccb) - void scsi_bus_reset(void) - void scsi_low_level_init(int busdevfunc) - - The SCSI API works through the scsi_exec function, the actual operation - requested is found in the ccb structure. - - Block devices are kept in scsi_dev_desc[], which lives only in cmd_scsi.c. - Callbacks of the block device use functions from cmd_scsi.c, which in turn - call scsi_exec of the controller. The scsi_get_dev function is also defined - in cmd_scsi.c. - - 3) mg_disk interface - -------------------- - - The mg_disk interface drivers implement the following functions: - - struct mg_drv_data* mg_get_drv_data (void) - uint mg_disk_init (void) - uint mg_disk_read (u32 addr, u8 *buff, u32 len) - uint mg_disk_write(u32 addr, u8 *buff, u32 len) - uint mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt) - uint mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt) - - The mg_get_drv_data function is to be overridden per-board, but there are no - board in-tree that do this. - - Only one driver for this API exists, and it only supports one block device. - Callbacks for this device are implemented in mg_disk.c and call the mg_disk - API. The mg_disk_get_dev function is defined in mg_disk.c and ignores the - device number, always returning the same device. - - 4) systemace interface - ---------------------- - - The systemace interface does not define any driver API, and has no command - itself. The single defined function is systemace_get_devs() from - systemace.c, which returns a single static structure for the only supported - block device. Callbacks for this device are also implemented in systemace.c. - - 5) IDE interface - ---------------- - - The IDE interface drivers implement the following functions, but only if - CONFIG_IDE_AHB is set: - - uchar ide_read_register(int dev, unsigned int port); - void ide_write_register(int dev, unsigned int port, unsigned char val); - void ide_read_data(int dev, ulong *sect_buf, int words); - void ide_write_data(int dev, const ulong *sect_buf, int words); - - The first two functions are called from ide_inb()/ide_outb(), and will - default to direct memory access if CONFIG_IDE_AHB is not set, or - ide_inb()/ide_outb() functions will get overridden by the board altogether. - - The second two functions are called from input_data()/output_data() - functions, and also default to direct memory access, but cannot be - overridden by the board. - - One function shared by IDE drivers (but not defined in ide.h) is - int ide_preinit(void) - This function gets called from ide_init in cmd_ide.c if CONFIG_IDE_PREINIT - is defined, and will do the driver-specific initialization of the device. - - Block devices are kept in ide_dev_desc[], which is filled in cmd_ide.c. - Callbacks of the block device are defined in cmd_ide.c, and use the - ide_inb()/ide_outb()/input_data()/output_data() functions mentioned above. - The ide_get_dev function is defined in cmd_ide.c. - -II) Approach ------------- - - A new block controller core and an associated API will be created to mimic the - current SATA API, its drivers will have the following ops: - - struct block_ctrl_ops { - int scan(instance *i); - int reset(instance *i, int port); - lbaint_t read(instance *i, int port, lbaint_t start, lbatin_t length, - void *buffer); - lbaint_t write(instance *i, int port, lbaint_t start, lbatin_t length, - void*buffer); - } - - The current sata_init() function will be changed into the driver probe() - function. The read() and write() functions should never be called directly, - instead they should be called by block device driver for disks. - - Other block APIs would either be transformed into this API, or be kept as - legacy for old drivers, or be dropped altogether. - - Legacy driver APIs will each have its own driver core that will contain the - shared logic, which is currently located mostly in cmd_* files. Callbacks for - block device drivers will then probably be implemented as a part of the core - logic, and will use the driver ops (which will copy current state of - respective APIs) to do the work. - - All drivers will be cleaned up, most ifdefs should be converted into - platform_data, to enable support for multiple devices with different settings. - - A new block device core will also be created, and will keep track of all - block devices on all interfaces. - - Current block_dev_desc structure will be changed to fit the driver model, all - identification and configuration will be placed in private data, and - a single accessor and modifier will be defined, to accommodate the need for - different sets of options for different interfaces, while keeping the - structure small. The new block device drivers will have the following ops - structure (lbaint_t is either 32bit or 64bit unsigned, depending on - CONFIG_LBA48): - - struct blockdev_ops { - lbaint_t (*block_read)(struct instance *i, lbaint_t start, lbaint_t blkcnt, - void *buffer); - lbaint_t (*block_write)(struct instance *i, lbaint_t start, lbaint_t blkcnt, - void *buffer); - lbaint_t (*block_erase)(struct instance *i, lbaint_t start, lbaint_t blkcnt - ); - int (*get_option)(struct instance *i, enum blockdev_option_code op, - struct option *res); - int (*set_option)(struct instance *i, enum blockdev_option_code op, - struct option *val); - } - - struct option { - uint32_t flags - union data { - uint64_t data_u; - char* data_s; - void* data_p; - } - } - - enum blockdev_option_code { - BLKD_OPT_IFTYPE=0, - BLKD_OPT_TYPE, - BLKD_OPT_BLOCKSIZE, - BLKD_OPT_BLOCKCOUNT, - BLKD_OPT_REMOVABLE, - BLKD_OPT_LBA48, - BLKD_OPT_VENDOR, - BLKD_OPT_PRODICT, - BLKD_OPT_REVISION, - BLKD_OPT_SCSILUN, - BLKD_OPT_SCSITARGET, - BLKD_OPT_OFFSET - } - - Flags in option above will contain the type of returned data (which should be - checked against what is expected, even though the option requested should - specify it), and a flag to indicate whether the returned pointer needs to be - free()'d. - - The block device core will contain the logic now located in disk/part.c and - related files, and will be used to forward requests to block devices. The API - for the block device core will copy the ops of a block device (with a string - identifier instead of instance pointer). This means that partitions will also - be handled by the block device core, and exported as block devices, making - them transparent to the rest of the code. - - Sadly, this will change how file systems can access the devices, and thus will - affect a lot of places. However, these changes should be localized and easy to - implement. - - AHCI driver will be rewritten to fit the new unified block controller API, - making SCSI API easy to merge with sym53c8xx, or remove it once the device - driver has died. - - Optionally, IDE core may be changed into one driver with unified block - controller API, as most of it is already in one place and device drivers are - just sets of hooks. Additionally, mg_disk driver is unused and may be removed - in near future. - - -III) Analysis of in-tree drivers --------------------------------- - - ahci.c - ------ - SCSI API, will be rewritten for a different API. - - ata_piix.c - ---------- - SATA API, easy to port. - - fsl_sata.c - ---------- - SATA API, few CONFIG macros, easy to port. - - ftide020.c - ---------- - IDE API, defines CONFIG_IDE_AHB and ide_preinit hook functions. - - mg_disk.c - --------- - Single driver with mg_disk API, not much to change, easy to port. - - mvsata_ide.c - ------------ - IDE API, only defines ide_preinit hook function. - - mxc_ata.c - --------- - IDE API, only defines ide_preinit hook function. - - pata_bfin.c - ----------- - SATA API, easy to port. - - sata_dwc.c - ---------- - SATA API, easy to port. - - sata_sil3114.c - -------------- - SATA API, easy to port. - - sata_sil.c - ---------- - SATA API, easy to port. - - sil680.c - -------- - IDE API, only defines ide_preinit hook function. - - sym53c8xx.c - ----------- - SCSI API, may be merged with code from cmd_scsi. - - systemace.c - ----------- - Single driver with systemace API, not much to change, easy to port. diff --git a/doc/driver-model/UDM-cores.txt b/doc/driver-model/UDM-cores.txt deleted file mode 100644 index 60323335b8..0000000000 --- a/doc/driver-model/UDM-cores.txt +++ /dev/null @@ -1,126 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Driver cores API document -========================= - -Pavel Herrmann - -1) Overview ------------ - Driver cores will be used as a wrapper for devices of the same type, and as - an abstraction for device driver APIs. For each driver API (which roughly - correspond to device types), there will be one driver core. Each driver core - will implement three APIs - a driver API (which will be the same as API of - drivers the core wraps around), a core API (which will be implemented by all - cores) and a command API (core-specific API which will be exposed to - commands). - - A) Command API - The command API will provide access to shared functionality for a specific - device, which is currently located mostly in commands. Commands will be - rewritten to be more lightweight by using this API. As this API will be - different for each core, it is out of scope of this document. - - B) Driver API - The driver API will act as a wrapper around actual device drivers, - providing a single entrypoint for device access. All functions in this API - have an instance* argument (probably called "this" or "i"), which will be - examined by the core, and a correct function for the specified driver will - get called. - - If the core gets called with a group instance pointer (as discussed in - design), it will automatically select the instance that is associated - with this core, and use it as target of the call. if the group contains - multiple instances of a single type, the caller must explicitly use an - accessor to select the correct instance. - - This accessor will look like: - struct instance *get_instance_from_group(struct instance *group, int i) - - When called with a non-group instance, it will simply return the instance. - - C) Core API - The core API will be implemented by all cores, and will provide - functionality for getting driver instances from non-driver code. This API - will consist of following functions: - - int get_count(struct instance *core); - struct instance* get_instance(struct instance *core, int index); - int init(struct instance *core); - int bind(struct instance *core, struct instance *dev, void *ops, - void *hint); - int unbind(struct instance *core, instance *dev); - int replace(struct instance *core, struct_instance *new_dev, - struct instance *old_dev); - int destroy(struct instance *core); - int reloc(struct instance *new_core, struct instance *old_core); - - The 'hint' parameter of bind() serves for additional data a driver can - pass to the core, to help it create the correct internal state for this - instance. the replace() function will get called during instance - relocation, and will replace the old instance with the new one, keeping - the internal state untouched. - - -2) Lifetime of a driver core ----------------------------- - Driver cores will be initialized at runtime, to limit memory footprint in - early-init stage, when we have to fit into ~1KB of memory. All active cores - will be stored in a tree structure (referenced as "Core tree") in global data, - which provides good tradeoff between size and access time. - Every core will have a number constant associated with it, which will be used - to find the instance in Core tree, and to refer to the core in all calls - working with the Core tree. - The Core Tree should be implemented using B-tree (or a similar structure) - to guarantee acceptable time overhead in all cases. - - Code for working with the core (i2c in this example) follows: - - core_init(CORE_I2C); - This will check whether we already have a i2c core, and if not it creates - a new instance and adds it into the Core tree. This will not be exported, - all code should depend on get_core_instance to init the core when - necessary. - - get_core_instance(CORE_I2C); - This is an accessor into the Core tree, which will return the instance - of i2c core, creating it if necessary - - core_bind(CORE_I2C, instance, driver_ops); - This will get called in bind() function of a driver, and will add the - instance into cores internal list of devices. If the core is not found, it - will get created. - - driver_activate(instance *inst); - This call will recursively activate all devices necessary for using the - specified device. the code could be simplified as: - { - if (is_activated(inst)) - return; - driver_activate(inst->bus); - get_driver(inst)->probe(inst); - } - - The case with multiple parents will need to be handled here as well. - get_driver is an accessor to available drivers, which will get struct - driver based on a name in the instance. - - i2c_write(instance *inst, ...); - An actual call to some method of the driver. This code will look like: - { - driver_activate(inst); - struct instance *core = get_core_instance(CORE_I2C); - device_ops = get_ops(inst); - device_ops->write(...); - } - - get_ops will not be an exported function, it will be internal and specific - to the core, as it needs to know how are the ops stored, and what type - they are. - - Please note that above examples represent the algorithm, not the actual code, - as they are missing checks for validity of return values. - - core_init() function will get called the first time the core is requested, - either by core_link() or core_get_instance(). This way, the cores will get - created only when they are necessary, which will reduce our memory footprint. diff --git a/doc/driver-model/UDM-design.txt b/doc/driver-model/UDM-design.txt deleted file mode 100644 index 9f03bbaad3..0000000000 --- a/doc/driver-model/UDM-design.txt +++ /dev/null @@ -1,315 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Design document -=============== -Marek Vasut -Pavel Herrmann -2012-05-17 - -I) The modular concept ----------------------- - -The driver core design is done with modularity in mind. The long-term plan is to -extend this modularity to allow loading not only drivers, but various other -objects into U-Boot at runtime -- like commands, support for other boards etc. - -II) Driver core initialization stages -------------------------------------- - -The drivers have to be initialized in two stages, since the U-Boot bootloader -runs in two stages itself. The first stage is the one which is executed before -the bootloader itself is relocated. The second stage then happens after -relocation. - - 1) First stage - -------------- - - The first stage runs after the bootloader did very basic hardware init. This - means the stack pointer was configured, caches disabled and that's about it. - The problem with this part is the memory management isn't running at all. To - make things even worse, at this point, the RAM is still likely uninitialized - and therefore unavailable. - - 2) Second stage - --------------- - - At this stage, the bootloader has initialized RAM and is running from it's - final location. Dynamic memory allocations are working at this point. Most of - the driver initialization is executed here. - -III) The drivers ----------------- - - 1) The structure of a driver - ---------------------------- - - The driver will contain a structure located in a separate section, which - will allow linker to create a list of compiled-in drivers at compile time. - Let's call this list "driver_list". - - struct driver __attribute__((section(driver_list))) { - /* The name of the driver */ - char name[STATIC_CONFIG_DRIVER_NAME_LENGTH]; - - /* - * This function should connect this driver with cores it depends on and - * with other drivers, likely bus drivers - */ - int (*bind)(struct instance *i); - - /* This function actually initializes the hardware. */ - int (*probe)(struct instance *i); - - /* - * The function of the driver called when U-Boot finished relocation. - * This is particularly important to eg. move pointers to DMA buffers - * and such from the location before relocation to their final location. - */ - int (*reloc)(struct instance *i); - - /* - * This is called when the driver is shuting down, to deinitialize the - * hardware. - */ - int (*remove)(struct instance *i); - - /* This is called to remove the driver from the driver tree */ - int (*unbind)(struct instance *i); - - /* This is a list of cores this driver depends on */ - struct driver *cores[]; - }; - - The cores[] array in here is very important. It allows u-boot to figure out, - in compile-time, which possible cores can be activated at runtime. Therefore - if there are cores that won't be ever activated, GCC LTO might remove them - from the final binary. Actually, this information might be used to drive build - of the cores. - - FIXME: Should *cores[] be really struct driver, pointing to drivers that - represent the cores? Shouldn't it be core instance pointer? - - 2) Instantiation of a driver - ---------------------------- - - The driver is instantiated by calling: - - driver_bind(struct instance *bus, const struct driver_info *di) - - The "struct instance *bus" is a pointer to a bus with which this driver should - be registered with. The "root" bus pointer is supplied to the board init - functions. - - FIXME: We need some functions that will return list of busses of certain type - registered with the system so the user can find proper instance even if - he has no bus pointer (this will come handy if the user isn't - registering the driver from board init function, but somewhere else). - - The "const struct driver_info *di" pointer points to a structure defining the - driver to be registered. The structure is defined as follows: - - struct driver_info { - char name[STATIC_CONFIG_DRIVER_NAME_LENGTH]; - void *platform_data; - } - - The instantiation of a driver by calling driver_bind() creates an instance - of the driver by allocating "struct driver_instance". Note that only struct - instance is passed to the driver. The wrapping struct driver_instance is there - for purposes of the driver core: - - struct driver_instance { - uint32_t flags; - struct instance i; - }; - - struct instance { - /* Pointer to a driver information passed by driver_register() */ - const struct driver_info *info; - /* Pointer to a bus this driver is bound with */ - struct instance *bus; - /* Pointer to this driver's own private data */ - void *private_data; - /* Pointer to the first block of successor nodes (optional) */ - struct successor_block *succ; - } - - The instantiation of a driver does not mean the hardware is initialized. The - driver_bind() call only creates the instance of the driver, fills in the "bus" - pointer and calls the drivers' .bind() function. The .bind() function of the - driver should hook the driver with the remaining cores and/or drivers it - depends on. - - It's important to note here, that in case the driver instance has multiple - parents, such parent can be connected with this instance by calling: - - driver_link(struct instance *parent, struct instance *dev); - - This will connect the other parent driver with the newly instantiated driver. - Note that this must be called after driver_bind() and before driver_acticate() - (driver_activate() will be explained below). To allow struct instance to have - multiple parent pointer, the struct instance *bus will utilize it's last bit - to indicate if this is a pointer to struct instance or to an array if - instances, struct successor block. The approach is similar as the approach to - *succ in struct instance, described in the following paragraph. - - The last pointer of the struct instance, the pointer to successor nodes, is - used only in case of a bus driver. Otherwise the pointer contains NULL value. - The last bit of this field indicates if this is a bus having a single child - node (so the last bit is 0) or if this bus has multiple child nodes (the last - bit is 1). In the former case, the driver core should clear the last bit and - this pointer points directly to the child node. In the later case of a bus - driver, the pointer points to an instance of structure: - - struct successor_block { - /* Array of pointers to instances of devices attached to this bus */ - struct instance *dev[BLOCKING_FACTOR]; - /* Pointer to next block of successors */ - struct successor_block *next; - } - - Some of the *dev[] array members might be NULL in case there are no more - devices attached. The *next is NULL in case the list of attached devices - doesn't continue anymore. The BLOCKING_FACTOR is used to allocate multiple - slots for successor devices at once to avoid fragmentation of memory. - - 3) The bind() function of a driver - ---------------------------------- - - The bind function of a driver connects the driver with various cores the - driver provides functions for. The driver model related part will look like - the following example for a bus driver: - - int driver_bind(struct instance *in) - { - ... - core_bind(&core_i2c_static_instance, in, i2c_bus_funcs); - ... - } - - FIXME: What if we need to run-time determine, depending on some hardware - register, what kind of i2c_bus_funcs to pass? - - This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant - structure of functions any i2c bus driver must provide to work. This will - allow the i2c command operate with the bus. The core_i2c_static_instance is - the pointer to the instance of a core this driver provides function to. - - FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of - the core? - - 4) The instantiation of a core driver - ------------------------------------- - - The core driver is special in the way that it's single-instance driver. It is - always present in the system, though it might not be activated. The fact that - it's single instance allows it to be instantiated at compile time. - - Therefore, all possible structures of this driver can be in read-only memory, - especially struct driver and struct driver_instance. But the successor list, - which needs special treatment. - - To solve the problem with a successor list and the core driver flags, a new - entry in struct gd (global data) will be introduced. This entry will point to - runtime allocated array of struct driver_instance. It will be possible to - allocate the exact amount of struct driver_instance necessary, as the number - of cores that might be activated will be known at compile time. The cores will - then behave like any usual driver. - - Pointers to the struct instance of cores can be computed at compile time, - therefore allowing the resulting u-boot binary to save some overhead. - - 5) The probe() function of a driver - ----------------------------------- - - The probe function of a driver allocates necessary resources and does required - initialization of the hardware itself. This is usually called only when the - driver is needed, as a part of the defered probe mechanism. - - The driver core should implement a function called - - int driver_activate(struct instance *in); - - which should call the .probe() function of the driver and then configure the - state of the driver instance to "ACTIVATED". This state of a driver instance - should be stored in a wrap-around structure for the structure instance, the - struct driver_instance. - - 6) The command side interface to a driver - ----------------------------------------- - - The U-Boot command shall communicate only with the specific driver core. The - driver core in turn exports necessary API towards the command. - - 7) Demonstration imaginary board - -------------------------------- - - Consider the following computer: - - * - | - +-- System power management logic - | - +-- CPU clock controlling logc - | - +-- NAND controller - | | - | +-- NAND flash chip - | - +-- 128MB of DDR DRAM - | - +-- I2C bus #0 - | | - | +-- RTC - | | - | +-- EEPROM #0 - | | - | +-- EEPROM #1 - | - +-- USB host-only IP core - | | - | +-- USB storage device - | - +-- USB OTG-capable IP core - | | - | +-- connection to the host PC - | - +-- GPIO - | | - | +-- User LED #0 - | | - | +-- User LED #1 - | - +-- UART0 - | - +-- UART1 - | - +-- Ethernet controller #0 - | - +-- Ethernet controller #1 - | - +-- Audio codec - | - +-- PCI bridge - | | - | +-- Ethernet controller #2 - | | - | +-- SPI host card - | | | - | | +-- Audio amplifier (must be operational before codec) - | | - | +-- GPIO host card - | | - | +-- User LED #2 - | - +-- LCD controller - | - +-- PWM controller (must be enabled after LCD controller) - | - +-- SPI host controller - | | - | +-- SD/MMC connected via SPI - | | - | +-- SPI flash - | - +-- CPLD/FPGA with stored configuration of the board diff --git a/doc/driver-model/UDM-fpga.txt b/doc/driver-model/UDM-fpga.txt deleted file mode 100644 index 4f9df940ed..0000000000 --- a/doc/driver-model/UDM-fpga.txt +++ /dev/null @@ -1,115 +0,0 @@ -The U-Boot Driver Model Project -=============================== -I/O system analysis -=================== -Marek Vasut -2012-02-21 - -I) Overview ------------ - -The current FPGA implementation is handled by command "fpga". This command in -turn calls the following functions: - -fpga_info() -fpga_load() -fpga_dump() - -These functions are implemented by what appears to be FPGA multiplexer, located -in drivers/fpga/fpga.c . This code determines which device to operate with -depending on the device ID. - -The fpga_info() function is multiplexer of the functions providing information -about the particular FPGA device. These functions are implemented in the drivers -for the particular FPGA device: - -xilinx_info() -altera_info() -lattice_info() - -Similar approach is used for fpga_load(), which multiplexes "xilinx_load()", -"altera_load()" and "lattice_load()" and is used to load firmware into the FPGA -device. - -The fpga_dump() function, which prints the contents of the FPGA device, is no -different either, by multiplexing "xilinx_dump()", "altera_dump()" and -"lattice_dump()" functions. - -Finally, each new FPGA device is registered by calling "fpga_add()" function. -This function takes two arguments, the second one being particularly important, -because it's basically what will become platform_data. Currently, it's data that -are passed to the driver from the board/platform code. - -II) Approach ------------- - -The path to conversion of the FPGA subsystem will be very straightforward, since -the FPGA subsystem is already quite dynamic. Multiple things will need to be -modified though. - -First is the registration of the new FPGA device towards the FPGA core. This -will be achieved by calling: - - fpga_device_register(struct instance *i, const struct fpga_ops *ops); - -The particularly interesting part is the struct fpga_ops, which contains -operations supported by the FPGA device. These are basically the already used -calls in the current implementation: - -struct fpga_ops { - int info(struct instance *i); - int load(struct instance *i, const char *buf, size_t size); - int dump(struct instance *i, const char *buf, size_t size); -} - -The other piece that'll have to be modified is how the devices are tracked. -It'll be necessary to introduce a linked list of devices within the FPGA core -instead of tracking them by ID number. - -Next, the "Xilinx_desc", "Lattice_desc" and "Altera_desc" structures will have -to be moved to driver's private_data. Finally, structures passed from the board -and/or platform files, like "Xilinx_Virtex2_Slave_SelectMap_fns" would be passed -via platform_data to the driver. - -III) Analysis of in-tree drivers --------------------------------- - - 1) Altera driver - ---------------- - The driver is realized using the following files: - - drivers/fpga/altera.c - drivers/fpga/ACEX1K.c - drivers/fpga/cyclon2.c - drivers/fpga/stratixII.c - - All of the sub-drivers implement basically the same info-load-dump interface - and there's no expected problem during the conversion. The driver itself will - be realised by altera.c and all the sub-drivers will be linked in. The - distinction will be done by passing different platform data. - - 2) Lattice driver - ----------------- - The driver is realized using the following files: - - drivers/fpga/lattice.c - drivers/fpga/ivm_core.c - - This driver also implements the standard interface, but to realise the - operations with the FPGA device, uses functions from "ivm_core.c" file. This - file implements the main communications logic and has to be linked in together - with "lattice.c". No problem converting is expected here. - - 3) Xilinx driver - ---------------- - The driver is realized using the following files: - - drivers/fpga/xilinx.c - drivers/fpga/spartan2.c - drivers/fpga/spartan3.c - drivers/fpga/virtex2.c - - This set of sub-drivers is special by defining a big set of macros in - "include/spartan3.h" and similar files. These macros would need to be either - rewritten or replaced. Otherwise, there are no problems expected during the - conversion process. diff --git a/doc/driver-model/UDM-gpio.txt b/doc/driver-model/UDM-gpio.txt deleted file mode 100644 index 585d45868c..0000000000 --- a/doc/driver-model/UDM-gpio.txt +++ /dev/null @@ -1,106 +0,0 @@ -The U-Boot Driver Model Project -=============================== -GPIO analysis -============= -Viktor Krivak -2012-02-24 - -I) Overview ------------ - - At this moment U-Boot provides standard API that consists of 7 functions. - - int gpio_request(unsigned gpio, const char *label) - int gpio_free(unsigned gpio) - int gpio_direction_input(unsigned gpio) - int gpio_direction_output(unsigned gpio, int value) - int gpio_get_value(unsigned gpio) - void gpio_set_value(unsigned gpio, int value) - - Methods "gpio_request()" and "gpio_free()" are used for claiming and releasing - GPIOs. First one should check if the desired pin exists and if the pin wasn't - requested already elsewhere. The method also has a label argument that can be - used for debug purposes. The label argument should be copied into the internal - memory, but only if the DEBUG macro is set. The "gpio_free()" is the exact - opposite. It releases the particular pin. Other methods are used for setting - input or output direction and obtaining or setting values of the pins. - -II) Approach ------------- - - 1) Request and free GPIO - ------------------------ - - The "gpio_request()" implementation is basically the same for all boards. - The function checks if the particular GPIO is correct and checks if the - GPIO pin is still free. If the conditions are met, the method marks the - GPIO claimed in it's internal structure. If macro DEBUG is defined, the - function also copies the label argument to the structure. If the pin is - already locked, the function returns -1 and if DEBUG is defined, certain - debug output is generated, including the contents of the label argument. - The "gpio_free()" function releases the lock and eventually deallocates - data used by the copied label argument. - - 2) Internal data - ---------------- - - Internal data are driver specific. They have to contain some mechanism to - realise the locking though. This can be done for example using a bit field. - - 3) Operations provided by the driver - ------------------------------------ - - The driver operations basically meet API that is already defined and used. - Except for "gpio_request()" and "gpio_free()", all methods can be converted in - a simple manner. The driver provides the following structure: - - struct gpio_driver_ops { - int (*gpio_request)(struct instance *i, unsigned gpio, - const char *label); - int (*gpio_free)(struct instance *i, unsigned gpio); - int (*gpio_direction_input)(struct instance *i, unsigned gpio); - int (*gpio_direction_output)(struct instance *i, unsigned gpio, - int value); - int (*gpio_get_value)(struct instance *i, unsigned gpio); - void (*gpio_set_value)(struct instance *i, unsigned gpio, int value); - } - -III) Analysis of in-tree drivers --------------------------------- - - altera_pio.c - ------------ - Meets standard API. Implements gpio_request() properly. Simple conversion - possible. - - at91_gpio.c - ----------- - Don't meet standard API. Need some other methods to implement. - - da8xx_gpio.c - ------------ - Meets standard API. Implements gpio_request() properly. Simple conversion - possible. - - kw_gpio.c - --------- - Doesn't meet standard API. Needs some other methods to implement and move some - methods to another file. - - mpc83xx_gpio.c - -------------- - Meets standard API. Doesn't implement gpio_request() properly (only checks - if the pin is valid). Simple conversion possible. - - mvgpio.c - -------- - Meets standard API. Doesn't implement gpio_request() properly (only checks - if the pin is valid). Simple conversion possible. - - mvgpio.h - -------- - Wrong placement. Will be moved to another location. - - mvmfp.c - ------- - Wrong placement. Will be moved to another location. diff --git a/doc/driver-model/UDM-hwmon.txt b/doc/driver-model/UDM-hwmon.txt deleted file mode 100644 index 03a96a057a..0000000000 --- a/doc/driver-model/UDM-hwmon.txt +++ /dev/null @@ -1,118 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Hwmon device subsystem analysis -=============================== - -Tomas Hlavacek -2012-03-02 - -I) Overview ------------ - -U-Boot currently implements one API for HW monitoring devices. The -interface is defined in include/dtt.h and comprises of functions: - - void dtt_init(void); - int dtt_init_one(int); - int dtt_read(int sensor, int reg); - int dtt_write(int sensor, int reg, int val); - int dtt_get_temp(int sensor); - -The functions are implemented by a proper device driver in drivers/hwmon -directory and the driver to be compiled in is selected in a Makefile. -Drivers are mutually exclusive. - -Drivers depends on I2O code and naturally on board specific data. There are -few ad-hoc constants put in dtt.h file and driver headers and code. This -has to be consolidated into board specific data or driver headers if those -constants makes sense globally. - - -II) Approach ------------- - - 1) New API - ---------- - In the UDM each hwmon driver would register itself by a function - - int hwmon_device_register(struct instance *i, - struct hwmon_device_ops *o); - - The structure being defined as follows: - - struct hwmon_device_ops { - int (*read)(struct instance *i, int sensor, int reg); - int (*write)(struct instance *i, int sensor, int reg, - int val); - int (*get_temp)(struct instance *i, int sensor); - }; - - - 2) Conversion thougths - ---------------------- - U-Boot hwmon drivers exports virtually the same functions (with exceptions) - and we are considering low number of drivers and code anyway. The interface - is already similar and unified by the interface defined in dtt.h. - Current initialization functions dtt_init() and dtt_init_one() will be - converted into probe() and hwmon_device_register(), so the funcionality will - be kept in more proper places. Besides implementing core registration and - initialization we need to do code cleanup, especially separate - driver-specific and HW specific constants. - - 3) Special consideration due to early initialization - ---------------------------------------------------- - The dtt_init() function call is used during early initialization in - board/gdsys/405ex/io64.c for starting up fans. The dtt code is perfectly - usable in the early stage because it uses only local variables and no heap - memory is required at this level. However the underlying code of I2C has to - keep the same properties with regard to possibility of running in early - initialization stage. - -III) Analysis of in-tree drivers --------------------------------- - - drivers/hwmon/lm81.c - -------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/ds1722.c - ---------------------- - The driver is not standard dtt, but interface is similar to dtt. - The interface has to be changed in order to comply to above mentioned - specification. - - - drivers/hwmon/ds1775.c - ---------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/lm73.c - -------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/lm63.c - -------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/adt7460.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/lm75.c - -------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/ds1621.c - ---------------------- - The driver is standard dtt. Simple conversion is possible. - - - drivers/hwmon/adm1021.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. diff --git a/doc/driver-model/UDM-keyboard.txt b/doc/driver-model/UDM-keyboard.txt deleted file mode 100644 index 5babfc55f1..0000000000 --- a/doc/driver-model/UDM-keyboard.txt +++ /dev/null @@ -1,47 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Keyboard input analysis -======================= -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The keyboard drivers are most often registered with STDIO subsystem. There are -components of the keyboard drivers though, which operate in severe ad-hoc -manner, often being related to interrupt-driven keypress reception. This -components will require the most sanitization of all parts of keyboard input -subsystem. - -Otherwise, the keyboard is no different from other standard input but with the -necessity to decode scancodes. These are decoded using tables provided by -keyboard drivers. These tables are often driver specific. - -II) Approach ------------- - -The most problematic part is the interrupt driven keypress reception. For this, -the buffers that are currently shared throughout the whole U-Boot would need to -be converted into driver's private data. - -III) Analysis of in-tree drivers --------------------------------- - - board/mpl/common/kbd.c - ---------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - Only necessary change will be to move this driver to a proper location. - - board/rbc823/kbd.c - ------------------ - This driver is a classic STDIO driver, no problem with conversion is expected. - Only necessary change will be to move this driver to a proper location. - - drivers/input/keyboard.c - ------------------------ - This driver is special in many ways. Firstly because this is a universal stub - driver for converting scancodes from i8042 and the likes. Secondly because the - buffer is filled by various other ad-hoc implementations of keyboard input by - using this buffer as an extern. This will need to be fixed by allowing drivers - to pass certain routines to this driver via platform data. diff --git a/doc/driver-model/UDM-mmc.txt b/doc/driver-model/UDM-mmc.txt deleted file mode 100644 index 97f83a7776..0000000000 --- a/doc/driver-model/UDM-mmc.txt +++ /dev/null @@ -1,319 +0,0 @@ -The U-Boot Driver Model Project -=============================== -MMC system analysis -=================== -Marek Vasut -2012-02-25 - -I) Overview ------------ - -The MMC subsystem is already quite dynamic in it's nature. It's only necessary -to flip the subsystem to properly defined API. - -The probing process of MMC drivers start by calling "mmc_initialize()", -implemented by MMC framework, from the architecture initialization file. The -"mmc_initialize()" function in turn calls "board_mmc_init()" function and if -this doesn't succeed, "cpu_mmc_init()" function is called. It is important to -note that both of the "*_mmc_init()" functions have weak aliases to functions -which automatically fail. - -Both of the "*_mmc_init()" functions though serve only one purpose. To call -driver specific probe function, which in turn actually registers the driver with -MMC subsystem. Each of the driver specific probe functions is currently done in -very ad-hoc manner. - -The registration with the MMC subsystem is done by calling "mmc_register()", -whose argument is a runtime configured structure of information about the MMC -driver. Currently, the information structure is intermixed with driver's internal -data. The description of the structure follows: - -struct mmc { - /* - * API: Allows this driver to be a member of the linked list of all MMC drivers - * registered with MMC subsystem - */ - struct list_head link; - - /* DRIVER: Name of the registered driver */ - char name[32]; - - /* DRIVER: Driver's private data */ - void *priv; - - /* DRIVER: Voltages the host bus can provide */ - uint voltages; - - /* API: Version of the card */ - uint version; - - /* API: Test if the driver was already initialized */ - uint has_init; - - /* DRIVER: Minimum frequency the host bus can provide */ - uint f_min; - - /* DRIVER: Maximum frequency the host bus can provide */ - uint f_max; - - /* API: Is the card SDHC */ - int high_capacity; - - /* API: Actual width of the bus used by the current card */ - uint bus_width; - - /* - * DRIVER: Clock frequency to be configured on the host bus, this is read-only - * for the driver. - */ - uint clock; - - /* API: Capabilities of the card */ - uint card_caps; - - /* DRIVER: MMC bus capabilities */ - uint host_caps; - - /* API: Configuration and ID data retrieved from the card */ - uint ocr; - uint scr[2]; - uint csd[4]; - uint cid[4]; - ushort rca; - - /* API: Partition configuration */ - char part_config; - - /* API: Number of partitions */ - char part_num; - - /* API: Transmission speed */ - uint tran_speed; - - /* API: Read block length */ - uint read_bl_len; - - /* API: Write block length */ - uint write_bl_len; - - /* API: Erase group size */ - uint erase_grp_size; - - /* API: Capacity of the card */ - u64 capacity; - - /* API: Descriptor of this block device */ - block_dev_desc_t block_dev; - - /* DRIVER: Function used to submit command to the card */ - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - - /* DRIVER: Function used to configure the host */ - void (*set_ios)(struct mmc *mmc); - - /* DRIVER: Function used to initialize the host */ - int (*init)(struct mmc *mmc); - - /* DRIVER: Function used to report the status of Card Detect pin */ - int (*getcd)(struct mmc *mmc); - - /* - * DRIVER: Maximum amount of blocks sent during multiblock xfer, - * set to 0 to autodetect. - */ - uint b_max; -}; - -The API above is the new API used by most of the drivers. There're still drivers -in the tree that use old, legacy API though. - -2) Approach ------------ - -To convert the MMC subsystem to a proper driver model, the "struct mmc" -structure will have to be properly split in the first place. The result will -consist of multiple parts, first will be the structure defining operations -provided by the MMC driver: - -struct mmc_driver_ops { - /* Function used to submit command to the card */ - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - /* DRIVER: Function used to configure the host */ - void (*set_ios)(struct mmc *mmc); - /* Function used to initialize the host */ - int (*init)(struct mmc *mmc); - /* Function used to report the status of Card Detect pin */ - int (*getcd)(struct mmc *mmc); -} - -The second part will define the parameters of the MMC driver: - -struct mmc_driver_params { - /* Voltages the host bus can provide */ - uint32_t voltages; - /* Minimum frequency the host bus can provide */ - uint32_t f_min; - /* Maximum frequency the host bus can provide */ - uint32_t f_max; - /* MMC bus capabilities */ - uint32_t host_caps; - /* - * Maximum amount of blocks sent during multiblock xfer, - * set to 0 to autodetect. - */ - uint32_t b_max; -} - -And finally, the internal per-card data of the MMC subsystem core: - -struct mmc_card_props { - /* Version of the card */ - uint32_t version; - /* Test if the driver was already initializes */ - bool has_init; - /* Is the card SDHC */ - bool high_capacity; - /* Actual width of the bus used by the current card */ - uint8_t bus_width; - /* Capabilities of the card */ - uint32_t card_caps; - /* Configuration and ID data retrieved from the card */ - uint32_t ocr; - uint32_t scr[2]; - uint32_t csd[4]; - uint32_t cid[4]; - uint16_t rca; - /* Partition configuration */ - uint8_t part_config; - /* Number of partitions */ - uint8_t part_num; - /* Transmission speed */ - uint32_t tran_speed; - /* Read block length */ - uint32_t read_bl_len; - /* Write block length */ - uint32_t write_bl_len; - /* Erase group size */ - uint32_t erase_grp_size; - /* Capacity of the card */ - uint64_t capacity; - /* Descriptor of this block device */ - block_dev_desc_t block_dev; -} - -The probe() function will then register the MMC driver by calling: - - mmc_device_register(struct instance *i, struct mmc_driver_ops *o, - struct mmc_driver_params *p); - -The struct mmc_driver_params will have to be dynamic in some cases, but the -driver shouldn't modify it's contents elsewhere than in probe() call. - -Next, since the MMC drivers will now be consistently registered into the driver -tree from board file, the functions "board_mmc_init()" and "cpu_mmc_init()" will -disappear altogether. - -As for the legacy drivers, these will either be converted or removed altogether. - -III) Analysis of in-tree drivers --------------------------------- - - arm_pl180_mmci.c - ---------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - atmel_mci.c - ----------- - This driver uses the legacy API and should be removed unless converted. It is - probably possbible to replace this driver with gen_atmel_mci.c . No conversion - will be done on this driver. - - bfin_sdh.c - ---------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - davinci_mmc.c - ------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - fsl_esdhc.c - ----------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple, unless some problem appears due to the FDT - component of the driver. - - ftsdc010_esdhc.c - ---------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - gen_atmel_mci.c - --------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - mmc_spi.c - --------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - mv_sdhci.c - ---------- - This is a component of the SDHCI support, allowing it to run on Marvell - Kirkwood chip. It is probable the SDHCI support will have to be modified to - allow calling functions from this file based on information passed via - platform_data. - - mxcmmc.c - -------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - mxsmmc.c - -------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - omap_hsmmc.c - ------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - pxa_mmc.c - --------- - This driver uses the legacy API and is written in a severely ad-hoc manner. - This driver will be removed in favor of pxa_mmc_gen.c, which is proved to work - better and is already well tested. No conversion will be done on this driver - anymore. - - pxa_mmc_gen.c - ------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - s5p_mmc.c - --------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - sdhci.c - ------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple, though it'd be necessary to modify this driver - to also support the Kirkwood series and probably also Tegra series of CPUs. - See the respective parts of this section for details. - - sh_mmcif.c - ---------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - tegra2_mmc.c - ------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. diff --git a/doc/driver-model/UDM-net.txt b/doc/driver-model/UDM-net.txt deleted file mode 100644 index 097ed69600..0000000000 --- a/doc/driver-model/UDM-net.txt +++ /dev/null @@ -1,428 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Net system analysis -=================== -Marek Vasut -2012-03-03 - -I) Overview ------------ - -The networking subsystem already supports multiple devices. Therefore the -conversion shall not be very hard. - -The network subsystem is operated from net/eth.c, which tracks all registered -ethernet interfaces and calls their particular functions registered via -eth_register(). - -The eth_register() is called from the network driver initialization function, -which in turn is called most often either from "board_net_init()" or -"cpu_net_init()". This function has one important argument, which is the -"struct eth_device", defined at include/net.h: - -struct eth_device { - /* DRIVER: Name of the device */ - char name[NAMESIZE]; - /* DRIVER: MAC address */ - unsigned char enetaddr[6]; - /* DRIVER: Register base address */ - int iobase; - /* CORE: state of the device */ - int state; - - /* DRIVER: Device initialization function */ - int (*init) (struct eth_device*, bd_t*); - /* DRIVER: Function for sending packets */ - int (*send) (struct eth_device*, volatile void* packet, int length); - /* DRIVER: Function for receiving packets */ - int (*recv) (struct eth_device*); - /* DRIVER: Function to cease operation of the device */ - void (*halt) (struct eth_device*); - /* DRIVER: Function to send multicast packet (OPTIONAL) */ - int (*mcast) (struct eth_device*, u32 ip, u8 set); - /* DRIVER: Function to change ethernet MAC address */ - int (*write_hwaddr) (struct eth_device*); - /* CORE: Next device in the linked list of devices managed by net core */ - struct eth_device *next; - /* CORE: Device index */ - int index; - /* DRIVER: Driver's private data */ - void *priv; -}; - -This structure defines the particular driver, though also contains elements that -should not be exposed to the driver, like core state. - -Small, but important part of the networking subsystem is the PHY management -layer, whose drivers are contained in drivers/net/phy. These drivers register in -a very similar manner to network drivers, by calling "phy_register()" with the -argument of "struct phy_driver": - -struct phy_driver { - /* DRIVER: Name of the PHY driver */ - char *name; - /* DRIVER: UID of the PHY driver */ - unsigned int uid; - /* DRIVER: Mask for UID of the PHY driver */ - unsigned int mask; - /* DRIVER: MMDS of the PHY driver */ - unsigned int mmds; - /* DRIVER: Features the PHY driver supports */ - u32 features; - /* DRIVER: Initialize the PHY hardware */ - int (*probe)(struct phy_device *phydev); - /* DRIVER: Reconfigure the PHY hardware */ - int (*config)(struct phy_device *phydev); - /* DRIVER: Turn on the PHY hardware, allow it to send/receive */ - int (*startup)(struct phy_device *phydev); - /* DRIVER: Turn off the PHY hardware */ - int (*shutdown)(struct phy_device *phydev); - /* CORE: Allows this driver to be part of list of drivers */ - struct list_head list; -}; - -II) Approach ------------- - -To convert the elements of network subsystem to proper driver model method, the -"struct eth_device" will have to be split into multiple components. The first -will be a structure defining the driver operations: - -struct eth_driver_ops { - int (*init)(struct instance*, bd_t*); - int (*send)(struct instance*, void *packet, int length); - int (*recv)(struct instance*); - void (*halt)(struct instance*); - int (*mcast)(struct instance*, u32 ip, u8 set); - int (*write_hwaddr)(struct instance*); -}; - -Next, there'll be platform data which will be per-driver and will replace the -"priv" part of "struct eth_device". Last part will be the per-device core state. - -With regards to the PHY part of the API, the "struct phy_driver" is almost ready -to be used with the new driver model approach. The only change will be the -replacement of per-driver initialization functions and removal of -"phy_register()" function in favor or driver model approach. - -III) Analysis of in-tree drivers --------------------------------- - - drivers/net/4xx_enet.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/altera_tse.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/armada100_fec.c - --------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/at91_emac.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ax88180.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ax88796.c - --------------------- - - This file contains a components of the NE2000 driver, implementing only - different parts on the NE2000 clone AX88796. This being no standalone driver, - no conversion will be done here. - - drivers/net/bfin_mac.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/calxedaxgmac.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/cs8900.c - -------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/davinci_emac.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/dc2114x.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/designware.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/dm9000x.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/dnet.c - ------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/e1000.c - ------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/e1000_spi.c - ----------------------- - - Driver for the SPI bus integrated on the Intel E1000. This is not part of the - network stack. - - drivers/net/eepro100.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/enc28j60.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ep93xx_eth.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ethoc.c - ------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/fec_mxc.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/fsl_mcdmafec.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/fsl_mdio.c - ---------------------- - - This file contains driver for FSL MDIO interface, which is not part of the - networking stack. - - drivers/net/ftgmac100.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ftmac100.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/greth.c - ------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/inca-ip_sw.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ks8695eth.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/lan91c96.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/macb.c - ------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/mcffec.c - -------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/mcfmii.c - -------------------- - - This file contains MII interface driver for MCF FEC. - - drivers/net/mpc512x_fec.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/mpc5xxx_fec.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/mvgbe.c - ------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/natsemi.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/ne2000_base.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. This driver contains the core - implementation of NE2000, which needs a few external functions, implemented by - AX88796, NE2000 etc. - - drivers/net/ne2000.c - -------------------- - - This file implements external functions necessary for native NE2000 compatible - networking card to work. - - drivers/net/netconsole.c - ------------------------ - - This is actually an STDIO driver. - - drivers/net/ns8382x.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/pcnet.c - ------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/plb2800_eth.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/rtl8139.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/rtl8169.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/sh_eth.c - -------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/smc91111.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/smc911x.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/tsec.c - ------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/tsi108_eth.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/uli526x.c - --------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/vsc7385.c - --------------------- - - This is a driver that only uploads firmware to a switch. This is not subject - of conversion. - - drivers/net/xilinx_axi_emac.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - drivers/net/xilinx_emaclite.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt deleted file mode 100644 index 059a4329fb..0000000000 --- a/doc/driver-model/UDM-pci.txt +++ /dev/null @@ -1,257 +0,0 @@ -The U-Boot Driver Model Project -=============================== -PCI subsystem analysis -====================== - -Pavel Herrmann -2012-03-17 - -I) Overview ------------ - - U-Boot already supports multiple PCI busses, stored in a linked-list of - pci_controller structures. This structure contains generic driver data, bus - interface operations and private data for the driver. - - Bus interface operations for PCI are (names are self-explanatory): - - read_byte() - read_word() - read_dword() - write_byte() - write_word() - write_dword() - - Each driver has to implement dword operations, and either implement word and - byte operations, or use shared $operation_config_$type_via_dword (eg. - read_config_byte_via_dword and similar) function. These functions are used - for config space I/O (read_config_dword and similar functions of the PCI - subsystem), which is used to configure the connected devices for standard MMIO - operations. All data transfers by respective device drivers are then done by - MMIO - - Each driver also defines a separate init function, which has unique symbol - name, and thus more drivers can be compiled in without colliding. This init - function is typically called from pci_init_board(), different for each - particular board. - - Some boards also define a function called fixup_irq, which gets called after - scanning the PCI bus for devices, and should dismiss any interrupts. - - Several drivers are also located in arch/ and should be moved to drivers/pci. - -II) Approach ------------- - - The pci_controller structure needs to be broken down to fit the new driver - model. Due to a large number of members, this will be done through three - distinct accessors, one for memory regions, one for config table and one for - everything else. That will make the pci_ops structure look like this: - - struct pci_ops { - int (*read_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 *buf); - int (*read_word)(struct instance *bus, pci_dev_t *dev, int addr, - u16 *buf); - int (*read_dword)(struct instance *bus, pci_dev_t *dev, int addr, - u32 *buf); - int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 val); - int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 val); - int (*write_dword)(struct instance *bus, pci_dev_t *dev, int addr, - u32 val); - void (*fixup_irq)(struct instance *bus, pci_dev_t *dev); - struct pci_region* (*get_region)(struct instance *, uint num); - struct pci_config_table* (*get_cfg_table)(struct instance *bus); - uint (*get_option)(struct instance * bus, enum pci_option_code op); - } - - enum pci_option_code { - PCI_OPT_BUS_NUMBER=0, - PCI_OPT_REGION_COUNT, - PCI_OPT_INDIRECT_TYPE, - PCI_OPT_AUTO_MEM, - PCI_OPT_AUTO_IO, - PCI_OPT_AUTO_PREFETCH, - PCI_OPT_AUTO_FB, - PCI_OPT_CURRENT_BUS, - PCI_OPT_CFG_ADDR, - } - - The return value for get_option will be an unsigned integer value for any - option code. If the option currently is a pointer to pci_region, it will - return an index for get_region function. Special case has to be made for - PCI_OPT_CFG_ADDR, which should be interpreted as a pointer, but it is only - used for equality in find_hose_by_cfg_addr, and thus can be returned as an - uint. Other function using cfg_addr value are read/write functions for - specific drivers (especially ops for indirect bridges), and thus have access - to private_data of the driver instance. - - The config table accessor will return a pointer to a NULL-terminated array of - pci_config_table, which is supplied by the board in platform_data, or NULL if - the board didn't specify one. This table is used to override PnP - auto-initialization, or to specific initialization functions for non-PNP - devices. - - Transparent PCI-PCI bridges will get their own driver, and will forward all - operations to operations of their parent bus. This however makes it - impossible to use instances to identify devices, as not all devices will be - directly visible to the respective bus driver. - - Init functions of controller drivers will be moved to their respective - probe() functions, in accordance to the driver model. - - The PCI core will handle all mapping functions currently found in pci.c, as - well as proxy functions for read/write operations of the drivers. The PCI - core will also handle bus scanning and device configuration. - - The PnP helper functions currently in pci_auto.c will also be a part of PCI - core, but they will be exposed only to PCI controller drivers, not to other - device drivers. - - The PCI API for device drivers will remain largely unchanged, most drivers - will require no changes at all, and all modifications will be limited to - changing the pci_controlle into instance*. - -III) Analysis of in-tree drivers --------------------------------- - - A) drivers in drivers/pci/ - -------------------------- - - pci_indirect.c - -------------- - Shared driver for indirect PCI bridges, several CONFIG macros - will - require significant cleanup. - - pci_ixp.c - --------- - Standard driver, specifies all read/write functions separately. - - pci_sh4.c - --------- - Shared init function for SH4 drivers, uses dword for read/write ops. - - pci_sh7751.c - ------------ - Standard driver, uses SH4 shared init. - - pci_sh7780.c - ------------ - Standard driver, uses SH4 shared init. - - tsi108_pci.c - ------------ - Standard driver, uses dword for read/write ops. - - fsl_pci_init.c - -------------- - Driver for PCI and PCI-e, uses indirect functions. - - pci_ftpci100.c - -------------- - Standard driver, uses indirect functions, has separate scan/setup - functions. - - B) driver in arch/ - ------------------ - - x86/lib/pci_type1.c - ------------------- - Standard driver, specifies all read/write functions separately. - - m68k/cpu/mcf5445x/pci.c - ----------------------- - Standard driver, specifies all read/write functions separately. - - m68k/cpu/mcf547x_8x/pci.c - ------------------------- - Standard driver, specifies all read/write functions separately. - - powerpc/cpu/mpc824x/pci.c - ------------------------- - Standard driver, uses indirect functions, does not setup HW. - - powerpc/cpu/mpc8260/pci.c - ------------------------- - Standard driver, uses indirect functions. - - powerpc/cpu/ppc4xx/4xx_pci.c - ---------------------------- - Standard driver, uses indirect functions. - - powerpc/cpu/ppc4xx/4xx_pcie.c - ----------------------------- - PCI-e driver, specifies all read/write functions separately. - - powerpc/cpu/mpc83xx/pci.c - ------------------------- - Standard driver, uses indirect functions. - - powerpc/cpu/mpc83xx/pcie.c - -------------------------- - PCI-e driver, specifies all read/write functions separately. - - powerpc/cpu/mpc5xxx/pci_mpc5200.c - --------------------------------- - Standard driver, uses dword for read/write ops. - - powerpc/cpu/mpc512x/pci.c - ------------------------- - Standard driver, uses indirect functions. - - powerpc/cpu/mpc85xx/pci.c - ------------------------- - Standard driver, uses indirect functions, has two busses. - - C) drivers in board/ - -------------------- - - eltec/elppc/pci.c - ----------------- - Standard driver, uses indirect functions. - - amirix/ap1000/pci.c - ------------------- - Standard driver, specifies all read/write functions separately. - - prodrive/p3mx/pci.c - ------------------- - Standard driver, uses dword for read/write ops, has two busses. - - esd/cpci750/pci.c - ----------------- - Standard driver, uses dword for read/write ops, has two busses. - - esd/common/pci.c - ---------------- - Standard driver, uses dword for read/write ops. - - dave/common/pci.c - ----------------- - Standard driver, uses dword for read/write ops. - - ppmc7xx/pci.c - ------------- - Standard driver, uses indirect functions. - - Marvell/db64360/pci.c - --------------------- - Standard driver, uses dword for read/write ops, has two busses. - - Marvell/db64460/pci.c - --------------------- - Standard driver, uses dword for read/write ops, has two busses. - - evb64260/pci.c - -------------- - Standard driver, uses dword for read/write ops, has two busses. - - armltd/integrator/pci.c - ----------------------- - Standard driver, specifies all read/write functions separately. - - All drivers will be moved to drivers/pci. Several drivers seem - similar/identical, especially those located under board, and may be merged - into one. diff --git a/doc/driver-model/UDM-pcmcia.txt b/doc/driver-model/UDM-pcmcia.txt deleted file mode 100644 index d55e89df6a..0000000000 --- a/doc/driver-model/UDM-pcmcia.txt +++ /dev/null @@ -1,78 +0,0 @@ -The U-Boot Driver Model Project -=============================== -PCMCIA analysis -=============== -Viktor Krivak -2012-03-17 - -I) Overview ------------ - - U-boot implements only 2 methods to interoperate with pcmcia. One to turn - device on and other to turn device off. Names of these methods are usually - pcmcia_on() and pcmcia_off() without any parameters. Some files in driver - directory implements only internal API. These methods aren't used outside - driver directory and they are not converted to new driver model. - -II) Approach ------------ - - 1) New API - ---------- - - Current API is preserved and all internal methods are hiden. - - struct ops { - void (*pcmcia_on)(struct instance *i); - void (*pcmcia_off)(struct instance *i); - } - - 2) Conversion - ------------- - - In header file pcmcia.h are some other variables which are used for - additional configuration. But all have to be moved to platform data or to - specific driver implementation. - - 3) Platform data - ---------------- - - Many boards have custom implementation of internal API. Pointers to these - methods are stored in platform_data. But the most implementations for Intel - 82365 and compatible PC Card controllers and Yenta-compatible - PCI-to-CardBus controllers implement whole API per board. In these cases - pcmcia_on() and pcmcia_off() behave only as wrappers and call specific - board methods. - -III) Analysis of in-tree drivers --------------------------------- - - i82365.c - -------- - Driver methods have different name i82365_init() and i82365_exit but - all functionality is the same. Board files board/atc/ti113x.c and - board/cpc45/pd67290.c use their own implementation of these method. - In this case all methods in driver behave only as wrappers. - - marubun_pcmcia.c - ---------------- - Meets standard API behaviour. Simple conversion. - - mpc8xx_pcmcia.c - --------------- - Meets standard API behaviour. Simple conversion. - - rpx_pcmcia.c - ------------ - Implements only internal API used in other drivers. Non of methods - implemented here are used outside driver model. - - ti_pci1410a.c - ------------- - Has different API but methods in this file are never called. Probably - dead code. - - tqm8xx_pcmcia.c - --------------- - Implements only internal API used in other drivers. Non of methods - implemented here are used outside driver model. diff --git a/doc/driver-model/UDM-power.txt b/doc/driver-model/UDM-power.txt deleted file mode 100644 index 666d55305f..0000000000 --- a/doc/driver-model/UDM-power.txt +++ /dev/null @@ -1,88 +0,0 @@ -The U-Boot Driver Model Project -=============================== -POWER analysis -============== -Viktor Krivak -2012-03-09 - -I) Overview ------------ - - 1) Actual state - --------------- - - At this moment power doesn't contain API. There are many methods for - initialization of some board specific functions but only few does what is - expected. Basically only one file contains something meaningful for this - driver. - - 2) Current implementation - ------------------------- - - In file twl6030.c are methods twl6030_stop_usb_charging() and - twl6030_start_usb_charging() for start and stop charging from USB. There are - also methods to get information about battery state and initialization of - battery charging. Only these methods are used in converted API. - - -II) Approach ------------- - - 1) New API - ---------- - - New API implements only functions specific for managing power. All board - specific init methods are moved to other files. Name of methods are - self-explanatory. - - struct ops { - void (*start_usb_charging)(struct instance *i); - void (*stop_usb_charging)(struct instance *i); - int (*get_battery_current)(struct instance *i); - int (*get_battery_voltage)(struct instance *i); - void (*init_battery_charging)(struct instance *i); - } - - 2) Conversions of other methods - ------------------------------- - - Methods that can't be converted to new API are moved to board file or to - special file for board hacks. - -III) Analysis of in-tree drivers --------------------------------- - - ftpmu010.c - ---------- - All methods of this file are moved to another location. - void ftpmu010_32768osc_enable(void): Move to boards hacks - void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file - arch/nds32/lib/board.c - void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code - void ftpmu010_dlldis_disable(void): Dead code - void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file - arch/nds32/lib/board.c - void ftpmu010_sdramhtc_set(unsigned int val): Move to board file - arch/nds32/lib/board.c - - twl4030.c - --------- - All methods of this file are moved to another location. - void twl4030_power_reset_init(void): Move to board hacks - void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp, - u8 dev_grp_sel): Move to board hacks - void twl4030_power_init(void): Move to board hacks - void twl4030_power_mmc_init(void): Move to board hacks - - twl6030.c - --------- - Some methods are converted to new API and rest are moved to another location. - void twl6030_stop_usb_charging(void): Convert to new API - void twl6030_start_usb_charging(void): Convert to new API - int twl6030_get_battery_current(void): Convert to new API - int twl6030_get_battery_voltage(void): Convert to new API - void twl6030_init_battery_charging(void): Convert to new API - void twl6030_power_mmc_init(): Move to board file - drivers/mmc/omap_hsmmc.c - void twl6030_usb_device_settings(): Move to board file - drivers/usb/musb/omap3.c diff --git a/doc/driver-model/UDM-rtc.txt b/doc/driver-model/UDM-rtc.txt deleted file mode 100644 index 3640d24c28..0000000000 --- a/doc/driver-model/UDM-rtc.txt +++ /dev/null @@ -1,253 +0,0 @@ -============================= -RTC device subsystem analysis -============================= - -Tomas Hlavacek -2012-03-10 - -I) Overview ------------ - -U-Boot currently implements one common API for RTC devices. The interface -is defined in include/rtc.h and comprises of functions and structures: - - struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; - }; - - int rtc_get (struct rtc_time *); - int rtc_set (struct rtc_time *); - void rtc_reset (void); - -The functions are implemented by a proper device driver in drivers/rtc -directory and the driver to be compiled in is selected in a Makefile. -Drivers are mutually exclusive. - -Drivers depends on date code in drivers/rtc/date.c and naturally on board -specific data. - -II) Approach ------------- - - 1) New API - ---------- - In the UDM each rtc driver would register itself by a function - - int rtc_device_register(struct instance *i, - struct rtc_device_ops *o); - - The structure being defined as follows: - - struct rtc_device_ops { - int (*get_time)(struct instance *i, struct rtc_time *t); - int (*set_time)(struct instance *i, struct rtc_time *t); - int (*reset)(struct instance *i); - }; - - - 2) Conversion thougths - ---------------------- - U-Boot RTC drivers exports the same functions and therefore the conversion - of the drivers is straight-forward. There is no initialization needed. - - -III) Analysis of in-tree drivers --------------------------------- - - drivers/rtc/rv3029.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/s3c24x0_rtc.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/pt7c4338.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mvrtc.c - ------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ftrtc010.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mpc5xxx.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds164x.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/rs5c372.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/m41t94.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mc13xxx-rtc.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mcfrtc.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/davinci.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/rx8025.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/bfin_rtc.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/m41t62.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1306.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mpc8xx.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds3231.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds12887.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1302.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1374.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds174x.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/m41t60.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/m48t35ax.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/pl031.c - ------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/x1205.c - ------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/m41t11.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/pcf8563.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mk48t59.c - --------------------- - Macros needs cleanup. Besides that the driver is standard rtc. - Simple conversion is possible. - - - drivers/rtc/mxsrtc.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1307.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1556.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/rtc4543.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/ds1337.c - -------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/isl1208.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/max6900.c - --------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/mc146818.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - drivers/rtc/at91sam9_rtt.c - -------------------------- - The driver is standard rtc. Simple conversion is possible. diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt deleted file mode 100644 index 279e941fc0..0000000000 --- a/doc/driver-model/UDM-serial.txt +++ /dev/null @@ -1,159 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Serial I/O analysis -=================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The serial port support currently requires the driver to export the following -functions: - - serial_putc() ...... Output a character - serial_puts() ...... Output string, often done using serial_putc() - serial_tstc() ...... Test if incoming character is in a buffer - serial_getc() ...... Retrieve incoming character - serial_setbrg() .... Configure port options - serial_init() ...... Initialize the hardware - -The simpliest implementation, supporting only one port, simply defines these six -functions and calls them. Such calls are scattered all around U-Boot, especiall -serial_putc(), serial_puts(), serial_tstc() and serial_getc(). The serial_init() -and serial_setbrg() are often called from platform-dependent places. - -It's important to consider current implementation of CONFIG_SERIAL_MULTI though. -This resides in common/serial.c and behaves as a multiplexer for serial ports. -This, by calling serial_assign(), allows user to switch I/O from one serial port -to another. Though the environmental variables "stdin", "stdout", "stderr" -remain set to "serial". - -These variables are managed by the IOMUX. This resides in common/iomux.c and -manages all console input/output from U-Boot. For serial port, only one IOMUX is -always registered, called "serial" and the switching of different serial ports -is done by code in common/serial.c. - -On a final note, it's important to mention function default_serial_console(), -which is platform specific and reports the default serial console for the -platform, unless proper environment variable overrides this. - -II) Approach ------------- - -Drivers not using CONFIG_SERIAL_MULTI already will have to be converted to -similar approach. The probe() function of a driver will call a function -registering the driver with a STDIO subsystem core, stdio_device_register(). - -The serial_init() function will now be replaced by probe() function of the -driver, the rest of the components of the driver will be converted to standard -STDIO driver calls. See [ UDM-stdio.txt ] for details. - -The serial_setbrg() function depends on global data pointer. This is wrong, -since there is likely to be user willing to configure different baudrate on two -different serial ports. The function will be replaced with STDIO's "conf()" -call, with STDIO_CONFIG_SERIAL_BAUDRATE argument. - -III) Analysis of in-tree drivers --------------------------------- - - altera_jtag_uart.c - ------------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - altera_uart.c - ------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - arm_dcc.c - --------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible, unless used - with CONFIG_ARM_DCC_MULTI. Then it registers another separate IOMUX. - - atmel_usart.c - ------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - mcfuart.c - --------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - ns16550.c - --------- - This driver seems complicated and certain consideration will need to be made - during conversion. This driver is implemented in very universal manner, - therefore it'll be necessary to properly design it's platform_data. - - opencores_yanu.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - sandbox.c - --------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial.c - -------- - This is a complementary part of NS16550 UART driver, see above. - - serial_imx.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver - might be removed in favor of serial_mxc.c . - - serial_ixp.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_ks8695.c - --------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_max3100.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_mxc.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_pl01x.c - -------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this - driver in fact contains two drivers in total. - - serial_pxa.c - ------------ - This driver is a bit complicated, but due to clean support for - CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the - conversion process. - - serial_s3c24x0.c - ---------------- - This driver, being quite ad-hoc might need some work to bring back to shape. - - serial_s5p.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_sa1100.c - --------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_sh.c - ----------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - serial_xuartlite.c - ------------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - usbtty.c - -------- - This driver seems very complicated and entangled with USB framework. The - conversion might be complicated here. - - arch/powerpc/cpu/mpc512x/serial.c - --------------------------------- - This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to - proper place. diff --git a/doc/driver-model/UDM-spi.txt b/doc/driver-model/UDM-spi.txt deleted file mode 100644 index 9ba0f841ef..0000000000 --- a/doc/driver-model/UDM-spi.txt +++ /dev/null @@ -1,200 +0,0 @@ -The U-Boot Driver Model Project -=============================== -SPI analysis -============ -Viktor Krivak -2012-03-03 - -I) Overview ------------ - - 1) The SPI driver - ----------------- - - At this moment U-Boot provides standard API that consist of 7 functions: - - void spi_init(void); - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); - void spi_free_slave(struct spi_slave *slave); - int spi_claim_bus(struct spi_slave *slave); - void spi_release_bus(struct spi_slave *slave); - int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags); - int spi_cs_is_valid(unsigned int bus, unsigned int cs); - void spi_cs_activate(struct spi_slave *slave); - void spi_cs_deactivate(struct spi_slave *slave); - void spi_set_speed(struct spi_slave *slave, uint hz); - - Method spi_init() is usually empty. All necessary configuration are sets by - spi_setup_slave(). But this configuration is usually stored only in memory. - No real hardware sets are made. All hardware settings are provided by method - spi_claim_bus(). This method claims the bus and it can't be claimed again - until it's release. That's mean all calls of method spi_claim_bus() will - fail. But lots of cpu implementation don't meet this behaviour. - Method spi_release_bus() does exact opposite. It release bus directly by - some hardware sets. spi_free_slave() only free memory allocated by - spi_setup_slave(). Method spi_xfer() do actually read and write operation - throw specified bus and cs. Other methods are self explanatory. - - 2) Current limitations - ---------------------- - - Theoretically at this moment api allows use more then one bus per device at - the time. But in real this can be achieved only when all buses have their - own base addresses in memory. - - -II) Approach ------------- - - 1) Claiming bus - --------------- - - The current api cannot be used because struct spi_slave have to be in - private data. In that case user are prohibited to use different bus on one - device at same time. But when base memory address for bus are different. - It's possible make more instance of this driver. Otherwise it can't can be - done because of hardware limitation. - - 2) API change - ------------- - - Method spi_init() is moved to probe. Methods spi_setup_slave() and - spi_claim_bus() are joined to one method. This method checks if desired bus - exists and is available then configure necessary hardware and claims bus. - Method spi_release_bus() and spi_free_slave() are also joined to meet this - new approach. Other function remain same. Only struct spi_slave was change - to instance. - - struct ops { - int (*spi_request_bus)(struct instance *i, unsigned int bus, - unsigned int cs, unsigned int max_hz, - unsigned int mode); - void (*spi_release_bus)(struct instance *i); - int (*spi_xfer) (struct instance *i, unsigned int bitlen, - const void *dout, void *din, unsigned long flags); - int (*spi_cs_is_valid)(struct instance *i, unsigned int bus, - unsigned int cs); - void (*spi_cs_activate)(struct instance *i); - void (*spi_cs_deactivate)(struct instance *i); - void (*spi_set_speed)(struct instance *i, uint hz); - } - - 3) Legacy API - ------------- - - To easy conversion of the whole driver. Original and new api can exist next - to each other. New API is designed to be only a wrapper that extracts - necessary information from private_data and use old api. When driver can - use more than one bus at the time. New API require multiple instance. One - for each bus. In this case spi_slave have to be copied in each instance. - - 4) Conversion TIME-LINE - ----------------------- - - To prevent build corruption api conversion have to be processed in several - independent steps. In first step all old API methods are renamed. After that - new API and core function are implemented. Next step is conversion of all - board init methods to set platform data. After all these steps it is possible - to start conversion of all remaining calls. This procedure guarantees that - build procedure and binaries are never broken. - -III) Analysis of in-tree drivers --------------------------------- - - altera_spi.c - ------------ - All methods have designated structure. Simple conversion possible. - - andes_spi.c - ----------- - All methods have designated structure. Simple conversion possible. - - andes_spi.h - ----------- - Support file for andes_spi.c. No conversion is needed. - - armada100_spi.c - --------------- - All methods have designated structure. Simple conversion possible. - - atmel_dataflash_spi.c - --------------------- - Wrong placement. Will be moved to another location. - - atmel_spi.c - ----------- - Supports more than one bus. Need some minor change. - - atmel_spi.h - ----------- - Support file for andes_spi.c. No conversion is needed. - - bfin_spi.c - ---------- - Supports more than one bus. Need some minor change. - - cf_spi.c - -------- - Cooperate with some cpu specific methods from other files. Hard conversion. - - davinci_spi.c - ------------- - All methods have designated structure. Simple conversion possible. - - davinci_spi.h - ------------- - Support file for davinci_spi.h. No conversion is needed. - - fsl_espi.c - ---------- - All methods have designated structure. Simple conversion possible. - - kirkwood_spi.c - -------------- - All methods have designated structure. Simple conversion possible. - - mpc8xxx_spi.c - ------------- - All methods have designated structure. Simple conversion possible. - - mpc52xx_spi.c - ------------- - All methods have designated structure. Simple conversion possible. - - mxc_spi.c - --------- - All methods have designated structure. Simple conversion possible. - - mxs_spi.c - --------- - All methods have designated structure. Simple conversion possible. - - oc_tiny_spi.c - ------------- - Supports more than one bus. Need some minor change. - - omap3_spi.c - ----------- - Supports more than one bus. Need some minor change. - - omap3_spi.h - ----------- - Support file for omap3_spi.c. No conversion is needed. - - sh_spi.c - -------- - All methods have designated structure. Simple conversion possible. - - sh_spi.h - -------- - Support file for sh_spi.h. No conversion is needed. - - soft_spi.c - ---------- - Use many board specific method linked from other files. Need careful debugging. - - tegra2_spi.c - ------------ - Some hardware specific problem when releasing bus. diff --git a/doc/driver-model/UDM-stdio.txt b/doc/driver-model/UDM-stdio.txt deleted file mode 100644 index 156627b515..0000000000 --- a/doc/driver-model/UDM-stdio.txt +++ /dev/null @@ -1,191 +0,0 @@ -The U-Boot Driver Model Project -=============================== -I/O system analysis -=================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The console input and output is currently done using the STDIO subsystem in -U-Boot. The design of this subsystem is already flexible enough to be easily -converted to new driver model approach. Minor changes will need to be done -though. - -Each device that wants to register with STDIO subsystem has to define struct -stdio_dev, defined in include/stdio_dev.h and containing the following fields: - -struct stdio_dev { - int flags; /* Device flags: input/output/system */ - int ext; /* Supported extensions */ - char name[16]; /* Device name */ - -/* GENERAL functions */ - - int (*start) (void); /* To start the device */ - int (*stop) (void); /* To stop the device */ - -/* OUTPUT functions */ - - void (*putc) (const char c); /* To put a char */ - void (*puts) (const char *s); /* To put a string (accelerator) */ - -/* INPUT functions */ - - int (*tstc) (void); /* To test if a char is ready... */ - int (*getc) (void); /* To get that char */ - -/* Other functions */ - - void *priv; /* Private extensions */ - struct list_head list; -}; - -Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM, -extensions being only one, the DEV_EXT_VIDEO. - -The private extensions are now used as a per-device carrier of private data and -finally list allows this structure to be a member of linked list of STDIO -devices. - -The STDIN, STDOUT and STDERR routing is handled by environment variables -"stdin", "stdout" and "stderr". By configuring the variable to the name of a -driver, functions of such driver are called to execute that particular -operation. - -II) Approach ------------- - - 1) Similarity of serial, video and keyboard drivers - --------------------------------------------------- - - All of these drivers can be unified under the STDIO subsystem if modified - slightly. The serial drivers basically define both input and output functions - and need function to configure baudrate. The keyboard drivers provide only - input. On the other hand, video drivers provide output, but need to be - configured in certain way. This configuration might be dynamic, therefore the - STDIO has to be modified to provide such flexibility. - - 2) Unification of serial, video and keyboard drivers - ---------------------------------------------------- - - Every STDIO device would register a structure containing operation it supports - with the STDIO core by calling: - - int stdio_device_register(struct instance *i, struct stdio_device_ops *o); - - The structure being defined as follows: - - struct stdio_device_ops { - void (*putc)(struct instance *i, const char c); - void (*puts)(struct instance *i, const char *s); /* OPTIONAL */ - - int (*tstc)(struct instance *i); - int (*getc)(struct instance *i); - - int (*init)(struct instance *i); - int (*exit)(struct instance *i); - int (*conf)(struct instance *i, enum stdio_config c, const void *data); - }; - - The "putc()" function will emit a character, the "puts()" function will emit a - string. If both of these are set to NULL, the device is considered STDIN only, - aka input only device. - - The "getc()" retrieves a character from a STDIN device, while "tstc()" tests - if there is a character in the buffer of STDIN device. In case these two are - set to NULL, this device is STDOUT / STDERR device. - - Setting all "putc()", "puts()", "getc()" and "tstc()" calls to NULL isn't an - error condition, though such device does nothing. By instroducing tests for - these functions being NULL, the "flags" and "ext" fields from original struct - stdio_dev can be eliminated. - - The "init()" and "exit()" calls are replacement for "start()" and "exit()" - calls in the old approach. The "priv" part of the old struct stdio_dev will be - replaced by common private data in the driver model and the struct list_head - list will be eliminated by introducing common STDIO core, that tracks all the - STDIO devices. - - Lastly, the "conf()" call will allow the user to configure various options of - the driver. The enum stdio_config contains all possible configuration options - available to the STDIO devices, const void *data being the argument to be - configured. Currently, the enum stdio_config will contain at least the - following options: - - enum stdio_config { - STDIO_CONFIG_SERIAL_BAUDRATE, - }; - - 3) Transformation of stdio routing - ---------------------------------- - - By allowing multiple instances of drivers, the environment variables "stdin", - "stdout" and "stderr" can no longer be set to the name of the driver. - Therefore the STDIO core, tracking all of the STDIO devices in the system will - need to have a small amount of internal data for each device: - - struct stdio_device_node { - struct instance *i; - struct stdio_device_ops *ops; - uint8_t id; - uint8_t flags; - struct list_head list; - } - - The "id" is the order of the instance of the same driver. The "flags" variable - allows multiple drivers to be used at the same time and even for different - purpose. The following flags will be defined: - - STDIO_FLG_STDIN ..... This device will be used as an input device. All input - from all devices with this flag set will be received - and passed to the upper layers. - STDIO_FLG_STDOUT .... This device will be used as an output device. All - output sent to stdout will be routed to all devices - with this flag set. - STDIO_FLG_STDERR .... This device will be used as an standard error output - device. All output sent to stderr will be routed to - all devices with this flag set. - - The "list" member of this structure allows to have a linked list of all - registered STDIO devices. - -III) Analysis of in-tree drivers --------------------------------- - -For in-depth analysis of serial port drivers, refer to [ UDM-serial.txt ]. -For in-depth analysis of keyboard drivers, refer to [ UDM-keyboard.txt ]. -For in-depth analysis of video drivers, refer to [ UDM-video.txt ]. - - arch/blackfin/cpu/jtag-console.c - -------------------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - - board/mpl/pati/pati.c - --------------------- - This driver registers with the STDIO framework, though it uses a lot of ad-hoc - stuff which will need to be sorted out. - - board/netphone/phone_console.c - ------------------------------ - This driver is a classic STDIO driver, no problem with conversion is expected. - - drivers/net/netconsole.c - ------------------------ - This driver is a classic STDIO driver, no problem with conversion is expected. - -IV) Other involved files (To be removed) ----------------------------------------- - -common/cmd_console.c -common/cmd_log.c -common/cmd_terminal.c -common/console.c -common/fdt_support.c -common/iomux.c -common/lcd.c -common/serial.c -common/stdio.c -common/usb_kbd.c -doc/README.iomux diff --git a/doc/driver-model/UDM-tpm.txt b/doc/driver-model/UDM-tpm.txt deleted file mode 100644 index 0beff4a857..0000000000 --- a/doc/driver-model/UDM-tpm.txt +++ /dev/null @@ -1,48 +0,0 @@ -The U-Boot Driver Model Project -=============================== -TPM system analysis -=================== -Marek Vasut -2012-02-23 - -I) Overview ------------ - -There is currently only one TPM chip driver available and therefore the API -controlling it is very much based on this. The API is very simple: - - int tis_open(void); - int tis_close(void); - int tis_sendrecv(const u8 *sendbuf, size_t send_size, - u8 *recvbuf, size_t *recv_len); - -The command operating the TPM chip only provides operations to send and receive -bytes from the chip. - -II) Approach ------------- - -The API can't be generalised too much considering there's only one TPM chip -supported. But it's a good idea to split the tis_sendrecv() function in two -functions. Therefore the new API will use register the TPM chip by calling: - - tpm_device_register(struct instance *i, const struct tpm_ops *ops); - -And the struct tpm_ops will contain the following members: - - struct tpm_ops { - int (*tpm_open)(struct instance *i); - int (*tpm_close)(struct instance *i); - int (*tpm_send)(const uint8_t *buf, const size_t size); - int (*tpm_recv)(uint8_t *buf, size_t *size); - }; - -The behaviour of "tpm_open()" and "tpm_close()" will basically copy the -behaviour of "tis_open()" and "tis_close()". The "tpm_send()" will be based on -the "tis_senddata()" and "tis_recv()" will be based on "tis_readresponse()". - -III) Analysis of in-tree drivers --------------------------------- - -There is only one in-tree driver present, the "drivers/tpm/generic_lpc_tpm.c", -which will be simply converted as outlined in previous chapter. diff --git a/doc/driver-model/UDM-twserial.txt b/doc/driver-model/UDM-twserial.txt deleted file mode 100644 index 5f2c5a3d40..0000000000 --- a/doc/driver-model/UDM-twserial.txt +++ /dev/null @@ -1,47 +0,0 @@ -================================== -TWserial device subsystem analysis -================================== - -Tomas Hlavacek -2012-03-21 - -I) Overview ------------ - -U-Boot currently implements one common API for TWSerial devices. The interface -is defined in include/tws.h and comprises of functions: - - int tws_read(uchar *buffer, int len); - int tws_write(uchar *buffer, int len); - -The functions are implemented by a proper device driver in drivers/twserial -directory and the driver to be compiled in is selected in a Makefile. There is -only one driver present now. - -The driver depends on ad-hoc code in board specific data, namely functions: - - void tws_ce(unsigned bit); - void tws_wr(unsigned bit); - void tws_clk(unsigned bit); - void tws_data(unsigned bit); - unsigned tws_data_read(void); - void tws_data_config_output(unsigned output); - -implemented in include/configs/inka4x0.h . - -II) Approach ------------- - - U-Boot TWserial drivers exports two simple functions and therefore the conversion - of the driver and creating a core for it is not needed. It should be consolidated - with include/configs/inka4x0.h and taken to the misc/ dir. - - -III) Analysis of in-tree drivers --------------------------------- - - drivers/twserial/soft_tws.c - --------------------------- - The driver is the only TWserial driver. The ad-hoc part in - include/configs/inka4x0.h and the core soft_tws driver should be consolidated - to one compact driver and moved to misc/ . diff --git a/doc/driver-model/UDM-usb.txt b/doc/driver-model/UDM-usb.txt deleted file mode 100644 index 5ce85b5d60..0000000000 --- a/doc/driver-model/UDM-usb.txt +++ /dev/null @@ -1,94 +0,0 @@ -The U-Boot Driver Model Project -=============================== -USB analysis -============ -Marek Vasut -2012-02-16 - -I) Overview ------------ - - 1) The USB Host driver - ---------------------- - There are basically four or five USB host drivers. All such drivers currently - provide at least the following fuctions: - - usb_lowlevel_init() ... Do the initialization of the USB controller hardware - usb_lowlevel_stop() ... Do the shutdown of the USB controller hardware - - usb_event_poll() ...... Poll interrupt from USB device, often used by KBD - - submit_control_msg() .. Submit message via Control endpoint - submit_int_msg() ...... Submit message via Interrupt endpoint - submit_bulk_msg() ..... Submit message via Bulk endpoint - - - This allows for the host driver to be easily abstracted. - - 2) The USB hierarchy - -------------------- - - In the current implementation, the USB Host driver provides operations to - communicate via the USB bus. This is realised by providing access to a USB - root port to which an USB root hub is attached. The USB bus is scanned and for - each newly found device, a struct usb_device is allocated. See common/usb.c - and include/usb.h for details. - -II) Approach ------------- - - 1) The USB Host driver - ---------------------- - - Converting the host driver will follow the classic driver model consideration. - Though, the host driver will have to call a function that registers a root - port with the USB core in it's probe() function, let's call this function - - usb_register_root_port(&ops); - - This will allow the USB core to track all available root ports. The ops - parameter will contain structure describing operations supported by the root - port: - - struct usb_port_ops { - void (*usb_event_poll)(); - int (*submit_control_msg)(); - int (*submit_int_msg)(); - int (*submit_bulk_msg)(); - } - - 2) The USB hierarchy and hub drivers - ------------------------------------ - - Converting the USB heirarchy should be fairy simple, considering the already - dynamic nature of the implementation. The current usb_hub_device structure - will have to be converted to a struct instance. Every such instance will - contain components of struct usb_device and struct usb_hub_device in it's - private data, providing only accessors in order to properly encapsulate the - driver. - - By registering the root port, the USB framework will instantiate a USB hub - driver, which is always present, the root hub. The root hub and any subsequent - hub instance is represented by struct instance and it's private data contain - amongst others common bits from struct usb_device. - - Note the USB hub driver is partly defying the usual method of registering a - set of callbacks to a particular core driver. Instead, a static set of - functions is defined and the USB hub instance is passed to those. This creates - certain restrictions as of how the USB hub driver looks, but considering the - specification for USB hub is given and a different type of USB hub won't ever - exist, this approach is ok: - - - Report how many ports does this hub have: - uint get_nr_ports(struct instance *hub); - - Get pointer to device connected to a port: - struct instance *(*get_child)(struct instance *hub, int port); - - Instantiate and configure device on port: - struct instance *(*enum_dev_on_port)(struct instance *hub, int port); - - 3) USB device drivers - --------------------- - - The USB device driver, in turn, will have to register various ops structures - with certain cores. For example, USB disc driver will have to register it's - ops with core handling USB discs etc. diff --git a/doc/driver-model/UDM-video.txt b/doc/driver-model/UDM-video.txt deleted file mode 100644 index e67e9e41b4..0000000000 --- a/doc/driver-model/UDM-video.txt +++ /dev/null @@ -1,74 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Video output analysis -===================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The video drivers are most often registered with video subsystem. This subsystem -often expects to be allowed access to framebuffer of certain parameters. This -subsystem also provides calls for STDIO subsystem to allow it to output -characters on the screen. For this part, see [ UDM-stdio.txt ]. - -Therefore the API has two parts, the video driver part and the part where the -video driver core registers with STDIO API. - -The video driver part will follow the current cfb_console approach, though -allowing it to be more dynamic. - -II) Approach ------------- - -Registering the video driver into the video driver core is done by calling the -following function from the driver probe() function: - - video_device_register(struct instance *i, GraphicDevice *gd); - -Because the video driver core is in charge or rendering characters as well as -bitmaps on the screen, it will in turn call stdio_device_register(i, so), where -"i" is the same instance as the video driver's one. But "so" will be special -static struct stdio_device_ops handling the character output. - - -III) Analysis of in-tree drivers --------------------------------- - - arch/powerpc/cpu/mpc8xx/video.c - ------------------------------- - This driver copies the cfb_console [ see drivers/video/cfb_console.c ] - approach and acts only as a STDIO device. Therefore there are currently two - possible approaches, first being the conversion of this driver to usual STDIO - device and second, long-term one, being conversion of this driver to video - driver that provides console. - - arch/x86/lib/video.c - -------------------- - This driver registers two separate STDIO devices and should be therefore - converted as such. - - board/bf527-ezkit/video.c - ------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - board/bf533-stamp/video.c - ------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - board/bf548-ezkit/video.c - ------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - board/cm-bf548/video.c - ---------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. diff --git a/doc/driver-model/UDM-watchdog.txt b/doc/driver-model/UDM-watchdog.txt deleted file mode 100644 index 3f130635dc..0000000000 --- a/doc/driver-model/UDM-watchdog.txt +++ /dev/null @@ -1,329 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Watchdog device subsystem analysis -================================== - -Tomas Hlavacek -2012-03-09 - -I) Overview ------------ - -U-Boot currently implements an API for HW watchdog devices as explicit drivers -in drivers/watchdog directory. There are also drivers for both hardware and -software watchdog on particular CPUs implemented in arch/*/cpu/*/cpu.c. There -are macros in include/watchdog.h that selects between SW and HW watchdog and -assembly SW implementation. - -The current common interface comprises of one set out of these two possible -variants: - - 1) - void watchdog_reset(void); - int watchdog_disable(void); - int watchdog_init(void); - - 2) - void hw_watchdog_reset(void); - void hw_watchdog_init(void); - -The watchdog implementations are also spread through board/*/*.c that in -some cases. The API and semantics is in most cases same as the above -mentioned common functions. - - -II) Approach ------------- - - 1) New API - ---------- - - In the UDM each watchdog driver would register itself by a function - - int watchdog_device_register(struct instance *i, - const struct watchdog_device_ops *o); - - The structure being defined as follows: - - struct watchdog_device_ops { - int (*disable)(struct instance *i); - void (*reset)(struct instance *i); - }; - - The watchdog_init() function will be dissolved into probe() function. - - 2) Conversion thougths - ---------------------- - - Conversion of watchdog implementations to a new API could be divided - to three subsections: a) HW implementations, which are mostly compliant - to the above mentioned API; b) SW implementations, which are compliant - to the above mentioned API and c) SW implementations that are not compliant - to the API and has to be rectified or partially rewritten. - -III) Analysis of in-tree drivers --------------------------------- - - drivers/watchdog/at91sam9_wdt.c - ------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - drivers/watchdog/ftwdt010_wdt.c - ------------------------------- - The driver is ad-hoc HW watchdog. Conversion has to take into account - driver parts spread in include/faraday/*. Restructuring the driver and - code cleanup has to be considered. - - - arch/arm/cpu/arm1136/mx31/timer.c - --------------------------------- - The driver is semi-standard ad-hoc HW watchdog. Conversion has to take - into account driver parts spread in the timer.c file. - - - arch/arm/cpu/arm926ejs/davinci/timer.c - -------------------------------------- - The driver is ad-hoc semi-standard HW watchdog. Conversion has to take - into account driver parts spread in the timer.c file. - - - arch/arm/cpu/armv7/omap-common/hwinit-common.c - ---------------------------------------------- - The driver is non-standard ad-hoc HW watchdog. Conversion is possible - but functions has to be renamed and constants moved to another places. - - - arch/arm/cpu/armv7/omap3/board.c - -------------------------------- - The driver is non-standard ad-hoc HW watchdog. Conversion is possible - but functions has to be renamed and constants moved to another places. - - - arch/blackfin/cpu/watchdog.c - ---------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/m68k/cpu/mcf523x/cpu.c - --------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/m68k/cpu/mcf52x2/cpu.c - --------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/m68k/cpu/mcf532x/cpu.c - --------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/m68k/cpu/mcf547x_8x/cpu.c - ------------------------------ - The driver is standard HW watchdog (there is slight naming convention - violation that has to be rectified). Simple conversion is possible. - - - arch/powerpc/cpu/74xx_7xx/cpu.c - ------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc512x/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc5xx/cpu.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc5xxx/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc8260/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc83xx/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc85xx/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc86xx/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/mpc8xx/cpu.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/powerpc/cpu/ppc4xx/cpu.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/sh/cpu/sh2/watchdog.c - -------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/sh/cpu/sh3/watchdog.c - -------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - arch/sh/cpu/sh4/watchdog.c - -------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/amcc/luan/luan.c - ---------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/amcc/yosemite/yosemite.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - board/apollon/apollon.c - ----------------------- - The driver is standard HW watchdog however the watchdog_init() - function is called in early initialization. Simple conversion is possible. - - - board/bmw/m48t59y.c - ------------------- - Special watchdog driver. Dead code. To be removed. - - - board/davedenx/qong/qong.c - -------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/dvlhost/watchdog.c - ------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - board/eNET/eNET.c - ----------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/eltec/elppc/elppc.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/enbw/enbw_cmc/enbw_cmc.c - ------------------------------ - Only function proxy call. Code cleanup needed. - - - board/freescale/mx31pdk/mx31pdk.c - --------------------------------- - Only function proxy call. Code cleanup needed. - - - board/gth2/gth2.c - ----------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/lwmon5/lwmon5.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/manroland/mucmc52/mucmc52.c - --------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/manroland/uc101/uc101.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/mousse/m48t59y.c - ---------------------- - Special watchdog driver. Dead code. To be removed. - - - board/mvblue/mvblue.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/netphone/netphone.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/netta/netta.c - ------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/netta2/netta2.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/omicron/calimain/calimain.c - --------------------------------- - Only function proxy call. Code cleanup needed. - - - board/pcs440ep/pcs440ep.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/stx/stxxtc/stxxtc.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/ti/omap2420h4/omap2420h4.c - -------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/ttcontrol/vision2/vision2.c - --------------------------------- - The driver is standard HW watchdog but namespace is polluted by - non-standard macros. Simple conversion is possible, code cleanup - needed. - - - board/v38b/v38b.c - ----------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/ve8313/ve8313.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - board/w7o/watchdog.c - -------------------- - The driver is standard HW watchdog. Simple conversion is possible. diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index 1c79c14a3b..16819c7754 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -19,22 +19,6 @@ Who: Tom Rini --------------------------- -What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL -When: Release v2013.07 - -Why: When set these options enable "all" of the pads and clocks found - on OMAP4/5 platforms, so that the Linux Kernel does not have to. - It has been agreed that this goes against the U-Boot design - philosophy and since f3f98bb0 we have not enabled more than is - used in U-Boot. The kernel has been updating drivers to enable - rather than assume pads/clocks have been enabled already. Our - expectation is that by v2013.07 a suitable kernel shall exist that - does not need these options set for a reasonable I/O set to function. - -Who: Tom Rini and Sricharan R - ---------------------------- - What: Users of the legacy miiphy_* code When: undetermined diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 52a2ceb475..e56356ee86 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -8,8 +8,5 @@ obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -EXTRA_CFLAGS += -I. -I./include \ +ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ -D__PPC__ -D__BIG_ENDIAN__ - -CFLAGS += $(EXTRA_CFLAGS) -CPPFLAGS += $(EXTRA_CFLAGS) diff --git a/drivers/bios_emulator/include/x86emu/prim_asm.h b/drivers/bios_emulator/include/x86emu/prim_asm.h deleted file mode 100644 index 4cb4cab5d5..0000000000 --- a/drivers/bios_emulator/include/x86emu/prim_asm.h +++ /dev/null @@ -1,970 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: Watcom C++ 10.6 or later -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Inline assembler versions of the primitive operand -* functions for faster performance. At the moment this is -* x86 inline assembler, but these functions could be replaced -* with native inline assembler for each supported processor -* platform. -* -****************************************************************************/ - -#ifndef __X86EMU_PRIM_ASM_H -#define __X86EMU_PRIM_ASM_H - -#ifdef __WATCOMC__ - -#ifndef VALIDATE -#define __HAVE_INLINE_ASSEMBLER__ -#endif - -u32 get_flags_asm(void); -#pragma aux get_flags_asm = \ - "pushf" \ - "pop eax" \ - value [eax] \ - modify exact [eax]; - -u16 aaa_word_asm(u32 * flags, u16 d); -#pragma aux aaa_word_asm = \ - "push [edi]" \ - "popf" \ - "aaa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aas_word_asm(u32 * flags, u16 d); -#pragma aux aas_word_asm = \ - "push [edi]" \ - "popf" \ - "aas" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aad_word_asm(u32 * flags, u16 d); -#pragma aux aad_word_asm = \ - "push [edi]" \ - "popf" \ - "aad" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aam_word_asm(u32 * flags, u8 d); -#pragma aux aam_word_asm = \ - "push [edi]" \ - "popf" \ - "aam" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [ax] \ - modify exact [ax]; - -u8 adc_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux adc_byte_asm = \ - "push [edi]" \ - "popf" \ - "adc al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 adc_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux adc_word_asm = \ - "push [edi]" \ - "popf" \ - "adc ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 adc_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux adc_long_asm = \ - "push [edi]" \ - "popf" \ - "adc eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 add_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux add_byte_asm = \ - "push [edi]" \ - "popf" \ - "add al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 add_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux add_word_asm = \ - "push [edi]" \ - "popf" \ - "add ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 add_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux add_long_asm = \ - "push [edi]" \ - "popf" \ - "add eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 and_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux and_byte_asm = \ - "push [edi]" \ - "popf" \ - "and al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 and_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux and_word_asm = \ - "push [edi]" \ - "popf" \ - "and ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 and_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux and_long_asm = \ - "push [edi]" \ - "popf" \ - "and eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 cmp_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux cmp_byte_asm = \ - "push [edi]" \ - "popf" \ - "cmp al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 cmp_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux cmp_word_asm = \ - "push [edi]" \ - "popf" \ - "cmp ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 cmp_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux cmp_long_asm = \ - "push [edi]" \ - "popf" \ - "cmp eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 daa_byte_asm(u32 * flags, u8 d); -#pragma aux daa_byte_asm = \ - "push [edi]" \ - "popf" \ - "daa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 das_byte_asm(u32 * flags, u8 d); -#pragma aux das_byte_asm = \ - "push [edi]" \ - "popf" \ - "das" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 dec_byte_asm(u32 * flags, u8 d); -#pragma aux dec_byte_asm = \ - "push [edi]" \ - "popf" \ - "dec al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 dec_word_asm(u32 * flags, u16 d); -#pragma aux dec_word_asm = \ - "push [edi]" \ - "popf" \ - "dec ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 dec_long_asm(u32 * flags, u32 d); -#pragma aux dec_long_asm = \ - "push [edi]" \ - "popf" \ - "dec eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 inc_byte_asm(u32 * flags, u8 d); -#pragma aux inc_byte_asm = \ - "push [edi]" \ - "popf" \ - "inc al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 inc_word_asm(u32 * flags, u16 d); -#pragma aux inc_word_asm = \ - "push [edi]" \ - "popf" \ - "inc ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 inc_long_asm(u32 * flags, u32 d); -#pragma aux inc_long_asm = \ - "push [edi]" \ - "popf" \ - "inc eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 or_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux or_byte_asm = \ - "push [edi]" \ - "popf" \ - "or al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 or_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux or_word_asm = \ - "push [edi]" \ - "popf" \ - "or ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 or_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux or_long_asm = \ - "push [edi]" \ - "popf" \ - "or eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 neg_byte_asm(u32 * flags, u8 d); -#pragma aux neg_byte_asm = \ - "push [edi]" \ - "popf" \ - "neg al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 neg_word_asm(u32 * flags, u16 d); -#pragma aux neg_word_asm = \ - "push [edi]" \ - "popf" \ - "neg ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 neg_long_asm(u32 * flags, u32 d); -#pragma aux neg_long_asm = \ - "push [edi]" \ - "popf" \ - "neg eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 not_byte_asm(u32 * flags, u8 d); -#pragma aux not_byte_asm = \ - "push [edi]" \ - "popf" \ - "not al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 not_word_asm(u32 * flags, u16 d); -#pragma aux not_word_asm = \ - "push [edi]" \ - "popf" \ - "not ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 not_long_asm(u32 * flags, u32 d); -#pragma aux not_long_asm = \ - "push [edi]" \ - "popf" \ - "not eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 rcl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcl_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcl_word_asm = \ - "push [edi]" \ - "popf" \ - "rcl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcl_long_asm = \ - "push [edi]" \ - "popf" \ - "rcl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rcr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcr_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcr_word_asm = \ - "push [edi]" \ - "popf" \ - "rcr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcr_long_asm = \ - "push [edi]" \ - "popf" \ - "rcr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rol_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rol_byte_asm = \ - "push [edi]" \ - "popf" \ - "rol al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rol_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rol_word_asm = \ - "push [edi]" \ - "popf" \ - "rol ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rol_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rol_long_asm = \ - "push [edi]" \ - "popf" \ - "rol eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 ror_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux ror_byte_asm = \ - "push [edi]" \ - "popf" \ - "ror al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 ror_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux ror_word_asm = \ - "push [edi]" \ - "popf" \ - "ror ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 ror_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux ror_long_asm = \ - "push [edi]" \ - "popf" \ - "ror eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shl_byte_asm = \ - "push [edi]" \ - "popf" \ - "shl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shl_word_asm = \ - "push [edi]" \ - "popf" \ - "shl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shl_long_asm = \ - "push [edi]" \ - "popf" \ - "shl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shr_byte_asm = \ - "push [edi]" \ - "popf" \ - "shr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shr_word_asm = \ - "push [edi]" \ - "popf" \ - "shr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shr_long_asm = \ - "push [edi]" \ - "popf" \ - "shr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 sar_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sar_byte_asm = \ - "push [edi]" \ - "popf" \ - "sar al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 sar_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux sar_word_asm = \ - "push [edi]" \ - "popf" \ - "sar ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 sar_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux sar_long_asm = \ - "push [edi]" \ - "popf" \ - "sar eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shld_word_asm = \ - "push [edi]" \ - "popf" \ - "shld ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shld_long_asm = \ - "push [edi]" \ - "popf" \ - "shld eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shrd_word_asm = \ - "push [edi]" \ - "popf" \ - "shrd ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shrd_long_asm = \ - "push [edi]" \ - "popf" \ - "shrd eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u8 sbb_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sbb_byte_asm = \ - "push [edi]" \ - "popf" \ - "sbb al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sbb_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sbb_word_asm = \ - "push [edi]" \ - "popf" \ - "sbb ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sbb_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sbb_long_asm = \ - "push [edi]" \ - "popf" \ - "sbb eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 sub_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sub_byte_asm = \ - "push [edi]" \ - "popf" \ - "sub al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sub_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sub_word_asm = \ - "push [edi]" \ - "popf" \ - "sub ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sub_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sub_long_asm = \ - "push [edi]" \ - "popf" \ - "sub eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void test_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux test_byte_asm = \ - "push [edi]" \ - "popf" \ - "test al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - modify exact [al bl]; - -void test_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux test_word_asm = \ - "push [edi]" \ - "popf" \ - "test ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - modify exact [ax bx]; - -void test_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux test_long_asm = \ - "push [edi]" \ - "popf" \ - "test eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - modify exact [eax ebx]; - -u8 xor_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux xor_byte_asm = \ - "push [edi]" \ - "popf" \ - "xor al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 xor_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux xor_word_asm = \ - "push [edi]" \ - "popf" \ - "xor ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 xor_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux xor_long_asm = \ - "push [edi]" \ - "popf" \ - "xor eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux imul_byte_asm = \ - "push [edi]" \ - "popf" \ - "imul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux imul_word_asm = \ - "push [edi]" \ - "popf" \ - "imul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux imul_long_asm = \ - "push [edi]" \ - "popf" \ - "imul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux mul_byte_asm = \ - "push [edi]" \ - "popf" \ - "mul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux mul_word_asm = \ - "push [edi]" \ - "popf" \ - "mul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux mul_long_asm = \ - "push [edi]" \ - "popf" \ - "mul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux idiv_byte_asm = \ - "push [edi]" \ - "popf" \ - "idiv bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux idiv_word_asm = \ - "push [edi]" \ - "popf" \ - "idiv bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux idiv_long_asm = \ - "push [edi]" \ - "popf" \ - "idiv ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux div_byte_asm = \ - "push [edi]" \ - "popf" \ - "div bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux div_word_asm = \ - "push [edi]" \ - "popf" \ - "div bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux div_long_asm = \ - "push [edi]" \ - "popf" \ - "div ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -#endif - -#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index e64df4f98d..c8f65739e9 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS]; #define WAIT_MS_SPINUP 20000 #define WAIT_MS_DATAIO 5000 #define WAIT_MS_FLUSH 5000 -#define WAIT_MS_LINKUP 4 +#define WAIT_MS_LINKUP 40 static inline u32 ahci_port_base(u32 base, u32 port) { @@ -623,6 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; + u16 *idbuf; ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; @@ -649,17 +650,25 @@ static int ata_scsiop_inquiry(ccb *pccb) return -EIO; } - if (ataid[port]) - free(ataid[port]); - ataid[port] = tmpid; - ata_swap_buf_le16(tmpid, ATA_ID_WORDS); + if (!ataid[port]) { + ataid[port] = malloc(ATA_ID_WORDS * 2); + if (!ataid[port]) { + printf("%s: No memory for ataid[port]\n", __func__); + return -ENOMEM; + } + } + + idbuf = ataid[port]; + + memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); + ata_swap_buf_le16(idbuf, ATA_ID_WORDS); memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4); + ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); #ifdef DEBUG - ata_dump_id(tmpid); + ata_dump_id(idbuf); #endif return 0; } @@ -930,6 +939,11 @@ int ahci_init(u32 base) err_out: return rc; } + +void __weak scsi_init(void) +{ +} + #endif /* diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index 27ecaf4f9e..b7fd1cd634 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index bed6971aa5..6f1c419c7a 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o +obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c new file mode 100644 index 0000000000..e27b168c55 --- /dev/null +++ b/drivers/bootcount/bootcount_i2c.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BC_MAGIC 0xbc + +void bootcount_store(ulong a) +{ + unsigned char buf[3]; + int ret; + + buf[0] = BC_MAGIC; + buf[1] = (a & 0xff); + ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) + puts("Error writing bootcount\n"); +} + +ulong bootcount_load(void) +{ + unsigned char buf[3]; + int ret; + + ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) { + puts("Error loading bootcount\n"); + return 0; + } + if (buf[0] == BC_MAGIC) + return buf[1]; + + bootcount_store(0); + + return 0; +} diff --git a/drivers/core/Makefile b/drivers/core/Makefile new file mode 100644 index 0000000000..90b2a7f068 --- /dev/null +++ b/drivers/core/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM) := device.o lists.o root.o uclass.o util.o diff --git a/drivers/core/device.c b/drivers/core/device.c new file mode 100644 index 0000000000..55ba281be0 --- /dev/null +++ b/drivers/core/device.c @@ -0,0 +1,348 @@ +/* + * Device manager + * + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * device_chld_unbind() - Unbind all device's children from the device + * + * On error, the function continues to unbind all children, and reports the + * first error. + * + * @dev: The device that is to be stripped of its children + * @return 0 on success, -ve on error + */ +static int device_chld_unbind(struct device *dev) +{ + struct device *pos, *n; + int ret, saved_ret = 0; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_unbind(pos); + if (ret && !saved_ret) + saved_ret = ret; + } + + return saved_ret; +} + +/** + * device_chld_remove() - Stop all device's children + * @dev: The device whose children are to be removed + * @return 0 on success, -ve on error + */ +static int device_chld_remove(struct device *dev) +{ + struct device *pos, *n; + int ret; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_remove(pos); + if (ret) + return ret; + } + + return 0; +} + +int device_bind(struct device *parent, struct driver *drv, const char *name, + void *platdata, int of_offset, struct device **devp) +{ + struct device *dev; + struct uclass *uc; + int ret = 0; + + *devp = NULL; + if (!name) + return -EINVAL; + + ret = uclass_get(drv->id, &uc); + if (ret) + return ret; + + dev = calloc(1, sizeof(struct device)); + if (!dev) + return -ENOMEM; + + INIT_LIST_HEAD(&dev->sibling_node); + INIT_LIST_HEAD(&dev->child_head); + INIT_LIST_HEAD(&dev->uclass_node); + dev->platdata = platdata; + dev->name = name; + dev->of_offset = of_offset; + dev->parent = parent; + dev->driver = drv; + dev->uclass = uc; + if (!dev->platdata && drv->platdata_auto_alloc_size) + dev->flags |= DM_FLAG_ALLOC_PDATA; + + /* put dev into parent's successor list */ + if (parent) + list_add_tail(&dev->sibling_node, &parent->child_head); + + ret = uclass_bind_device(dev); + if (ret) + goto fail_bind; + + /* if we fail to bind we remove device from successors and free it */ + if (drv->bind) { + ret = drv->bind(dev); + if (ret) { + if (uclass_unbind_device(dev)) { + dm_warn("Failed to unbind dev '%s' on error path\n", + dev->name); + } + goto fail_bind; + } + } + if (parent) + dm_dbg("Bound device %s to %s\n", dev->name, parent->name); + *devp = dev; + + return 0; + +fail_bind: + list_del(&dev->sibling_node); + free(dev); + return ret; +} + +int device_bind_by_name(struct device *parent, const struct driver_info *info, + struct device **devp) +{ + struct driver *drv; + + drv = lists_driver_lookup_name(info->name); + if (!drv) + return -ENOENT; + + return device_bind(parent, drv, info->name, (void *)info->platdata, + -1, devp); +} + +int device_unbind(struct device *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (dev->flags & DM_FLAG_ACTIVATED) + return -EINVAL; + + drv = dev->driver; + assert(drv); + + if (drv->unbind) { + ret = drv->unbind(dev); + if (ret) + return ret; + } + + ret = device_chld_unbind(dev); + if (ret) + return ret; + + ret = uclass_unbind_device(dev); + if (ret) + return ret; + + if (dev->parent) + list_del(&dev->sibling_node); + free(dev); + + return 0; +} + +/** + * device_free() - Free memory buffers allocated by a device + * @dev: Device that is to be started + */ +static void device_free(struct device *dev) +{ + int size; + + if (dev->driver->priv_auto_alloc_size) { + free(dev->priv); + dev->priv = NULL; + } + if (dev->flags & DM_FLAG_ALLOC_PDATA) { + free(dev->platdata); + dev->platdata = NULL; + } + size = dev->uclass->uc_drv->per_device_auto_alloc_size; + if (size) { + free(dev->uclass_priv); + dev->uclass_priv = NULL; + } +} + +int device_probe(struct device *dev) +{ + struct driver *drv; + int size = 0; + int ret; + + if (!dev) + return -EINVAL; + + if (dev->flags & DM_FLAG_ACTIVATED) + return 0; + + drv = dev->driver; + assert(drv); + + /* Allocate private data and platdata if requested */ + if (drv->priv_auto_alloc_size) { + dev->priv = calloc(1, drv->priv_auto_alloc_size); + if (!dev->priv) { + ret = -ENOMEM; + goto fail; + } + } + /* Allocate private data if requested */ + if (dev->flags & DM_FLAG_ALLOC_PDATA) { + dev->platdata = calloc(1, drv->platdata_auto_alloc_size); + if (!dev->platdata) { + ret = -ENOMEM; + goto fail; + } + } + size = dev->uclass->uc_drv->per_device_auto_alloc_size; + if (size) { + dev->uclass_priv = calloc(1, size); + if (!dev->uclass_priv) { + ret = -ENOMEM; + goto fail; + } + } + + /* Ensure all parents are probed */ + if (dev->parent) { + ret = device_probe(dev->parent); + if (ret) + goto fail; + } + + if (drv->ofdata_to_platdata && dev->of_offset >= 0) { + ret = drv->ofdata_to_platdata(dev); + if (ret) + goto fail; + } + + if (drv->probe) { + ret = drv->probe(dev); + if (ret) + goto fail; + } + + dev->flags |= DM_FLAG_ACTIVATED; + + ret = uclass_post_probe_device(dev); + if (ret) { + dev->flags &= ~DM_FLAG_ACTIVATED; + goto fail_uclass; + } + + return 0; +fail_uclass: + if (device_remove(dev)) { + dm_warn("%s: Device '%s' failed to remove on error path\n", + __func__, dev->name); + } +fail: + device_free(dev); + + return ret; +} + +int device_remove(struct device *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (!(dev->flags & DM_FLAG_ACTIVATED)) + return 0; + + drv = dev->driver; + assert(drv); + + ret = uclass_pre_remove_device(dev); + if (ret) + return ret; + + ret = device_chld_remove(dev); + if (ret) + goto err; + + if (drv->remove) { + ret = drv->remove(dev); + if (ret) + goto err_remove; + } + + device_free(dev); + + dev->flags &= ~DM_FLAG_ACTIVATED; + + return 0; + +err_remove: + /* We can't put the children back */ + dm_warn("%s: Device '%s' failed to remove, but children are gone\n", + __func__, dev->name); +err: + ret = uclass_post_probe_device(dev); + if (ret) { + dm_warn("%s: Device '%s' failed to post_probe on error path\n", + __func__, dev->name); + } + + return ret; +} + +void *dev_get_platdata(struct device *dev) +{ + if (!dev) { + dm_warn("%s: null device", __func__); + return NULL; + } + + return dev->platdata; +} + +void *dev_get_priv(struct device *dev) +{ + if (!dev) { + dm_warn("%s: null device", __func__); + return NULL; + } + + return dev->priv; +} diff --git a/drivers/core/lists.c b/drivers/core/lists.c new file mode 100644 index 0000000000..4f2c12631d --- /dev/null +++ b/drivers/core/lists.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct driver *lists_driver_lookup_name(const char *name) +{ + struct driver *drv = + ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + struct driver *entry; + int len; + + if (!drv || !n_ents) + return NULL; + + len = strlen(name); + + for (entry = drv; entry != drv + n_ents; entry++) { + if (strncmp(name, entry->name, len)) + continue; + + /* Full match */ + if (len == strlen(entry->name)) + return entry; + } + + /* Not found */ + return NULL; +} + +struct uclass_driver *lists_uclass_lookup(enum uclass_id id) +{ + struct uclass_driver *uclass = + ll_entry_start(struct uclass_driver, uclass); + const int n_ents = ll_entry_count(struct uclass_driver, uclass); + struct uclass_driver *entry; + + if ((id == UCLASS_INVALID) || !uclass) + return NULL; + + for (entry = uclass; entry != uclass + n_ents; entry++) { + if (entry->id == id) + return entry; + } + + return NULL; +} + +int lists_bind_drivers(struct device *parent) +{ + struct driver_info *info = + ll_entry_start(struct driver_info, driver_info); + const int n_ents = ll_entry_count(struct driver_info, driver_info); + struct driver_info *entry; + struct device *dev; + int result = 0; + int ret; + + for (entry = info; entry != info + n_ents; entry++) { + ret = device_bind_by_name(parent, entry, &dev); + if (ret) { + dm_warn("No match for driver '%s'\n", entry->name); + if (!result || ret != -ENOENT) + result = ret; + } + } + + return result; +} + +#ifdef CONFIG_OF_CONTROL +/** + * driver_check_compatible() - Check if a driver is compatible with this node + * + * @param blob: Device tree pointer + * @param offset: Offset of node in device tree + * @param of_matchL List of compatible strings to match + * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node + * does not have a compatible string, other error <0 if there is a device + * tree error + */ +static int driver_check_compatible(const void *blob, int offset, + const struct device_id *of_match) +{ + int ret; + + if (!of_match) + return -ENOENT; + + while (of_match->compatible) { + ret = fdt_node_check_compatible(blob, offset, + of_match->compatible); + if (!ret) + return 0; + else if (ret == -FDT_ERR_NOTFOUND) + return -ENODEV; + else if (ret < 0) + return -EINVAL; + of_match++; + } + + return -ENOENT; +} + +int lists_bind_fdt(struct device *parent, const void *blob, int offset) +{ + struct driver *driver = ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + struct driver *entry; + struct device *dev; + const char *name; + int result = 0; + int ret; + + dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL)); + for (entry = driver; entry != driver + n_ents; entry++) { + ret = driver_check_compatible(blob, offset, entry->of_match); + if (ret == -ENOENT) { + continue; + } else if (ret == -ENODEV) { + break; + } else if (ret) { + dm_warn("Device tree error at offset %d\n", offset); + if (!result || ret != -ENOENT) + result = ret; + break; + } + + name = fdt_get_name(blob, offset, NULL); + dm_dbg(" - found match at '%s'\n", entry->name); + ret = device_bind(parent, entry, name, NULL, offset, &dev); + if (ret) { + dm_warn("No match for driver '%s'\n", entry->name); + if (!result || ret != -ENOENT) + result = ret; + } + } + + return result; +} +#endif diff --git a/drivers/core/root.c b/drivers/core/root.c new file mode 100644 index 0000000000..407bc0d046 --- /dev/null +++ b/drivers/core/root.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct driver_info root_info = { + .name = "root_driver", +}; + +struct device *dm_root(void) +{ + if (!gd->dm_root) { + dm_warn("Virtual root driver does not exist!\n"); + return NULL; + } + + return gd->dm_root; +} + +int dm_init(void) +{ + int ret; + + if (gd->dm_root) { + dm_warn("Virtual root driver already exists!\n"); + return -EINVAL; + } + INIT_LIST_HEAD(&gd->uclass_root); + + ret = device_bind_by_name(NULL, &root_info, &gd->dm_root); + if (ret) + return ret; + + return 0; +} + +int dm_scan_platdata(void) +{ + int ret; + + ret = lists_bind_drivers(gd->dm_root); + if (ret == -ENOENT) { + dm_warn("Some drivers were not found\n"); + ret = 0; + } + if (ret) + return ret; + + return 0; +} + +#ifdef CONFIG_OF_CONTROL +int dm_scan_fdt(const void *blob) +{ + int offset = 0; + int ret = 0, err; + int depth = 0; + + do { + offset = fdt_next_node(blob, offset, &depth); + if (offset > 0 && depth == 1) { + err = lists_bind_fdt(gd->dm_root, blob, offset); + if (err && !ret) + ret = err; + } + } while (offset > 0); + + if (ret) + dm_warn("Some drivers failed to bind\n"); + + return ret; +} +#endif + +/* This is the root driver - all drivers are children of this */ +U_BOOT_DRIVER(root_driver) = { + .name = "root_driver", + .id = UCLASS_ROOT, +}; + +/* This is the root uclass */ +UCLASS_DRIVER(root) = { + .name = "root", + .id = UCLASS_ROOT, +}; diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c new file mode 100644 index 0000000000..4df5a8bd39 --- /dev/null +++ b/drivers/core/uclass.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct uclass *uclass_find(enum uclass_id key) +{ + struct uclass *uc; + + /* + * TODO(sjg@chromium.org): Optimise this, perhaps moving the found + * node to the start of the list, or creating a linear array mapping + * id to node. + */ + list_for_each_entry(uc, &gd->uclass_root, sibling_node) { + if (uc->uc_drv->id == key) + return uc; + } + + return NULL; +} + +/** + * uclass_add() - Create new uclass in list + * @id: Id number to create + * @ucp: Returns pointer to uclass, or NULL on error + * @return 0 on success, -ve on error + * + * The new uclass is added to the list. There must be only one uclass for + * each id. + */ +static int uclass_add(enum uclass_id id, struct uclass **ucp) +{ + struct uclass_driver *uc_drv; + struct uclass *uc; + int ret; + + *ucp = NULL; + uc_drv = lists_uclass_lookup(id); + if (!uc_drv) { + dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n", + id); + return -ENOENT; + } + if (uc_drv->ops) { + dm_warn("No ops for uclass id %d\n", id); + return -EINVAL; + } + uc = calloc(1, sizeof(*uc)); + if (!uc) + return -ENOMEM; + if (uc_drv->priv_auto_alloc_size) { + uc->priv = calloc(1, uc_drv->priv_auto_alloc_size); + if (!uc->priv) { + ret = -ENOMEM; + goto fail_mem; + } + } + uc->uc_drv = uc_drv; + INIT_LIST_HEAD(&uc->sibling_node); + INIT_LIST_HEAD(&uc->dev_head); + list_add(&uc->sibling_node, &gd->uclass_root); + + if (uc_drv->init) { + ret = uc_drv->init(uc); + if (ret) + goto fail; + } + + *ucp = uc; + + return 0; +fail: + if (uc_drv->priv_auto_alloc_size) { + free(uc->priv); + uc->priv = NULL; + } + list_del(&uc->sibling_node); +fail_mem: + free(uc); + + return ret; +} + +int uclass_destroy(struct uclass *uc) +{ + struct uclass_driver *uc_drv; + struct device *dev, *tmp; + int ret; + + list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) { + ret = device_remove(dev); + if (ret) + return ret; + ret = device_unbind(dev); + if (ret) + return ret; + } + + uc_drv = uc->uc_drv; + if (uc_drv->destroy) + uc_drv->destroy(uc); + list_del(&uc->sibling_node); + if (uc_drv->priv_auto_alloc_size) + free(uc->priv); + free(uc); + + return 0; +} + +int uclass_get(enum uclass_id id, struct uclass **ucp) +{ + struct uclass *uc; + + *ucp = NULL; + uc = uclass_find(id); + if (!uc) + return uclass_add(id, ucp); + *ucp = uc; + + return 0; +} + +int uclass_find_device(enum uclass_id id, int index, struct device **devp) +{ + struct uclass *uc; + struct device *dev; + int ret; + + *devp = NULL; + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (!index--) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int uclass_get_device(enum uclass_id id, int index, struct device **devp) +{ + struct device *dev; + int ret; + + *devp = NULL; + ret = uclass_find_device(id, index, &dev); + if (ret) + return ret; + + ret = device_probe(dev); + if (ret) + return ret; + + *devp = dev; + + return 0; +} + +int uclass_first_device(enum uclass_id id, struct device **devp) +{ + struct uclass *uc; + struct device *dev; + int ret; + + *devp = NULL; + ret = uclass_get(id, &uc); + if (ret) + return ret; + if (list_empty(&uc->dev_head)) + return 0; + + dev = list_first_entry(&uc->dev_head, struct device, uclass_node); + ret = device_probe(dev); + if (ret) + return ret; + *devp = dev; + + return 0; +} + +int uclass_next_device(struct device **devp) +{ + struct device *dev = *devp; + int ret; + + *devp = NULL; + if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) + return 0; + + dev = list_entry(dev->uclass_node.next, struct device, uclass_node); + ret = device_probe(dev); + if (ret) + return ret; + *devp = dev; + + return 0; +} + +int uclass_bind_device(struct device *dev) +{ + struct uclass *uc; + int ret; + + uc = dev->uclass; + + list_add_tail(&dev->uclass_node, &uc->dev_head); + + if (uc->uc_drv->post_bind) { + ret = uc->uc_drv->post_bind(dev); + if (ret) { + list_del(&dev->uclass_node); + return ret; + } + } + + return 0; +} + +int uclass_unbind_device(struct device *dev) +{ + struct uclass *uc; + int ret; + + uc = dev->uclass; + if (uc->uc_drv->pre_unbind) { + ret = uc->uc_drv->pre_unbind(dev); + if (ret) + return ret; + } + + list_del(&dev->uclass_node); + return 0; +} + +int uclass_post_probe_device(struct device *dev) +{ + struct uclass_driver *uc_drv = dev->uclass->uc_drv; + + if (uc_drv->post_probe) + return uc_drv->post_probe(dev); + + return 0; +} + +int uclass_pre_remove_device(struct device *dev) +{ + struct uclass_driver *uc_drv; + struct uclass *uc; + int ret; + + uc = dev->uclass; + uc_drv = uc->uc_drv; + if (uc->uc_drv->pre_remove) { + ret = uc->uc_drv->pre_remove(dev); + if (ret) + return ret; + } + if (uc_drv->per_device_auto_alloc_size) { + free(dev->uclass_priv); + dev->uclass_priv = NULL; + } + + return 0; +} diff --git a/drivers/core/util.c b/drivers/core/util.c new file mode 100644 index 0000000000..e01dd06d28 --- /dev/null +++ b/drivers/core/util.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void dm_warn(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); +} + +void dm_dbg(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); +} + +int list_count_items(struct list_head *head) +{ + struct list_head *node; + int count = 0; + + list_for_each(node, head) + count++; + + return count; +} diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index acbafde97c..ed4f541823 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -5,10 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include "ace_sha.h" + +#ifdef CONFIG_SHA_HW_ACCEL #include #include #include -#include "ace_sha.h" /* SHA1 value for the message of zero length */ static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { @@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) debug("ACE was not setup properly or it is faulty\n"); } +#endif /* CONFIG_SHA_HW_ACCEL */ + +#ifdef CONFIG_LIB_HW_RAND +static unsigned int seed_done; + +void srand(unsigned int seed) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + + /* Seed data */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + writel(seed << i, ®->hash_seed[i]); + + /* Wait for seed setup done */ + while (1) { + status = readl(®->hash_status); + if ((status & ACE_HASH_SEEDSETTING_MASK) || + (status & ACE_HASH_PRNGERROR_MASK)) + break; + } + + seed_done = 1; +} + +unsigned int rand(void) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + unsigned int seed = (unsigned int)&status; + unsigned int ret = 0; + + if (!seed_done) + srand(seed); + + /* Start PRNG */ + writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, ®->hash_control); + + /* Wait for PRNG done */ + while (1) { + status = readl(®->hash_status); + if (status & ACE_HASH_PRNGDONE_MASK) + break; + if (status & ACE_HASH_PRNGERROR_MASK) { + seed_done = 0; + return 0; + } + } + + /* Clear Done IRQ */ + writel(ACE_HASH_PRNGDONE_MASK, ®->hash_status); + + /* Read a PRNG result */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + ret += readl(®->hash_prng[i]); + + seed_done = 0; + return ret; +} + +unsigned int rand_r(unsigned int *seedp) +{ + srand(*seedp); + + return rand(); +} +#endif /* CONFIG_LIB_HW_RAND */ diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index a426d52372..f1097f72dc 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -72,9 +72,10 @@ struct exynos_ace_sfr { unsigned char res12[0x30]; unsigned int hash_result[8]; unsigned char res13[0x20]; - unsigned int hash_seed[8]; - unsigned int hash_prng[8]; - unsigned char res14[0x180]; + unsigned int hash_seed[5]; + unsigned char res14[12]; + unsigned int hash_prng[5]; + unsigned char res15[0x18c]; unsigned int pka_sfr[5]; /* base + 0x700 */ }; @@ -291,6 +292,7 @@ struct exynos_ace_sfr { #define ACE_HASH_PRNGERROR_MASK (1 << 7) #define ACE_HASH_PRNGERROR_OFF (0 << 7) #define ACE_HASH_PRNGERROR_ON (1 << 7) +#define ACE_HASH_PRNG_REG_NUM 5 #define ACE_SHA_TYPE_SHA1 1 #define ACE_SHA_TYPE_SHA256 2 diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index bf113908fd..d4ed9aec2a 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -11,6 +11,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -63,54 +64,54 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); + ddr_out32(&ddr->eor, regs->ddr_eor); for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); } } - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU /* * Skip these two registers if running on emulator @@ -118,23 +119,23 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, */ if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); #endif - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { if (regs->debug[i]) { debug("Write to debug_%d as %08x\n", i + 1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); } } @@ -155,7 +156,7 @@ step2: /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); /* * 500 painful micro-seconds must elapse between @@ -167,8 +168,8 @@ step2: asm volatile("dsb sy;isb"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("dsb sy;isb"); total_gb_size_per_controller = 0; @@ -202,7 +203,7 @@ step2: debug("Need to wait up to %d * 10ms\n", timeout); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && (timeout >= 0)) { udelay(10000); /* throttle polling rate */ timeout--; diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 6bf22cfbd6..0882932b07 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -25,8 +25,8 @@ static u32 fsl_ddr_get_version(void) u32 ver_major_minor_errata; ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; return ver_major_minor_errata; } @@ -145,6 +145,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, if (!popts->memctl_interleaving) break; switch (popts->memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d0cd58925c..d62ca63c77 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -17,6 +17,18 @@ #include #include +/* + * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * all Power SoCs. But it could be different for ARM SoCs. For example, + * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of + * 0x00_8000_0000 ~ 0x00_ffff_ffff + * 0x80_8000_0000 ~ 0xff_ffff_ffff + */ +#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#endif + #ifdef CONFIG_PPC #include @@ -255,7 +267,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); } - current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE; + current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; total_mem = 0; if (pinfo->memctl_opts[0].memctl_interleaving) { rank_density = pinfo->dimm_params[0][0].rank_density >> @@ -279,6 +291,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { if (pinfo->memctl_opts[i].memctl_interleaving) { switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: @@ -536,7 +549,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } total_mem = 1 + (((unsigned long long)max_end << 24ULL) | - 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE; + 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; } return total_mem; diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 9f04133094..c805086416 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -39,6 +39,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + u32 save1, save2; +#endif switch (ctrl_num) { case 0: @@ -197,6 +200,8 @@ step2: out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); out_be32(&ddr->mtcr, 0); + save1 = in_be32(&ddr->debug[12]); + save2 = in_be32(&ddr->debug[21]); out_be32(&ddr->debug[12], 0x00000015); out_be32(&ddr->debug[21], 0x24000000); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); @@ -214,6 +219,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif break; case 0x00100000: out_be32(&ddr->sdram_md_cntl, @@ -222,6 +239,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x0a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); +#endif break; case 0x00200000: out_be32(&ddr->sdram_md_cntl, @@ -230,6 +259,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x12)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); +#endif break; case 0x00300000: out_be32(&ddr->sdram_md_cntl, @@ -238,6 +279,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x1a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); +#endif break; default: out_be32(&ddr->sdram_md_cntl, @@ -246,6 +299,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif printf("Unsupported RC10\n"); break; } @@ -259,8 +324,8 @@ step2: out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->debug[12], 0x0); - out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->debug[12], save1); + out_be32(&ddr->debug[21], save2); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); } diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 4aafcceaf5..b0cf046fdc 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -818,21 +818,33 @@ unsigned int populate_memctl_options(int all_dimms_registered, * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for all memory controllers. * - * XXX: Attempt to set all controllers to the same chip select + * Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. + * + * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving + * with 256 Byte is enabled. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + ; +#else goto done; - +#endif if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d.\n", ctrl_num); popts->memctl_interleaving = 0; goto done; } popts->memctl_interleaving = 1; +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; + popts->memctl_interleaving = 1; + debug("256 Byte interleaving\n"); + goto done; +#endif /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -1085,6 +1097,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) "Memory controller interleaving disabled.\n"); } else { switch (check_intlv) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 0658261d8d..ad53658fc9 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -146,21 +146,21 @@ void board_add_ram_info(int use_default) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); #endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); + uint32_t cs0_config = ddr_in32(&ddr->cs0_config); #endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); + uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); int cas_lat; #if CONFIG_NUM_DDR_CONTROLLERS >= 2 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif #if CONFIG_NUM_DDR_CONTROLLERS >= 3 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif puts(" (DDR"); @@ -188,8 +188,8 @@ void board_add_ram_info(int use_default) puts(", 64-bit"); /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) + cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; + if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1) cas_lat += (8 << 1); printf(", CL=%d", cas_lat >> 1); if (cas_lat & 0x1) @@ -228,6 +228,9 @@ void board_add_ram_info(int use_default) puts(" DDR Controller Interleaving Mode: "); switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_256B_INTERLEAVING: + puts("256B"); + break; case FSL_DDR_CACHE_LINE_INTERLEAVING: puts("cache line"); break; diff --git a/drivers/demo/Makefile b/drivers/demo/Makefile new file mode 100644 index 0000000000..baaa2baa4e --- /dev/null +++ b/drivers/demo/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM_DEMO) += demo-uclass.o demo-pdata.o +obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o +obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o diff --git a/drivers/demo/demo-pdata.c b/drivers/demo/demo-pdata.c new file mode 100644 index 0000000000..e92841db69 --- /dev/null +++ b/drivers/demo/demo-pdata.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static const struct dm_demo_pdata red_square = { + .colour = "red", + .sides = 4. +}; +static const struct dm_demo_pdata green_triangle = { + .colour = "green", + .sides = 3. +}; +static const struct dm_demo_pdata yellow_hexagon = { + .colour = "yellow", + .sides = 6. +}; + +U_BOOT_DEVICE(demo0) = { + .name = "demo_shape_drv", + .platdata = &red_square, +}; + +U_BOOT_DEVICE(demo1) = { + .name = "demo_simple_drv", + .platdata = &red_square, +}; + +U_BOOT_DEVICE(demo2) = { + .name = "demo_shape_drv", + .platdata = &green_triangle, +}; + +U_BOOT_DEVICE(demo3) = { + .name = "demo_simple_drv", + .platdata = &yellow_hexagon, +}; + +U_BOOT_DEVICE(demo4) = { + .name = "demo_shape_drv", + .platdata = &yellow_hexagon, +}; diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c new file mode 100644 index 0000000000..2f0eb96bb6 --- /dev/null +++ b/drivers/demo/demo-shape.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Shape size */ +#define WIDTH 8 +#define HEIGHT 6 + +struct shape_data { + int num_chars; /* Number of non-space characters output so far */ +}; + +/* Crazy little function to draw shapes on the console */ +static int shape_hello(struct device *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + struct shape_data *data = dev_get_priv(dev); + static const struct shape { + int start; + int end; + int dstart; + int dend; + } shapes[3] = { + { 0, 1, 0, 1 }, + { 0, WIDTH, 0, 0 }, + { HEIGHT / 2 - 1, WIDTH - HEIGHT / 2 + 1, -1, 1}, + }; + struct shape shape; + unsigned int index; + int line, pos, inside; + const char *colour = pdata->colour; + int first = 0; + + if (!ch) + ch = pdata->default_char; + if (!ch) + ch = '@'; + + index = (pdata->sides / 2) - 1; + if (index >= ARRAY_SIZE(shapes)) + return -EIO; + shape = shapes[index]; + + for (line = 0; line < HEIGHT; line++) { + first = 1; + for (pos = 0; pos < WIDTH; pos++) { + inside = pos >= shape.start && pos < shape.end; + if (inside) { + putc(first ? *colour++ : ch); + data->num_chars++; + first = 0; + if (!*colour) + colour = pdata->colour; + } else { + putc(' '); + } + } + putc('\n'); + shape.start += shape.dstart; + shape.end += shape.dend; + if (shape.start < 0) { + shape.dstart = -shape.dstart; + shape.dend = -shape.dend; + shape.start += shape.dstart; + shape.end += shape.dend; + } + } + + return 0; +} + +static int shape_status(struct device *dev, int *status) +{ + struct shape_data *data = dev_get_priv(dev); + + *status = data->num_chars; + return 0; +} + +static const struct demo_ops shape_ops = { + .hello = shape_hello, + .status = shape_status, +}; + +static int shape_ofdata_to_platdata(struct device *dev) +{ + struct dm_demo_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Parse the data that is common with all demo devices */ + ret = demo_parse_dt(dev); + if (ret) + return ret; + + /* Parse the data that only we need */ + pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "character", '@'); + + return 0; +} + +static const struct device_id demo_shape_id[] = { + { "demo-shape", 0 }, + { }, +}; + +U_BOOT_DRIVER(demo_shape_drv) = { + .name = "demo_shape_drv", + .of_match = demo_shape_id, + .id = UCLASS_DEMO, + .ofdata_to_platdata = shape_ofdata_to_platdata, + .ops = &shape_ops, + .priv_auto_alloc_size = sizeof(struct shape_data), + .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata), +}; diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c new file mode 100644 index 0000000000..6ba8131728 --- /dev/null +++ b/drivers/demo/demo-simple.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static int simple_hello(struct device *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + + printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), pdata->colour, + pdata->sides); + + return 0; +} + +static const struct demo_ops simple_ops = { + .hello = simple_hello, +}; + +static int demo_shape_ofdata_to_platdata(struct device *dev) +{ + /* Parse the data that is common with all demo devices */ + return demo_parse_dt(dev); +} + +static const struct device_id demo_shape_id[] = { + { "demo-simple", 0 }, + { }, +}; + +U_BOOT_DRIVER(demo_simple_drv) = { + .name = "demo_simple_drv", + .of_match = demo_shape_id, + .id = UCLASS_DEMO, + .ofdata_to_platdata = demo_shape_ofdata_to_platdata, + .ops = &simple_ops, + .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata), +}; diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c new file mode 100644 index 0000000000..48588be907 --- /dev/null +++ b/drivers/demo/demo-uclass.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +UCLASS_DRIVER(demo) = { + .id = UCLASS_DEMO, +}; + +int demo_hello(struct device *dev, int ch) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->hello) + return -ENOSYS; + + return ops->hello(dev, ch); +} + +int demo_status(struct device *dev, int *status) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->status) + return -ENOSYS; + + return ops->status(dev, status); +} + +int demo_parse_dt(struct device *dev) +{ + struct dm_demo_pdata *pdata = dev_get_platdata(dev); + int dn = dev->of_offset; + + pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0); + pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL); + if (!pdata->sides || !pdata->colour) { + debug("%s: Invalid device tree data\n", __func__); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 07011e99a8..8a09aafbf2 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -19,6 +19,7 @@ static bool dfu_reset_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; +static int alt_num_cnt; bool dfu_reset(void) { @@ -126,6 +127,28 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) return ret; } +int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) +{ + int ret = 0; + + if (dfu->flush_medium) + ret = dfu->flush_medium(dfu); + + printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); + + /* clear everything */ + dfu_free_buf(); + dfu->crc = 0; + dfu->offset = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf; + dfu->i_buf = dfu->i_buf_start; + dfu->inited = 0; + + return ret; +} + int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; @@ -196,26 +219,6 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) ret = tret; } - /* end? */ - if (size == 0) { - /* Now try and flush to the medium if needed. */ - if (dfu->flush_medium) - ret = dfu->flush_medium(dfu); - printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); - - /* clear everything */ - dfu_free_buf(); - dfu->crc = 0; - dfu->offset = 0; - dfu->i_blk_seq_num = 0; - dfu->i_buf_start = dfu_buf; - dfu->i_buf_end = dfu_buf; - dfu->i_buf = dfu->i_buf_start; - - dfu->inited = 0; - - } - return ret = 0 ? size : ret; } @@ -377,6 +380,8 @@ void dfu_free_entities(void) if (t) free(t); INIT_LIST_HEAD(&dfu_list); + + alt_num_cnt = 0; } int dfu_config_entities(char *env, char *interface, int num) @@ -394,11 +399,12 @@ int dfu_config_entities(char *env, char *interface, int num) for (i = 0; i < dfu_alt_num; i++) { s = strsep(&env, ";"); - ret = dfu_fill_entity(&dfu[i], s, i, interface, num); + ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, num); if (ret) return -1; list_add_tail(&dfu[i].list, &dfu_list); + alt_num_cnt++; } return 0; diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index f942758696..651cfff5b3 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -12,6 +12,7 @@ #include #include #include +#include static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; @@ -20,8 +21,8 @@ static long dfu_file_buf_len; static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { - char cmd_buf[DFU_CMD_BUF_SIZE]; - u32 blk_start, blk_count; + struct mmc *mmc = find_mmc_device(dfu->dev_num); + u32 blk_start, blk_count, n = 0; /* * We must ensure that we work in lba_blk_size chunks, so ALIGN @@ -38,12 +39,28 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EINVAL; } - sprintf(cmd_buf, "mmc %s %p %x %x", - op == DFU_OP_READ ? "read" : "write", - buf, blk_start, blk_count); + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, + op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num, + blk_start, blk_count, buf); + switch (op) { + case DFU_OP_READ: + n = mmc->block_dev.block_read(dfu->dev_num, blk_start, + blk_count, buf); + break; + case DFU_OP_WRITE: + n = mmc->block_dev.block_write(dfu->dev_num, blk_start, + blk_count, buf); + break; + default: + error("Operation not supported\n"); + } - debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); - return run_command(cmd_buf, 0); + if (n != blk_count) { + error("MMC operation failed"); + return -EIO; + } + + return 0; } static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) @@ -73,16 +90,12 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); break; case DFU_FS_EXT4: sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %ld", *len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -90,6 +103,9 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, return -1; } + if (op == DFU_OP_WRITE) + sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); + debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); ret = run_command(cmd_buf, 0); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index e098d1389a..90a97db54b 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #if defined(CONFIG_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b903c45c52..4e001e12bd 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -5,9 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o + obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MARVELL_MFP) += mvmfp.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 8b766665c6..0b70071871 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c new file mode 100644 index 0000000000..56bfd11466 --- /dev/null +++ b/drivers/gpio/gpio-uclass.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/** + * gpio_to_device() - Convert global GPIO number to device, number + * gpio: The numeric representation of the GPIO + * + * Convert the GPIO number to an entry in the list of GPIOs + * or GPIO blocks registered with the GPIO controller. Returns + * entry on success, NULL on error. + */ +static int gpio_to_device(unsigned int gpio, struct device **devp, + unsigned int *offset) +{ + struct gpio_dev_priv *uc_priv; + struct device *dev; + int ret; + + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + uc_priv = dev->uclass_priv; + if (gpio >= uc_priv->gpio_base && + gpio < uc_priv->gpio_base + uc_priv->gpio_count) { + *devp = dev; + *offset = gpio - uc_priv->gpio_base; + return 0; + } + } + + /* No such GPIO */ + return ret ? ret : -EINVAL; +} + +int gpio_lookup_name(const char *name, struct device **devp, + unsigned int *offsetp, unsigned int *gpiop) +{ + struct gpio_dev_priv *uc_priv; + struct device *dev; + int ret; + + if (devp) + *devp = NULL; + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + ulong offset; + int len; + + uc_priv = dev->uclass_priv; + len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0; + + if (!strncmp(name, uc_priv->bank_name, len)) { + if (strict_strtoul(name + len, 10, &offset)) + continue; + if (devp) + *devp = dev; + if (offsetp) + *offsetp = offset; + if (gpiop) + *gpiop = uc_priv->gpio_base + offset; + return 0; + } + } + + return ret ? ret : -EINVAL; +} + +/** + * gpio_request() - [COMPAT] Request GPIO + * gpio: GPIO number + * label: Name for the requested GPIO + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_request(unsigned gpio, const char *label) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + if (!gpio_get_ops(dev)->request) + return 0; + + return gpio_get_ops(dev)->request(dev, offset, label); +} + +/** + * gpio_free() - [COMPAT] Relinquish GPIO + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_free(unsigned gpio) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + if (!gpio_get_ops(dev)->free) + return 0; + return gpio_get_ops(dev)->free(dev, offset); +} + +/** + * gpio_direction_input() - [COMPAT] Set GPIO direction to input + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_direction_input(unsigned gpio) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + return gpio_get_ops(dev)->direction_input(dev, offset); +} + +/** + * gpio_direction_output() - [COMPAT] Set GPIO direction to output and set value + * gpio: GPIO number + * value: Logical value to be set on the GPIO pin + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_direction_output(unsigned gpio, int value) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + return gpio_get_ops(dev)->direction_output(dev, offset, value); +} + +/** + * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns the value of the GPIO pin, or negative value + * on error. + */ +int gpio_get_value(unsigned gpio) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + return gpio_get_ops(dev)->get_value(dev, offset); +} + +/** + * gpio_set_value() - [COMPAT] Configure logical value on GPIO pin + * gpio: GPIO number + * value: Logical value to be set on the GPIO pin. + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_set_value(unsigned gpio, int value) +{ + unsigned int offset; + struct device *dev; + int ret; + + ret = gpio_to_device(gpio, &dev, &offset); + if (ret) + return ret; + + return gpio_get_ops(dev)->set_value(dev, offset, value); +} + +const char *gpio_get_bank_info(struct device *dev, int *bit_count) +{ + struct gpio_dev_priv *priv; + + /* Must be called on an active device */ + priv = dev->uclass_priv; + assert(priv); + + *bit_count = priv->gpio_count; + return priv->bank_name; +} + +/* We need to renumber the GPIOs when any driver is probed/removed */ +static int gpio_renumber(void) +{ + struct gpio_dev_priv *uc_priv; + struct device *dev; + struct uclass *uc; + unsigned base; + int ret; + + ret = uclass_get(UCLASS_GPIO, &uc); + if (ret) + return ret; + + /* Ensure that we have a base for each bank */ + base = 0; + uclass_foreach_dev(dev, uc) { + if (device_active(dev)) { + uc_priv = dev->uclass_priv; + uc_priv->gpio_base = base; + base += uc_priv->gpio_count; + } + } + + return 0; +} + +static int gpio_post_probe(struct device *dev) +{ + return gpio_renumber(); +} + +static int gpio_pre_remove(struct device *dev) +{ + return gpio_renumber(); +} + +UCLASS_DRIVER(gpio) = { + .id = UCLASS_GPIO, + .name = "gpio", + .post_probe = gpio_post_probe, + .pre_remove = gpio_pre_remove, + .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv), +}; diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c new file mode 100644 index 0000000000..65117438c5 --- /dev/null +++ b/drivers/gpio/kona_gpio.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define GPIO_BASE (void *)GPIO2_BASE_ADDR + +#define GPIO_PASSWD 0x00a5a501 +#define GPIO_PER_BANK 32 +#define GPIO_MAX_BANK_NUM 8 + +#define GPIO_BANK(gpio) ((gpio) >> 5) +#define GPIO_BITMASK(gpio) \ + (1UL << ((gpio) & (GPIO_PER_BANK - 1))) + +#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) +#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) +#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) +#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) +#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) +#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) +#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) +#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) +#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) + +#define GPIO_GPPWR_OFFSET 0x00000520 + +#define GPIO_GPCTR0_DBR_SHIFT 5 +#define GPIO_GPCTR0_DBR_MASK 0x000001e0 + +#define GPIO_GPCTR0_ITR_SHIFT 3 +#define GPIO_GPCTR0_ITR_MASK 0x00000018 +#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 +#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 +#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 + +#define GPIO_GPCTR0_IOTR_MASK 0x00000001 +#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 +#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 + +int gpio_request(unsigned gpio, const char *label) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_free(unsigned gpio) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + u32 val; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_INPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* read the GPIO bank status */ + off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? + GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); + val = readl(GPIO_BASE + off); + + /* return the specified bit status */ + return !!(val & bitmask); +} + +void gpio_set_value(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* this function only applies to output pin */ + if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { + printf("%s: Cannot set an input pin %d\n", __func__, gpio); + return; + } + + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); +} diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 7eeb96d19f..11a0472c69 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -9,6 +9,11 @@ #include #include +#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \ + & S5P_GPIO_BANK_MASK) + +#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK) + #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -124,17 +129,15 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) { - int bank; - unsigned g = gpio - s5p_gpio_part_max(gpio); + unsigned bank = S5P_GPIO_GET_BANK(gpio); + unsigned base = s5p_gpio_base(gpio); - bank = g / GPIO_PER_BANK; - bank *= sizeof(struct s5p_gpio_bank); - return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); + return (struct s5p_gpio_bank *)(base + bank); } int s5p_gpio_get_pin(unsigned gpio) { - return gpio % GPIO_PER_BANK; + return S5P_GPIO_GET_PIN(gpio); } /* Common GPIO API */ diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 3c6cfec179..22b6a5f794 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -4,8 +4,13 @@ */ #include +#include +#include +#include #include +DECLARE_GLOBAL_DATA_PTR; + /* Flags for each GPIO */ #define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */ #define GPIOF_HIGH (1 << 1) /* Currently set high */ @@ -16,34 +21,30 @@ struct gpio_state { u8 flags; /* flags (GPIOF_...) */ }; -/* - * State of GPIOs - * TODO: Put this into sandbox state - */ -static struct gpio_state state[CONFIG_SANDBOX_GPIO_COUNT]; - /* Access routines for GPIO state */ -static u8 *get_gpio_flags(unsigned gp) +static u8 *get_gpio_flags(struct device *dev, unsigned offset) { - /* assert()'s could be disabled, so make sure we handle that */ - assert(gp < ARRAY_SIZE(state)); - if (gp >= ARRAY_SIZE(state)) { + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct gpio_state *state = dev_get_priv(dev); + + if (offset >= uc_priv->gpio_count) { static u8 invalid_flags; - printf("sandbox_gpio: error: invalid gpio %u\n", gp); + printf("sandbox_gpio: error: invalid gpio %u\n", offset); return &invalid_flags; } - return &state[gp].flags; + return &state[offset].flags; } -static int get_gpio_flag(unsigned gp, int flag) +static int get_gpio_flag(struct device *dev, unsigned offset, int flag) { - return (*get_gpio_flags(gp) & flag) != 0; + return (*get_gpio_flags(dev, offset) & flag) != 0; } -static int set_gpio_flag(unsigned gp, int flag, int value) +static int set_gpio_flag(struct device *dev, unsigned offset, int flag, + int value) { - u8 *gpio = get_gpio_flags(gp); + u8 *gpio = get_gpio_flags(dev, offset); if (value) *gpio |= flag; @@ -53,11 +54,12 @@ static int set_gpio_flag(unsigned gp, int flag, int value) return 0; } -static int check_reserved(unsigned gpio, const char *func) +static int check_reserved(struct device *dev, unsigned offset, + const char *func) { - if (!get_gpio_flag(gpio, GPIOF_RESERVED)) { - printf("sandbox_gpio: %s: error: gpio %u not reserved\n", - func, gpio); + if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) { + printf("sandbox_gpio: %s: error: offset %u not reserved\n", + func, offset); return -1; } @@ -68,126 +70,185 @@ static int check_reserved(unsigned gpio, const char *func) * Back-channel sandbox-internal-only access to GPIO state */ -int sandbox_gpio_get_value(unsigned gp) +int sandbox_gpio_get_value(struct device *dev, unsigned offset) { - if (get_gpio_flag(gp, GPIOF_OUTPUT)) - debug("sandbox_gpio: get_value on output gpio %u\n", gp); - return get_gpio_flag(gp, GPIOF_HIGH); + if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) + debug("sandbox_gpio: get_value on output gpio %u\n", offset); + return get_gpio_flag(dev, offset, GPIOF_HIGH); } -int sandbox_gpio_set_value(unsigned gp, int value) +int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value) { - return set_gpio_flag(gp, GPIOF_HIGH, value); + return set_gpio_flag(dev, offset, GPIOF_HIGH, value); } -int sandbox_gpio_get_direction(unsigned gp) +int sandbox_gpio_get_direction(struct device *dev, unsigned offset) { - return get_gpio_flag(gp, GPIOF_OUTPUT); + return get_gpio_flag(dev, offset, GPIOF_OUTPUT); } -int sandbox_gpio_set_direction(unsigned gp, int output) +int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output) { - return set_gpio_flag(gp, GPIOF_OUTPUT, output); + return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output); } /* * These functions implement the public interface within U-Boot */ -/* set GPIO port 'gp' as an input */ -int gpio_direction_input(unsigned gp) +/* set GPIO port 'offset' as an input */ +static int sb_gpio_direction_input(struct device *dev, unsigned offset) { - debug("%s: gp:%u\n", __func__, gp); + debug("%s: offset:%u\n", __func__, offset); - if (check_reserved(gp, __func__)) + if (check_reserved(dev, offset, __func__)) return -1; - return sandbox_gpio_set_direction(gp, 0); + return sandbox_gpio_set_direction(dev, offset, 0); } -/* set GPIO port 'gp' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gp, int value) +/* set GPIO port 'offset' as an output, with polarity 'value' */ +static int sb_gpio_direction_output(struct device *dev, unsigned offset, + int value) { - debug("%s: gp:%u, value = %d\n", __func__, gp, value); + debug("%s: offset:%u, value = %d\n", __func__, offset, value); - if (check_reserved(gp, __func__)) + if (check_reserved(dev, offset, __func__)) return -1; - return sandbox_gpio_set_direction(gp, 1) | - sandbox_gpio_set_value(gp, value); + return sandbox_gpio_set_direction(dev, offset, 1) | + sandbox_gpio_set_value(dev, offset, value); } -/* read GPIO IN value of port 'gp' */ -int gpio_get_value(unsigned gp) +/* read GPIO IN value of port 'offset' */ +static int sb_gpio_get_value(struct device *dev, unsigned offset) { - debug("%s: gp:%u\n", __func__, gp); + debug("%s: offset:%u\n", __func__, offset); - if (check_reserved(gp, __func__)) + if (check_reserved(dev, offset, __func__)) return -1; - return sandbox_gpio_get_value(gp); + return sandbox_gpio_get_value(dev, offset); } -/* write GPIO OUT value to port 'gp' */ -int gpio_set_value(unsigned gp, int value) +/* write GPIO OUT value to port 'offset' */ +static int sb_gpio_set_value(struct device *dev, unsigned offset, int value) { - debug("%s: gp:%u, value = %d\n", __func__, gp, value); + debug("%s: offset:%u, value = %d\n", __func__, offset, value); - if (check_reserved(gp, __func__)) + if (check_reserved(dev, offset, __func__)) return -1; - if (!sandbox_gpio_get_direction(gp)) { - printf("sandbox_gpio: error: set_value on input gpio %u\n", gp); + if (!sandbox_gpio_get_direction(dev, offset)) { + printf("sandbox_gpio: error: set_value on input gpio %u\n", + offset); return -1; } - return sandbox_gpio_set_value(gp, value); + return sandbox_gpio_set_value(dev, offset, value); } -int gpio_request(unsigned gp, const char *label) +static int sb_gpio_request(struct device *dev, unsigned offset, + const char *label) { - debug("%s: gp:%u, label:%s\n", __func__, gp, label); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct gpio_state *state = dev_get_priv(dev); - if (gp >= ARRAY_SIZE(state)) { - printf("sandbox_gpio: error: invalid gpio %u\n", gp); + debug("%s: offset:%u, label:%s\n", __func__, offset, label); + + if (offset >= uc_priv->gpio_count) { + printf("sandbox_gpio: error: invalid gpio %u\n", offset); return -1; } - if (get_gpio_flag(gp, GPIOF_RESERVED)) { - printf("sandbox_gpio: error: gpio %u already reserved\n", gp); + if (get_gpio_flag(dev, offset, GPIOF_RESERVED)) { + printf("sandbox_gpio: error: gpio %u already reserved\n", + offset); return -1; } - state[gp].label = label; - return set_gpio_flag(gp, GPIOF_RESERVED, 1); + state[offset].label = label; + return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1); } -int gpio_free(unsigned gp) +static int sb_gpio_free(struct device *dev, unsigned offset) { - debug("%s: gp:%u\n", __func__, gp); + struct gpio_state *state = dev_get_priv(dev); - if (check_reserved(gp, __func__)) + debug("%s: offset:%u\n", __func__, offset); + + if (check_reserved(dev, offset, __func__)) return -1; - state[gp].label = NULL; - return set_gpio_flag(gp, GPIOF_RESERVED, 0); + state[offset].label = NULL; + return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0); } -/* Display GPIO information */ -void gpio_info(void) +static int sb_gpio_get_state(struct device *dev, unsigned int offset, + char *buf, int bufsize) { - unsigned gpio; + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct gpio_state *state = dev_get_priv(dev); + const char *label; - puts("Sandbox GPIOs\n"); + label = state[offset].label; + snprintf(buf, bufsize, "%s%d: %s: %d [%c]%s%s", + uc_priv->bank_name ? uc_priv->bank_name : "", offset, + sandbox_gpio_get_direction(dev, offset) ? "out" : " in", + sandbox_gpio_get_value(dev, offset), + get_gpio_flag(dev, offset, GPIOF_RESERVED) ? 'x' : ' ', + label ? " " : "", + label ? label : ""); - for (gpio = 0; gpio < ARRAY_SIZE(state); ++gpio) { - const char *label = state[gpio].label; - - printf("%4d: %s: %d [%c] %s\n", - gpio, - sandbox_gpio_get_direction(gpio) ? "out" : " in", - sandbox_gpio_get_value(gpio), - get_gpio_flag(gpio, GPIOF_RESERVED) ? 'x' : ' ', - label ? label : ""); - } + return 0; } + +static const struct dm_gpio_ops gpio_sandbox_ops = { + .request = sb_gpio_request, + .free = sb_gpio_free, + .direction_input = sb_gpio_direction_input, + .direction_output = sb_gpio_direction_output, + .get_value = sb_gpio_get_value, + .set_value = sb_gpio_set_value, + .get_state = sb_gpio_get_state, +}; + +static int sandbox_gpio_ofdata_to_platdata(struct device *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "num-gpios", 0); + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "gpio-bank-name", NULL); + + return 0; +} + +static int gpio_sandbox_probe(struct device *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + if (dev->of_offset == -1) { + /* Tell the uclass how many GPIOs we have */ + uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT; + } + + dev->priv = calloc(sizeof(struct gpio_state), uc_priv->gpio_count); + + return 0; +} + +static const struct device_id sandbox_gpio_ids[] = { + { .compatible = "sandbox,gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_sandbox) = { + .name = "gpio_sandbox", + .id = UCLASS_GPIO, + .of_match = sandbox_gpio_ids, + .ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata, + .probe = gpio_sandbox_probe, + .ops = &gpio_sandbox_ops, +}; diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index a78a724253..25b8e8a2d7 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -8,7 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_DTT_ADM1021) += adm1021.o obj-$(CONFIG_DTT_ADT7460) += adt7460.o diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index fa3a875705..36d5e5f1a2 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o +obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index b3a04d3207..cfab064dfa 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -10,6 +10,7 @@ #include #include +#include #include /* Every register is 32bit aligned, but only 16bits in size */ @@ -274,7 +275,7 @@ unsigned int i2c_get_bus_speed(void) */ void i2c_init(int speed, int slaveaddr) { - uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; + uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ twi->control = prescale; diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 9ed929521a..c891ebd39e 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -7,7 +7,6 @@ #include #include -#include #include "designware_i2c.h" #ifdef CONFIG_I2C_MULTI_BUS @@ -197,35 +196,18 @@ static int i2c_wait_for_bb(void) return 0; } -/* check parameters for i2c_read and i2c_write */ -static int check_params(uint addr, int alen, uchar *buffer, int len) -{ - if (buffer == NULL) { - printf("Buffer is invalid\n"); - return 1; - } - - if (alen > 1) { - printf("addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf("address out of range\n"); - return 1; - } - - return 0; -} - -static int i2c_xfer_init(uchar chip, uint addr) +static int i2c_xfer_init(uchar chip, uint addr, int alen) { if (i2c_wait_for_bb()) return 1; i2c_setaddress(chip); - writel(addr, &i2c_regs_p->ic_cmd_data); - + while (alen) { + alen--; + /* high byte address going out first */ + writel((addr >> (alen * 8)) & 0xff, + &i2c_regs_p->ic_cmd_data); + } return 0; } @@ -285,10 +267,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_rx = get_timer(0); @@ -345,10 +324,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_tx = get_timer(0); diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c new file mode 100644 index 0000000000..0b1715abf0 --- /dev/null +++ b/drivers/i2c/kona_i2c.c @@ -0,0 +1,730 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware register offsets and field defintions */ +#define CS_OFFSET 0x00000020 +#define CS_ACK_SHIFT 3 +#define CS_ACK_MASK 0x00000008 +#define CS_ACK_CMD_GEN_START 0x00000000 +#define CS_ACK_CMD_GEN_RESTART 0x00000001 +#define CS_CMD_SHIFT 1 +#define CS_CMD_CMD_NO_ACTION 0x00000000 +#define CS_CMD_CMD_START_RESTART 0x00000001 +#define CS_CMD_CMD_STOP 0x00000002 +#define CS_EN_SHIFT 0 +#define CS_EN_CMD_ENABLE_BSC 0x00000001 + +#define TIM_OFFSET 0x00000024 +#define TIM_PRESCALE_SHIFT 6 +#define TIM_P_SHIFT 3 +#define TIM_NO_DIV_SHIFT 2 +#define TIM_DIV_SHIFT 0 + +#define DAT_OFFSET 0x00000028 + +#define TOUT_OFFSET 0x0000002c + +#define TXFCR_OFFSET 0x0000003c +#define TXFCR_FIFO_FLUSH_MASK 0x00000080 +#define TXFCR_FIFO_EN_MASK 0x00000040 + +#define IER_OFFSET 0x00000044 +#define IER_READ_COMPLETE_INT_MASK 0x00000010 +#define IER_I2C_INT_EN_MASK 0x00000008 +#define IER_FIFO_INT_EN_MASK 0x00000002 +#define IER_NOACK_EN_MASK 0x00000001 + +#define ISR_OFFSET 0x00000048 +#define ISR_RESERVED_MASK 0xffffff60 +#define ISR_CMDBUSY_MASK 0x00000080 +#define ISR_READ_COMPLETE_MASK 0x00000010 +#define ISR_SES_DONE_MASK 0x00000008 +#define ISR_ERR_MASK 0x00000004 +#define ISR_TXFIFOEMPTY_MASK 0x00000002 +#define ISR_NOACK_MASK 0x00000001 + +#define CLKEN_OFFSET 0x0000004c +#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 +#define CLKEN_M_SHIFT 4 +#define CLKEN_N_SHIFT 1 +#define CLKEN_CLKEN_MASK 0x00000001 + +#define FIFO_STATUS_OFFSET 0x00000054 +#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 +#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 + +#define HSTIM_OFFSET 0x00000058 +#define HSTIM_HS_MODE_MASK 0x00008000 +#define HSTIM_HS_HOLD_SHIFT 10 +#define HSTIM_HS_HIGH_PHASE_SHIFT 5 +#define HSTIM_HS_SETUP_SHIFT 0 + +#define PADCTL_OFFSET 0x0000005c +#define PADCTL_PAD_OUT_EN_MASK 0x00000004 + +#define RXFCR_OFFSET 0x00000068 +#define RXFCR_NACK_EN_SHIFT 7 +#define RXFCR_READ_COUNT_SHIFT 0 +#define RXFIFORDOUT_OFFSET 0x0000006c + +/* Locally used constants */ +#define MAX_RX_FIFO_SIZE 64U /* bytes */ +#define MAX_TX_FIFO_SIZE 64U /* bytes */ + +#define I2C_TIMEOUT 100000 /* usecs */ + +#define WAIT_INT_CHK 100 /* usecs */ +#if I2C_TIMEOUT % WAIT_INT_CHK +#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK +#endif + +/* Operations that can be commanded to the controller */ +enum bcm_kona_cmd_t { + BCM_CMD_NOACTION = 0, + BCM_CMD_START, + BCM_CMD_RESTART, + BCM_CMD_STOP, +}; + +enum bus_speed_index { + BCM_SPD_100K = 0, + BCM_SPD_400K, + BCM_SPD_1MHZ, +}; + +/* Internal divider settings for standard mode, fast mode and fast mode plus */ +struct bus_speed_cfg { + uint8_t time_m; /* Number of cycles for setup time */ + uint8_t time_n; /* Number of cycles for hold time */ + uint8_t prescale; /* Prescale divider */ + uint8_t time_p; /* Timing coefficient */ + uint8_t no_div; /* Disable clock divider */ + uint8_t time_div; /* Post-prescale divider */ +}; + +static const struct bus_speed_cfg std_cfg_table[] = { + [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, + [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, + [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, +}; + +struct bcm_kona_i2c_dev { + void *base; + uint speed; + const struct bus_speed_cfg *std_cfg; +}; + +/* Keep these two defines in sync */ +#define DEF_SPD 100000 +#define DEF_SPD_ENUM BCM_SPD_100K + +#define DEF_DEVICE(num) \ +{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} + +static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_DEVICE(0), +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_DEVICE(1), +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_DEVICE(2), +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_DEVICE(3), +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_DEVICE(4), +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_DEVICE(5), +#endif +}; + +#define I2C_M_TEN 0x0010 /* ten bit address */ +#define I2C_M_RD 0x0001 /* read data */ +#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ + +struct i2c_msg { + uint16_t addr; + uint16_t flags; + uint16_t len; + uint8_t *buf; +}; + +static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + debug("%s, %d\n", __func__, cmd); + + switch (cmd) { + case BCM_CMD_NOACTION: + writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_START: + writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_RESTART: + writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_STOP: + writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + default: + printf("Unknown command %d\n", cmd); + } +} + +static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +/* Wait until at least one of the mask bit(s) are set */ +static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, + unsigned long time_left, + uint32_t mask) +{ + uint32_t status; + + while (time_left) { + status = readl(dev->base + ISR_OFFSET); + + if ((status & ~ISR_RESERVED_MASK) == 0) { + debug("Bogus I2C interrupt 0x%x\n", status); + continue; + } + + /* Must flush the TX FIFO when NAK detected */ + if (status & ISR_NOACK_MASK) + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); + + if (status & mask) { + /* We are done since one of the mask bits are set */ + return time_left; + } + udelay(WAIT_INT_CHK); + time_left -= WAIT_INT_CHK; + } + return 0; +} + +/* Send command to I2C bus */ +static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + int rc = 0; + unsigned long time_left = I2C_TIMEOUT; + + /* Send the command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); + + /* Wait for transaction to finish or timeout */ + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + printf("controller timed out\n"); + rc = -ETIMEDOUT; + } + + /* Clear command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + return rc; +} + +/* Read a single RX FIFO worth of data from the i2c bus */ +static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len, + unsigned int last_byte_nak) +{ + unsigned long time_left = I2C_TIMEOUT; + + /* Start the RX FIFO */ + writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | + (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); + + /* Wait for FIFO read to complete */ + time_left = + wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); + + if (!time_left) { + printf("RX FIFO time out\n"); + return -EREMOTEIO; + } + + /* Read data from FIFO */ + for (; len > 0; len--, buf++) + *buf = readl(dev->base + RXFIFORDOUT_OFFSET); + + return 0; +} + +/* Read any amount of data using the RX FIFO from the i2c bus */ +static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; + unsigned int last_byte_nak = 0; + unsigned int bytes_read = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_read < msg->len) { + if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { + last_byte_nak = 1; /* NAK last byte of transfer */ + bytes_to_read = msg->len - bytes_read; + } + + rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, + last_byte_nak); + if (rc < 0) + return -EREMOTEIO; + + bytes_read += bytes_to_read; + tmp_buf += bytes_to_read; + } + + return 0; +} + +/* Write a single byte of data to the i2c bus */ +static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, + unsigned int nak_expected) +{ + unsigned long time_left = I2C_TIMEOUT; + unsigned int nak_received; + + /* Clear pending session done interrupt */ + writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); + + /* Send one byte of data */ + writel(data, dev->base + DAT_OFFSET); + + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + debug("controller timed out\n"); + return -ETIMEDOUT; + } + + nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; + + if (nak_received ^ nak_expected) { + debug("unexpected NAK/ACK\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write a single TX FIFO worth of data to the i2c bus */ +static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len) +{ + int k; + unsigned long time_left = I2C_TIMEOUT; + unsigned int fifo_status; + + /* Write data into FIFO */ + for (k = 0; k < len; k++) + writel(buf[k], (dev->base + DAT_OFFSET)); + + /* Wait for FIFO to empty */ + do { + time_left = + wait_for_int_timeout(dev, time_left, + (IER_FIFO_INT_EN_MASK | + IER_NOACK_EN_MASK)); + fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); + } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); + + /* Check if there was a NAK */ + if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { + printf("unexpected NAK\n"); + return -EREMOTEIO; + } + + /* Check if a timeout occured */ + if (!time_left) { + printf("completion timed out\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write any amount of data using TX FIFO to the i2c bus */ +static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; + unsigned int bytes_written = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_written < msg->len) { + if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) + bytes_to_write = msg->len - bytes_written; + + rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, + bytes_to_write); + if (rc < 0) + return -EREMOTEIO; + + bytes_written += bytes_to_write; + tmp_buf += bytes_to_write; + } + + return 0; +} + +/* Send i2c address */ +static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned char addr; + + if (msg->flags & I2C_M_TEN) { + /* First byte is 11110XX0 where XX is upper 2 bits */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7); + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + /* Second byte is the remaining 8 bits */ + addr = msg->addr & 0xff; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + if (msg->flags & I2C_M_RD) { + /* For read, send restart command */ + if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) + return -EREMOTEIO; + + /* Then re-send the first byte with the read bit set */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + } else { + addr = msg->addr << 1; + + if (msg->flags & I2C_M_RD) + addr |= 1; + + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + + return 0; +} + +static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, + dev->base + HSTIM_OFFSET); + + writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | + (dev->std_cfg->time_p << TIM_P_SHIFT) | + (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | + (dev->std_cfg->time_div << TIM_DIV_SHIFT), + dev->base + TIM_OFFSET); + + writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | + (dev->std_cfg->time_n << CLKEN_N_SHIFT) | + CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); +} + +/* Master transfer function */ +static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, + struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + int rc = 0; + int i; + + /* Enable pad output */ + writel(0, dev->base + PADCTL_OFFSET); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Send start command */ + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); + if (rc < 0) { + printf("Start command failed rc = %d\n", rc); + goto xfer_disable_pad; + } + + /* Loop through all messages */ + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + + /* Send restart for subsequent messages */ + if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); + if (rc < 0) { + printf("restart cmd failed rc = %d\n", rc); + goto xfer_send_stop; + } + } + + /* Send slave address */ + if (!(pmsg->flags & I2C_M_NOSTART)) { + rc = bcm_kona_i2c_do_addr(dev, pmsg); + if (rc < 0) { + debug("NAK from addr %2.2x msg#%d rc = %d\n", + pmsg->addr, i, rc); + goto xfer_send_stop; + } + } + + /* Perform data transfer */ + if (pmsg->flags & I2C_M_RD) { + rc = bcm_kona_i2c_read_fifo(dev, pmsg); + if (rc < 0) { + printf("read failure\n"); + goto xfer_send_stop; + } + } else { + rc = bcm_kona_i2c_write_fifo(dev, pmsg); + if (rc < 0) { + printf("write failure"); + goto xfer_send_stop; + } + } + } + + rc = num; + +xfer_send_stop: + /* Send a STOP command */ + bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); + +xfer_disable_pad: + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); + + /* Stop internal clock */ + bcm_kona_i2c_disable_clock(dev); + + return rc; +} + +static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, + uint speed) +{ + switch (speed) { + case 100000: + dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; + break; + case 400000: + dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; + break; + case 1000000: + dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; + break; + default: + printf("%d hz bus speed not supported\n", speed); + return -EINVAL; + } + dev->speed = speed; + return 0; +} + +static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) +{ + /* Parse bus speed */ + bcm_kona_i2c_assign_bus_speed(dev, dev->speed); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Configure internal dividers */ + bcm_kona_i2c_config_timing(dev); + + /* Disable timeout */ + writel(0, dev->base + TOUT_OFFSET); + + /* Enable autosense */ + bcm_kona_i2c_enable_autosense(dev); + + /* Enable TX FIFO */ + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + /* Clear all pending interrupts */ + writel(ISR_CMDBUSY_MASK | + ISR_READ_COMPLETE_MASK | + ISR_SES_DONE_MASK | + ISR_ERR_MASK | + ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); + + /* Enable the controller but leave it idle */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); +} + +/* + * uboot layer + */ +struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) +{ + return &g_i2c_devs[adap->hwadapnr]; +} + +static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + if (clk_bsc_enable(dev->base)) + return; + + bcm_kona_i2c_init(dev); +} + +static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + /* msg[0] writes the addr, msg[1] reads the data */ + struct i2c_msg msg[2]; + unsigned char msgbuf0[64]; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ + + msg[1].addr = chip; + msg[1].flags = I2C_M_RD; + /* msg[1].buf dest ptr increments each read */ + + msgbuf0[0] = (unsigned char)addr; + msg[1].buf = buffer; + msg[1].len = len; + if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { + /* Sending 2 i2c messages */ + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C read: I/O error\n"); + return -EIO; + } + return 0; +} + +static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c_msg msg[0]; + unsigned char msgbuf0[64]; + unsigned int i; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 2; /* addr byte plus data */ + msg[0].buf = msgbuf0; + + for (i = 0; i < len; i++) { + msgbuf0[0] = addr++; + msgbuf0[1] = buffer[i]; + if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C write: I/O error\n"); + return -EIO; + } + } + return 0; +} + +static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + uchar tmp; + + /* + * read addr 0x0 of the given chip. + */ + return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); +} + +static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + return bcm_kona_i2c_assign_bus_speed(dev, speed); +} + +/* + * Register kona i2c adapters. Keep the order below so + * that the bus number matches the adapter number. + */ +#define DEF_ADAPTER(num) \ +U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ + kona_i2c_read, kona_i2c_write, \ + kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) + +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_ADAPTER(0) +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_ADAPTER(1) +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_ADAPTER(2) +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_ADAPTER(3) +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_ADAPTER(4) +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_ADAPTER(5) +#endif diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index a298c95e14..de3b19402b 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -64,16 +64,17 @@ static void mxs_i2c_setup_read(uint8_t chip, int len) writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); } -static void mxs_i2c_write(uchar chip, uint addr, int alen, +static int mxs_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int blen, int stop) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - uint32_t data; + uint32_t data, tmp; int i, remain, off; + int timeout = MXS_I2C_MAX_TIMEOUT; if ((alen > 4) || (alen == 0)) { debug("MXS I2C: Invalid address length\n"); - return; + return -EINVAL; } if (stop) @@ -106,6 +107,19 @@ static void mxs_i2c_write(uchar chip, uint addr, int alen, writel(data >> remain, &i2c_regs->hw_i2c_data); writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); + + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed transmitting data!\n"); + return -EINVAL; + } + + return 0; } static int mxs_i2c_wait_for_ack(void) @@ -154,7 +168,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int ret; int i; - mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) { debug("MXS I2C: Failed writing address\n"); @@ -193,7 +212,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { int ret; - mxs_i2c_write(chip, addr, alen, buffer, len, 1); + ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) debug("MXS I2C: Failed writing address\n"); @@ -204,8 +228,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { int ret; - mxs_i2c_write(chip, 0, 1, NULL, 0, 1); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1); + if (!ret) + ret = mxs_i2c_wait_for_ack(); mxs_i2c_reset(); return ret; } diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index c7840049b1..a39b5917ec 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -32,6 +32,10 @@ * - Status functions now read irqstatus_raw as per TRM guidelines * (except for OMAP243X and OMAP34XX). * - Driver now supports up to I2C5 (OMAP5). + * + * Copyright (c) 2014 Hannes Petermaier , B&R + * - Added support for set_speed + * */ #include @@ -53,43 +57,66 @@ static int wait_for_bb(struct i2c_adapter *adap); static struct i2c *omap24_get_base(struct i2c_adapter *adap); static u16 wait_for_event(struct i2c_adapter *adap); static void flush_fifo(struct i2c_adapter *adap); +static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) +{ + unsigned int sampleclk, prescaler; + int fsscll, fssclh; -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) + speed <<= 1; + prescaler = 0; + /* + * some divisors may cause a precission loss, but shouldn't + * be a big thing, because i2c_clk is then allready very slow. + */ + while (prescaler <= 0xFF) { + sampleclk = I2C_IP_CLK / (prescaler+1); + + fsscll = sampleclk / speed; + fssclh = fsscll; + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; + + if (((fsscll > 0) && (fssclh > 0)) && + ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) && + (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) { + if (pscl) + *pscl = fsscll; + if (psch) + *psch = fssclh; + + return prescaler; + } + prescaler++; + } + return -1; +} +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) { struct i2c *i2c_base = omap24_get_base(adap); - int psc, fsscll, fssclh; + int psc, fsscll = 0, fssclh = 0; int hsscll = 0, hssclh = 0; - u32 scll, sclh; - int timeout = I2C_TIMEOUT; + u32 scll = 0, sclh = 0; - /* Only handle standard, fast and high speeds */ - if ((speed != OMAP_I2C_STANDARD) && - (speed != OMAP_I2C_FAST_MODE) && - (speed != OMAP_I2C_HIGH_SPEED)) { - printf("Error : I2C unsupported speed %d\n", speed); - return; - } - - psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; - psc -= 1; - if (psc < I2C_PSC_MIN) { - printf("Error : I2C unsupported prescalar %d\n", psc); - return; - } - - if (speed == OMAP_I2C_HIGH_SPEED) { + if (speed >= OMAP_I2C_HIGH_SPEED) { /* High speed */ + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescaler %d\n", psc); + return -1; + } /* For first phase of HS mode */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / - (2 * OMAP_I2C_FAST_MODE); + fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + fssclh = fsscll; fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing first phase clock\n"); - return; + return -1; } /* For second phase of HS mode */ @@ -100,7 +127,7 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing second phase clock\n"); - return; + return -1; } scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; @@ -108,20 +135,29 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) } else { /* Standard and fast speed */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); - - fsscll -= I2C_FASTSPEED_SCLL_TRIM; - fssclh -= I2C_FASTSPEED_SCLH_TRIM; - if (((fsscll < 0) || (fssclh < 0)) || - ((fsscll > 255) || (fssclh > 255))) { + psc = omap24_i2c_findpsc(&scll, &sclh, speed); + if (0 > psc) { puts("Error : I2C initializing clock\n"); - return; + return -1; } - - scll = (unsigned int)fsscll; - sclh = (unsigned int)fssclh; } + adap->speed = speed; + adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + writew(0, &i2c_base->con); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); + writew(I2C_CON_EN, &i2c_base->con); + writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ + + return 0; +} +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int timeout = I2C_TIMEOUT; + if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); @@ -139,14 +175,14 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) udelay(1000); } - writew(0, &i2c_base->con); - writew(psc, &i2c_base->psc); - writew(scll, &i2c_base->scll); - writew(sclh, &i2c_base->sclh); + if (0 != omap24_i2c_setspeed(adap, speed)) { + printf("ERROR: failed to setup I2C bus-speed!\n"); + return; + } /* own address */ writew(slaveadd, &i2c_base->oa); - writew(I2C_CON_EN, &i2c_base->con); + #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have @@ -165,7 +201,8 @@ static void flush_fifo(struct i2c_adapter *adap) struct i2c *i2c_base = omap24_get_base(adap); u16 stat; - /* note: if you try and read data when its not there or ready + /* + * note: if you try and read data when its not there or ready * you get a bus error */ while (1) { @@ -220,8 +257,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { - res = 0; /* Device found */ - udelay(I2C_WAIT); /* Required by AM335X in SPL */ + res = 0; /* Device found */ + udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -307,7 +344,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); @@ -351,7 +388,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; goto rd_exit; } @@ -379,6 +416,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int i; u16 status; int i2c_error = 0; + int timeout = I2C_TIMEOUT; if (alen < 0) { puts("I2C write: addr len < 0\n"); @@ -428,7 +466,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto wr_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", status); @@ -448,7 +486,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, /* Address phase is over, now write data */ for (i = 0; i < len; i++) { status = wait_for_event(adap); - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", status); @@ -464,6 +502,15 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, goto wr_exit; } } + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(adap); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) + printf("i2c_write: timed out writig last byte!\n"); wr_exit: flush_fifo(adap); @@ -490,7 +537,7 @@ static int wait_for_bb(struct i2c_adapter *adap) I2C_STAT_BB) && timeout--) { #endif writew(stat, &i2c_base->stat); - udelay(I2C_WAIT); + udelay(adap->waitdelay); } if (timeout <= 0) { @@ -513,7 +560,7 @@ static u16 wait_for_event(struct i2c_adapter *adap) int timeout = I2C_TIMEOUT; do { - udelay(I2C_WAIT); + udelay(adap->waitdelay); #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); #else @@ -580,12 +627,12 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) #endif U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE, 0) U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED1, CONFIG_SYS_OMAP24_I2C_SLAVE1, 1) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index cc19100750..e7e96921d2 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -269,7 +269,9 @@ static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, static int sh_i2c_probe(struct i2c_adapter *adap, u8 dev) { - return sh_i2c_read(adap, dev, 0, 0, NULL, 0); + u8 dummy[1]; + + return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy); } static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index dfea54ae73..db9b4026b3 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -29,9 +29,6 @@ #include #endif #endif -#ifdef CONFIG_IXP425 /* only valid for IXP425 */ -#include -#endif #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) #include #endif diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index e8dac237a9..a2501e0206 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -39,20 +40,34 @@ static struct keyb { * @param config Keyboard config * @param keys List of keys that we have detected * @param max_count Maximum number of keys to return - * @return number of pressed keys, 0 for none + * @param samep Set to true if this scan repeats the last, else false + * @return number of pressed keys, 0 for none, -EIO on error */ static int check_for_keys(struct keyb *config, - struct key_matrix_key *keys, int max_count) + struct key_matrix_key *keys, int max_count, + bool *samep) { struct key_matrix_key *key; + static struct mbkp_keyscan last_scan; + static bool last_scan_valid; struct mbkp_keyscan scan; unsigned int row, col, bit, data; int num_keys; if (cros_ec_scan_keyboard(config->dev, &scan)) { debug("%s: keyboard scan failed\n", __func__); - return -1; + return -EIO; } + *samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan)); + + /* + * This is a bit odd. The EC has no way to tell us that it has run + * out of key scans. It just returns the same scan over and over + * again. So the only way to detect that we have run out is to detect + * that this scan is the same as the last. + */ + last_scan_valid = true; + memcpy(&last_scan, &scan, sizeof(last_scan)); for (col = num_keys = bit = 0; col < config->matrix.num_cols; col++) { @@ -112,6 +127,7 @@ int cros_ec_kbc_check(struct input_config *input) int keycodes[KBC_MAX_KEYS]; int num_keys, num_keycodes; int irq_pending, sent; + bool same = false; /* * Loop until the EC has no more keyscan records, or we have @@ -125,7 +141,10 @@ int cros_ec_kbc_check(struct input_config *input) do { irq_pending = cros_ec_interrupt_pending(config.dev); if (irq_pending) { - num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS); + num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS, + &same); + if (num_keys < 0) + return 0; last_num_keys = num_keys; memcpy(last_keys, keys, sizeof(keys)); } else { @@ -142,6 +161,13 @@ int cros_ec_kbc_check(struct input_config *input) num_keycodes = key_matrix_decode(&config.matrix, keys, num_keys, keycodes, KBC_MAX_KEYS); sent = input_send_keycodes(input, keycodes, num_keycodes); + + /* + * For those ECs without an interrupt, stop scanning when we + * see that the scan is the same as last time. + */ + if ((irq_pending < 0) && same) + break; } while (irq_pending && !sent); return 1; diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c77e40a2d4..2f2e48f979 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -11,11 +11,13 @@ obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o +obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_GPIO_LED) += gpio_led.o obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_STATUS_LED) += status_led.o diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 301e8ebbf5..068373b942 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -7,10 +7,11 @@ */ /* - * The Matrix Keyboard Protocol driver handles talking to the keyboard - * controller chip. Mostly this is for keyboard functions, but some other - * things have slipped in, so we provide generic services to talk to the - * KBC. + * This is the interface to the Chrome OS EC. It provides keyboard functions, + * power control and battery management. Quite a few other functions are + * provided to enable the EC software to be updated, talk to the EC's I2C bus + * and store a small amount of data in a memory which persists while the EC + * is not reset. */ #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include @@ -73,11 +75,184 @@ int cros_ec_calc_checksum(const uint8_t *data, int size) return csum & 0xff; } +/** + * Create a request packet for protocol version 3. + * + * The packet is stored in the device's internal output buffer. + * + * @param dev CROS-EC device + * @param cmd Command to send (EC_CMD_...) + * @param cmd_version Version of command to send (EC_VER_...) + * @param dout Output data (may be NULL If dout_len=0) + * @param dout_len Size of output data in bytes + * @return packet size in bytes, or <0 if error. + */ +static int create_proto3_request(struct cros_ec_dev *dev, + int cmd, int cmd_version, + const void *dout, int dout_len) +{ + struct ec_host_request *rq = (struct ec_host_request *)dev->dout; + int out_bytes = dout_len + sizeof(*rq); + + /* Fail if output size is too big */ + if (out_bytes > (int)sizeof(dev->dout)) { + debug("%s: Cannot send %d bytes\n", __func__, dout_len); + return -EC_RES_REQUEST_TRUNCATED; + } + + /* Fill in request packet */ + rq->struct_version = EC_HOST_REQUEST_VERSION; + rq->checksum = 0; + rq->command = cmd; + rq->command_version = cmd_version; + rq->reserved = 0; + rq->data_len = dout_len; + + /* Copy data after header */ + memcpy(rq + 1, dout, dout_len); + + /* Write checksum field so the entire packet sums to 0 */ + rq->checksum = (uint8_t)(-cros_ec_calc_checksum(dev->dout, out_bytes)); + + cros_ec_dump_data("out", cmd, dev->dout, out_bytes); + + /* Return size of request packet */ + return out_bytes; +} + +/** + * Prepare the device to receive a protocol version 3 response. + * + * @param dev CROS-EC device + * @param din_len Maximum size of response in bytes + * @return maximum expected number of bytes in response, or <0 if error. + */ +static int prepare_proto3_response_buffer(struct cros_ec_dev *dev, int din_len) +{ + int in_bytes = din_len + sizeof(struct ec_host_response); + + /* Fail if input size is too big */ + if (in_bytes > (int)sizeof(dev->din)) { + debug("%s: Cannot receive %d bytes\n", __func__, din_len); + return -EC_RES_RESPONSE_TOO_BIG; + } + + /* Return expected size of response packet */ + return in_bytes; +} + +/** + * Handle a protocol version 3 response packet. + * + * The packet must already be stored in the device's internal input buffer. + * + * @param dev CROS-EC device + * @param dinp Returns pointer to response data + * @param din_len Maximum size of response in bytes + * @return number of bytes of response data, or <0 if error + */ +static int handle_proto3_response(struct cros_ec_dev *dev, + uint8_t **dinp, int din_len) +{ + struct ec_host_response *rs = (struct ec_host_response *)dev->din; + int in_bytes; + int csum; + + cros_ec_dump_data("in-header", -1, dev->din, sizeof(*rs)); + + /* Check input data */ + if (rs->struct_version != EC_HOST_RESPONSE_VERSION) { + debug("%s: EC response version mismatch\n", __func__); + return -EC_RES_INVALID_RESPONSE; + } + + if (rs->reserved) { + debug("%s: EC response reserved != 0\n", __func__); + return -EC_RES_INVALID_RESPONSE; + } + + if (rs->data_len > din_len) { + debug("%s: EC returned too much data\n", __func__); + return -EC_RES_RESPONSE_TOO_BIG; + } + + cros_ec_dump_data("in-data", -1, dev->din + sizeof(*rs), rs->data_len); + + /* Update in_bytes to actual data size */ + in_bytes = sizeof(*rs) + rs->data_len; + + /* Verify checksum */ + csum = cros_ec_calc_checksum(dev->din, in_bytes); + if (csum) { + debug("%s: EC response checksum invalid: 0x%02x\n", __func__, + csum); + return -EC_RES_INVALID_CHECKSUM; + } + + /* Return error result, if any */ + if (rs->result) + return -(int)rs->result; + + /* If we're still here, set response data pointer and return length */ + *dinp = (uint8_t *)(rs + 1); + + return rs->data_len; +} + +static int send_command_proto3(struct cros_ec_dev *dev, + int cmd, int cmd_version, + const void *dout, int dout_len, + uint8_t **dinp, int din_len) +{ + int out_bytes, in_bytes; + int rv; + + /* Create request packet */ + out_bytes = create_proto3_request(dev, cmd, cmd_version, + dout, dout_len); + if (out_bytes < 0) + return out_bytes; + + /* Prepare response buffer */ + in_bytes = prepare_proto3_response_buffer(dev, din_len); + if (in_bytes < 0) + return in_bytes; + + switch (dev->interface) { +#ifdef CONFIG_CROS_EC_SPI + case CROS_EC_IF_SPI: + rv = cros_ec_spi_packet(dev, out_bytes, in_bytes); + break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case CROS_EC_IF_SANDBOX: + rv = cros_ec_sandbox_packet(dev, out_bytes, in_bytes); + break; +#endif + case CROS_EC_IF_NONE: + /* TODO: support protocol 3 for LPC, I2C; for now fall through */ + default: + debug("%s: Unsupported interface\n", __func__); + rv = -1; + } + if (rv < 0) + return rv; + + /* Process the response */ + return handle_proto3_response(dev, dinp, din_len); +} + static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - int ret; + int ret = -1; + + /* Handle protocol version 3 support */ + if (dev->protocol_version == 3) { + return send_command_proto3(dev, cmd, cmd_version, + dout, dout_len, dinp, din_len); + } switch (dev->interface) { #ifdef CONFIG_CROS_EC_SPI @@ -129,19 +304,15 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - uint8_t *din; + uint8_t *din = NULL; int len; - if (cmd_version != 0 && !dev->cmd_version_is_supported) { - debug("%s: Command version >0 unsupported\n", __func__); - return -1; - } len = send_command(dev, cmd, cmd_version, dout, dout_len, &din, din_len); /* If the command doesn't complete, wait a while */ if (len == -EC_RES_IN_PROGRESS) { - struct ec_response_get_comms_status *resp; + struct ec_response_get_comms_status *resp = NULL; ulong start; /* Wait for command to complete */ @@ -169,7 +340,8 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd, NULL, 0, &din, din_len); } - debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, *dinp); + debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, + dinp ? *dinp : NULL); if (dinp) { /* If we have any data to return, it must be 64bit-aligned */ assert(len <= 0 || !((uintptr_t)din & 7)); @@ -220,8 +392,8 @@ static int ec_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan) { - if (ec_command(dev, EC_CMD_CROS_EC_STATE, 0, NULL, 0, scan, - sizeof(scan->data)) < sizeof(scan->data)) + if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, + sizeof(scan->data)) != sizeof(scan->data)) return -1; return 0; @@ -232,10 +404,10 @@ int cros_ec_read_id(struct cros_ec_dev *dev, char *id, int maxlen) struct ec_response_get_version *r; if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, - (uint8_t **)&r, sizeof(*r)) < sizeof(*r)) + (uint8_t **)&r, sizeof(*r)) != sizeof(*r)) return -1; - if (maxlen > sizeof(r->version_string_ro)) + if (maxlen > (int)sizeof(r->version_string_ro)) maxlen = sizeof(r->version_string_ro); switch (r->current_image) { @@ -258,7 +430,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev, { if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, (uint8_t **)versionp, sizeof(**versionp)) - < sizeof(**versionp)) + != sizeof(**versionp)) return -1; return 0; @@ -267,7 +439,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev, int cros_ec_read_build_info(struct cros_ec_dev *dev, char **strp) { if (ec_command_inptr(dev, EC_CMD_GET_BUILD_INFO, 0, NULL, 0, - (uint8_t **)strp, EC_HOST_PARAM_SIZE) < 0) + (uint8_t **)strp, EC_PROTO2_MAX_PARAM_SIZE) < 0) return -1; return 0; @@ -279,7 +451,7 @@ int cros_ec_read_current_image(struct cros_ec_dev *dev, struct ec_response_get_version *r; if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, - (uint8_t **)&r, sizeof(*r)) < sizeof(*r)) + (uint8_t **)&r, sizeof(*r)) != sizeof(*r)) return -1; *image = r->current_image; @@ -336,7 +508,7 @@ int cros_ec_read_hash(struct cros_ec_dev *dev, debug("%s: No valid hash (status=%d size=%d). Compute one...\n", __func__, hash->status, hash->size); - p.cmd = EC_VBOOT_HASH_RECALC; + p.cmd = EC_VBOOT_HASH_START; p.hash_type = EC_VBOOT_HASH_TYPE_SHA256; p.nonce_size = 0; p.offset = EC_VBOOT_HASH_OFFSET_RW; @@ -413,15 +585,15 @@ int cros_ec_interrupt_pending(struct cros_ec_dev *dev) { /* no interrupt support : always poll */ if (!fdt_gpio_isvalid(&dev->ec_int)) - return 1; + return -ENOENT; return !gpio_get_value(dev->ec_int.gpio); } -int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_cros_ec_info *info) +int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_mkbp_info *info) { - if (ec_command(dev, EC_CMD_CROS_EC_INFO, 0, NULL, 0, info, - sizeof(*info)) < sizeof(*info)) + if (ec_command(dev, EC_CMD_MKBP_INFO, 0, NULL, 0, info, + sizeof(*info)) != sizeof(*info)) return -1; return 0; @@ -436,7 +608,7 @@ int cros_ec_get_host_events(struct cros_ec_dev *dev, uint32_t *events_ptr) * used by ACPI/SMI. */ if (ec_command_inptr(dev, EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0, - (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp)) + (uint8_t **)&resp, sizeof(*resp)) < (int)sizeof(*resp)) return -1; if (resp->mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) @@ -474,7 +646,7 @@ int cros_ec_flash_protect(struct cros_ec_dev *dev, if (ec_command(dev, EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT, ¶ms, sizeof(params), - resp, sizeof(*resp)) < sizeof(*resp)) + resp, sizeof(*resp)) != sizeof(*resp)) return -1; return 0; @@ -504,23 +676,30 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) * * So for now, just read all the data anyway. */ - dev->cmd_version_is_supported = 1; + + /* Try sending a version 3 packet */ + dev->protocol_version = 3; if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), - (uint8_t **)&resp, sizeof(*resp)) > 0) { - /* It appears to understand new version commands */ - dev->cmd_version_is_supported = 1; - } else { - dev->cmd_version_is_supported = 0; - if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, - sizeof(req), (uint8_t **)&resp, - sizeof(*resp)) < 0) { - debug("%s: Failed both old and new command style\n", - __func__); - return -1; - } + (uint8_t **)&resp, sizeof(*resp)) > 0) { + return 0; } - return 0; + /* Try sending a version 2 packet */ + dev->protocol_version = 2; + if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), + (uint8_t **)&resp, sizeof(*resp)) > 0) { + return 0; + } + + /* + * Fail if we're still here, since the EC doesn't understand any + * protcol version we speak. Version 1 interface without command + * version is no longer supported, and we don't know about any new + * protocol versions. + */ + dev->protocol_version = 0; + printf("%s: ERROR: old EC interface not supported\n", __func__); + return -1; } int cros_ec_test(struct cros_ec_dev *dev) @@ -599,8 +778,8 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev, p.offset = offset; p.size = size; - assert(data && p.size <= sizeof(p.data)); - memcpy(p.data, data, p.size); + assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE); + memcpy(&p + 1, data, p.size); return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0, &p, sizeof(p), NULL, 0) >= 0 ? 0 : -1; @@ -611,8 +790,7 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev, */ static int cros_ec_flash_write_burst_size(struct cros_ec_dev *dev) { - struct ec_params_flash_write p; - return sizeof(p.data); + return EC_FLASH_WRITE_VER0_SIZE; } /** @@ -718,7 +896,7 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, if (cros_ec_flash_offset(dev, EC_FLASH_REGION_RW, &rw_offset, &rw_size)) return -1; - if (image_size > rw_size) + if (image_size > (int)rw_size) return -1; /* Invalidate the existing hash, just in case the AP reboots @@ -804,7 +982,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state) if (ec_command_inptr(dev, EC_CMD_LDO_GET, 0, ¶ms, sizeof(params), - (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp)) + (uint8_t **)&resp, sizeof(*resp)) != sizeof(*resp)) return -1; *state = resp->state; @@ -813,7 +991,8 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state) } /** - * Decode MBKP details from the device tree and allocate a suitable device. + * Decode EC interface details from the device tree and allocate a suitable + * device. * * @param blob Device tree blob * @param node Node to decode from @@ -858,6 +1037,11 @@ static int cros_ec_decode_fdt(const void *blob, int node, case COMPAT_INTEL_LPC: dev->interface = CROS_EC_IF_LPC; break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case COMPAT_SANDBOX_HOST_EMULATION: + dev->interface = CROS_EC_IF_SANDBOX; + break; #endif default: debug("%s: Unknown compat id %d\n", __func__, compat); @@ -913,6 +1097,12 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) if (cros_ec_lpc_init(dev, blob)) return -CROS_EC_ERR_DEV_INIT; break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case CROS_EC_IF_SANDBOX: + if (cros_ec_sandbox_init(dev, blob)) + return -CROS_EC_ERR_DEV_INIT; + break; #endif case CROS_EC_IF_NONE: default: @@ -941,7 +1131,6 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) return 0; } -#ifdef CONFIG_CMD_CROS_EC int cros_ec_decode_region(int argc, char * const argv[]) { if (argc > 0) { @@ -958,6 +1147,139 @@ int cros_ec_decode_region(int argc, char * const argv[]) return -1; } +int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config) +{ + int flash_node, node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC); + if (node < 0) { + debug("Failed to find chrome-ec node'\n"); + return -1; + } + + flash_node = fdt_subnode_offset(blob, node, "flash"); + if (flash_node < 0) { + debug("Failed to find flash node\n"); + return -1; + } + + if (fdtdec_read_fmap_entry(blob, flash_node, "flash", + &config->flash)) { + debug("Failed to decode flash node in chrome-ec'\n"); + return -1; + } + + config->flash_erase_value = fdtdec_get_int(blob, flash_node, + "erase-value", -1); + for (node = fdt_first_subnode(blob, flash_node); node >= 0; + node = fdt_next_subnode(blob, node)) { + const char *name = fdt_get_name(blob, node, NULL); + enum ec_flash_region region; + + if (0 == strcmp(name, "ro")) { + region = EC_FLASH_REGION_RO; + } else if (0 == strcmp(name, "rw")) { + region = EC_FLASH_REGION_RW; + } else if (0 == strcmp(name, "wp-ro")) { + region = EC_FLASH_REGION_WP_RO; + } else { + debug("Unknown EC flash region name '%s'\n", name); + return -1; + } + + if (fdtdec_read_fmap_entry(blob, node, "reg", + &config->region[region])) { + debug("Failed to decode flash region in chrome-ec'\n"); + return -1; + } + } + + return 0; +} + +int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read) +{ + union { + struct ec_params_i2c_passthru p; + uint8_t outbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } params; + union { + struct ec_response_i2c_passthru r; + uint8_t inbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } response; + struct ec_params_i2c_passthru *p = ¶ms.p; + struct ec_response_i2c_passthru *r = &response.r; + struct ec_params_i2c_passthru_msg *msg = p->msg; + uint8_t *pdata; + int read_len, write_len; + int size; + int rv; + + p->port = 0; + + if (alen != 1) { + printf("Unsupported address length %d\n", alen); + return -1; + } + if (is_read) { + read_len = len; + write_len = alen; + p->num_msgs = 2; + } else { + read_len = 0; + write_len = alen + len; + p->num_msgs = 1; + } + + size = sizeof(*p) + p->num_msgs * sizeof(*msg); + if (size + write_len > sizeof(params)) { + puts("Params too large for buffer\n"); + return -1; + } + if (sizeof(*r) + read_len > sizeof(response)) { + puts("Read length too big for buffer\n"); + return -1; + } + + /* Create a message to write the register address and optional data */ + pdata = (uint8_t *)p + size; + msg->addr_flags = chip; + msg->len = write_len; + pdata[0] = addr; + if (!is_read) + memcpy(pdata + 1, buffer, len); + msg++; + + if (read_len) { + msg->addr_flags = chip | EC_I2C_FLAG_READ; + msg->len = read_len; + } + + rv = ec_command(dev, EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, + r, sizeof(*r) + read_len); + if (rv < 0) + return rv; + + /* Parse response */ + if (r->i2c_status & EC_I2C_STATUS_ERROR) { + printf("Transfer failed with status=0x%x\n", r->i2c_status); + return -1; + } + + if (rv < sizeof(*r) + read_len) { + puts("Truncated read response\n"); + return -1; + } + + if (read_len) + memcpy(buffer, r->data, read_len); + + return 0; +} + +#ifdef CONFIG_CMD_CROS_EC + /** * Perform a flash read or write command * @@ -1011,6 +1333,187 @@ static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc, return 0; } +/** + * get_alen() - Small parser helper function to get address length + * + * Returns the address length. + */ +static uint get_alen(char *arg) +{ + int j; + int alen; + + alen = 1; + for (j = 0; j < 8; j++) { + if (arg[j] == '.') { + alen = arg[j+1] - '0'; + break; + } else if (arg[j] == '\0') { + break; + } + } + return alen; +} + +#define DISP_LINE_LEN 16 + +/* + * TODO(sjg@chromium.org): This code copied almost verbatim from cmd_i2c.c + * so we can remove it later. + */ +static int cros_ec_i2c_md(struct cros_ec_dev *dev, int flag, int argc, + char * const argv[]) +{ + u_char chip; + uint addr, alen, length = 0x10; + int j, nbytes, linebytes; + + if (argc < 2) + return CMD_RET_USAGE; + + if (1 || (flag & CMD_FLAG_REPEAT) == 0) { + /* + * New command specified. + */ + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[0], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + addr = simple_strtoul(argv[1], NULL, 16); + alen = get_alen(argv[1]); + if (alen > 3) + return CMD_RET_USAGE; + + /* + * If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if (argc > 2) + length = simple_strtoul(argv[2], NULL, 16); + } + + /* + * Print the lines. + * + * We buffer all read data, so we can make sure data is read only + * once. + */ + nbytes = length; + do { + unsigned char linebuf[DISP_LINE_LEN]; + unsigned char *cp; + + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + + if (cros_ec_i2c_xfer(dev, chip, addr, alen, linebuf, linebytes, + 1)) + puts("Error reading the chip.\n"); + else { + printf("%04x:", addr); + cp = linebuf; + for (j = 0; j < linebytes; j++) { + printf(" %02x", *cp++); + addr++; + } + puts(" "); + cp = linebuf; + for (j = 0; j < linebytes; j++) { + if ((*cp < 0x20) || (*cp > 0x7e)) + puts("."); + else + printf("%c", *cp); + cp++; + } + putc('\n'); + } + nbytes -= linebytes; + } while (nbytes > 0); + + return 0; +} + +static int cros_ec_i2c_mw(struct cros_ec_dev *dev, int flag, int argc, + char * const argv[]) +{ + uchar chip; + ulong addr; + uint alen; + uchar byte; + int count; + + if ((argc < 3) || (argc > 4)) + return CMD_RET_USAGE; + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[0], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[1], NULL, 16); + alen = get_alen(argv[1]); + if (alen > 3) + return CMD_RET_USAGE; + + /* + * Value to write is always specified. + */ + byte = simple_strtoul(argv[2], NULL, 16); + + /* + * Optional count + */ + if (argc == 4) + count = simple_strtoul(argv[3], NULL, 16); + else + count = 1; + + while (count-- > 0) { + if (cros_ec_i2c_xfer(dev, chip, addr++, alen, &byte, 1, 0)) + puts("Error writing the chip.\n"); + /* + * Wait for the write to complete. The write can take + * up to 10mSec (we allow a little more time). + */ +/* + * No write delay with FRAM devices. + */ +#if !defined(CONFIG_SYS_I2C_FRAM) + udelay(11000); +#endif + } + + return 0; +} + +/* Temporary code until we have driver model and can use the i2c command */ +static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag, + int argc, char * const argv[]) +{ + const char *cmd; + + if (argc < 1) + return CMD_RET_USAGE; + cmd = *argv++; + argc--; + if (0 == strcmp("md", cmd)) + cros_ec_i2c_md(dev, flag, argc, argv); + else if (0 == strcmp("mw", cmd)) + cros_ec_i2c_mw(dev, flag, argc, argv); + else + return CMD_RET_USAGE; + + return 0; +} + static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct cros_ec_dev *dev = last_dev; @@ -1044,7 +1547,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } printf("%s\n", id); } else if (0 == strcmp("info", cmd)) { - struct ec_response_cros_ec_info info; + struct ec_response_mkbp_info info; if (cros_ec_info(dev, &info)) { debug("%s: Could not read KBC info\n", __func__); @@ -1213,10 +1716,10 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!ret) { /* Print versions */ printf("RO version: %1.*s\n", - sizeof(p->version_string_ro), + (int)sizeof(p->version_string_ro), p->version_string_ro); printf("RW version: %1.*s\n", - sizeof(p->version_string_rw), + (int)sizeof(p->version_string_rw), p->version_string_rw); printf("Firmware copy: %s\n", (p->current_image < @@ -1254,6 +1757,8 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) debug("%s: Could not access LDO%d\n", __func__, index); return ret; } + } else if (0 == strcmp("i2c", cmd)) { + ret = cros_ec_i2c_passthrough(dev, flag, argc - 2, argv + 2); } else { return CMD_RET_USAGE; } @@ -1267,7 +1772,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - crosec, 5, 1, do_cros_ec, + crosec, 6, 1, do_cros_ec, "CROS-EC utility command", "init Re-init CROS-EC (done on startup automatically)\n" "crosec id Read CROS-EC ID\n" @@ -1284,6 +1789,8 @@ U_BOOT_CMD( "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n" "crosec ldo [] Switch/Read LDO state\n" "crosec test run tests on cros_ec\n" - "crosec version Read CROS-EC version" + "crosec version Read CROS-EC version\n" + "crosec i2c md chip address[.0, .1, .2] [# of objects] - read from I2C passthru\n" + "crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)" ); #endif diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c index 0fbab991b5..513cdb1cb0 100644 --- a/drivers/misc/cros_ec_i2c.c +++ b/drivers/misc/cros_ec_i2c.c @@ -35,7 +35,7 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, uint8_t *ptr; /* Receive input data, so that args will be dword aligned */ uint8_t *in_ptr; - int ret; + int len, csum, ret; old_bus = i2c_get_bus_num(); @@ -67,24 +67,24 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, * will be dword aligned. */ in_ptr = dev->din + sizeof(int64_t); - if (!dev->cmd_version_is_supported) { - /* Send an old-style command */ - *ptr++ = cmd; - out_bytes = dout_len + 1; - in_bytes = din_len + 2; - in_ptr--; /* Expect just a status byte */ - } else { - *ptr++ = EC_CMD_VERSION0 + cmd_version; - *ptr++ = cmd; - *ptr++ = dout_len; - in_ptr -= 2; /* Expect status, length bytes */ + + if (dev->protocol_version != 2) { + /* Something we don't support */ + debug("%s: Protocol version %d unsupported\n", + __func__, dev->protocol_version); + return -1; } + + *ptr++ = EC_CMD_VERSION0 + cmd_version; + *ptr++ = cmd; + *ptr++ = dout_len; + in_ptr -= 2; /* Expect status, length bytes */ + memcpy(ptr, dout, dout_len); ptr += dout_len; - if (dev->cmd_version_is_supported) - *ptr++ = (uint8_t) - cros_ec_calc_checksum(dev->dout, dout_len + 3); + *ptr++ = (uint8_t) + cros_ec_calc_checksum(dev->dout, dout_len + 3); /* Set to the proper i2c bus */ if (i2c_set_bus_num(dev->bus_num)) { @@ -121,26 +121,20 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, return -(int)*in_ptr; } - if (dev->cmd_version_is_supported) { - int len, csum; - - len = in_ptr[1]; - if (len + 3 > sizeof(dev->din)) { - debug("%s: Received length %#02x too large\n", - __func__, len); - return -1; - } - csum = cros_ec_calc_checksum(in_ptr, 2 + len); - if (csum != in_ptr[2 + len]) { - debug("%s: Invalid checksum rx %#02x, calced %#02x\n", - __func__, in_ptr[2 + din_len], csum); - return -1; - } - din_len = min(din_len, len); - cros_ec_dump_data("in", -1, in_ptr, din_len + 3); - } else { - cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes); + len = in_ptr[1]; + if (len + 3 > sizeof(dev->din)) { + debug("%s: Received length %#02x too large\n", + __func__, len); + return -1; } + csum = cros_ec_calc_checksum(in_ptr, 2 + len); + if (csum != in_ptr[2 + len]) { + debug("%s: Invalid checksum rx %#02x, calced %#02x\n", + __func__, in_ptr[2 + din_len], csum); + return -1; + } + din_len = min(din_len, len); + cros_ec_dump_data("in", -1, in_ptr, din_len + 3); /* Return pointer to dword-aligned input data, if any */ *dinp = dev->din + sizeof(int64_t); @@ -178,7 +172,5 @@ int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob) { i2c_init(dev->max_frequency, dev->addr); - dev->cmd_version_is_supported = 0; - return 0; } diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 725747693d..0e02671c93 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -40,71 +40,6 @@ static int wait_for_sync(struct cros_ec_dev *dev) return 0; } -/** - * Send a command to a LPC CROS_EC device and return the reply. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS_EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Place to put pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -static int old_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len) -{ - int ret, i; - - if (dout_len > EC_OLD_PARAM_SIZE) { - debug("%s: Cannot send %d bytes\n", __func__, dout_len); - return -1; - } - - if (din_len > EC_OLD_PARAM_SIZE) { - debug("%s: Cannot receive %d bytes\n", __func__, din_len); - return -1; - } - - if (wait_for_sync(dev)) { - debug("%s: Timeout waiting ready\n", __func__); - return -1; - } - - debug_trace("cmd: %02x, ", cmd); - for (i = 0; i < dout_len; i++) { - debug_trace("%02x ", dout[i]); - outb(dout[i], EC_LPC_ADDR_OLD_PARAM + i); - } - outb(cmd, EC_LPC_ADDR_HOST_CMD); - debug_trace("\n"); - - if (wait_for_sync(dev)) { - debug("%s: Timeout waiting ready\n", __func__); - return -1; - } - - ret = inb(EC_LPC_ADDR_HOST_DATA); - if (ret) { - debug("%s: CROS_EC result code %d\n", __func__, ret); - return -ret; - } - - debug_trace("resp: %02x, ", ret); - for (i = 0; i < din_len; i++) { - dev->din[i] = inb(EC_LPC_ADDR_OLD_PARAM + i); - debug_trace("%02x ", dev->din[i]); - } - debug_trace("\n"); - *dinp = dev->din; - - return din_len; -} - int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len) @@ -119,11 +54,6 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int csum; int i; - /* Fall back to old-style command interface if args aren't supported */ - if (!dev->cmd_version_is_supported) - return old_lpc_command(dev, cmd, dout, dout_len, dinp, - din_len); - if (dout_len > EC_HOST_PARAM_SIZE) { debug("%s: Cannot send %d bytes\n", __func__, dout_len); return -1; @@ -256,13 +186,9 @@ int cros_ec_lpc_check_version(struct cros_ec_dev *dev) (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS) & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) { - dev->cmd_version_is_supported = 1; - } else { - /* We are going to use the old IO ports */ - dev->cmd_version_is_supported = 0; + return 0; } - debug("lpc: version %s\n", dev->cmd_version_is_supported ? - "new" : "old"); - return 0; + printf("%s: ERROR: old EC interface not supported\n", __func__); + return -1; } diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c new file mode 100644 index 0000000000..4bb1d60e5a --- /dev/null +++ b/drivers/misc/cros_ec_sandbox.c @@ -0,0 +1,559 @@ +/* + * Chromium OS cros_ec driver - sandbox emulation + * + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Ultimately it shold be possible to connect an Chrome OS EC emulation + * to U-Boot and remove all of this code. But this provides a test + * environment for bringing up chromeos_sandbox and demonstrating its + * utility. + * + * This emulation includes the following: + * + * 1. Emulation of the keyboard, by converting keypresses received from SDL + * into key scan data, passed back from the EC as key scan messages. The + * key layout is read from the device tree. + * + * 2. Emulation of vboot context - so this can be read/written as required. + * + * 3. Save/restore of EC state, so that the vboot context, flash memory + * contents and current image can be preserved across boots. This is important + * since the EC is supposed to continue running even if the AP resets. + * + * 4. Some event support, in particular allowing Escape to be pressed on boot + * to enter recovery mode. The EC passes this to U-Boot through the normal + * event message. + * + * 5. Flash read/write/erase support, so that software sync works. The + * protect messages are supported but no protection is implemented. + * + * 6. Hashing of the EC image, again to support software sync. + * + * Other features can be added, although a better path is probably to link + * the EC image in with U-Boot (Vic has demonstrated a prototype for this). + */ + +DECLARE_GLOBAL_DATA_PTR; + +#define KEYBOARD_ROWS 8 +#define KEYBOARD_COLS 13 + +/* A single entry of the key matrix */ +struct ec_keymatrix_entry { + int row; /* key matrix row */ + int col; /* key matrix column */ + int keycode; /* corresponding linux key code */ +}; + +/** + * struct ec_state - Information about the EC state + * + * @vbnv_context: Vboot context data stored by EC + * @ec_config: FDT config information about the EC (e.g. flashmap) + * @flash_data: Contents of flash memory + * @flash_data_len: Size of flash memory + * @current_image: Current image the EC is running + * @matrix_count: Number of keys to decode in matrix + * @matrix: Information about keyboard matrix + * @keyscan: Current keyscan information (bit set for each row/column pressed) + * @recovery_req: Keyboard recovery requested + */ +struct ec_state { + uint8_t vbnv_context[EC_VBNV_BLOCK_SIZE]; + struct fdt_cros_ec ec_config; + uint8_t *flash_data; + int flash_data_len; + enum ec_current_image current_image; + int matrix_count; + struct ec_keymatrix_entry *matrix; /* the key matrix info */ + uint8_t keyscan[KEYBOARD_COLS]; + bool recovery_req; +} s_state, *state; + +/** + * cros_ec_read_state() - read the sandbox EC state from the state file + * + * If data is available, then blob and node will provide access to it. If + * not this function sets up an empty EC. + * + * @param blob: Pointer to device tree blob, or NULL if no data to read + * @param node: Node offset to read from + */ +static int cros_ec_read_state(const void *blob, int node) +{ + struct ec_state *ec = &s_state; + const char *prop; + int len; + + /* Set everything to defaults */ + ec->current_image = EC_IMAGE_RO; + if (!blob) + return 0; + + /* Read the data if available */ + ec->current_image = fdtdec_get_int(blob, node, "current-image", + EC_IMAGE_RO); + prop = fdt_getprop(blob, node, "vbnv-context", &len); + if (prop && len == sizeof(ec->vbnv_context)) + memcpy(ec->vbnv_context, prop, len); + + prop = fdt_getprop(blob, node, "flash-data", &len); + if (prop) { + ec->flash_data_len = len; + ec->flash_data = os_malloc(len); + if (!ec->flash_data) + return -ENOMEM; + memcpy(ec->flash_data, prop, len); + debug("%s: Loaded EC flash data size %#x\n", __func__, len); + } + + return 0; +} + +/** + * cros_ec_write_state() - Write out our state to the state file + * + * The caller will ensure that there is a node ready for the state. The node + * may already contain the old state, in which case it is overridden. + * + * @param blob: Device tree blob holding state + * @param node: Node to write our state into + */ +static int cros_ec_write_state(void *blob, int node) +{ + struct ec_state *ec = &s_state; + + /* We are guaranteed enough space to write basic properties */ + fdt_setprop_u32(blob, node, "current-image", ec->current_image); + fdt_setprop(blob, node, "vbnv-context", ec->vbnv_context, + sizeof(ec->vbnv_context)); + return state_setprop(node, "flash-data", ec->flash_data, + ec->ec_config.flash.length); +} + +SANDBOX_STATE_IO(cros_ec, "google,cros-ec", cros_ec_read_state, + cros_ec_write_state); + +/** + * Return the number of bytes used in the specified image. + * + * This is the actual size of code+data in the image, as opposed to the + * amount of space reserved in flash for that image. This code is similar to + * that used by the real EC code base. + * + * @param ec Current emulated EC state + * @param entry Flash map entry containing the image to check + * @return actual image size in bytes, 0 if the image contains no content or + * error. + */ +static int get_image_used(struct ec_state *ec, struct fmap_entry *entry) +{ + int size; + + /* + * Scan backwards looking for 0xea byte, which is by definition the + * last byte of the image. See ec.lds.S for how this is inserted at + * the end of the image. + */ + for (size = entry->length - 1; + size > 0 && ec->flash_data[entry->offset + size] != 0xea; + size--) + ; + + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ +} + +/** + * Read the key matrix from the device tree + * + * Keymap entries in the fdt take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * + * @param ec Current emulated EC state + * @param blob Device tree blob containing keyscan information + * @param node Keyboard node of device tree containing keyscan information + * @return 0 if ok, -1 on error + */ +static int keyscan_read_fdt_matrix(struct ec_state *ec, const void *blob, + int node) +{ + const u32 *cell; + int upto; + int len; + + cell = fdt_getprop(blob, node, "linux,keymap", &len); + ec->matrix_count = len / 4; + ec->matrix = calloc(ec->matrix_count, sizeof(*ec->matrix)); + if (!ec->matrix) { + debug("%s: Out of memory for key matrix\n", __func__); + return -1; + } + + /* Now read the data */ + for (upto = 0; upto < ec->matrix_count; upto++) { + struct ec_keymatrix_entry *matrix = &ec->matrix[upto]; + u32 word; + + word = fdt32_to_cpu(*cell++); + matrix->row = word >> 24; + matrix->col = (word >> 16) & 0xff; + matrix->keycode = word & 0xffff; + + /* Hard-code some sanity limits for now */ + if (matrix->row >= KEYBOARD_ROWS || + matrix->col >= KEYBOARD_COLS) { + debug("%s: Matrix pos out of range (%d,%d)\n", + __func__, matrix->row, matrix->col); + return -1; + } + } + + if (upto != ec->matrix_count) { + debug("%s: Read mismatch from key matrix\n", __func__); + return -1; + } + + return 0; +} + +/** + * Return the next keyscan message contents + * + * @param ec Current emulated EC state + * @param scan Place to put keyscan bytes for the keyscan message (must hold + * enough space for a full keyscan) + * @return number of bytes of valid scan data + */ +static int cros_ec_keyscan(struct ec_state *ec, uint8_t *scan) +{ + const struct ec_keymatrix_entry *matrix; + int bytes = KEYBOARD_COLS; + int key[8]; /* allow up to 8 keys to be pressed at once */ + int count; + int i; + + memset(ec->keyscan, '\0', bytes); + count = sandbox_sdl_scan_keys(key, ARRAY_SIZE(key)); + + /* Look up keycode in matrix */ + for (i = 0, matrix = ec->matrix; i < ec->matrix_count; i++, matrix++) { + bool found; + int j; + + for (found = false, j = 0; j < count; j++) { + if (matrix->keycode == key[j]) + found = true; + } + + if (found) { + debug("%d: %d,%d\n", matrix->keycode, matrix->row, + matrix->col); + ec->keyscan[matrix->col] |= 1 << matrix->row; + } + } + + memcpy(scan, ec->keyscan, bytes); + return bytes; +} + +/** + * Process an emulated EC command + * + * @param ec Current emulated EC state + * @param req_hdr Pointer to request header + * @param req_data Pointer to body of request + * @param resp_hdr Pointer to place to put response header + * @param resp_data Pointer to place to put response data, if any + * @return length of response data, or 0 for no response data, or -1 on error + */ +static int process_cmd(struct ec_state *ec, + struct ec_host_request *req_hdr, const void *req_data, + struct ec_host_response *resp_hdr, void *resp_data) +{ + int len; + + /* TODO(sjg@chromium.org): Check checksums */ + debug("EC command %#0x\n", req_hdr->command); + + switch (req_hdr->command) { + case EC_CMD_HELLO: { + const struct ec_params_hello *req = req_data; + struct ec_response_hello *resp = resp_data; + + resp->out_data = req->in_data + 0x01020304; + len = sizeof(*resp); + break; + } + case EC_CMD_GET_VERSION: { + struct ec_response_get_version *resp = resp_data; + + strcpy(resp->version_string_ro, "sandbox_ro"); + strcpy(resp->version_string_rw, "sandbox_rw"); + resp->current_image = ec->current_image; + debug("Current image %d\n", resp->current_image); + len = sizeof(*resp); + break; + } + case EC_CMD_VBNV_CONTEXT: { + const struct ec_params_vbnvcontext *req = req_data; + struct ec_response_vbnvcontext *resp = resp_data; + + switch (req->op) { + case EC_VBNV_CONTEXT_OP_READ: + memcpy(resp->block, ec->vbnv_context, + sizeof(resp->block)); + len = sizeof(*resp); + break; + case EC_VBNV_CONTEXT_OP_WRITE: + memcpy(ec->vbnv_context, resp->block, + sizeof(resp->block)); + len = 0; + break; + default: + printf(" ** Unknown vbnv_context command %#02x\n", + req->op); + return -1; + } + break; + } + case EC_CMD_REBOOT_EC: { + const struct ec_params_reboot_ec *req = req_data; + + printf("Request reboot type %d\n", req->cmd); + switch (req->cmd) { + case EC_REBOOT_DISABLE_JUMP: + len = 0; + break; + case EC_REBOOT_JUMP_RW: + ec->current_image = EC_IMAGE_RW; + len = 0; + break; + default: + puts(" ** Unknown type"); + return -1; + } + break; + } + case EC_CMD_HOST_EVENT_GET_B: { + struct ec_response_host_event_mask *resp = resp_data; + + resp->mask = 0; + if (ec->recovery_req) { + resp->mask |= EC_HOST_EVENT_MASK( + EC_HOST_EVENT_KEYBOARD_RECOVERY); + } + + len = sizeof(*resp); + break; + } + case EC_CMD_VBOOT_HASH: { + const struct ec_params_vboot_hash *req = req_data; + struct ec_response_vboot_hash *resp = resp_data; + struct fmap_entry *entry; + int ret, size; + + entry = &state->ec_config.region[EC_FLASH_REGION_RW]; + + switch (req->cmd) { + case EC_VBOOT_HASH_RECALC: + case EC_VBOOT_HASH_GET: + size = SHA256_SUM_LEN; + len = get_image_used(ec, entry); + ret = hash_block("sha256", + ec->flash_data + entry->offset, + len, resp->hash_digest, &size); + if (ret) { + printf(" ** hash_block() failed\n"); + return -1; + } + resp->status = EC_VBOOT_HASH_STATUS_DONE; + resp->hash_type = EC_VBOOT_HASH_TYPE_SHA256; + resp->digest_size = size; + resp->reserved0 = 0; + resp->offset = entry->offset; + resp->size = len; + len = sizeof(*resp); + break; + default: + printf(" ** EC_CMD_VBOOT_HASH: Unknown command %d\n", + req->cmd); + return -1; + } + break; + } + case EC_CMD_FLASH_PROTECT: { + const struct ec_params_flash_protect *req = req_data; + struct ec_response_flash_protect *resp = resp_data; + uint32_t expect = EC_FLASH_PROTECT_ALL_NOW | + EC_FLASH_PROTECT_ALL_AT_BOOT; + + printf("mask=%#x, flags=%#x\n", req->mask, req->flags); + if (req->flags == expect || req->flags == 0) { + resp->flags = req->flags ? EC_FLASH_PROTECT_ALL_NOW : + 0; + resp->valid_flags = EC_FLASH_PROTECT_ALL_NOW; + resp->writable_flags = 0; + len = sizeof(*resp); + } else { + puts(" ** unexpected flash protect request\n"); + return -1; + } + break; + } + case EC_CMD_FLASH_REGION_INFO: { + const struct ec_params_flash_region_info *req = req_data; + struct ec_response_flash_region_info *resp = resp_data; + struct fmap_entry *entry; + + switch (req->region) { + case EC_FLASH_REGION_RO: + case EC_FLASH_REGION_RW: + case EC_FLASH_REGION_WP_RO: + entry = &state->ec_config.region[req->region]; + resp->offset = entry->offset; + resp->size = entry->length; + len = sizeof(*resp); + printf("EC flash region %d: offset=%#x, size=%#x\n", + req->region, resp->offset, resp->size); + break; + default: + printf("** Unknown flash region %d\n", req->region); + return -1; + } + break; + } + case EC_CMD_FLASH_ERASE: { + const struct ec_params_flash_erase *req = req_data; + + memset(ec->flash_data + req->offset, + ec->ec_config.flash_erase_value, + req->size); + len = 0; + break; + } + case EC_CMD_FLASH_WRITE: { + const struct ec_params_flash_write *req = req_data; + + memcpy(ec->flash_data + req->offset, req + 1, req->size); + len = 0; + break; + } + case EC_CMD_MKBP_STATE: + len = cros_ec_keyscan(ec, resp_data); + break; + default: + printf(" ** Unknown EC command %#02x\n", req_hdr->command); + return -1; + } + + return len; +} + +int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, + int in_bytes) +{ + struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout; + const void *req_data = req_hdr + 1; + struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din; + void *resp_data = resp_hdr + 1; + int len; + + len = process_cmd(&s_state, req_hdr, req_data, resp_hdr, resp_data); + if (len < 0) + return len; + + resp_hdr->struct_version = 3; + resp_hdr->result = EC_RES_SUCCESS; + resp_hdr->data_len = len; + resp_hdr->reserved = 0; + len += sizeof(*resp_hdr); + resp_hdr->checksum = 0; + resp_hdr->checksum = (uint8_t) + -cros_ec_calc_checksum((const uint8_t *)resp_hdr, len); + + return in_bytes; +} + +int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob) +{ + return 0; +} + +void cros_ec_check_keyboard(struct cros_ec_dev *dev) +{ + struct ec_state *ec = &s_state; + ulong start; + + printf("Press keys for EC to detect on reset (ESC=recovery)..."); + start = get_timer(0); + while (get_timer(start) < 1000) + ; + putc('\n'); + if (!sandbox_sdl_key_pressed(KEY_ESC)) { + ec->recovery_req = true; + printf(" - EC requests recovery\n"); + } +} + +/** + * Initialize sandbox EC emulation. + * + * @param dev CROS_EC device + * @param blob Device tree blob + * @return 0 if ok, -1 on error + */ +int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob) +{ + struct ec_state *ec = &s_state; + int node; + int err; + + state = &s_state; + err = cros_ec_decode_ec_flash(blob, &ec->ec_config); + if (err) + return err; + + node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB); + if (node < 0) { + debug("%s: No cros_ec keyboard found\n", __func__); + } else if (keyscan_read_fdt_matrix(ec, blob, node)) { + debug("%s: Could not read key matrix\n", __func__); + return -1; + } + + /* If we loaded EC data, check that the length matches */ + if (ec->flash_data && + ec->flash_data_len != ec->ec_config.flash.length) { + printf("EC data length is %x, expected %x, discarding data\n", + ec->flash_data_len, ec->ec_config.flash.length); + os_free(ec->flash_data); + ec->flash_data = NULL; + } + + /* Otherwise allocate the memory */ + if (!ec->flash_data) { + ec->flash_data_len = ec->ec_config.flash.length; + ec->flash_data = os_malloc(ec->flash_data_len); + if (!ec->flash_data) + return -ENOMEM; + } + + return 0; +} diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 2fc911025e..7df709cc71 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -17,6 +17,30 @@ #include #include +int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes) +{ + int rv; + + /* Do the transfer */ + if (spi_claim_bus(dev->spi)) { + debug("%s: Cannot claim SPI bus\n", __func__); + return -1; + } + + rv = spi_xfer(dev->spi, max(out_bytes, in_bytes) * 8, + dev->dout, dev->din, + SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(dev->spi); + + if (rv) { + debug("%s: Cannot complete SPI transfer\n", __func__); + return -1; + } + + return in_bytes; +} + /** * Send a command to a LPC CROS_EC device and return the reply. * @@ -42,6 +66,12 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int csum, len; int rv; + if (dev->protocol_version != 2) { + debug("%s: Unsupported EC protcol version %d\n", + __func__, dev->protocol_version); + return -1; + } + /* * Sanity-check input size to make sure it plus transaction overhead * fits in the internal device buffer. diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c new file mode 100644 index 0000000000..545d3ebf52 --- /dev/null +++ b/drivers/misc/mxs_ocotp.c @@ -0,0 +1,311 @@ +/* + * Freescale i.MX28 OCOTP Driver + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block + * used in i.MX6 . While these blocks are very similar at the first + * glance, by digging deeper, one will notice differences (like the + * tight dependence on MXS power block, some completely new registers + * etc.) which would make common driver an ifdef nightmare :-( + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MXS_OCOTP_TIMEOUT 100000 + +static struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; +static struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; +static struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + +static int mxs_ocotp_wait_busy_clear(void) +{ + uint32_t reg; + int timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&ocotp_regs->hw_ocotp_ctrl); + if (!(reg & OCOTP_CTRL_BUSY)) + break; + udelay(10); + } + + if (!timeout) + return -EINVAL; + + /* Wait a little as per FSL datasheet's 'write postamble' section. */ + udelay(10); + + return 0; +} + +static void mxs_ocotp_clear_error(void) +{ + writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr); +} + +static int mxs_ocotp_read_bank_open(bool open) +{ + int ret = 0; + + if (open) { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_set); + + /* + * Wait before polling the BUSY bit, since the BUSY bit might + * be asserted only after a few HCLK cycles and if we were to + * poll immediatelly, we could miss the busy bit. + */ + udelay(10); + ret = mxs_ocotp_wait_busy_clear(); + } else { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_clr); + } + + return ret; +} + +static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val) +{ + uint32_t scale_val; + + if (enter) { + /* + * Enter the fuse programming VDDIO voltage setup. We start + * scaling the voltage from it's current value down to 2.8V + * which is the one and only correct voltage for programming + * the OCOTP fuses (according to datasheet). + */ + scale_val = readl(&power_regs->hw_power_vddioctrl); + scale_val &= POWER_VDDIOCTRL_TRG_MASK; + + /* Return the original voltage. */ + *val = scale_val; + + /* + * Start scaling VDDIO down to 0x2, which is 2.8V . Actually, + * the value 0x0 should be 2.8V, but that's not the case on + * most designs due to load etc., so we play safe. Undervolt + * can actually cause incorrect programming of the fuses and + * or reboots of the board. + */ + while (scale_val > 2) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, --scale_val); + udelay(500); + } + } else { + /* Start scaling VDDIO up to original value . */ + for (scale_val = 2; scale_val <= *val; scale_val++) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, scale_val); + udelay(500); + } + } + + mdelay(10); +} + +static int mxs_ocotp_wait_hclk_ready(void) +{ + uint32_t reg, timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&clkctrl_regs->hw_clkctrl_hbus); + if (!(reg & CLKCTRL_HBUS_ASM_BUSY)) + break; + } + + if (!timeout) + return -EINVAL; + + return 0; +} + +static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) +{ + uint32_t scale_val; + int ret; + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + if (enter) { + /* Return the original HCLK clock speed. */ + *val = readl(&clkctrl_regs->hw_clkctrl_hbus); + *val &= CLKCTRL_HBUS_DIV_MASK; + + /* Scale the HCLK to 454/19 = 23.9 MHz . */ + scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } else { + /* Scale the HCLK back to original frequency. */ + scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } + + writel(CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_set); + writel(scale_val, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + mdelay(10); + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + mdelay(10); + + return 0; +} + +static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask) +{ + uint32_t hclk_val, vddio_val; + int ret; + + /* Make sure the banks are closed for reading. */ + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + ret = mxs_ocotp_scale_hclk(1, &hclk_val); + if (ret) { + puts("Failed scaling down the HCLK!\n"); + return ret; + } + mxs_ocotp_scale_vddio(1, &vddio_val); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + + /* Program the fuse address */ + writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl); + + /* Program the data. */ + writel(mask, &ocotp_regs->hw_ocotp_data); + + udelay(10); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + +fail: + mxs_ocotp_scale_vddio(0, &vddio_val); + ret = mxs_ocotp_scale_hclk(0, &hclk_val); + if (ret) { + puts("Failed scaling up the HCLK!\n"); + return ret; + } + + return ret; +} + +static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val) +{ + int ret; + + /* Register offset from CUST0 */ + reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + return ret; + } + + mxs_ocotp_clear_error(); + + ret = mxs_ocotp_read_bank_open(1); + if (ret) { + puts("Failed opening banks for reading!\n"); + return ret; + } + + *val = readl(reg); + + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + return ret; +} + +static int mxs_ocotp_valid(u32 bank, u32 word) +{ + if (bank > 4) + return -EINVAL; + if (word > 7) + return -EINVAL; + return 0; +} + +/* + * The 'fuse' command API + */ +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_read_fuse((bank << 3) | word, val); +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_write_fuse((bank << 3) | word, val); +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* We do not support sensing :-( */ + return -EINVAL; +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* We do not support overriding :-( */ + return -EINVAL; +} diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e793ed994e..931922bc4a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SDHCI) += sdhci.o obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o +obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 5a55fe73b7..5ef7ff7ff2 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -287,9 +287,9 @@ static void host_set_ios(struct mmc *dev) u32 clkdiv = 0; u32 tmp_clock; - if (dev->clock >= dev->f_max) { + if (dev->clock >= dev->cfg->f_max) { clkdiv = 0; - dev->clock = dev->f_max; + dev->clock = dev->cfg->f_max; } else { clkdiv = (host->clock_in / dev->clock) - 2; } @@ -335,6 +335,12 @@ static void host_set_ios(struct mmc *dev) udelay(CLK_CHANGE_DELAY); } +static const struct mmc_ops arm_pl180_mmci_ops = { + .send_cmd = host_request, + .set_ios = host_set_ios, + .init = mmc_host_reset, +}; + /* * mmc_host_init - initialize the mmc controller. * Set initial clock and power for mmc slot. @@ -342,16 +348,9 @@ static void host_set_ios(struct mmc *dev) */ int arm_pl180_mmci_init(struct pl180_mmc_host *host) { - struct mmc *dev; + struct mmc *mmc; u32 sdi_u32; - dev = malloc(sizeof(struct mmc)); - if (!dev) - return -ENOMEM; - - memset(dev, 0, sizeof(struct mmc)); - dev->priv = host; - writel(host->pwr_init, &host->base->power); writel(host->clkdiv_init, &host->base->clock); udelay(CLK_CHANGE_DELAY); @@ -359,19 +358,24 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) /* Disable mmc interrupts */ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK; writel(sdi_u32, &host->base->mask0); - strncpy(dev->name, host->name, sizeof(dev->name)); - dev->send_cmd = host_request; - dev->set_ios = host_set_ios; - dev->init = mmc_host_reset; - dev->getcd = NULL; - dev->getwp = NULL; - dev->host_caps = host->caps; - dev->voltages = host->voltages; - dev->f_min = host->clock_min; - dev->f_max = host->clock_max; - dev->b_max = host->b_max; - mmc_register(dev); - debug("registered mmc interface number is:%d\n", dev->block_dev.dev); + + host->cfg.name = host->name; + host->cfg.ops = &arm_pl180_mmci_ops; + /* TODO remove the duplicates */ + host->cfg.host_caps = host->caps; + host->cfg.voltages = host->voltages; + host->cfg.f_min = host->clock_min; + host->cfg.f_max = host->clock_max; + if (host->b_max != 0) + host->cfg.b_max = host->b_max; + else + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; + + debug("registered mmc interface number is:%d\n", mmc->block_dev.dev); return 0; } diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h index 72344498d6..f23bd391ee 100644 --- a/drivers/mmc/arm_pl180_mmci.h +++ b/drivers/mmc/arm_pl180_mmci.h @@ -13,6 +13,9 @@ #ifndef __ARM_PL180_MMCI_H__ #define __ARM_PL180_MMCI_H__ +/* need definition of struct mmc_config */ +#include + #define COMMAND_REG_DELAY 300 #define DATA_REG_DELAY 1000 #define CLK_CHANGE_DELAY 2000 @@ -184,6 +187,7 @@ struct pl180_mmc_host { unsigned int clkdiv_init; unsigned int pwr_init; int version2; + struct mmc_config cfg; }; int arm_pl180_mmci_init(struct pl180_mmc_host *); diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 26311741f5..bcd6a3e52f 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -273,30 +274,30 @@ static int bfin_sdh_init(struct mmc *mmc) return 0; } +static const struct mmc_ops bfin_mmc_ops = { + .send_cmd = bfin_sdh_request, + .set_ios = bfin_sdh_set_ios, + .init = bfin_sdh_init, +}; + +static struct mmc_config bfin_mmc_cfg = { + .name = "Blackfin SDH", + .ops = &bfin_mmc_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; int bfin_mmc_init(bd_t *bis) { - struct mmc *mmc = NULL; + struct mmc *mmc; - mmc = malloc(sizeof(struct mmc)); + bfin_mmc_cfg.f_max = get_sclk(); + bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9; - if (!mmc) - return -ENOMEM; - sprintf(mmc->name, "Blackfin SDH"); - mmc->send_cmd = bfin_sdh_request; - mmc->set_ios = bfin_sdh_set_ios; - mmc->init = bfin_sdh_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = get_sclk(); - mmc->f_min = mmc->f_max >> 9; - - mmc->b_max = 0; - - mmc_register(mmc); + mmc = mmc_create(&bfin_mmc_cfg, NULL); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index b380961188..aae00e9dab 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -30,10 +30,10 @@ static void dmmc_set_clock(struct mmc *mmc, uint clock) struct davinci_mmc_regs *regs = host->reg_base; uint clkrt, sysclk2, act_clock; - if (clock < mmc->f_min) - clock = mmc->f_min; - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; set_val(®s->mmcclk, 0); sysclk2 = host->input_clk; @@ -363,32 +363,27 @@ static void dmmc_set_ios(struct mmc *mmc) dmmc_set_clock(mmc, mmc->clock); } +static const struct mmc_ops dmmc_ops = { + .send_cmd = dmmc_send_cmd, + .set_ios = dmmc_set_ios, + .init = dmmc_init, +}; + /* Called from board_mmc_init during startup. Can be called multiple times * depending on the number of slots available on board and controller */ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) { - struct mmc *mmc; + host->cfg.name = "davinci"; + host->cfg.ops = &dmmc_ops; + host->cfg.f_min = 200000; + host->cfg.f_max = 25000000; + host->cfg.voltages = host->voltages; + host->cfg.host_caps = host->host_caps; - mmc = malloc(sizeof(struct mmc)); - memset(mmc, 0, sizeof(struct mmc)); + host->cfg.b_max = DAVINCI_MAX_BLOCKS; - sprintf(mmc->name, "davinci"); - mmc->priv = host; - mmc->send_cmd = dmmc_send_cmd; - mmc->set_ios = dmmc_set_ios; - mmc->init = dmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - - mmc->f_min = 200000; - mmc->f_max = 25000000; - mmc->voltages = host->voltages; - mmc->host_caps = host->host_caps; - - mmc->b_max = DAVINCI_MAX_BLOCKS; - - mmc_register(mmc); + mmc_create(&host->cfg, host); return 0; } diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aaa60..eb4e2be514 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -107,7 +107,7 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data ? DIV_ROUND_UP(data->blocks, 8) : 0); int flags = 0, i; @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { @@ -284,7 +284,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; u32 ctype; debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); @@ -310,7 +310,7 @@ static void dwmci_set_ios(struct mmc *mmc) static int dwmci_init(struct mmc *mmc) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; if (host->board_init) host->board_init(host); @@ -323,7 +323,7 @@ static int dwmci_init(struct mmc *mmc) } /* Enumerate at 400KHz */ - dwmci_setup_bus(host, mmc->f_min); + dwmci_setup_bus(host, mmc->cfg->f_min); dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0); @@ -343,41 +343,37 @@ static int dwmci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, + .init = dwmci_init, +}; + int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; - int err = 0; + host->cfg.name = host->name; + host->cfg.ops = &dwmci_ops; + host->cfg.f_min = min_clk; + host->cfg.f_max = max_clk; - mmc = calloc(sizeof(struct mmc), 1); - if (!mmc) { - printf("mmc calloc fail!\n"); - return -1; - } + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->priv = host; - host->mmc = mmc; - - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = dwmci_send_cmd; - mmc->set_ios = dwmci_set_ios; - mmc->init = dwmci_init; - mmc->f_min = min_clk; - mmc->f_max = max_clk; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - - mmc->host_caps = host->caps; + host->cfg.host_caps = host->caps; if (host->buswidth == 8) { - mmc->host_caps |= MMC_MODE_8BIT; - mmc->host_caps &= ~MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps &= ~MMC_MODE_4BIT; } else { - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps &= ~MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps &= ~MMC_MODE_8BIT; } - mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; - err = mmc_register(mmc); + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - return err; + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) + return -1; + + return 0; } diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e5e0..de8cdcc42b 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e3cd0c777e..4c3b93d413 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -172,7 +172,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { int timeout; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO uint wml_value; @@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * 2)Timeout period should be minimum 0.250sec as per SD Card spec * So, Number of SD Clock cycles for 0.25sec should be minimum * (SD Clock/sec * 0.25 sec) SD Clock cycles - * = (mmc->tran_speed * 1/4) SD Clock cycles + * = (mmc->clock * 1/4) SD Clock cycles * As 1) >= 2) - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * => (2^(timeout+13)) >= mmc->clock * 1/4 * Taking log2 both the sides - * => timeout + 13 >= log2(mmc->tran_speed/4) + * => timeout + 13 >= log2(mmc->clock/4) * Rounding up to next power of 2 - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 - * => timeout + 13 = fls(mmc->tran_speed/4) + * => timeout + 13 = log2(mmc->clock/4) + 1 + * => timeout + 13 = fls(mmc->clock/4) */ - timeout = fls(mmc->tran_speed/4); + timeout = fls(mmc->clock/4); timeout -= 13; if (timeout > 14) @@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) timeout++; #endif +#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + timeout = 0xE; +#endif esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; @@ -265,9 +268,10 @@ static void check_and_invalidate_dcache_range static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { + int err = 0; uint xfertyp; uint irqstat; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -296,8 +300,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Set up for a data transfer if we have one */ if (data) { - int err; - err = esdhc_setup_data(mmc, data); if(err) return err; @@ -325,27 +327,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(®s->irqstat); - /* Reset CMD and DATA portions on error */ - if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { - esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | - SYSCTL_RSTC); - while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) - ; - - if (data) { - esdhc_write32(®s->sysctl, - esdhc_read32(®s->sysctl) | - SYSCTL_RSTD); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) - ; - } + if (irqstat & CMD_ERR) { + err = COMM_ERR; + goto out; } - if (irqstat & CMD_ERR) - return COMM_ERR; - - if (irqstat & IRQSTAT_CTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_CTOE) { + err = TIMEOUT; + goto out; + } /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { @@ -360,7 +350,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - return TIMEOUT; + err = TIMEOUT; + goto out; } } @@ -387,32 +378,53 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) do { irqstat = esdhc_read32(®s->irqstat); - if (irqstat & IRQSTAT_DTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_DTOE) { + err = TIMEOUT; + goto out; + } - if (irqstat & DATA_ERR) - return COMM_ERR; + if (irqstat & DATA_ERR) { + err = COMM_ERR; + goto out; + } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); #endif if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); } +out: + /* Reset CMD and DATA portions on error */ + if (err) { + esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(®s->sysctl, + esdhc_read32(®s->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) + ; + } + } + esdhc_write32(®s->irqstat, -1); - return 0; + return err; } static void set_sysctl(struct mmc *mmc, uint clock) { int div, pre_div; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int sdhc_clk = cfg->sdhc_clk; uint clk; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; if (sdhc_clk / 16 > clock) { for (pre_div = 2; pre_div < 256; pre_div *= 2) @@ -443,7 +455,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) static void esdhc_set_ios(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; /* Set the clock speed */ @@ -461,7 +473,7 @@ static void esdhc_set_ios(struct mmc *mmc) static int esdhc_init(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; @@ -496,10 +508,14 @@ static int esdhc_init(struct mmc *mmc) static int esdhc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; +#ifdef CONFIG_ESDHC_DETECT_QUIRK + if (CONFIG_ESDHC_DETECT_QUIRK) + return 1; +#endif while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -520,6 +536,13 @@ static void esdhc_reset(struct fsl_esdhc *regs) printf("MMC/SD: Reset never completed.\n"); } +static const struct mmc_ops esdhc_ops = { + .send_cmd = esdhc_send_cmd, + .set_ios = esdhc_set_ios, + .init = esdhc_init, + .getcd = esdhc_getcd, +}; + int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc *regs; @@ -529,12 +552,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (!cfg) return -1; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - - memset(mmc, 0, sizeof(struct mmc)); - sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; /* First reset the eSDHC controller */ @@ -543,12 +560,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); - mmc->priv = cfg; - mmc->send_cmd = esdhc_send_cmd; - mmc->set_ios = esdhc_set_ios; - mmc->init = esdhc_init; - mmc->getcd = esdhc_getcd; - mmc->getwp = NULL; + memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; caps = regs->hostcapblt; @@ -570,33 +582,43 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps & ESDHC_HOSTCAPBLT_VS33) voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.name = "FSL_SDHC"; + cfg->cfg.ops = &esdhc_ops; #ifdef CONFIG_SYS_SD_VOLTAGE - mmc->voltages = CONFIG_SYS_SD_VOLTAGE; + cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; #else - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; #endif - if ((mmc->voltages & voltage_caps) == 0) { + if ((cfg->cfg.voltages & voltage_caps) == 0) { printf("voltage not supported by controller\n"); return -1; } - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; + cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) - mmc->host_caps &= ~MMC_MODE_8BIT; + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; if (cfg->max_bus_width < 4) - mmc->host_caps &= ~MMC_MODE_4BIT; + cfg->cfg.host_caps &= ~MMC_MODE_4BIT; } if (caps & ESDHC_HOSTCAPBLT_HSS) - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - mmc->f_min = 400000; - mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); +#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; +#endif - mmc->b_max = 0; - mmc_register(mmc); + cfg->cfg.f_min = 400000; + cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000); + + cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&cfg->cfg, cfg); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 7600d5ce55..a620678e5f 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -27,6 +27,7 @@ struct ftsdc010_chip { uint32_t sclk; /* FTSDC010 source clock in Hz */ uint32_t fifo; /* fifo depth in bytes */ uint32_t acmd; + struct mmc_config cfg; /* mmc configuration */ }; static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) @@ -123,14 +124,6 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) } } -static inline int ftsdc010_is_ro(struct mmc *mmc) -{ - struct ftsdc010_chip *chip = mmc->priv; - const uint8_t *csd = (const uint8_t *)mmc->csd; - - return chip->wprot || (csd[1] & 0x30); -} - static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = TIMEOUT; @@ -316,6 +309,12 @@ static int ftsdc010_init(struct mmc *mmc) return 0; } +static const struct mmc_ops ftsdc010_ops = { + .send_cmd = ftsdc010_request, + .set_ios = ftsdc010_set_ios, + .init = ftsdc010_init, +}; + int ftsdc010_mmc_init(int devid) { struct mmc *mmc; @@ -331,50 +330,44 @@ int ftsdc010_mmc_init(int devid) regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20)); #endif - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - memset(mmc, 0, sizeof(struct mmc)); - chip = malloc(sizeof(struct ftsdc010_chip)); - if (!chip) { - free(mmc); + if (!chip) return -ENOMEM; - } memset(chip, 0, sizeof(struct ftsdc010_chip)); chip->regs = regs; - mmc->priv = chip; - - sprintf(mmc->name, "ftsdc010"); - mmc->send_cmd = ftsdc010_request; - mmc->set_ios = ftsdc010_set_ios; - mmc->init = ftsdc010_init; - - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; - switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { - case FTSDC010_BWR_CAPS_4BIT: - mmc->host_caps |= MMC_MODE_4BIT; - break; - case FTSDC010_BWR_CAPS_8BIT: - mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - break; - default: - break; - } - #ifdef CONFIG_SYS_CLK_FREQ chip->sclk = CONFIG_SYS_CLK_FREQ; #else chip->sclk = clk_get_rate("SDC"); #endif - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = chip->sclk / 2; - mmc->f_min = chip->sclk / 0x100; - mmc->block_dev.part_type = PART_TYPE_DOS; + chip->cfg.name = "ftsdc010"; + chip->cfg.ops = &ftsdc010_ops; + chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; + switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { + case FTSDC010_BWR_CAPS_4BIT: + chip->cfg.host_caps |= MMC_MODE_4BIT; + break; + case FTSDC010_BWR_CAPS_8BIT: + chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + break; + default: + break; + } - mmc_register(mmc); + chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + chip->cfg.f_max = chip->sclk / 2; + chip->cfg.f_min = chip->sclk / 0x100; + + chip->cfg.part_type = PART_TYPE_DOS; + chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&chip->cfg, chip); + if (mmc == NULL) { + free(chip); + return -ENOMEM; + } return 0; } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index c11dcd0f97..acca0269e5 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -55,7 +55,7 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) /* Setup for MCI Clock and Block Size */ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 bus_hz = get_mci_clk_rate(); u32 clkdiv = 255; @@ -165,7 +165,7 @@ io_fail: static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 cmdr; u32 error_flags = 0; u32 status; @@ -289,7 +289,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Entered into mmc structure during driver init */ static void mci_set_ios(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; @@ -325,7 +325,7 @@ static void mci_set_ios(struct mmc *mmc) /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; /* Initialize controller */ writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ @@ -344,6 +344,12 @@ static int mci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops atmel_mci_ops = { + .send_cmd = mci_send_cmd, + .set_ios = mci_set_ios, + .init = mci_init, +}; + /* * This is the only exported function * @@ -351,40 +357,45 @@ static int mci_init(struct mmc *mmc) */ int atmel_mci_init(void *regs) { - struct mmc *mmc = malloc(sizeof(struct mmc)); + struct mmc *mmc; + struct mmc_config *cfg; struct atmel_mci *mci; unsigned int version; - if (!mmc) + cfg = malloc(sizeof(*cfg)); + if (cfg == NULL) return -1; + memset(cfg, 0, sizeof(*cfg)); - strcpy(mmc->name, "mci"); - mmc->priv = regs; - mmc->send_cmd = mci_send_cmd; - mmc->set_ios = mci_set_ios; - mmc->init = mci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + mci = (struct atmel_mci *)regs; + + cfg->name = "mci"; + cfg->ops = &atmel_mci_ops; /* need to be able to pass these in on a board by board basis */ - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mci = (struct atmel_mci *)mmc->priv; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; version = atmel_mci_get_version(mci); if ((version & 0xf00) >= 0x300) - mmc->host_caps = MMC_MODE_8BIT; + cfg->host_caps = MMC_MODE_8BIT; - mmc->host_caps |= MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_4BIT; /* * min and max frequencies determined by * max and min of clock divider */ - mmc->f_min = get_mci_clk_rate() / (2*256); - mmc->f_max = get_mci_clk_rate() / (2*1); + cfg->f_min = get_mci_clk_rate() / (2*256); + cfg->f_max = get_mci_clk_rate() / (2*1); - mmc->b_max = 0; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc_register(mmc); + mmc = mmc_create(cfg, regs); + + if (mmc == NULL) { + free(cfg); + return -1; + } + /* NOTE: possibly leaking the cfg structure */ return 0; } diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c new file mode 100644 index 0000000000..77e42c8afe --- /dev/null +++ b/drivers/mmc/kona_sdhci.c @@ -0,0 +1,134 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define SDHCI_CORECTRL_OFFSET 0x00008000 +#define SDHCI_CORECTRL_EN 0x01 +#define SDHCI_CORECTRL_RESET 0x02 + +#define SDHCI_CORESTAT_OFFSET 0x00008004 +#define SDHCI_CORESTAT_CD_SW 0x01 + +#define SDHCI_COREIMR_OFFSET 0x00008008 +#define SDHCI_COREIMR_IP 0x01 + +static int init_kona_mmc_core(struct sdhci_host *host) +{ + unsigned int mask; + unsigned int timeout; + + if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) { + printf("%s: sd host controller reset error\n", __func__); + return 1; + } + + /* For kona a hardware reset before anything else. */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + do { + if (timeout == 0) { + printf("%s: reset timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } while (0 == + (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & + SDHCI_CORECTRL_RESET)); + + /* Clear the reset bit. */ + mask = mask & ~SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Enable AHB clock */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); + sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); + + /* Enable interrupts */ + sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); + + /* Make sure Card is detected in controller */ + mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); + sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { + if (timeout == 0) { + printf("%s: CARD DETECT timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } + return 0; +} + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) +{ + int ret = 0; + u32 max_clk; + void *reg_base; + struct sdhci_host *host = NULL; + + host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("%s: sdhci host malloc fail!\n", __func__); + return -ENOMEM; + } + switch (dev_index) { + case 0: + reg_base = (void *)CONFIG_SYS_SDIO_BASE0; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, + &max_clk); + break; + case 1: + reg_base = (void *)CONFIG_SYS_SDIO_BASE1; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, + &max_clk); + break; + case 2: + reg_base = (void *)CONFIG_SYS_SDIO_BASE2; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, + &max_clk); + break; + case 3: + reg_base = (void *)CONFIG_SYS_SDIO_BASE3; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, + &max_clk); + break; + default: + printf("%s: sdio dev index %d not supported\n", + __func__, dev_index); + ret = -EINVAL; + } + if (ret) + return ret; + + host->name = "kona-sdhci"; + host->ioaddr = reg_base; + host->quirks = quirks; + host->host_caps = MMC_MODE_HC; + + if (init_kona_mmc_core(host)) + return -EINVAL; + + if (quirks & SDHCI_QUIRK_REG32_RW) + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; + else + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + add_sdhci(host, max_clk, min_clk); + return ret; +} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c6a1c23fbf..16051e52ff 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -17,11 +17,6 @@ #include #include "mmc_private.h" -/* Set block count limit because of 16 bit register limit on some hardware*/ -#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -#endif - static struct list_head mmc_devices; static int cur_dev_num = -1; @@ -37,8 +32,8 @@ int mmc_getwp(struct mmc *mmc) wp = board_mmc_getwp(mmc); if (wp < 0) { - if (mmc->getwp) - wp = mmc->getwp(mmc); + if (mmc->cfg->ops->getwp) + wp = mmc->cfg->ops->getwp(mmc); else wp = 0; } @@ -63,7 +58,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) printf("CMD_SEND:%d\n", cmd->cmdidx); printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); switch (cmd->resp_type) { case MMC_RSP_NONE: printf("\t\tMMC_RSP_NONE\n"); @@ -106,7 +101,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) break; } #else - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); #endif return ret; } @@ -253,7 +248,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) return 0; do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; if(mmc_read_blocks(mmc, dst, start, cur) != cur) return 0; blocks_todo -= cur; @@ -312,7 +308,7 @@ static int sd_send_op_cond(struct mmc *mmc) * specified. */ cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : - (mmc->voltages & 0xff8000); + (mmc->cfg->voltages & 0xff8000); if (mmc->version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; @@ -361,11 +357,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, cmd->cmdarg = 0; if (use_arg && !mmc_host_is_spi(mmc)) { cmd->cmdarg = - (mmc->voltages & + (mmc->cfg->voltages & (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | (mmc->op_cond_response & OCR_ACCESS_MODE); - if (mmc->host_caps & MMC_MODE_HC) + if (mmc->cfg->host_caps & MMC_MODE_HC) cmd->cmdarg |= OCR_HCS; } err = mmc_send_cmd(mmc, cmd, NULL); @@ -430,7 +426,7 @@ int mmc_complete_op_cond(struct mmc *mmc) mmc->ocr = cmd.response[0]; mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); - mmc->rca = 0; + mmc->rca = 1; return 0; } @@ -578,8 +574,8 @@ int mmc_getcd(struct mmc *mmc) cd = board_mmc_getcd(mmc); if (cd < 0) { - if (mmc->getcd) - cd = mmc->getcd(mmc); + if (mmc->cfg->ops->getcd) + cd = mmc->cfg->ops->getcd(mmc); else cd = 1; } @@ -703,8 +699,8 @@ retry_scr: * This can avoid furthur problem when the card runs in different * mode between the host. */ - if (!((mmc->host_caps & MMC_MODE_HS_52MHz) && - (mmc->host_caps & MMC_MODE_HS))) + if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && + (mmc->cfg->host_caps & MMC_MODE_HS))) return 0; err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); @@ -751,16 +747,17 @@ static const int multipliers[] = { static void mmc_set_ios(struct mmc *mmc) { - mmc->set_ios(mmc); + if (mmc->cfg->ops->set_ios) + mmc->cfg->ops->set_ios(mmc); } void mmc_set_clock(struct mmc *mmc, uint clock) { - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; mmc->clock = clock; @@ -1026,7 +1023,7 @@ static int mmc_startup(struct mmc *mmc) return err; /* Restrict card's capabilities by what the host can do */ - mmc->card_caps &= mmc->host_caps; + mmc->card_caps &= mmc->cfg->host_caps; if (IS_SD(mmc)) { if (mmc->card_caps & MMC_MODE_4BIT) { @@ -1081,7 +1078,7 @@ static int mmc_startup(struct mmc *mmc) * this bus width, if it's more than 1 */ if (extw != EXT_CSD_BUS_WIDTH_1 && - !(mmc->host_caps & ext_to_hostcaps[extw])) + !(mmc->cfg->host_caps & ext_to_hostcaps[extw])) continue; err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, @@ -1154,7 +1151,7 @@ static int mmc_send_if_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_SEND_IF_COND; /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ - cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa; + cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; cmd.resp_type = MMC_RSP_R7; err = mmc_send_cmd(mmc, &cmd, NULL); @@ -1170,8 +1167,33 @@ static int mmc_send_if_cond(struct mmc *mmc) return 0; } -int mmc_register(struct mmc *mmc) +/* not used any more */ +int __deprecated mmc_register(struct mmc *mmc) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + printf("%s is deprecated! use mmc_create() instead.\n", __func__); +#endif + return -1; +} + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) +{ + struct mmc *mmc; + + /* quick validation */ + if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || + cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) + return NULL; + + mmc = calloc(1, sizeof(*mmc)); + if (mmc == NULL) + return NULL; + + mmc->cfg = cfg; + mmc->priv = priv; + + /* the following chunk was mmc_register() */ + /* Setup dsr related values */ mmc->dsr_imp = 0; mmc->dsr = 0xffffffff; @@ -1182,14 +1204,21 @@ int mmc_register(struct mmc *mmc) mmc->block_dev.block_read = mmc_bread; mmc->block_dev.block_write = mmc_bwrite; mmc->block_dev.block_erase = mmc_berase; - if (!mmc->b_max) - mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - INIT_LIST_HEAD (&mmc->link); + /* setup initial part type */ + mmc->block_dev.part_type = mmc->cfg->part_type; - list_add_tail (&mmc->link, &mmc_devices); + INIT_LIST_HEAD(&mmc->link); - return 0; + list_add_tail(&mmc->link, &mmc_devices); + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ + /* only freeing memory for now */ + free(mmc); } #ifdef CONFIG_PARTITIONS @@ -1207,7 +1236,8 @@ int mmc_start_init(struct mmc *mmc) { int err; - if (mmc_getcd(mmc) == 0) { + /* we pretend there's no card when init is NULL */ + if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { mmc->has_init = 0; #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: no card present\n"); @@ -1218,7 +1248,8 @@ int mmc_start_init(struct mmc *mmc) if (mmc->has_init) return 0; - err = mmc->init(mmc); + /* made sure it's not NULL earlier */ + err = mmc->cfg->ops->init(mmc); if (err) return err; @@ -1320,7 +1351,7 @@ void print_mmc_devices(char separator) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); - printf("%s: %d", m->name, m->block_dev.dev); + printf("%s: %d", m->cfg->name, m->block_dev.dev); if (entry->next != &mmc_devices) printf("%c ", separator); @@ -1442,67 +1473,56 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, } /* - * This function shall form and send the commands to open / close the - * boot partition specified by user. - * - * Input Parameters: - * ack: 0x0 - No boot acknowledge sent (default) - * 0x1 - Boot acknowledge sent during boot operation - * part_num: User selects boot data that will be sent to master - * 0x0 - Device not boot enabled (default) - * 0x1 - Boot partition 1 enabled for boot - * 0x2 - Boot partition 2 enabled for boot - * access: User selects partitions to access - * 0x0 : No access to boot partition (default) - * 0x1 : R/W boot partition 1 - * 0x2 : R/W boot partition 2 - * 0x3 : R/W Replay Protected Memory Block (RPMB) + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. * * Returns 0 on success. */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) { int err; - struct mmc_cmd cmd; - /* Boot ack enable, boot partition enable , boot partition access */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_PART_CONF << 16) | - ((EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - if (access) { - debug("mmc boot partition#%d open fail:Error1 = %d\n", - part_num, err); - } else { - debug("mmc boot partition#%d close fail:Error = %d\n", - part_num, err); - } + if (err) return err; - } - - if (access) { - /* 4bit transfer mode at booting time. */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_BOOT_BUS_WIDTH << 16) | - ((1 << 0) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc boot partition#%d open fail:Error2 = %d\n", - part_num, err); - return err; - } - } return 0; } + +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); + + if (err) + return err; + return 0; +} + +/* + * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value + * for enable. Note that this is a write-once field for non-zero values. + * + * Returns 0 on success. + */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) +{ + return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, + enable); +} #endif diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index fe6a5a166d..5b5b33a4b2 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -92,7 +92,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf, spi_xfer(spi, 2 * 8, NULL, &crc, 0); #ifdef CONFIG_MMC_SPI_CRC_ON if (swab16(cyg_crc16(buf, bsize)) != crc) { - debug("%s: CRC error\n", mmc->name); + debug("%s: CRC error\n", mmc->cfg->name); r1 = R1_SPI_COM_CRC; break; } @@ -238,6 +238,7 @@ done: static void mmc_spi_set_ios(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; + debug("%s: clock %u\n", __func__, mmc->clock); if (mmc->clock) spi_set_speed(spi, mmc->clock); @@ -246,7 +247,6 @@ static void mmc_spi_set_ios(struct mmc *mmc) static int mmc_spi_init_p(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; - mmc->clock = 0; spi_set_speed(spi, MMC_SPI_MIN_CLOCK); spi_claim_bus(spi); /* cs deactivated for 100+ clock */ @@ -255,33 +255,37 @@ static int mmc_spi_init_p(struct mmc *mmc) return 0; } +static const struct mmc_ops mmc_spi_ops = { + .send_cmd = mmc_spi_request, + .set_ios = mmc_spi_set_ios, + .init = mmc_spi_init_p, +}; + +static struct mmc_config mmc_spi_cfg = { + .name = "MMC_SPI", + .ops = &mmc_spi_ops, + .host_caps = MMC_MODE_SPI, + .voltages = MMC_SPI_VOLTAGE, + .f_min = MMC_SPI_MIN_CLOCK, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode) { struct mmc *mmc; + struct spi_slave *spi; - mmc = malloc(sizeof(*mmc)); - if (!mmc) + spi = spi_setup_slave(bus, cs, speed, mode); + if (spi == NULL) return NULL; - memset(mmc, 0, sizeof(*mmc)); - mmc->priv = spi_setup_slave(bus, cs, speed, mode); - if (!mmc->priv) { - free(mmc); + + mmc_spi_cfg.f_max = speed; + + mmc = mmc_create(&mmc_spi_cfg, spi); + if (mmc == NULL) { + spi_free_slave(spi); return NULL; } - sprintf(mmc->name, "MMC_SPI"); - mmc->send_cmd = mmc_spi_request; - mmc->set_ios = mmc_spi_set_ios; - mmc->init = mmc_spi_init_p; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_SPI; - - mmc->voltages = MMC_SPI_VOLTAGE; - mmc->f_max = speed; - mmc->f_min = MMC_SPI_MIN_CLOCK; - mmc->block_dev.part_type = PART_TYPE_DOS; - - mmc_register(mmc); - return mmc; } diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index aa2fdefa75..3db9669c82 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -167,7 +167,8 @@ ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) return 0; do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; if (mmc_write_blocks(mmc, start, cur, src) != cur) return 0; blocks_todo -= cur; diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 4f99617b9a..561b204598 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -122,6 +122,8 @@ struct mxcmci_host { }; static struct mxcmci_host mxcmci_host; + +/* maintainer note: do we really want to have a global host pointer? */ static struct mxcmci_host *host = &mxcmci_host; static inline int mxcmci_use_dma(struct mxcmci_host *host) @@ -485,35 +487,30 @@ static int mxcmci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops mxcmci_ops = { + .send_cmd = mxcmci_request, + .set_ios = mxcmci_set_ios, + .init = mxcmci_init, +}; + +static struct mmc_config mxcmci_cfg = { + .name = "MXC MCI", + .ops = &mxcmci_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + static int mxcmci_initialize(bd_t *bis) { - struct mmc *mmc = NULL; - - mmc = malloc(sizeof(struct mmc)); - - if (!mmc) - return -ENOMEM; - - sprintf(mmc->name, "MXC MCI"); - mmc->send_cmd = mxcmci_request; - mmc->set_ios = mxcmci_set_ios; - mmc->init = mxcmci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; - host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; - mmc->priv = host; - host->mmc = mmc; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; + mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; - mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - - mmc->b_max = 0; - - mmc_register(mmc); + host->mmc = mmc_create(&mxcmci_cfg, host); + if (host->mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 245f9d0c67..2fa4eeef44 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -35,6 +35,7 @@ struct mxsmmc_priv { int (*mmc_is_wp)(int); int (*mmc_cd)(int); struct mxs_dma_desc *desc; + struct mmc_config cfg; /* mmc configuration */ }; #define MXSMMC_MAX_TIMEOUT 10000 @@ -134,7 +135,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; @@ -305,7 +306,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) static void mxsmmc_set_ios(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Set the clock speed */ @@ -334,7 +335,7 @@ static void mxsmmc_set_ios(struct mmc *mmc) static int mxsmmc_init(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Reset SSP */ @@ -363,6 +364,12 @@ static int mxsmmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops mxsmmc_ops = { + .send_cmd = mxsmmc_send_cmd, + .set_ios = mxsmmc_set_ios, + .init = mxsmmc_init, +}; + int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) { struct mmc *mmc = NULL; @@ -373,20 +380,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) if (!mxs_ssp_bus_id_valid(id)) return -ENODEV; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - priv = malloc(sizeof(struct mxsmmc_priv)); - if (!priv) { - free(mmc); + if (!priv) return -ENOMEM; - } priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { free(priv); - free(mmc); return -ENOMEM; } @@ -399,17 +399,12 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) priv->id = id; priv->regs = mxs_ssp_regs_by_bus(id); - sprintf(mmc->name, "MXS MMC"); - mmc->send_cmd = mxsmmc_send_cmd; - mmc->set_ios = mxsmmc_set_ios; - mmc->init = mxsmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->priv = priv; + priv->cfg.name = "MXS MMC"; + priv->cfg.ops = &mxsmmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | + priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; @@ -419,10 +414,15 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ - mmc->f_min = 400000; - mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; - mmc->b_max = 0x20; + priv->cfg.f_min = 400000; + priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; + priv->cfg.b_max = 0x20; - mmc_register(mmc); + mmc = mmc_create(&priv->cfg, priv); + if (mmc == NULL) { + mxs_dma_desc_free(priv->desc); + free(priv); + return -ENOMEM; + } return 0; } diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d3a8b5303d..17cbb0983d 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -35,14 +36,25 @@ #include #include +/* simplify defines to OMAP_HSMMC_USE_GPIO */ +#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#define OMAP_HSMMC_USE_GPIO +#else +#undef OMAP_HSMMC_USE_GPIO +#endif + /* common definitions for all OMAPs */ #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) struct omap_hsmmc_data { struct hsmmc *base_addr; + struct mmc_config cfg; +#ifdef OMAP_HSMMC_USE_GPIO int cd_gpio; int wp_gpio; +#endif }; /* If we fail after 1 second wait, something is really bad */ @@ -51,11 +63,8 @@ struct omap_hsmmc_data { static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); -static struct mmc hsmmc_dev[3]; -static struct omap_hsmmc_data hsmmc_dev_data[3]; -#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#ifdef OMAP_HSMMC_USE_GPIO static int omap_mmc_setup_gpio_in(int gpio, const char *label) { if (!gpio_is_valid(gpio)) @@ -69,26 +78,6 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label) return gpio; } - -static int omap_mmc_getcd(struct mmc *mmc) -{ - int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; - return gpio_get_value(cd_gpio); -} - -static int omap_mmc_getwp(struct mmc *mmc) -{ - int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; - return gpio_get_value(wp_gpio); -} -#else -static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) -{ - return -1; -} - -#define omap_mmc_getcd NULL -#define omap_mmc_getwp NULL #endif #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) @@ -158,7 +147,7 @@ unsigned char mmc_board_init(struct mmc *mmc) &t2_base->devconf1); /* Change from default of 52MHz to 26MHz if necessary */ - if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) + if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, &t2_base->ctl_prog_io1); @@ -213,7 +202,7 @@ void mmc_init_stream(struct hsmmc *mmc_base) } -static int mmc_init_setup(struct mmc *mmc) +static int omap_hsmmc_init_setup(struct mmc *mmc) { struct hsmmc *mmc_base; unsigned int reg_val; @@ -322,7 +311,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct hsmmc *mmc_base; @@ -552,7 +541,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, return 0; } -static void mmc_set_ios(struct mmc *mmc) +static void omap_hsmmc_set_ios(struct mmc *mmc) { struct hsmmc *mmc_base; unsigned int dsor = 0; @@ -606,19 +595,58 @@ static void mmc_set_ios(struct mmc *mmc) writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); } +#ifdef OMAP_HSMMC_USE_GPIO +static int omap_hsmmc_getcd(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int cd_gpio; + + /* if no CD return as 1 */ + cd_gpio = priv_data->cd_gpio; + if (cd_gpio < 0) + return 1; + + return gpio_get_value(cd_gpio); +} + +static int omap_hsmmc_getwp(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int wp_gpio; + + /* if no WP return as 0 */ + wp_gpio = priv_data->wp_gpio; + if (wp_gpio < 0) + return 0; + + return gpio_get_value(wp_gpio); +} +#endif + +static const struct mmc_ops omap_hsmmc_ops = { + .send_cmd = omap_hsmmc_send_cmd, + .set_ios = omap_hsmmc_set_ios, + .init = omap_hsmmc_init_setup, +#ifdef OMAP_HSMMC_USE_GPIO + .getcd = omap_hsmmc_getcd, + .getwp = omap_hsmmc_getwp, +#endif +}; + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio) { - struct mmc *mmc = &hsmmc_dev[dev_index]; - struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; - uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | - MMC_MODE_HC; + struct mmc *mmc; + struct omap_hsmmc_data *priv_data; + struct mmc_config *cfg; + uint host_caps_val; - sprintf(mmc->name, "OMAP SD/MMC"); - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_init_setup; - mmc->priv = priv_data; + priv_data = malloc(sizeof(*priv_data)); + if (priv_data == NULL) + return -1; + + host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | + MMC_MODE_HC; switch (dev_index) { case 0: @@ -647,42 +675,46 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; return 1; } +#ifdef OMAP_HSMMC_USE_GPIO + /* on error gpio values are set to -1, which is what we want */ priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); - if (priv_data->cd_gpio != -1) - mmc->getcd = omap_mmc_getcd; - priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); - if (priv_data->wp_gpio != -1) - mmc->getwp = omap_mmc_getwp; +#endif - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = host_caps_val & ~host_caps_mask; + cfg = &priv_data->cfg; - mmc->f_min = 400000; + cfg->name = "OMAP SD/MMC"; + cfg->ops = &omap_hsmmc_ops; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->host_caps = host_caps_val & ~host_caps_mask; + + cfg->f_min = 400000; if (f_max != 0) - mmc->f_max = f_max; + cfg->f_max = f_max; else { - if (mmc->host_caps & MMC_MODE_HS) { - if (mmc->host_caps & MMC_MODE_HS_52MHz) - mmc->f_max = 52000000; + if (cfg->host_caps & MMC_MODE_HS) { + if (cfg->host_caps & MMC_MODE_HS_52MHz) + cfg->f_max = 52000000; else - mmc->f_max = 26000000; + cfg->f_max = 26000000; } else - mmc->f_max = 20000000; + cfg->f_max = 20000000; } - mmc->b_max = 0; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; #if defined(CONFIG_OMAP34XX) /* * Silicon revs 2.1 and older do not support multiblock transfers. */ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) - mmc->b_max = 1; + cfg->b_max = 1; #endif - - mmc_register(mmc); + mmc = mmc_create(cfg, priv_data); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h deleted file mode 100644 index 6fa42686e6..0000000000 --- a/drivers/mmc/pxa_mmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -/* PXA-250 MMC controller registers */ - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) -#define MMC_STRPCL_START_CLK (0x0002UL) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) - -#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ - |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ - |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) -#define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) - -/* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) -#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) -#define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) -#define MMC_PRTBUF_BUF_FULL (0x00UL ) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ -#define CMD(x) (x) - -#define MMC_DEFAULT_RCA 1 - -#define MMC_BLOCK_SIZE 512 -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __MMC_PXA_P_H__ */ diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 29f3eaf30b..1f297571e5 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -52,7 +52,7 @@ struct pxa_mmc_priv { /* Wait for bit to be set */ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -71,7 +71,7 @@ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) static int pxa_mmc_stop_clock(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -100,7 +100,7 @@ static int pxa_mmc_stop_clock(struct mmc *mmc) static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, uint32_t cmdat) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; int ret; @@ -143,7 +143,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t a, b, c; int i; @@ -185,7 +185,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->dest; @@ -221,7 +221,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->src; @@ -264,7 +264,7 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t cmdat = 0; int ret; @@ -317,7 +317,7 @@ static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, static void pxa_mmc_set_ios(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t tmp; uint32_t pxa_mmc_clock; @@ -335,7 +335,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) /* Set clock to the card the usual way. */ pxa_mmc_clock = 0; - tmp = mmc->f_max / mmc->clock; + tmp = mmc->cfg->f_max / mmc->clock; tmp += tmp % 2; while (tmp > 1) { @@ -348,7 +348,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) static int pxa_mmc_init(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; /* Make sure the clock are stopped */ @@ -366,6 +366,22 @@ static int pxa_mmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops pxa_mmc_ops = { + .send_cmd = pxa_mmc_request, + .set_ios = pxa_mmc_set_ios, + .init = pxa_mmc_init, +}; + +static struct mmc_config pxa_mmc_cfg = { + .name = "PXA MMC", + .ops = &pxa_mmc_ops, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .f_max = PXAMMC_MAX_SPEED, + .f_min = PXAMMC_MIN_SPEED, + .host_caps = PXAMMC_HOST_CAPS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int pxa_mmc_register(int card_index) { struct mmc *mmc; @@ -373,13 +389,11 @@ int pxa_mmc_register(int card_index) uint32_t reg; int ret = -ENOMEM; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - goto err0; - priv = malloc(sizeof(struct pxa_mmc_priv)); if (!priv) - goto err1; + goto err0; + + memset(priv, 0, sizeof(*priv)); switch (card_index) { case 0: @@ -389,26 +403,12 @@ int pxa_mmc_register(int card_index) priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; break; default: + ret = -EINVAL; printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", card_index); - goto err2; + goto err1; } - mmc->priv = priv; - - sprintf(mmc->name, "PXA MMC"); - mmc->send_cmd = pxa_mmc_request; - mmc->set_ios = pxa_mmc_set_ios; - mmc->init = pxa_mmc_init; - mmc->getcd = NULL; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = PXAMMC_MAX_SPEED; - mmc->f_min = PXAMMC_MIN_SPEED; - mmc->host_caps = PXAMMC_HOST_CAPS; - - mmc->b_max = 0; - #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ reg = readl(CKEN); reg |= CKEN12_MMC; @@ -419,14 +419,14 @@ int pxa_mmc_register(int card_index) writel(reg, CKENA); #endif - mmc_register(mmc); + mmc = mmc_create(&pxa_mmc_cfg, priv); + if (mmc == NULL) + goto err1; return 0; -err2: - free(priv); err1: - free(mmc); + free(priv); err0: return ret; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 40ff8739bf..ccae4ccae1 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -8,8 +8,15 @@ #include #include #include +#include +#include +#include #include #include +#include +#ifdef CONFIG_OF_CONTROL +#include +#endif static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -86,3 +93,125 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) return add_sdhci(host, 52000000, 400000); } + +#ifdef CONFIG_OF_CONTROL +struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; + +static int do_sdhci_init(struct sdhci_host *host) +{ + int dev_id, flag; + int err = 0; + + flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + dev_id = host->index + PERIPH_ID_SDMMC0; + + if (fdt_gpio_isvalid(&host->pwr_gpio)) { + gpio_direction_output(host->pwr_gpio.gpio, 1); + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("MMC not configured\n"); + return err; + } + } + + if (fdt_gpio_isvalid(&host->cd_gpio)) { + gpio_direction_output(host->cd_gpio.gpio, 0xf); + if (gpio_get_value(host->cd_gpio.gpio)) + return -ENODEV; + + err = exynos_pinmux_config(dev_id, flag); + if (err) { + printf("external SD not configured\n"); + return err; + } + } + + host->name = S5P_NAME; + + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_WAIT_SEND_CMD; + host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + host->set_control_reg = &s5p_sdhci_set_control_reg; + host->set_clock = set_mmc_clk; + + host->host_caps = MMC_MODE_HC; + + return add_sdhci(host, 52000000, 400000); +} + +static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) +{ + int bus_width, dev_id; + unsigned int base; + + /* Get device id */ + dev_id = pinmux_decode_periph_id(blob, node); + if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) { + debug("MMC: Can't get device id\n"); + return -1; + } + host->index = dev_id - PERIPH_ID_SDMMC0; + + /* Get bus width */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width <= 0) { + debug("MMC: Can't get bus-width\n"); + return -1; + } + host->bus_width = bus_width; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("MMC: Can't get base address\n"); + return -1; + } + host->ioaddr = (void *)base; + + fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio); + fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); + + return 0; +} + +static int process_nodes(const void *blob, int node_list[], int count) +{ + struct sdhci_host *host; + int i, node; + + debug("%s: count = %d\n", __func__, count); + + /* build sdhci_host[] for each controller */ + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + + host = &sdhci_host[i]; + + if (sdhci_get_config(blob, node, host)) { + printf("%s: failed to decode dev %d\n", __func__, i); + return -1; + } + do_sdhci_init(host); + } + return 0; +} + +int exynos_mmc_init(const void *blob) +{ + int count; + int node_list[SDHCI_MAX_HOSTS]; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + COMPAT_SAMSUNG_EXYNOS_MMC, node_list, + SDHCI_MAX_HOSTS); + + process_nodes(blob, node_list, count); + + return 1; +} +#endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1e86b92bee..3125d13ba3 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -127,7 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int stat = 0; int ret = 0; int trans_bytes = 0, is_aligned = 1; @@ -268,7 +268,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int div, clk, timeout; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); @@ -278,18 +278,18 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { /* Version 3.00 divisors must be a multiple of 2. */ - if (mmc->f_max <= clock) + if (mmc->cfg->f_max <= clock) div = 1; else { for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } } else { /* Version 2.00 divisors must be a power of 2. */ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } @@ -358,7 +358,7 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) void sdhci_set_ios(struct mmc *mmc) { u32 ctrl; - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if (host->set_control_reg) host->set_control_reg(host); @@ -395,7 +395,7 @@ void sdhci_set_ios(struct mmc *mmc) int sdhci_init(struct mmc *mmc) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { aligned_buffer = memalign(8, 512*1024); @@ -406,7 +406,7 @@ int sdhci_init(struct mmc *mmc) } } - sdhci_set_power(host, fls(mmc->voltages) - 1); + sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); if (host->quirks & SDHCI_QUIRK_NO_CD) { unsigned int status; @@ -430,26 +430,19 @@ int sdhci_init(struct mmc *mmc) return 0; } + +static const struct mmc_ops sdhci_ops = { + .send_cmd = sdhci_send_command, + .set_ios = sdhci_set_ios, + .init = sdhci_init, +}; + int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; unsigned int caps; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) { - printf("%s: mmc malloc fail!\n", __func__); - return -1; - } - - mmc->priv = host; - host->mmc = mmc; - - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = sdhci_send_command; - mmc->set_ios = sdhci_set_ios; - mmc->init = sdhci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + host->cfg.name = host->name; + host->cfg.ops = &sdhci_ops; caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA @@ -461,51 +454,60 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) #endif if (max_clk) - mmc->f_max = max_clk; + host->cfg.f_max = max_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) + host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else - mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) + host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - mmc->f_max *= 1000000; + host->cfg.f_max *= 1000000; } - if (mmc->f_max == 0) { + if (host->cfg.f_max == 0) { printf("%s: Hardware doesn't specify base clock frequency\n", __func__); return -1; } if (min_clk) - mmc->f_min = min_clk; + host->cfg.f_min = min_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_300; else - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_200; } - mmc->voltages = 0; + host->cfg.voltages = 0; if (caps & SDHCI_CAN_VDD_330) - mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; if (caps & SDHCI_CAN_VDD_300) - mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; if (caps & SDHCI_CAN_VDD_180) - mmc->voltages |= MMC_VDD_165_195; + host->cfg.voltages |= MMC_VDD_165_195; if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) - mmc->voltages |= host->voltages; + host->cfg.voltages |= host->voltages; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; + host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (caps & SDHCI_CAN_DO_8BIT) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; } if (host->host_caps) - mmc->host_caps |= host->host_caps; + host->cfg.host_caps |= host->host_caps; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; sdhci_reset(host, SDHCI_RESET_ALL); - mmc_register(mmc); + + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) { + printf("%s: mmc create fail!\n", __func__); + return -1; + } return 0; } diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 011d4f3e63..ed83a14c2d 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -20,11 +20,6 @@ #define DRIVER_NAME "sh_mmcif" -static void *mmc_priv(struct mmc *mmc) -{ - return (void *)mmc->priv; -} - static int sh_mmcif_intr(void *dev_id) { struct sh_mmcif_host *host = dev_id; @@ -522,7 +517,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -550,7 +545,7 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, static void sh_mmcif_set_ios(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -567,44 +562,48 @@ static void sh_mmcif_set_ios(struct mmc *mmc) static int sh_mmcif_init(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +static const struct mmc_ops sh_mmcif_ops = { + .send_cmd = sh_mmcif_request, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_init, +}; + +static struct mmc_config sh_mmcif_cfg = { + .name = DRIVER_NAME, + .ops = &sh_mmcif_ops, + .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | + MMC_MODE_8BIT | MMC_MODE_HC, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .f_min = CLKDEV_MMC_INIT, + .f_max = CLKDEV_EMMC_DATA, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int mmcif_mmc_init(void) { - int ret = 0; struct mmc *mmc; struct sh_mmcif_host *host = NULL; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - ret = -ENOMEM; - memset(mmc, 0, sizeof(*mmc)); host = malloc(sizeof(struct sh_mmcif_host)); if (!host) - ret = -ENOMEM; + return -ENOMEM; memset(host, 0, sizeof(*host)); - mmc->f_min = CLKDEV_MMC_INIT; - mmc->f_max = CLKDEV_EMMC_DATA; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | - MMC_MODE_8BIT | MMC_MODE_HC; - memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); - mmc->send_cmd = sh_mmcif_request; - mmc->set_ios = sh_mmcif_set_ios; - mmc->init = sh_mmcif_init; - mmc->getcd = NULL; - mmc->getwp = NULL; host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; - mmc->priv = host; - mmc_register(mmc); + mmc = mmc_create(&sh_mmcif_cfg, host); + if (mmc == NULL) { + free(host); + return -ENOMEM; + } - return ret; + return 0; } diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index e1817e24f6..ed67eec252 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -18,7 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct mmc mmc_dev[MAX_HOSTS]; struct mmc_host mmc_host[MAX_HOSTS]; #ifndef CONFIG_OF_CONTROL @@ -145,7 +144,7 @@ static int mmc_wait_inhibit(struct mmc_host *host, static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data, struct bounce_buffer *bbstate) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; int flags, i; int result; unsigned int mask = 0; @@ -314,7 +313,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, return 0; } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { void *buf; @@ -396,7 +395,7 @@ out: host->clock = clock; } -static void mmc_set_ios(struct mmc *mmc) +static void tegra_mmc_set_ios(struct mmc *mmc) { struct mmc_host *host = mmc->priv; unsigned char ctrl; @@ -456,7 +455,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) } /* Set SD bus voltage & enable bus power */ - mmc_set_power(host, fls(mmc->voltages) - 1); + mmc_set_power(host, fls(mmc->cfg->voltages) - 1); debug("%s: power control = %02X, host control = %02X\n", __func__, readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); @@ -464,9 +463,9 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) pad_init_mmc(host); } -static int mmc_core_init(struct mmc *mmc) +static int tegra_mmc_core_init(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; unsigned int mask; debug(" mmc_core_init called\n"); @@ -511,7 +510,7 @@ static int mmc_core_init(struct mmc *mmc) int tegra_mmc_getcd(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; debug("tegra_mmc_getcd called\n"); @@ -521,6 +520,13 @@ int tegra_mmc_getcd(struct mmc *mmc) return 1; } +static const struct mmc_ops tegra_mmc_ops = { + .send_cmd = tegra_mmc_send_cmd, + .set_ios = tegra_mmc_set_ios, + .init = tegra_mmc_core_init, + .getcd = tegra_mmc_getcd, +}; + static int do_mmc_init(int dev_index) { struct mmc_host *host; @@ -554,23 +560,18 @@ static int do_mmc_init(int dev_index) debug(" CD GPIO name = %s\n", host->cd_gpio.name); } - mmc = &mmc_dev[dev_index]; + memset(&host->cfg, 0, sizeof(host->cfg)); - sprintf(mmc->name, "Tegra SD/MMC"); - mmc->priv = host; - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_core_init; - mmc->getcd = tegra_mmc_getcd; - mmc->getwp = NULL; + host->cfg.name = "Tegra SD/MMC"; + host->cfg.ops = &tegra_mmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = 0; + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->cfg.host_caps = 0; if (host->width == 8) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; if (host->width >= 4) - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; /* * min freq is for card identification, and is the highest @@ -578,10 +579,14 @@ static int do_mmc_init(int dev_index) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) */ - mmc->f_min = 375000; - mmc->f_max = 48000000; + host->cfg.f_min = 375000; + host->cfg.f_max = 48000000; - mmc_register(mmc); + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; return 0; } @@ -668,6 +673,15 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra124 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 72a272f2ba..fdce2c2c10 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -32,3 +34,30 @@ int zynq_sdhci_init(u32 regbase) add_sdhci(host, 52000000, 52000000 >> 9); return 0; } + +#ifdef CONFIG_OF_CONTROL +int zynq_sdhci_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg; + + debug("ZYNQ SDHCI: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "arasan,sdhci-8.9a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + ret |= zynq_sdhci_init(reg); + } else { + debug("ZYNQ SDHCI: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 05ddfbb644..e1fc48fca4 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -31,6 +31,10 @@ #ifdef CONFIG_ATMEL_NAND_HW_PMECC +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SYS_NAND_ONFI_DETECTION +#endif + struct atmel_nand_host { struct pmecc_regs __iomem *pmecc; struct pmecc_errloc_regs __iomem *pmerrloc; @@ -1169,6 +1173,209 @@ static int at91_nand_ready(struct mtd_info *mtd) } #endif +#ifdef CONFIG_SPL_BUILD +/* The following code is for SPL */ +static nand_info_t mtd; +static struct nand_chip nand_chip; + +static int nand_command(int block, int page, uint32_t offs, u8 cmd) +{ + struct nand_chip *this = mtd.priv; + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + + while (this->dev_ready(&mtd)) + ; + + if (cmd == NAND_CMD_READOOB) { + offs += CONFIG_SYS_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } + + hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + + if (this->options & NAND_BUSWIDTH_16) + offs >>= 1; + + hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); + hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); +#endif + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + while (this->dev_ready(&mtd)) + ; + + return 0; +} + +static int nand_is_bad_block(int block) +{ + struct nand_chip *this = mtd.priv; + + nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); + + if (this->options & NAND_BUSWIDTH_16) { + if (readw(this->IO_ADDR_R) != 0xffff) + return 1; + } else { + if (readb(this->IO_ADDR_R) != 0xff) + return 1; + } + + return 0; +} + +#ifdef CONFIG_SPL_NAND_ECC +static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + +static int nand_read_page(int block, int page, void *dst) +{ + struct nand_chip *this = mtd.priv; + u_char ecc_calc[ECCTOTAL]; + u_char ecc_code[ECCTOTAL]; + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; + int eccsize = CONFIG_SYS_NAND_ECCSIZE; + int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsteps = ECCSTEPS; + int i; + uint8_t *p = dst; + nand_command(block, page, 0, NAND_CMD_READ0); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + if (this->ecc.mode != NAND_ECC_SOFT) + this->ecc.hwctl(&mtd, NAND_ECC_READ); + this->read_buf(&mtd, p, eccsize); + this->ecc.calculate(&mtd, p, &ecc_calc[i]); + } + this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + + for (i = 0; i < ECCTOTAL; i++) + ecc_code[i] = oob_data[nand_ecc_pos[i]]; + + eccsteps = ECCSTEPS; + p = dst; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + + return 0; +} +#else +static int nand_read_page(int block, int page, void *dst) +{ + struct nand_chip *this = mtd.priv; + + nand_command(block, page, 0, NAND_CMD_READ0); + atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page); + + return 0; +} +#endif /* CONFIG_SPL_NAND_ECC */ + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + unsigned int block, lastblock; + unsigned int page; + + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; + lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; + + while (block <= lastblock) { + if (!nand_is_bad_block(block)) { + while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + nand_read_page(block, page, dst); + dst += CONFIG_SYS_NAND_PAGE_SIZE; + page++; + } + + page = 0; + } else { + lastblock++; + } + + block++; + } + + return 0; +} + +int at91_nand_wait_ready(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + udelay(this->chip_delay); + + return 0; +} + +int board_nand_init(struct nand_chip *nand) +{ + int ret = 0; + + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CONFIG_SYS_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; + nand->read_buf = nand_read_buf16; +#else + nand->read_buf = nand_read_buf; +#endif + nand->cmd_ctrl = at91_nand_hwcontrol; +#ifdef CONFIG_SYS_NAND_READY_PIN + nand->dev_ready = at91_nand_ready; +#else + nand->dev_ready = at91_nand_wait_ready; +#endif + nand->chip_delay = 20; + +#ifdef CONFIG_ATMEL_NAND_HWECC +#ifdef CONFIG_ATMEL_NAND_HW_PMECC + ret = atmel_pmecc_nand_init_params(nand, &mtd); +#endif +#endif + + return ret; +} + +void nand_init(void) +{ + mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE; + mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE; + mtd.priv = &nand_chip; + nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + board_nand_init(&nand_chip); + +#ifdef CONFIG_SPL_NAND_ECC + if (nand_chip.ecc.mode == NAND_ECC_SOFT) { + nand_chip.ecc.calculate = nand_calculate_ecc; + nand_chip.ecc.correct = nand_correct_data; + } +#endif + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); +} + +void nand_deselect(void) +{ + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, -1); +} + +#else + #ifndef CONFIG_SYS_NAND_BASE_LIST #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif @@ -1227,3 +1434,4 @@ void board_nand_init(void) dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip", i); } +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1808a7ffba..be5a16a1ba 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -230,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, page_addr); - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + ifc_out32(&ifc->ifc_nand.row0, page_addr); + ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); buf_num = page_addr & priv->bufnum_mask; @@ -294,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read/write seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) printf("%s: Flash Time Out Error\n", __func__); @@ -324,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector + chip->ecc.steps - 1; for (i = sector / 4; i <= sector_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); @@ -364,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip, /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ if (mtd->writesize > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); if (oob) - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); else - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } } @@ -408,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, switch (command) { /* READ0 read the entire buffer to use hardware ECC. */ case NAND_CMD_READ0: { - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); set_addr(mtd, 0, page_addr, 0); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -424,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); set_addr(mtd, column, page_addr, 1); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -441,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_PARAM) timing = IFC_FIR_OP_RBCD; - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (timing << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - command << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, column); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (timing << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + command << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, column); /* * although currently it's 8 bytes for READID, we always read * the maximum 256 bytes(for PARAM) */ - out_be32(&ifc->ifc_nand.nand_fbcr, 256); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 256); ctrl->read_bytes = 256; set_addr(mtd, 0, 0, 0); @@ -468,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* ERASE2 uses the block and page address from ERASE1 */ case NAND_CMD_ERASE2: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); ctrl->read_bytes = 0; fsl_ifc_run_command(mtd); return; @@ -494,17 +494,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << + IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | @@ -513,18 +514,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= @@ -539,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, column -= mtd->writesize; ctrl->oob = 1; } - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); set_addr(mtd, column, page_addr, ctrl->oob); return; } @@ -547,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ case NAND_CMD_PAGEPROG: if (ctrl->oob) - out_be32(&ifc->ifc_nand.nand_fbcr, - ctrl->index - ctrl->column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, + ctrl->index - ctrl->column); else - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); fsl_ifc_run_command(mtd); return; case NAND_CMD_STATUS: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -572,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, return; case NAND_CMD_RESET: - out_be32(&ifc->ifc_nand.nand_fir0, - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); fsl_ifc_run_command(mtd); return; @@ -647,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ctrl->index < ctrl->read_bytes) { - data = in_be16((uint16_t *)&ctrl-> - addr[ctrl->index]); + data = ifc_in16((uint16_t *)&ctrl-> + addr[ctrl->index]); ctrl->index += 2; return (uint8_t)data; } @@ -727,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; /* Use READ_STATUS command, but wait for the device to be ready */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << - IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -741,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); /* Chip sometimes reporting write protect even when it's not */ nand_fsr = nand_fsr | NAND_STATUS_WP; @@ -784,17 +785,17 @@ static void fsl_ifc_ctrl_init(void) ifc_ctrl->regs = IFC_BASE_ADDR; /* clear event registers */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); - out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); /* Enable error and event for any detected errors */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, - IFC_NAND_EVTER_EN_OPC_EN | - IFC_NAND_EVTER_EN_PGRDCMPL_EN | - IFC_NAND_EVTER_EN_FTOER_EN | - IFC_NAND_EVTER_EN_WPER_EN); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); - out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); } static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) @@ -810,50 +811,50 @@ static void fsl_ifc_sram_init(void) cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ - csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); - csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); /* chage PageSize 8K and SpareSize 1K*/ csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); /* READID */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, 0x0); - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0); /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, 0x0); - out_be32(&ifc->ifc_nand.col0, 0x0); + ifc_out32(&ifc->ifc_nand.row0, 0x0); + ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -883,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { phys_addr_t phys_addr = virt_to_phys(addr); - cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); - csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { @@ -1004,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->ecc.mode = NAND_ECC_SOFT; } - ver = in_be32(&ifc_ctrl->regs->ifc_rev); + ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); if (ver == FSL_IFC_V1_1_0) fsl_ifc_sram_init(); diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 9de327ba4d..2f82f7c5c6 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) bufnum_end = bufnum + bufperpage - 1; do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); + status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); } while (!(status & IFC_NAND_EVTER_STAT_OPC)); if (status & IFC_NAND_EVTER_STAT_FTOER) { @@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) } for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = bufnum; i <= bufnum_end; i++) { if (check_read_ecc(buf, eccstat, i, page_size)) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); } static inline int bad_block(uchar *marker, int port_size) @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +#ifdef CONFIG_TPL_BUILD +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#else +static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) +#endif { struct fsl_ifc *ifc = IFC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) int sram_addr; int pg_no; + uchar *dst = vdst; /* Get NAND Flash configuration */ csor = CONFIG_SYS_NAND_CSOR; @@ -135,38 +140,38 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) blk_size = pages_per_blk * page_size; /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); /* Program FIR/FCR for Large/Small page */ if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); /* Read and copy u-boot on SDRAM from NAND device, In parallel * check for Bad block if found skip it and read continue to @@ -179,11 +184,11 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) bufnum = pg_no & bufnum_mask; sram_addr = bufnum * page_size * 2; - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); + ifc_out32(&ifc->ifc_nand.row0, pg_no); + ifc_out32(&ifc->ifc_nand.col0, 0); /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for read to complete */ nand_wait(&buf[sram_addr], bufnum, page_size); @@ -208,8 +213,19 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) offs += page_size; } while ((offs & (blk_size - 1)) && (pos < uboot_size)); } + + return 0; } +/* + * Defines a static function nand_load_image() here, because non-static makes + * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) + */ +#ifndef CONFIG_TPL_BUILD +#define nand_spl_load_image(offs, uboot_size, vdst) \ + nand_load(offs, uboot_size, vdst) +#endif + /* * Main entrypoint for NAND Boot. It's necessary that SDRAM is already * configured and available since this code loads the main U-boot image @@ -221,16 +237,17 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST - nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST); + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif /* diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 34688e9bef..5510b13c01 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) *p++ = in_be32((u32 *)(base + NDFC_DATA)); } -#ifndef CONFIG_NAND_SPL /* * Don't use these speedup functions in NAND boot image, since the image * has to fit into 4kByte. @@ -148,8 +147,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) } -#endif /* #ifndef CONFIG_NAND_SPL */ - void board_nand_select_device(struct nand_chip *nand, int chip) { /* @@ -207,21 +204,11 @@ int board_nand_init(struct nand_chip *nand) nand->options |= NAND_BUSWIDTH_16; #endif -#ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; nand->verify_buf = ndfc_verify_buf; nand->read_byte = ndfc_read_byte; chip++; -#else - /* - * Setup EBC (CS0 only right now) - */ - mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); - - mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); - mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); -#endif return 0; } diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 2aa7807f3e..47b1f1bfe2 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -16,9 +16,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #define ELM_DEFAULT_POLY (0) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 389c4de59a..881a63618c 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -9,17 +9,24 @@ #include #include #include -#include -#include +#include #include #include #include #include -#include +#include #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +/* 4 bit padding to make byte aligned, 56 = 52 + 4 */ +#define BCH4_BIT_PAD 4 +#ifdef CONFIG_BCH +static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, + 0x97, 0x79, 0xe5, 0x24, 0xb5}; +#endif static uint8_t cs; static __maybe_unused struct nand_ecclayout omap_ecclayout; @@ -60,21 +67,6 @@ int omap_spl_dev_ready(struct mtd_info *mtd) } #endif -/* - * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * - */ -static void __maybe_unused omap_hwecc_init(struct nand_chip *chip) -{ - /* - * Init ECC Control Register - * Clear all ECC | Enable Reg1 - */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); -} /* * gen_true_ecc - This function will generate true ECC value, which @@ -155,74 +147,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, return 0; } -/* - * omap_calculate_ecc - Generate non-inverted ECC bytes. - * - * Using noninverted ECC can be considered ugly since writing a blank - * page ie. padding will clear the ECC bytes. This is no problem as - * long nobody is trying to write data on the seemingly unused page. - * Reading an erased page will produce an ECC mismatch between - * generated and read ECC bytes that has to be dealt with separately. - * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC - * is used, the result of read will be 0x0 while the ECC offsets of the - * spare area will be 0xFF which will result in an ECC mismatch. - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer - */ -static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd, - const uint8_t *dat, uint8_t *ecc_code) -{ - u_int32_t val; - - /* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(&gpmc_cfg->ecc1_result); - - ecc_code[0] = val & 0xFF; - ecc_code[1] = (val >> 16) & 0xFF; - ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - writel(0x000, &gpmc_cfg->ecc_config); - - return 0; -} - -/* - * omap_enable_ecc - This function enables the hardware ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - - switch (mode) { - case NAND_ECC_READ: - case NAND_ECC_WRITE: - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - /* - * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes - * tell all regs to generate size0 sized regs - * we just have a single ECC engine for all CS - */ - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - &gpmc_cfg->ecc_size_config); - val = (dev_width << 7) | (cs << 1) | (0x1); - writel(val, &gpmc_cfg->ecc_config); - break; - default: - printf("Error: Unrecognized Mode[%d]!\n", mode); - break; - } -} - /* * Generic BCH interface */ @@ -239,12 +163,7 @@ struct nand_bch_priv { #define ECC_BCH8 1 #define ECC_BCH16 2 -/* GPMC ecc engine settings */ -#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ -#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ - /* BCH nibbles for diff bch levels */ -#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1) #define ECC_BCH4_NIBBLES 13 #define ECC_BCH8_NIBBLES 26 #define ECC_BCH16_NIBBLES 52 @@ -256,266 +175,161 @@ struct nand_bch_priv { * When some users with other BCH strength will exists this have to change! */ static __maybe_unused struct nand_bch_priv bch_priv = { - .mode = NAND_ECC_HW_BCH, .type = ECC_BCH8, .nibbles = ECC_BCH8_NIBBLES, .control = NULL }; /* - * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -__maybe_unused -static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) + * omap_reverse_list - re-orders list elements in reverse order [internal] + * @list: pointer to start of list + * @length: length of list +*/ +void omap_reverse_list(u8 *list, unsigned int length) { - uint32_t val; - uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - uint32_t unused_length = 0; - uint32_t wr_mode = BCH_WRAPMODE_6; - struct nand_bch_priv *bch = chip->priv; - - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) { - wr_mode = BCH_WRAPMODE_1; - - switch (bch->nibbles) { - case ECC_BCH4_NIBBLES: - unused_length = 3; - break; - case ECC_BCH8_NIBBLES: - unused_length = 2; - break; - case ECC_BCH16_NIBBLES: - unused_length = 0; - break; - } - - /* - * This is ecc_size_config for ELM mode. Here we are using - * different settings for read and write access and also - * depending on BCH strength. - */ - switch (mode) { - case NAND_ECC_WRITE: - /* write access only setup eccsize1 config */ - val = ((unused_length + bch->nibbles) << 22); - break; - - case NAND_ECC_READ: - default: - /* - * by default eccsize0 selected for ecc1resultsize - * eccsize0 config. - */ - val = (bch->nibbles << 12); - /* eccsize1 config */ - val |= (unused_length << 22); - break; - } - } else { - /* - * This ecc_size_config setting is for BCH sw library. - * - * Note: we only support BCH8 currently with BCH sw library! - * Should be really easy to adobt to BCH4, however some omap3 - * have flaws with BCH4. - * - * Here we are using wrapping mode 6 both for reading and - * writing, with: - * size0 = 0 (no additional protected byte in spare area) - * size1 = 32 (skip 32 nibbles = 16 bytes per sector in - * spare area) - */ - val = (32 << 22) | (0 << 12); - } - /* ecc size configuration */ - writel(val, &gpmc_cfg->ecc_size_config); - - /* - * Configure the ecc engine in gpmc - * We assume 512 Byte sector pages for access to NAND. - */ - val = (1 << 16); /* enable BCH mode */ - val |= (bch->type << 12); /* setup BCH type */ - val |= (wr_mode << 8); /* setup wrapping mode */ - val |= (dev_width << 7); /* setup device width (16 or 8 bit) */ - val |= (cs << 1); /* setup chip select to work on */ - debug("set ECC_CONFIG=0x%08x\n", val); - writel(val, &gpmc_cfg->ecc_config); -} - -/* - * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -__maybe_unused -static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - - omap_hwecc_init_bch(chip, mode); - /* enable ecc */ - writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); -} - -/* - * omap_ecc_disable - Disable H/W ECC calculation - * - * @mtd: MTD device structure - */ -static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) -{ - writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); -} - -/* - * BCH support using ELM module - */ -#ifdef CONFIG_NAND_OMAP_ELM -/* - * omap_read_bch8_result - Read BCH result for BCH8 level - * - * @mtd: MTD device structure - * @big_endian: When set read register 3 first - * @ecc_code: Read syndrome from BCH result registers - */ -static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, - uint8_t *ecc_code) -{ - uint32_t *ptr; - int8_t i = 0, j; - - if (big_endian) { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; - ecc_code[i++] = readl(ptr) & 0xFF; - ptr--; - for (j = 0; j < 3; j++) { - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = readl(ptr) & 0xFF; - ptr--; - } - } else { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; - for (j = 0; j < 3; j++) { - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ptr++; - } - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = 0; /* 14th byte is always zero */ + unsigned int i, j; + unsigned int half_length = length / 2; + u8 tmp; + for (i = 0, j = length - 1; i < half_length; i++, j--) { + tmp = list[i]; + list[i] = list[j]; + list[j] = tmp; } } /* - * omap_rotate_ecc_bch - Rotate the syndrome bytes - * + * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write * @mtd: MTD device structure - * @calc_ecc: ECC read from ECC registers - * @syndrome: Rotated syndrome will be retuned in this array - * + * @mode: Read/Write mode */ -static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, - uint8_t *syndrome) +__maybe_unused +static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t n_bytes = 0; - int8_t i, j; + struct nand_chip *nand = mtd->priv; + struct nand_bch_priv *bch = nand->priv; + unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; + unsigned int ecc_algo = 0; + unsigned int bch_type = 0; + unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; + u32 ecc_size_config_val = 0; + u32 ecc_config_val = 0; - switch (bch->type) { - case ECC_BCH4: - n_bytes = 8; + /* configure GPMC for specific ecc-scheme */ + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + return; + case OMAP_ECC_HAM1_CODE_HW: + ecc_algo = 0x0; + bch_type = 0x0; + bch_wrapmode = 0x00; + eccsize0 = 0xFF; + eccsize1 = 0xFF; break; - - case ECC_BCH16: - n_bytes = 28; + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + case OMAP_ECC_BCH8_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x1; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 28; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 26; /* ECC bits in nibbles per sector */ + eccsize1 = 2; /* non-ECC bits in nibbles per sector */ + } break; - - case ECC_BCH8: default: - n_bytes = 13; - break; + return; } + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + /* Configure ecc size for BCH */ + ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); + writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); - for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--) - syndrome[i] = calc_ecc[j]; + /* Configure device details for BCH engine */ + ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ + (bch_type << 12) | /* BCH4/BCH8/BCH16 */ + (bch_wrapmode << 8) | /* wrap mode */ + (dev_width << 7) | /* bus width */ + (0x0 << 4) | /* number of sectors */ + (cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ + writel(ecc_config_val, &gpmc_cfg->ecc_config); } /* - * omap_calculate_ecc_bch - Read BCH ECC result - * + * omap_calculate_ecc - Read ECC result * @mtd: MTD structure * @dat: unused * @ecc_code: ecc_code buffer + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC + * is used, the result of read will be 0x0 while the ECC offsets of the + * spare area will be 0xFF which will result in an ECC mismatch. */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, +static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { struct nand_chip *chip = mtd->priv; struct nand_bch_priv *bch = chip->priv; - uint8_t big_endian = 1; - int8_t ret = 0; + uint32_t *ptr, val = 0; + int8_t i = 0, j; - if (bch->type == ECC_BCH8) - omap_read_bch8_result(mtd, big_endian, ecc_code); - else /* BCH4 and BCH16 currently not supported */ - ret = -1; - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - -/* - * omap_fix_errors_bch - Correct bch error in the data - * - * @mtd: MTD device structure - * @data: Data read from flash - * @error_count:Number of errors in data - * @error_loc: Locations of errors in the data - * - */ -static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data, - uint32_t error_count, uint32_t *error_loc) -{ - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t count = 0; - uint32_t error_byte_pos; - uint32_t error_bit_mask; - uint32_t last_bit = (bch->nibbles * 4) - 1; - - /* Flip all bits as specified by the error location array. */ - /* FOR( each found error location flip the bit ) */ - for (count = 0; count < error_count; count++) { - if (error_loc[count] > last_bit) { - /* Remove the ECC spare bits from correction. */ - error_loc[count] -= (last_bit + 1); - /* Offset bit in data region */ - error_byte_pos = ((512 * 8) - - (error_loc[count]) - 1) / 8; - /* Error Bit mask */ - error_bit_mask = 0x1 << (error_loc[count] % 8); - /* Toggle the error bit to make the correction. */ - data[error_byte_pos] ^= error_bit_mask; + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: + val = readl(&gpmc_cfg->ecc1_result); + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + break; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: +#endif + case OMAP_ECC_BCH8_CODE_HW: + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + val = readl(ptr); + ecc_code[i++] = (val >> 0) & 0xFF; + ptr--; + for (j = 0; j < 3; j++) { + val = readl(ptr); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + ptr--; } + break; + default: + return -EINVAL; } + /* ECC scheme specific syndrome customizations */ + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: + break; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + + for (i = 0; i < chip->ecc.bytes; i++) + *(ecc_code + i) = *(ecc_code + i) ^ + bch8_polynomial[i]; + break; +#endif + case OMAP_ECC_BCH8_CODE_HW: + ecc_code[chip->ecc.bytes - 1] = 0x00; + break; + default: + return -EINVAL; + } + return 0; } +#ifdef CONFIG_NAND_OMAP_ELM /* * omap_correct_data_bch - Compares the ecc read from nand spare area * with ECC registers values and corrects one bit error if it has occured @@ -532,40 +346,72 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, { struct nand_chip *chip = mtd->priv; struct nand_bch_priv *bch = chip->priv; - uint8_t syndrome[28]; - uint32_t error_count = 0; + uint32_t eccbytes = chip->ecc.bytes; + uint32_t error_count = 0, error_max; uint32_t error_loc[8]; - uint32_t i, ecc_flag; + uint32_t i, ecc_flag = 0; + uint8_t count, err = 0; + uint32_t byte_pos, bit_pos; - ecc_flag = 0; - for (i = 0; i < chip->ecc.bytes; i++) - if (read_ecc[i] != 0xff) + /* check calculated ecc */ + for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + if (calc_ecc[i] != 0x00) ecc_flag = 1; - + } if (!ecc_flag) return 0; - elm_reset(); - elm_config((enum bch_level)(bch->type)); + /* check for whether its a erased-page */ + ecc_flag = 0; + for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + if (read_ecc[i] != 0xff) + ecc_flag = 1; + } + if (!ecc_flag) + return 0; /* * while reading ECC result we read it in big endian. * Hence while loading to ELM we have rotate to get the right endian. */ - omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); - - /* use elm module to check for errors */ - if (elm_check_error(syndrome, bch->nibbles, &error_count, - error_loc) != 0) { - printf("ECC: uncorrectable.\n"); - return -1; + switch (bch->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: + omap_reverse_list(calc_ecc, eccbytes - 1); + break; + default: + return -EINVAL; + } + /* use elm module to check for errors */ + elm_config((enum bch_level)(bch->type)); + if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) { + printf("nand: error: uncorrectable ECC errors\n"); + return -EINVAL; } - /* correct bch error */ - if (error_count > 0) - omap_fix_errors_bch(mtd, dat, error_count, error_loc); - - return 0; + for (count = 0; count < error_count; count++) { + switch (bch->type) { + case ECC_BCH8: + /* 14th byte in ECC is reserved to match ROM layout */ + error_max = SECTOR_BYTES + (eccbytes - 1); + break; + default: + return -EINVAL; + } + byte_pos = error_max - (error_loc[count] / 8) - 1; + bit_pos = error_loc[count] % 8; + if (byte_pos < SECTOR_BYTES) { + dat[byte_pos] ^= 1 << bit_pos; + printf("nand: bit-flip corrected @data=%d\n", byte_pos); + } else if (byte_pos < error_max) { + read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos; + printf("nand: bit-flip corrected @oob=%d\n", byte_pos - + SECTOR_BYTES); + } else { + err = -EBADMSG; + printf("nand: error: invalid bit-flip location\n"); + } + } + return (err) ? err : error_count; } /** @@ -636,57 +482,6 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, * OMAP3 BCH8 support (with BCH library) */ #ifdef CONFIG_BCH -/* - * omap_calculate_ecc_bch_sw - Read BCH ECC result - * - * @mtd: MTD device structure - * @dat: The pointer to data on which ecc is computed (unused here) - * @ecc: The ECC output buffer - */ -static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc) -{ - int ret = 0; - size_t i; - unsigned long nsectors, val1, val2, val3, val4; - - nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; - - for (i = 0; i < nsectors; i++) { - /* Read hw-computed remainder */ - val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]); - val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]); - val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]); - val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); - - /* - * Add constant polynomial to remainder, in order to get an ecc - * sequence of 0xFFs for a buffer filled with 0xFFs. - */ - *ecc++ = 0xef ^ (val4 & 0xFF); - *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); - *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); - *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); - *ecc++ = 0xed ^ (val3 & 0xFF); - *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); - *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); - *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); - *ecc++ = 0x97 ^ (val2 & 0xFF); - *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); - *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); - *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); - *ecc++ = 0xb5 ^ (val1 & 0xFF); - } - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - /** * omap_correct_data_bch_sw - Decode received data and correct errors * @mtd: MTD device structure @@ -835,9 +630,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13; - nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch_sw; - nand->ecc.calculate = omap_calculate_ecc_bch_sw; + nand->ecc.calculate = omap_calculate_ecc; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; @@ -852,7 +647,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - omap_hwecc_init_bch(nand, NAND_ECC_READ); bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; break; #else @@ -878,9 +672,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14; - nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.calculate = omap_calculate_ecc; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index f46e1633e2..e01ef5606d 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -399,8 +400,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, } cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; - cmd = malloc(cmdsz); - memset(cmd, 0, cmdsz); + cmd = calloc(1, cmdsz); + if (!cmd) { + debug("SF: Failed to allocate cmd\n"); + return -ENOMEM; + } cmd[0] = flash->read_cmd; while (len) { diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 136eae348f..ac886fd071 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -54,8 +54,8 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 3f2f0ed810..9de867f674 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -123,12 +123,11 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, return NULL; } - flash = malloc(sizeof(*flash)); + flash = calloc(1, sizeof(*flash)); if (!flash) { debug("SF: Failed to allocate spi_flash\n"); return NULL; } - memset(flash, '\0', sizeof(*flash)); /* Assign spi data */ flash->spi = spi; @@ -147,7 +146,21 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; - flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; + /* + * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the + * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with + * the 0x4d00 Extended JEDEC code have 512b pages. All of the others + * have 256b pages. + */ + if (ext_jedec == 0x4d00) { + if ((jedec == 0x0215) || (jedec == 0x216)) + flash->page_size = 256; + else + flash->page_size = 512; + } else { + flash->page_size = 256; + } + flash->page_size <<= flash->shift; flash->sector_size = params->sector_size << flash->shift; flash->size = flash->sector_size * params->nr_sectors; #ifdef CONFIG_SF_DUAL_FLASH diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 0ffd59d497..0c2d2ef1a9 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -259,6 +260,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 50167aab63..bd5fba21ce 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -656,7 +656,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); - priv->phy_mask |= 1 << slave->data->phy_id; + priv->phy_mask |= 1 << slave->data->phy_addr; } static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) @@ -941,14 +941,10 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) { struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; struct phy_device *phydev; - u32 supported = (SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Full); + u32 supported = PHY_GBIT_FEATURES; phydev = phy_connect(priv->bus, - CONFIG_PHY_ADDR, + slave->data->phy_addr, dev, slave->data->phy_if); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4d94..c45593bcc0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,7 +17,75 @@ #include #include "designware.h" -static int configure_phy(struct eth_device *dev); +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -1; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -1; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} static void tx_descs_init(struct eth_device *dev) { @@ -51,7 +119,13 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; } static void rx_descs_init(struct eth_device *dev) @@ -63,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -78,39 +161,13 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); -} - -static void descs_init(struct eth_device *dev) -{ - tx_descs_init(dev); - rx_descs_init(dev); -} - -static int mac_reset(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; - - ulong start; - int timeout = CONFIG_MACRESET_TIMEOUT; - - writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - - if (priv->interface != PHY_INTERFACE_MODE_RGMII) - writel(MII_PORTSELECT, &mac_p->conf); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; - - /* Try again after 10usec */ - udelay(10); - }; - - return -1; + priv->rx_currdescnum = 0; } static int dw_write_hwaddr(struct eth_device *dev) @@ -120,8 +177,8 @@ static int dw_write_hwaddr(struct eth_device *dev) u32 macid_lo, macid_hi; u8 *mac_id = &dev->enetaddr[0]; - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); macid_hi = mac_id[4] + (mac_id[5] << 8); writel(macid_hi, &mac_p->macaddr0hi); @@ -130,60 +187,86 @@ static int dw_write_hwaddr(struct eth_device *dev) return 0; } +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) +{ + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; + + if (phydev->speed == 100) + conf |= FES_100; + + if (phydev->duplex) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +} + +static void dw_eth_halt(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); + + phy_shutdown(priv->phydev); +} + static int dw_eth_init(struct eth_device *dev, bd_t *bis) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; - if (priv->phy_configured != 1) - configure_phy(dev); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) + return -1; - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + mdelay(100); + }; - /* Resore the HW MAC address as it has been lost during MAC reset */ + /* Soft reset above clears HW address registers. + * So we have to set it here once again */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); + rx_descs_init(dev); + tx_descs_init(dev); - writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | - TXSECONDFRAME, &dma_p->opmode); + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); - if (priv->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - if ((priv->interface != PHY_INTERFACE_MODE_MII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { - - if (priv->speed == 100) - conf |= FES_100; + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; } - if (priv->duplex == FULL) - conf |= FULLDPLXMODE; + dw_adjust_link(mac_p, priv->phydev); - writel(conf, &mac_p->conf); - - descs_init(dev); - - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + if (!priv->phydev->link) + return -1; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); @@ -197,6 +280,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + /* Invalidate only "status" field for the following check */ + invalidate_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); @@ -205,6 +293,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) memcpy((void *)desc_p->dmamac_addr, packet, length); + /* Flush data to be sent */ + flush_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + length); + #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ @@ -220,6 +312,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + sizeof(struct dmamacdescr)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -235,18 +331,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) static int dw_eth_recv(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - - u32 status = desc_p->txrx_status; int length = 0; + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + + sizeof(struct dmamacdescr)); + + status = desc_p->txrx_status; + /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ + invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + + length); + NetReceive(desc_p->dmamac_addr, length); /* @@ -255,6 +361,11 @@ static int dw_eth_recv(struct eth_device *dev) */ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + /* Flush only status field - others weren't changed */ + flush_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) desc_num = 0; @@ -265,251 +376,30 @@ static int dw_eth_recv(struct eth_device *dev) return length; } -static void dw_eth_halt(struct eth_device *dev) +static int dw_phy_init(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; + struct phy_device *phydev; + int mask = 0xffffffff; - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } - - /* Try again after 10usec */ - udelay(10); - }; - - return -1; -} - -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - - /* Try again after 10usec */ - udelay(10); - }; - - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); - - return ret; -} - -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) -{ - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; -} +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; #endif -static int dw_reset_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - ulong start; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - - start = get_timer(0); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - - /* Try again after 10usec */ - udelay(10); - }; - - if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) return -1; -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); -#endif - return 0; + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 1; } -/* - * Add weak default function for board specific PHY configuration - */ -int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) -{ - return 0; -} - -static int configure_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - ulong start; -#endif - -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else - return -1; -#else - phy_addr = priv->address; -#endif - - /* - * Some boards need board specific PHY initialization. This is - * after the main driver init code but before the auto negotiation - * is run. - */ - if (designware_board_phy_init(dev, phy_addr, - eth_mdio_write, dw_reset_phy) < 0) - return -1; - - if (dw_reset_phy(dev) < 0) - return -1; - -#if defined(CONFIG_DW_AUTONEG) - /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ - eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; - -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - start = get_timer(0); - puts("Waiting for PHY auto negotiation to complete"); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) { - priv->phy_configured = 1; - break; - } - - /* Print dot all 1s to show progress */ - if ((get_timer(start) % 1000) == 0) - putc('.'); - - /* Try again after 1msec */ - udelay(1000); - }; - - if (!(bmsr & BMSR_ANEGCOMPLETE)) - puts(" TIMEOUT!\n"); - else - puts(" done\n"); -#else - priv->phy_configured = 1; -#endif - - priv->speed = miiphy_speed(dev->name, phy_addr); - priv->duplex = miiphy_duplex(dev->name, phy_addr); - - return 0; -} - -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); - - return 0; -} - -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; -} -#endif - -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -531,19 +421,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - priv->phy_configured = 0; - priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -553,8 +438,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); -#endif - return 1; + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(dev); } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 5440c9215f..382b0c7f0a 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,8 +16,6 @@ #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -112,7 +110,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); /* * txrx_status definitions @@ -217,14 +215,9 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 address; u32 interface; - u32 speed; - u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; - u32 phy_configured; - u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -236,15 +229,8 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; }; -/* Speed specific definitions */ -#define SPEED_10M 1 -#define SPEED_100M 2 -#define SPEED_1000M 3 - -/* Duplex mode specific definitions */ -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 - #endif diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 3b2b995b53..4cefda48e4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -128,8 +128,12 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, - ð->mii_speed); + register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); +#ifdef FEC_QUIRK_ENET_MAC + speed--; +#endif + speed <<= 1; + writel(speed, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 74c72d3ff7..cd787f4eed 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -276,64 +276,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) "status", "disabled", strlen("disabled") + 1, 1); } -#ifdef CONFIG_SYS_FMAN_V3 -static int ft_fixup_xgec(void *blob, struct fm_eth_info *info) -{ - int off, i, ci; -#define FM1_10GEC3_RX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x488000) -#define FM1_10GEC3_TX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4a8000) -#define FM1_10GEC3_MAC_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4e0000) - - if ((info->port == FM1_10GEC3) || (info->port == FM1_10GEC4)) { - ci = (info->port == FM1_10GEC3) ? 2 : 3; - i = (info->port == FM1_10GEC3) ? 0 : 1; - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-rx", - FM1_10GEC3_RX_PORT_ADDR + - i * 0x1000); - if (off > 0) { - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - fdt_setprop(blob, off, "compatible", - "fsl,fman-port-10g-rx", 20); - } else { - goto err; - } - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-tx", - FM1_10GEC3_TX_PORT_ADDR + - i * 0x1000); - if (off > 0) { - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - fdt_setprop(blob, off, "compatible", - "fsl,fman-port-10g-tx", 20); - } else { - goto err; - } - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-memac", - FM1_10GEC3_MAC_ADDR + - i * 0x2000); - if (off > 0) - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - else - goto err; - } - return 0; -err: - printf("WARNING: Fail to find the node\n"); - return -1; -} -#endif - void fdt_fixup_fman_ethernet(void *blob) { int i; #ifdef CONFIG_SYS_FMAN_V3 - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + for (i = 0; i < ARRAY_SIZE(fm_info); i++) ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); - ft_fixup_xgec(blob, &fm_info[i]); - } #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { if (fm_info[i].type == FM_ETH_1G_E) diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 83cf081f3d..bcc871d842 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -12,5 +12,61 @@ phy_interface_t fman_port_enet_if(enum fm_port port) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + return PHY_INTERFACE_MODE_NONE; } diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index b5c1e9f76e..3b6212f858 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -50,15 +50,17 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; - if ((port == FM1_10GEC1 || port == FM1_10GEC2 || - port == FM1_10GEC3 || port == FM1_10GEC4) && + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - (is_serdes_configured(XFI_FM1_MAC1)) || - (is_serdes_configured(XFI_FM1_MAC2)) || (is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) return PHY_INTERFACE_MODE_RGMII; diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h deleted file mode 100644 index ff422e7737..0000000000 --- a/drivers/net/nicext.h +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * Name: nicext.h - * - * Description: Broadcom Network Interface Card Extension (NICE) is an - * extension to Linux NET device kernel mode drivers. - * NICE is designed to provide additional functionalities, - * such as receive packet intercept. To support Broadcom NICE, - * the network device driver can be modified by adding an - * device ioctl handler and by indicating receiving packets - * to the NICE receive handler. Broadcom NICE will only be - * enabled by a NICE-aware intermediate driver, such as - * Broadcom Advanced Server Program Driver (BASP). When NICE - * is not enabled, the modified network device drivers - * functions exactly as other non-NICE aware drivers. - * - * Author: Frankie Fan - * - * Created: September 17, 2000 - * - ****************************************************************************/ -#ifndef _nicext_h_ -#define _nicext_h_ - -/* - * ioctl for NICE - */ -#define SIOCNICE SIOCDEVPRIVATE+7 - -/* - * SIOCNICE: - * - * The following structure needs to be less than IFNAMSIZ (16 bytes) because - * we're overloading ifreq.ifr_ifru. - * - * If 16 bytes is not enough, we should consider relaxing this because - * this is no field after ifr_ifru in the ifreq structure. But we may - * run into future compatiability problem in case of changing struct ifreq. - */ -struct nice_req -{ - __u32 cmd; - - union - { -#ifdef __KERNEL__ - /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ - struct - { - void (*nrqus1_rx)( struct sk_buff*, void* ); - void* nrqus1_ctx; - } nrqu_nrqus1; - - /* cmd = NICE_CMD_QUERY_SUPPORT */ - struct - { - __u32 nrqus2_magic; - __u32 nrqus2_support_rx:1; - __u32 nrqus2_support_vlan:1; - __u32 nrqus2_support_get_speed:1; - } nrqu_nrqus2; -#endif - - /* cmd = NICE_CMD_GET_SPEED */ - struct - { - unsigned int nrqus3_speed; /* 0 if link is down, */ - /* otherwise speed in Mbps */ - } nrqu_nrqus3; - - /* cmd = NICE_CMD_BLINK_LED */ - struct - { - unsigned int nrqus4_blink_time; /* blink duration in seconds */ - } nrqu_nrqus4; - - } nrq_nrqu; -}; - -#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx -#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx -#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx -#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic -#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan -#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed -#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed -#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time - -/* - * magic constants - */ -#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */ -#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */ - -/* - * command field - */ -#define NICE_CMD_QUERY_SUPPORT 0x00000001 -#define NICE_CMD_SET_RX 0x00000002 -#define NICE_CMD_GET_RX 0x00000003 -#define NICE_CMD_GET_SPEED 0x00000004 -#define NICE_CMD_BLINK_LED 0x00000005 - -#endif /* _nicext_h_ */ diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c deleted file mode 100644 index 05a9e053ff..0000000000 --- a/drivers/net/npe/IxEthAcc.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - * @file IxEthAcc.c - * - * @author Intel Corporation - * @date 20-Feb-2001 - * - * @brief This file contains the implementation of the IXP425 Ethernet Access Component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - - -#include "IxEthAcc.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxFeatureCtrl.h" - -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAcc - *@{ - */ - - -/** - * @brief System-wide information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccInfo ixEthAccDataInfo; -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -/** - * @brief System-wide information - * - * @ingroup IxEthAccPri - * - */ -BOOL ixEthAccServiceInit = false; - -/* global filtering bit mask */ -PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * @brief Per port information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PUBLIC IxEthAccStatus ixEthAccInit() -{ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* - * Initialize Control plane - */ - if (ixEthDBInit() != IX_ETH_DB_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - ixEthAccNewSrcMask = (~0); /* want all the bits */ - } - else - { - ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */ - } - - /* - * Initialize Data plane - */ - if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - - if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MII - */ - if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MAC I/O memory - */ - if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize control plane interface lock - */ - if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* initialiasation is complete */ - ixEthAccServiceInit = true; - - return IX_ETH_ACC_SUCCESS; - -} - -PUBLIC void ixEthAccUnload(void) -{ - IxEthAccPortId portId; - - if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - /* check none of the port is still active */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0); - return; - } - } - } - - /* unmap the memory areas */ - ixEthAccMiiUnload(); - ixEthAccMacUnload(); - - /* set all ports as uninitialized */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixEthAccPortData[portId].portInitialized = false; - } - - /* uninitialize the service */ - ixEthAccServiceInit = false; - } -} - -PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) -{ - - IxEthAccStatus ret=IX_ETH_ACC_SUCCESS; - - if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - return(IX_ETH_ACC_FAIL); - } - - /* - * Check for valid port - */ - - if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) ) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - /* Already initialized */ - return(IX_ETH_ACC_FAIL); - } - - if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set the port init flag. - */ - - ixEthAccPortData[portId].portInitialized = true; - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* init learning/filtering database structures for this port */ - ixEthDBPortInit(portId); -#endif - - return(ret); -} - - diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c deleted file mode 100644 index 8249737b0c..0000000000 --- a/drivers/net/npe/IxEthAccCommon.c +++ /dev/null @@ -1,1025 +0,0 @@ -/** - * @file IxEthAccCommon.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation common support routines for the component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* - * Component header files - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxNpeMh.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -extern IxEthAccInfo ixEthAccDataInfo; - -/** - * - * @brief Maximum number of RX queues set to be the maximum number - * of traffic calsses. - * - */ -#define IX_ETHACC_MAX_RX_QUEUES \ - (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \ - - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \ - + 1) - -/** - * - * @brief Maximum number of 128 entry RX queues - * - */ -#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4 - -/** - * - * @brief Data structure template for Default RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - -/** - * - * @brief Data structure template for Small RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - - -/** - * - * @brief Data structure used to register & initialize the Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= -{ - { - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, - "Eth Rx Fr Q 1", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, - "Eth Rx Fr Q 2", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, - "Eth Rx Fr Q 3", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_ENET0_Q, - "Eth Tx Q 1", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_TX_FRAME_ENET1_Q, - "Eth Tx Q 2", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_TX_FRAME_ENET2_Q, - "Eth Tx Q 3", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ - false, /** Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ - IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - "Eth Tx Done Q", - ixEthTxFrameDoneQMCallback, - (IxQMgrCallbackId) 0, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/** - * - * @brief Data structure used to register & initialize the Queues - * - * The structure will be filled at run time depending on the NPE - * image already loaded and the QoS configured in ethDB. - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]= -{ - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/* forward declarations */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes); - -/** - * @fn ixEthAccQMgrQueueSetup(void) - * - * @brief Setup one queue and its event, and register the callback required - * by this component to the QMgr - * - * @internal - */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes) -{ - /* - * Configure each Q. - */ - if ( ixQMgrQConfig( qInfoDes->qName, - qInfoDes->qId, - qInfoDes->qSize, - qInfoDes->qWords) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - if ( ixQMgrWatermarkSet( qInfoDes->qId, - qInfoDes->AlmostEmptyThreshold, - qInfoDes->AlmostFullThreshold - ) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set dispatcher priority. - */ - if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId, - IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY) - != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Register callbacks for each Q. - */ - if ( ixQMgrNotificationCallbackSet(qInfoDes->qId, - qInfoDes->qCallback, - qInfoDes->callbackTag) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set notification condition for Q - */ - if (qInfoDes->qNotificationEnableAtStartup == true) - { - if ( ixQMgrNotificationEnable(qInfoDes->qId, - qInfoDes->qConditionSource) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - } - - return(IX_ETH_ACC_SUCCESS); -} - -/** - * @fn ixEthAccQMgrQueuesConfig(void) - * - * @brief Setup all the queues and register all callbacks required - * by this component to the QMgr - * - * The RxFree queues, tx queues, rx queues are configured statically - * - * Rx queues configuration is driven by QoS setup. - * Many Rx queues may be required when QoS is enabled (this depends - * on IxEthDB setup and the images being downloaded). The configuration - * of the rxQueues is done in many steps as follows: - * - * @li select all Rx queues as configured by ethDB for all ports - * @li sort the queues by traffic class - * @li build the priority dependency for all queues - * @li fill the configuration for all rx queues - * @li configure all statically configured queues - * @li configure all dynamically configured queues - * - * @param none - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrQueuesConfig(void) -{ - struct - { - int npeCount; - UINT32 npeId; - IxQMgrQId qId; - IxEthDBProperty trafficClass; - } rxQueues[IX_ETHACC_MAX_RX_QUEUES]; - - UINT32 rxQueue = 0; - UINT32 rxQueueCount = 0; - IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES; - IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS; - IxEthDBPortId ixEthDbPortId = 0; - IxEthAccPortId ixEthAccPortId = 0; - UINT32 ixNpeId = 0; - UINT32 ixHighestNpeId = 0; - UINT32 sortIterations = 0; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - IxEthAccQregInfo *qInfoDes = NULL; - IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY; - UINT32 ixEthDBParameter = 0; - BOOL completelySorted = false; - - /* Fill the corspondance between ports and queues - * This defines the mapping from port to queue Ids. - */ - - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q; -#endif - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET2_Q; -#endif - /* Fill the corspondance between ports and NPEs - * This defines the mapping from port to npeIds. - */ - - ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB; - ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA; -#endif - /* set the default rx scheduling discipline */ - ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY; - - /* - * Queue Selection step: - * - * The following code selects all the queues and build - * a temporary array which contains for each queue - * - the queue Id, - * - the highest traffic class (in case of many - * priorities configured for the same queue on different - * ports) - * - the number of different Npes which are - * configured to write to this queue. - * - * The output of this loop is a temporary array of RX queues - * in any order. - * - */ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - for (ixEthAccPortId = 0; - (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS) - && (ret == IX_ETH_ACC_SUCCESS); - ixEthAccPortId++) - { - /* map between ethDb and ethAcc port Ids */ - ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId; - - /* map between npeId and ethAcc port Ids */ - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - - /* Iterate thru the different priorities */ - for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass++) - { - ixEthDBStatus = ixEthDBFeaturePropertyGet( - ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - ixEthDBTrafficClass, - &ixEthDBPropertyType, - (void *)&ixEthDBParameter); - - if (ixEthDBStatus == IX_ETH_DB_SUCCESS) - { - /* This port and QoS class are mapped to - * a RX queue. - */ - if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY) - { - /* remember the highest npe Id supporting ethernet */ - if (ixNpeId > ixHighestNpeId) - { - ixHighestNpeId = ixNpeId; - } - - /* search the queue in the list of queues - * already used by an other port or QoS - */ - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter) - { - /* found an existing setup, update the number of ports - * for this queue if the port maps to - * a different NPE. - */ - if (rxQueues[rxQueue].npeId != ixNpeId) - { - rxQueues[rxQueue].npeCount++; - rxQueues[rxQueue].npeId = ixNpeId; - } - /* get the highest traffic class for this queue */ - if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass) - { - rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass; - } - break; - } - } - if (rxQueue == rxQueueCount) - { - /* new queue not found in the current list, - * add a new entry. - */ - IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES); - rxQueues[rxQueueCount].qId = ixEthDBParameter; - rxQueues[rxQueueCount].npeCount = 1; - rxQueues[rxQueueCount].npeId = ixNpeId; - rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass; - rxQueueCount++; - } - } - else - { - /* unexpected property type (not Integer) */ - ret = IX_ETH_ACC_FAIL; - - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0); - - /* no point to continue to iterate */ - break; - } - } - else - { - /* No Rx queue configured for this port - * and this traffic class. Do nothing. - */ - } - } - - /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */ - ixEthDBFeaturePropertySet(ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE, - NULL /* ignored */); - } - -#else - - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - rxQueues[0].qId = 4; - rxQueues[0].npeCount = 1; - rxQueues[0].npeId = ixNpeId; - rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - rxQueueCount++; - -#endif - - /* check there is at least 1 rx queue : there is no point - * to continue if there is no rx queue configured - */ - if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - /* Queue sort step: - * - * Re-order the array of queues by decreasing traffic class - * using a bubble sort. (trafficClass 0 is the lowest - * priority traffic, trafficClass 7 is the highest priority traffic) - * - * Primary sort order is traffic class - * Secondary sort order is npeId - * - * Note that a bubble sort algorithm is not very efficient when - * the number of queues grows . However, this is not a very bad choice - * considering the very small number of entries to sort. Also, bubble - * sort is extremely fast when the list is already sorted. - * - * The output of this loop is a sorted array of queues. - * - */ - sortIterations = 0; - do - { - sortIterations++; - completelySorted = true; - for (rxQueue = 0; - rxQueue < rxQueueCount - sortIterations; - rxQueue++) - { - /* compare adjacent elements */ - if ((rxQueues[rxQueue].trafficClass < - rxQueues[rxQueue+1].trafficClass) - || ((rxQueues[rxQueue].trafficClass == - rxQueues[rxQueue+1].trafficClass) - &&(rxQueues[rxQueue].npeId < - rxQueues[rxQueue+1].npeId))) - { - /* swap adjacent elements */ - int npeCount = rxQueues[rxQueue].npeCount; - UINT32 npeId = rxQueues[rxQueue].npeId; - IxQMgrQId qId = rxQueues[rxQueue].qId; - IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass; - rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount; - rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId; - rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId; - rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass; - rxQueues[rxQueue+1].npeCount = npeCount; - rxQueues[rxQueue+1].npeId = npeId; - rxQueues[rxQueue+1].qId = qId; - rxQueues[rxQueue+1].trafficClass = trafficClass; - completelySorted = false; - } - } - } - while (!completelySorted); - - /* Queue traffic class list: - * - * Fill an array of rx queues linked by ascending traffic classes. - * - * If the queues are configured as follows - * qId 6 -> traffic class 0 (lowest) - * qId 7 -> traffic class 0 - * qId 8 -> traffic class 6 - * qId 12 -> traffic class 7 (highest) - * - * Then the output of this loop will be - * - * higherPriorityQueue[6] = 8 - * higherPriorityQueue[7] = 8 - * higherPriorityQueue[8] = 12 - * higherPriorityQueue[12] = Invalid queueId - * higherPriorityQueue[...] = Invalid queueId - * - * Note that this queue ordering does not handle all possibilities - * that could result from different rules associated with different - * ports, and inconsistencies in the rules. In all cases, the - * output of this algorithm is a simple linked list of queues, - * without closed circuit. - - * This list is implemented as an array with invalid values initialized - * with an "invalid" queue id which is the maximum number of queues. - * - */ - - /* - * Initialise the rx queue list. - */ - for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES; - } - - /* build the linked list for this NPE. - */ - for (ixNpeId = 0; - ixNpeId <= ixHighestNpeId; - ixNpeId++) - { - /* iterate thru the sorted list of queues - */ - ixQId = IX_QMGR_MAX_NUM_QUEUES; - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].npeId == ixNpeId) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - /* iterate thru queues with the same traffic class - * than the current queue. (queues are ordered by descending - * traffic classes and npeIds). - */ - while ((rxQueue < rxQueueCount - 1) - && (rxQueues[rxQueue].trafficClass - == rxQueues[rxQueue+1].trafficClass) - && (ixNpeId == rxQueues[rxQueue].npeId)) - { - rxQueue++; - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - } - ixQId = rxQueues[rxQueue].qId; - } - } - } - - /* point on the first dynamic queue description */ - qInfoDes = ixEthAccQmgrRxQueuesInfo; - - /* update the list of queues with the rx queues */ - for (rxQueue = 0; - (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS); - rxQueue++) - { - /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues - * with the full 128 entries. For the lower priority queues, use - * a smaller number of entries. This ensures queue resources - * remain available for other components. - */ - if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) && - (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) ) - { - /* add the small RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes)); - } else { - /* add the default RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes)); - } - - /* setup the RxQueue ID */ - qInfoDes->qId = rxQueues[rxQueue].qId; - - /* setup the RxQueue watermark level - * - * Each queue can be filled by many NPEs. To avoid the - * NPEs to write to a full queue, need to set the - * high watermark level for nearly full condition. - * (the high watermark level are a power of 2 - * starting from the top of the queue) - * - * Number of watermark - * ports level - * 1 0 - * 2 1 - * 3 2 - * 4 4 - * 5 4 - * 6 8 - * n approx. 2**ceil(log2(n)) - */ - if (rxQueues[rxQueue].npeCount == 1) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0; - } - else if (rxQueues[rxQueue].npeCount == 2) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1; - } - else if (rxQueues[rxQueue].npeCount == 3) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2; - } - else - { - /* reach the maximum number for CSR 2.0 */ - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0); - ret = IX_ETH_ACC_FAIL; - break; - } - - /* move to next queue entry */ - ++qInfoDes; - } - - /* configure the static list (RxFree, Tx and TxDone queues) */ - for (qInfoDes = ixEthAccQmgrStaticInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - /* configure the dynamic list (Rx queues) */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - return(ret); -} - -/** - * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries) - * - * @brief Add and return the total number of entries in all Rx queues - * - * @param UINT32 rxQueueEntries[in] number of entries in all queues - * - * @return void - * - * @note Rx queues configuration is driven by Qos Setup. There is a - * variable number of rx queues which are set at initialisation. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries) -{ - UINT32 rxQueueLevel; - IxEthAccQregInfo *qInfoDes;; - - *numRxQueueEntries = 0; - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - qInfoDes->qCallback != (IxQMgrCallback)NULL; - ++qInfoDes) - { - /* retrieve the rx queue level */ - rxQueueLevel = 0; - ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel); - (*numRxQueueEntries) += rxQueueLevel; - } -} - -/** - * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) - * - * @brief Change the callback registered to all rx queues. - * - * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register - * - * @return IxEthAccStatus - * - * @note The user may decide to use different Rx mechanisms - * (e.g. receive many frames at the same time , or receive - * one frame at a time, depending on the overall application - * performances). A different QMgr callback is registered. This - * way, there is no excessive pointer checks in the datapath. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) -{ - IxEthAccQregInfo *qInfoDes; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - - /* parameter check */ - if (NULL == ixQMgrCallback) - { - ret = IX_ETH_ACC_FAIL; - } - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - /* register the rx callback for all queues */ - if (ixQMgrNotificationCallbackSet(qInfoDes->qId, - ixQMgrCallback, - qInfoDes->callbackTag - ) != IX_SUCCESS) - { - ret = IX_ETH_ACC_FAIL; - } - } - return(ret); -} - -/** - * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) - * - * @brief Check the npe exists for this port - * - * @param IxEthAccPortId portId[in] port - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) -{ - - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -/** - * @fn ixEthAccStatsShow(void) - * - * @brief Displays all EthAcc stats - * - * @return void - * - */ -void ixEthAccStatsShow(IxEthAccPortId portId) -{ - ixEthAccMdioShow(); - - printf("\nPort %u\nUnicast MAC : ", portId); - ixEthAccPortUnicastAddressShow(portId); - ixEthAccPortMulticastAddressShow(portId); - printf("\n"); - - ixEthAccDataPlaneShow(); -} - - - diff --git a/drivers/net/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c deleted file mode 100644 index dbe32e133c..0000000000 --- a/drivers/net/npe/IxEthAccControlInterface.c +++ /dev/null @@ -1,509 +0,0 @@ -/** - * @file IxEthAccControlInterface.c - * - * @author Intel Corporation - * @date - * - * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" - -PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId); - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - /* check the context is iinitialized */ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnabledQueryPriv(portId, enabled); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeClearPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeSetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeaveAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC void -ixEthAccPortMulticastAddressShow(IxEthAccPortId portId) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - ixEthAccPortMulticastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeSetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeGetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccRxSchedulingDisciplineSetPriv(sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMacResetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c deleted file mode 100644 index c0b82d99b7..0000000000 --- a/drivers/net/npe/IxEthAccDataPlane.c +++ /dev/null @@ -1,2459 +0,0 @@ -/** - * @file IxEthDataPlane.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation of the IXPxxx - * Ethernet Access Data plane component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeMh.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxOsal.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * private functions prototype - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask); - -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr); - -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority); - -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId); - -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, - UINT32 qBuffer, - UINT32 priority); - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* increment a counter only when stats are enabled */ -#define TX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field) -#define RX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field) - -/* always increment the counter (mainly used for unexpected errors) */ -#define TX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccTxData.stats.field++ -#define RX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccRxData.stats.field++ - -PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -extern IxEthAccInfo ixEthAccDataInfo; - -PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; -PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/** - * - * @brief Mbuf header conversion macros : they implement the - * different conversions using a temporary value. They also double-check - * that the parameters can be converted to/from NPE format. - * - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \ - while(0) -#else -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \ - while(0) -#endif - -/** - * - * @brief Mbuf payload pointer conversion macros : Wince has its own - * method to convert the buffer pointers - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define DATAPTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#else -#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst) -#endif - - -/* Flush the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \ - do { \ - IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Invalidate the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \ - do { \ - IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Preload one cache line (shared mbuf headers are aligned - * and their size is 1 cache line) - * - * IX_OSAL_CACHED is defined when the mbuf headers are - * allocated from cached memory. - * - * Other processor on emulation environment may not implement - * preload function - */ -#ifdef IX_OSAL_CACHED - #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \ - do { /* preload a cache line (Xscale Processor) */ \ - __asm__ (" pld [%0]\n": : "r" (ptr)); \ - } \ - while(0) - #else - /* preload not implemented on different processor */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) - #endif -#else - /* preload not needed if cache is not enabled */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) -#endif - -/** - * - * @brief function to retrieve the correct pointer from - * a queue entry posted by the NPE - * - * @param qEntry : entry from qmgr queue - * mask : applicable mask for this queue - * (4 most significant bits are used for additional informations) - * - * @return IX_OSAL_MBUF * pointer to mbuf header - * - * @internal - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask) -{ - IX_OSAL_MBUF *mbufPtr; - - if (qEntry != 0) - { - /* mask NPE bits (e.g. priority, port ...) */ - qEntry &= mask; - -#if IX_ACC_DRAM_PHYS_OFFSET != 0 - /* restore the original address pointer (if PHYS_OFFSET is not 0) */ - qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); -#endif - /* get the mbuf pointer address from the npe-shared address */ - qEntry -= offsetof(IX_OSAL_MBUF,ix_ne); - - /* phys2virt mbuf */ - mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry); - - /* preload the cacheline shared with NPE */ - IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr)); - - /* preload the cacheline used by xscale */ - IX_ACC_DATA_CACHE_PRELOAD(mbufPtr); - } - else - { - mbufPtr = NULL; - } - - return mbufPtr; -} - -/* Convert the mbuf header for NPE transmission */ -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 qbuf; - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs); - - /* payload pointer conversion */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : the frame length is the mbuf length - * and the 2 identical lengths are stored in the same - * word. - */ - len = IX_OSAL_MBUF_MLEN(mbuf); - - /* set the length in both length and pktLen 16-bits fields */ - len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next contains 0 */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* get the frame length from the header of the first buffer */ - frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf); - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs); - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - /* Buffer length and frame length are stored in the same word */ - len = IX_OSAL_MBUF_MLEN(ptr); - len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* get the virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - if (nextPtr != NULL) - { - /* shared pointer of the next buffer is chained */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* move to next buffer */ - ptr = nextPtr; - - /* the frame length field is set only in the first buffer - * and is zeroed in the next buffers - */ - frmLen = 0; - } - while(ptr != NULL); - - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header for NPE reception */ -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - UINT32 qbuf; - - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs); - - /* unchained mbufs : payload pointer */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : set the buffer length - * and the frame length field is zeroed - */ - len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next pointer is null */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - - do - { - /* chained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs); - - /* we must save virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - - if (nextPtr != NULL) - { - /* chaining pointer for NPE */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - - /* buffer length */ - len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(ptr); - - /* next mbuf in the chain */ - ptr = nextPtr; - } - while(ptr != NULL); - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header after NPE transmission - * Since there is nothing changed by the NPE, there is no need - * to process anything but the update of internal stats - * when they are enabled -*/ -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf) -{ -#ifndef NDEBUG - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs : update the stats */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs); - } - else - { - /* chained mbufs : walk the chain and update the stats */ - IX_OSAL_MBUF *ptr = mbuf; - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs); - ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - } - while (ptr != NULL); - } -#endif -} - -/* Convert the mbuf header after NPE reception */ -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs); - - /* get the frame length. it is the same than the buffer length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - len &= IX_ETHNPE_ACC_PKTLENGTH_MASK; - IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len; - - /* clears the next packet field */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL; - } - else - { - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* convert the frame length */ - frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK); - - /* chained mbufs */ - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs); - - /* convert the length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr)); - IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET); - - /* get the next pointer */ - PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); - if (nextPtr != NULL) - { - nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne)); - } - /* set the next pointer */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr; - - /* move to the next buffer */ - ptr = nextPtr; - } - while (ptr != NULL); - } -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the tx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - TX_STATS_INC(portId, txOverflow); - } -#endif - ixOsalFastMutexUnlock(&txWriteMutex[portId]); - } - else - { - TX_STATS_INC(portId, txLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the Rx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - RX_STATS_INC(portId, rxFreeOverflow); - } -#endif - ixOsalFastMutexUnlock(&rxWriteMutex[portId]); - } - else - { - RX_STATS_INC(portId, rxFreeLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* - * Set the priority and write to a qmgr queue. - */ -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority) -{ - /* fill the priority field */ - qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R); - - return ixEthAccQmgrLockTxWrite(portId, qBuffer); -} - -/** - * - * @brief This function will discover the highest priority S/W Tx Q that - * has entries in it - * - * @param portId - (in) the id of the port whose S/W Tx queues are to be searched - * priorityPtr - (out) the priority of the highest priority occupied q will be written - * here - * - * @return IX_ETH_ACC_SUCCESS if an occupied Q is found - * IX_ETH_ACC_FAIL if no Q has entries - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr) -{ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline - == FIFO_NO_PRIORITY) - { - if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY])) - { - return IX_ETH_ACC_FAIL; - } - else - { - *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - TX_STATS_INC(portId,txPriority[*priorityPtr]); - return IX_ETH_ACC_SUCCESS; - } - } - else - { - IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7; - while(1) - { - if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[highestPriority])) - { - - *priorityPtr = highestPriority; - TX_STATS_INC(portId,txPriority[highestPriority]); - return IX_ETH_ACC_SUCCESS; - - } - if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0) - { - return IX_ETH_ACC_FAIL; - } - highestPriority--; - } - } -} - -/** - * - * @brief This function will take a buffer from a TX S/W Q and attempt - * to add it to the relevant TX H/W Q - * - * @param portId - the port whose TX queue is to be written to - * priority - identifies the queue from which the entry is to be read - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus; - - IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority"); - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - if (mbuf != NULL) - { - /* - * Add the Tx buffer to the H/W Tx Q - * We do not need to flush here as it is already done - * in TxFrameSubmit(). - */ - qStatus = ixEthAccQmgrTxWrite( - portId, - IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)), - priority); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txFromSwQOK); - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer - * back on the s/w Q. - * we must put it back on the head of the q to avoid - * reordering packet tx - */ - TX_STATS_INC(portId,txFromSwQDelayed); - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - /*enable Q notification*/ - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING) - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - TX_INC(portId,txUnexpectedError); - - /* recovery attempt */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - -/** - * - * @brief This function will take a buffer from a RXfree S/W Q and attempt - * to add it to the relevant RxFree H/W Q - * - * @param portId - the port whose RXFree queue is to be written to - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus = IX_SUCCESS; - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - if (mbuf != NULL) - { - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, - IX_OSAL_MMU_VIRT_TO_PHYS( - (UINT32)IX_ETHACC_NE_SHARED(mbuf))); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepFromSwQOK); - /* - * Buffer added to h/w Q. - */ - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer back on the s/w Q. - */ - RX_STATS_INC(portId,rxFreeRepFromSwQDelayed); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - } - else - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - - IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccInitDataPlane() -{ - UINT32 portId; - - /* - * Initialize the service and register callback to other services. - */ - - IX_ETH_ACC_MEMSET(&ixEthAccDataStats, - 0, - sizeof(ixEthAccDataStats)); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixOsalFastMutexInit(&txWriteMutex[portId]); - ixOsalFastMutexInit(&rxWriteMutex[portId]); - - IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId], - 0, - sizeof(ixEthAccPortData[portId])); - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY; - } - - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback - txCallbackFn, - UINT32 callbackTag) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - -/* HACK: removing this code to enable NPE-A preliminary testing - * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - * { - * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0); - * return IX_ETH_ACC_SUCCESS ; - * } - */ - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if (txCallbackFn == 0) - /* Check for null function pointer here. */ - { - return (IX_ETH_ACC_INVALID_ARG); - } - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag; - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0); - - RX_INC(portId,rxUnexpectedError); - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( - IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0); - - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - IxEthAccTxPriority highestPriority; - IxQMgrQStatus txQStatus; - -#ifndef NDEBUG - if (buffer == NULL) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n", - (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7) - { - return (IX_ETH_ACC_INVALID_ARG); - } -#endif - - /* - * Need to Flush the MBUF and its contents (data) as it may be - * read from the NPE. Convert virtual addresses to physical addresses also. - */ - qBuffer = ixEthAccMbufTxQPrepare(buffer); - - /* - * If no fifo priority set on Xscale ... - */ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_NO_PRIORITY) - { - /* - * Add The Tx Buffer to the H/W Tx Q if possible - * (the priority is passed to the NPE, because - * the NPE is able to reorder the frames - * before transmission to the underlying hardware) - */ - qStatus = ixEthAccQmgrTxWrite(portId, - qBuffer, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txQOK); - - /* - * "best case" scenario : Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in the sw Q. - * (use the default priority queue regardless of - * input parameter) - */ - priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - } - else - { - /* unexpected qmgr error */ - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - } - else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY) - { - - /* - * For priority transmission, put the frame directly on the H/W queue - * if the H/W queue is empty, otherwise, put it in a S/W Q - */ - ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus); - if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0) - { - /*The tx queue is empty, check whether there are buffers on the s/w queues*/ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - - /* the queue was empty, 1 buffer is already supplied - * but is likely to be immediately transmitted and the - * hw queue is likely to be empty again, so submit - * more from the sw queues - */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - ixEthAccTxFromSwQ(portId, highestPriority); - /* - * and force the buffer supplied to be placed - * on a priority queue - */ - qStatus = IX_QMGR_Q_OVERFLOW; - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - qStatus = IX_QMGR_Q_OVERFLOW; - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n", - 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - if(qStatus == IX_SUCCESS ) - { - TX_STATS_INC(portId,txQOK); - return IX_ETH_ACC_SUCCESS; - } - else if(qStatus == IX_QMGR_Q_OVERFLOW) - { - TX_STATS_INC(portId,txQDelayed); - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId]. - ixEthAccTxData.txQ[priority], - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - */ - TX_STATS_INC(portId,txLateNotificationEnabled); - - /* pull a buffer from the sw queue */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit from them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * - * @brief replenish: convert a chain of mbufs to the format - * expected by the NPE - * - */ - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - - /* - * Check buffer is valid. - */ - -#ifndef NDEBUG - /* check parameter value */ - if (buffer == 0) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - /* check initialisation is done */ - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - /* check boundaries and constraints */ - if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - { - return (IX_ETH_ACC_FAIL); - } -#endif - - qBuffer = ixEthAccMbufRxQPrepare(buffer); - - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepOK); - /* - * Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - RX_STATS_INC(portId,rxFreeRepDelayed); - /* - * We were unable to write the buffer to the approprate H/W Q, - * Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - * move an entry from the sw queue to the hw queue */ - RX_STATS_INC(portId,rxFreeLateNotificationEnabled); - ixEthAccRxFreeFromSwQ(portId); - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return(IX_ETH_ACC_FAIL); - } - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline - sched) -{ - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched; - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline - sched) -{ - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccDataInfo.schDiscipline = sched; - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) - * - * @brief process incoming frame : - * - * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback - * - * @return none - * - * @internal - * - */ -IX_ETH_ACC_PRIVATE BOOL -ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) -{ - UINT32 flags; - IxEthDBStatus result; - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameProcess: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return false; - } -#endif - - /* convert fields from mbuf header */ - ixEthAccMbufFromRxQ(mbufPtr); - - /* check about any special processing for this frame */ - flags = IX_ETHACC_NE_FLAGS(mbufPtr); - if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0) - { - /* "best case" scenario : nothing special to do for this frame */ - return true; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* if a new source MAC address is detected by the NPE, - * update IxEthDB with the portId and the MAC address. - */ - if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0) - { - result = ixEthDBFilteringDynamicEntryProvision(portId, - (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr)); - - if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE) - { - if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY)) - { - RX_STATS_INC(portId, rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \ - to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0); - } - else - { - /* we expect this to fail during PortDisable, as EthDB is disabled for - * that port and will refuse to learn new addresses - */ - } - } - else - { - RX_STATS_INC(portId, rxUnlearnedMacAddress); - } - } -#endif - - /* check if this frame should have been filtered - * by the NPE and take the appropriate action - */ - if (((flags & IX_ETHACC_NE_FILTERMASK) != 0) - && (ixEthAccMacState[portId].portDisableState == ACTIVE)) - { - /* If the mbuf was allocated with a small data size, or the current data pointer is not - * within the allocated data area, then the buffer is non-standard and has to be - * replenished with the minimum size only - */ - if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr)) - || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) + - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr)) - < IX_OSAL_MBUF_MDATA(mbufPtr)) ) - { - /* set to minimum length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN; - } - else - { - /* restore original length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) - - (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) ); - } - - /* replenish from here */ - if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\ - on port %d\n", portId, 0, 0, 0, 0, 0); - } - - RX_STATS_INC(portId, rxFiltered); - - /* indicate that frame should not be subjected to further processing */ - return false; - } - - return true; -} - - -/** - * @fn ixEthRxFrameQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed one-at-a-time to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 destPortId; - UINT32 npeId; - UINT32 rxQReadStatus; - - /* - * Design note : entries are read in a buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* process frame, check the return code and skip the remaining of - * the loop if the frame is to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* destination portId for this packet */ - destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr); - - if (destPortId != IX_ETH_DB_UNKNOWN_PORT) - { - destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId); - } - - /* test if QoS is enabled in ethAcc - */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag, - mbufPtr, - destPortId); - } - } - } while (rxQReadStatus == IX_SUCCESS); -} - -/** - * @fn ixEthRxMultiBufferQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed as an array to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 npeId; - UINT32 rxQReadStatus; - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS]; - - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* skip the remaining of the loop if the frame is - * to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* store a mbuf pointer in an array */ - *rxMbufPtr[portId]++ = mbufPtr; - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - } - - /* test for QoS enabled in ethAcc */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - } - - /* check if any of the the arrays contains any entry */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if (rxMbufPtr[portId] != rxMbufPortArray[portId]) - { - /* add a last NULL pointer at the end of the - * array of mbuf pointers - */ - *rxMbufPtr[portId] = NULL; - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback with an array of - * buffers (NULL terminated) - */ - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackTag, - rxMbufPortArray[portId]); - - /* reset the buffer pointer to the beginning of - * the array - */ - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - } - - } while (rxQReadStatus == IX_SUCCESS); -} - - -/** - * @brief rxFree low event handler - * - */ -void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD; - IX_STATUS qStatus = IX_SUCCESS; - - /* - * We have reached a low threshold on one of the Rx Free Qs - */ - - /*note that due to the fact that we are working off an Empty threshold, this callback - need only write a single entry to the Rx Free queue in order to re-arm the notification - */ - - RX_STATS_INC(portId,rxFreeLowCallback); - - /* - * Get buffers from approprite S/W Rx freeBufferList Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - /* - * Turn off Q callback notification for Q in Question. - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - return; - } - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - /* - * Load the H/W Q with buffers from the s/w Q. - */ - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * And endianess converted if required. - */ - if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - } - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - break; - } - } - while (--maxQWritesToPerform); - } -} -/** - * @fn Tx queue low event handler - * - */ -void -ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK; - IX_STATUS qStatus = IX_SUCCESS; - IxEthAccTxPriority highestPriority; - - - /* - * We have reached a low threshold on the Tx Q, and are being asked to - * supply a buffer for transmission from our S/W TX queues - */ - TX_STATS_INC(portId,txLowThreshCallback); - - /* - * Get buffers from approprite Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * and endianess already sone if required. - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) == - IX_ETH_ACC_FAIL) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId)); - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - - return; - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS) - { - /* nothing left in the sw queue or the hw queues are - * full. There is no point to continue to drain the - * sw queues - */ - return; - } - } - } - while (--maxQWritesToPerform); -} - -/** - * @brief TxDone event handler - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ - -void -ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - UINT32 qEntry; - UINT32 *qEntryPtr; - UINT32 txDoneQReadStatus; - UINT32 portId; - UINT32 npeId; - - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra entyry (which is zeroed by the compiler), so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication that Tx frames have been transmitted from the NPE. - */ - - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter); - - do{ - qEntryPtr = txDoneQEntry; - txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW - && (txDoneQReadStatus != IX_SUCCESS)) - { - /*major error*/ - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: %u\n", - (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - qEntry = *qEntryPtr; - - while(qEntry != 0) - { - mbufPtr = ixEthAccEntryFromQConvert(qEntry, - IX_ETHNPE_QM_Q_TXENET_ADDR_MASK); - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* endianness conversions and stats updates */ - ixEthAccMbufFromTxQ(mbufPtr); - - /* - * Get NPE id from message, then convert to portId. - */ - npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - TX_STATS_INC(portId,txDoneClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn( - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag, - mbufPtr); - - /* move to next queue entry */ - qEntry = *(++qEntryPtr); - - } - } while( txDoneQReadStatus == IX_SUCCESS ); -} - -IX_ETH_ACC_PUBLIC -void ixEthAccDataPlaneShow(void) -{ - UINT32 numTx0Entries; - UINT32 numTx1Entries; - UINT32 numTxDoneEntries; - UINT32 numRxEntries; - UINT32 numRxFree0Entries; - UINT32 numRxFree1Entries; - UINT32 portId; -#ifdef __ixp46X - UINT32 numTx2Entries; - UINT32 numRxFree2Entries; -#endif -#ifndef NDEBUG - UINT32 priority; - UINT32 numBuffersInRx=0; - UINT32 numBuffersInTx=0; - UINT32 numBuffersInSwQ=0; - UINT32 totalBuffers=0; - UINT32 rxFreeCallbackCounter = 0; - UINT32 txCallbackCounter = 0; -#endif - UINT32 key; - - /* snapshot of stats */ - IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccDataPlaneStats stats; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - /* get a reliable snapshot */ - key = ixOsalIrqLock(); - - numTx0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries); - numTx1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries); - numTxDoneEntries = 0; - ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries); - numRxEntries = 0; - ixEthAccQMgrRxQEntryGet(&numRxEntries); - numRxFree0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries); - numRxFree1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries); - -#ifdef __ixp46X - numTx2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries); - numRxFree2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries); -#endif - - for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - memcpy(&tx[portId], - &ixEthAccPortData[portId].ixEthAccTxData.stats, - sizeof(tx[portId])); - memcpy(&rx[portId], - &ixEthAccPortData[portId].ixEthAccRxData.stats, - sizeof(rx[portId])); - } - memcpy(&stats, &ixEthAccDataStats, sizeof(stats)); - - ixOsalIrqUnlock(key); - -#ifdef NDEBUG - printf("Detailed statistics collection not supported in this load\n"); -#endif - - /* print snapshot */ - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - } - - printf("PORT %u --------------------------------\n", - portId); -#ifndef NDEBUG - printf("Tx Done Frames : %u\n", - tx[portId].txDoneClientCallback + - tx[portId].txDoneSwQDuringDisable + - tx[portId].txDoneDuringDisable); - printf("Tx Frames : %u\n", - tx[portId].txQOK + tx[portId].txQDelayed); - printf("Tx H/W Q Added OK : %u\n", - tx[portId].txQOK); - printf("Tx H/W Q Delayed : %u\n", - tx[portId].txQDelayed); - printf("Tx From S/W Q Added OK : %u\n", - tx[portId].txFromSwQOK); - printf("Tx From S/W Q Delayed : %u\n", - tx[portId].txFromSwQDelayed); - printf("Tx Overflow : %u\n", - tx[portId].txOverflow); - printf("Tx Mutual Lock : %u\n", - tx[portId].txLock); - printf("Tx Late Ntf Enabled : %u\n", - tx[portId].txLateNotificationEnabled); - printf("Tx Low Thresh CB : %u\n", - tx[portId].txLowThreshCallback); - printf("Tx Done from H/W Q (Disable) : %u\n", - tx[portId].txDoneDuringDisable); - printf("Tx Done from S/W Q (Disable) : %u\n", - tx[portId].txDoneSwQDuringDisable); - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (tx[portId].txPriority[priority]) - { - printf("Tx Priority %u : %u\n", - priority, - tx[portId].txPriority[priority]); - } - } -#endif - printf("Tx unexpected errors : %u (should be 0)\n", - tx[portId].txUnexpectedError); - -#ifndef NDEBUG - printf("Rx Frames : %u\n", - rx[portId].rxFrameClientCallback + - rx[portId].rxSwQDuringDisable+ - rx[portId].rxDuringDisable); - printf("Rx Free Replenish : %u\n", - rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed); - printf("Rx Free H/W Q Added OK : %u\n", - rx[portId].rxFreeRepOK); - printf("Rx Free H/W Q Delayed : %u\n", - rx[portId].rxFreeRepDelayed); - printf("Rx Free From S/W Q Added OK : %u\n", - rx[portId].rxFreeRepFromSwQOK); - printf("Rx Free From S/W Q Delayed : %u\n", - rx[portId].rxFreeRepFromSwQDelayed); - printf("Rx Free Overflow : %u\n", - rx[portId].rxFreeOverflow); - printf("Rx Free Mutual Lock : %u\n", - rx[portId].rxFreeLock); - printf("Rx Free Late Ntf Enabled : %u\n", - rx[portId].rxFreeLateNotificationEnabled); - printf("Rx Free Low CB : %u\n", - rx[portId].rxFreeLowCallback); - printf("Rx From H/W Q (Disable) : %u\n", - rx[portId].rxDuringDisable); - printf("Rx From S/W Q (Disable) : %u\n", - rx[portId].rxSwQDuringDisable); - printf("Rx unlearned Mac Address : %u\n", - rx[portId].rxUnlearnedMacAddress); - printf("Rx Filtered (Rx => RxFree) : %u\n", - rx[portId].rxFiltered); - - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (rx[portId].rxPriority[priority]) - { - printf("Rx Priority %u : %u\n", - priority, - rx[portId].rxPriority[priority]); - } - } -#endif - printf("Rx unexpected errors : %u (should be 0)\n", - rx[portId].rxUnexpectedError); - -#ifndef NDEBUG - numBuffersInTx = tx[portId].txQOK + - tx[portId].txQDelayed - - tx[portId].txDoneClientCallback - - tx[portId].txDoneSwQDuringDisable - - tx[portId].txDoneDuringDisable; - - printf("# Tx Buffers currently for transmission : %u\n", - numBuffersInTx); - - numBuffersInRx = rx[portId].rxFreeRepOK + - rx[portId].rxFreeRepDelayed - - rx[portId].rxFrameClientCallback - - rx[portId].rxSwQDuringDisable - - rx[portId].rxDuringDisable; - - printf("# Rx Buffers currently for reception : %u\n", - numBuffersInRx); - - totalBuffers += numBuffersInRx + numBuffersInTx; -#endif - } - - printf("---------------------------------------\n"); - -#ifndef NDEBUG - printf("\n"); - printf("Mbufs :\n"); - printf("Tx Unchained mbufs : %u\n", - stats.unchainedTxMBufs); - printf("Tx Chained bufs : %u\n", - stats.chainedTxMBufs); - printf("TxDone Unchained mbufs : %u\n", - stats.unchainedTxDoneMBufs); - printf("TxDone Chained bufs : %u\n", - stats.chainedTxDoneMBufs); - printf("RxFree Unchained mbufs : %u\n", - stats.unchainedRxFreeMBufs); - printf("RxFree Chained bufs : %u\n", - stats.chainedRxFreeMBufs); - printf("Rx Unchained mbufs : %u\n", - stats.unchainedRxMBufs); - printf("Rx Chained bufs : %u\n", - stats.chainedRxMBufs); - - printf("\n"); - printf("Software queue usage :\n"); - printf("Buffers added to S/W Q : %u\n", - stats.addToSwQ); - printf("Buffers removed from S/W Q : %u\n", - stats.removeFromSwQ); - - printf("\n"); - printf("Hardware queues callbacks :\n"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxFreeCallbackCounter += rx[portId].rxFreeLowCallback; - txCallbackCounter += tx[portId].txLowThreshCallback; - } - printf("Tx Done QM Callback invoked : %u\n", - stats.txDoneCallbackCounter); - printf("Tx QM Callback invoked : %u\n", - txCallbackCounter); - printf("Rx QM Callback invoked : %u\n", - stats.rxCallbackCounter); - printf("Rx QM Callback burst read : %u\n", - stats.rxCallbackBurstRead); - printf("Rx Free QM Callback invoked : %u\n", - rxFreeCallbackCounter); -#endif - printf("Unexpected errors in CB : %u (should be 0)\n", - stats.unexpectedError); - printf("\n"); - - printf("Hardware queues levels :\n"); - printf("Transmit Port 1 Q : %u \n",numTx0Entries); - printf("Transmit Port 2 Q : %u \n",numTx1Entries); -#ifdef __ixp46X - printf("Transmit Port 3 Q : %u \n",numTx2Entries); -#endif - printf("Transmit Done Q : %u \n",numTxDoneEntries); - printf("Receive Q : %u \n",numRxEntries); - printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries); - printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries); -#ifdef __ixp46X - printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries); -#endif - -#ifndef NDEBUG - printf("\n"); - printf("# Total Buffers accounted for : %u\n", - totalBuffers); - - numBuffersInSwQ = ixEthAccDataStats.addToSwQ - - ixEthAccDataStats.removeFromSwQ; - - printf(" Buffers in S/W Qs : %u\n", - numBuffersInSwQ); - printf(" Buffers in H/W Qs or NPEs : %u\n", - totalBuffers - numBuffersInSwQ); -#endif - - printf("Rx QoS Discipline : %s\n", - (ixEthAccDataInfo.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - printf("Tx QoS Discipline port %u : %s\n", - portId, - (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - } - printf("\n"); -} - - - - - diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c deleted file mode 100644 index 65113448d2..0000000000 --- a/drivers/net/npe/IxEthAccMac.c +++ /dev/null @@ -1,2617 +0,0 @@ -/** - * @file IxEthAccMac.c - * - * @author Intel Corporation - * @date - * - * @brief MAC control functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMh.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxEthDBPortDefs.h" -#include "IxEthNpe.h" -#include "IxEthAcc.h" -#include "IxEthAccDataPlane_p.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" - -/* Maximum number of retries during ixEthAccPortDisable, which - * is approximately 10 seconds -*/ -#define IX_ETH_ACC_MAX_RETRY 500 - -/* Maximum number of retries during ixEthAccPortDisable when expecting - * timeout - */ -#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5 - -#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \ - do \ - { \ - if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \ - { \ - return IX_ETH_ACC_INVALID_PORT; \ - } \ - } while(0) - -PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/*Forward function declarations*/ -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableTxDone (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId); - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE void -ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId); - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2); - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m); - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId); - -IxEthAccStatus -ixEthAccMacMemInit(void) -{ - ixEthAccMacBase[IX_ETH_PORT_1] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, - IX_OSAL_IXP400_ETHA_MAP_SIZE); - ixEthAccMacBase[IX_ETH_PORT_2] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE, - IX_OSAL_IXP400_ETHB_MAP_SIZE); -#ifdef __ixp46X - ixEthAccMacBase[IX_ETH_PORT_3] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE, - IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE); - if (ixEthAccMacBase[IX_ETH_PORT_3] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (ixEthAccMacBase[IX_ETH_PORT_1] == 0 - || ixEthAccMacBase[IX_ETH_PORT_2] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMacUnload(void) -{ - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]); - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]); -#ifdef __ixp46X - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]); - ixEthAccMacBase[IX_ETH_PORT_3] = 0; -#endif - ixEthAccMacBase[IX_ETH_PORT_2] = 0; - ixEthAccMacBase[IX_ETH_PORT_1] = 0; -} - -IxEthAccStatus -ixEthAccPortEnablePriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL) - { - /* TxDone callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL) - && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL)) - { - /* Receive callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if(!ixEthAccMacState[portId].initDone) - { - printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId); - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing*/ - if (ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* enable ethernet database for this port */ - if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS) - { - printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId); - return IX_ETH_ACC_FAIL; - } -#endif - - /* set the MAC core registers */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL2, - IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RANDOM_SEED, - IX_ETH_ACC_RANDOM_SEED_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_EMPTY, - IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_FULL, - IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_DEFER, - IX_ETH_ACC_MAC_TX_DEFER_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_1, - IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_2, - IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_SLOT_TIME, - IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_BUF_SIZE_TX, - IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - IX_ETH_ACC_TX_CNTRL1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - IX_ETH_ACC_RX_CNTRL1_DEFAULT); - - /* set the global state */ - ixEthAccMacState[portId].portDisableState = ACTIVE; - ixEthAccMacState[portId].enabled = true; - - /* rewrite the setup (including mac filtering) depending - * on current options - */ - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* - * PortDisable local variables. They contain the intermediate steps - * while the port is being disabled and the buffers being drained out - * of the NPE. - */ -typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); -static IxEthAccPortRxCallback -ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortMultiBufferRxCallback -ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortDisableRx -ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static IxEthAccPortTxDoneCallback -ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static UINT32 -ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/* - * PortDisable private callbacks functions. They handle the user - * traffic, and the special buffers (one for tx, one for rx) used - * in portDisable. - */ -PRIVATE void -ixEthAccPortDisableTxDone(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - /* check for the special mbuf used in portDisable */ - if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr) - { - *txState = TRANSMIT_DONE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* call client TxDone function */ - ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf); - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - /* transmit the special buffer again if it is transmitted - * and update the txState - * This section is protected because the portDisable context - * run an identical code, so the system keeps transmitting at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*txState == TRANSMIT_DONE) - { - IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr; - *txState = TRANSMIT; - status = ixEthAccPortTxFrameSubmit(portId, - mbufTxPtr, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableTxDone(cbTag, mbuf); - - /* try to transmit the buffer used in portDisable - * if seen in TxDone - */ - ixEthAccPortDisableTryTransmit(portId); -} - -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - IX_OSAL_MBUF *mNextPtr; - - while (mBufPtr) - { - mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL; - - /* check for the special mbuf used in portDisable */ - if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr) - { - *rxState = RECEIVE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* reset the received payload length during portDisable */ - IX_OSAL_MBUF_MLEN(mBufPtr) = 0; - IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0; - - if (useMultiBufferCallback) - { - /* call the user callback with one unchained - * buffer, without payload. A small array is built - * to be used as a parameter (the user callback expects - * to receive an array ended by a NULL pointer. - */ - IX_OSAL_MBUF *mBufPtrArray[2]; - - mBufPtrArray[0] = mBufPtr; - mBufPtrArray[1] = NULL; - ixEthAccPortDisableMultiBufferFn[portId]( - ixEthAccPortDisableMultiBufferCbTag[portId], - mBufPtrArray); - } - else - { - /* call the user callback with a unchained - * buffer, without payload and the destination port is - * unknown. - */ - ixEthAccPortDisableFn[portId]( - ixEthAccPortDisableCbTag[portId], - mBufPtr, - IX_ETH_DB_UNKNOWN_PORT /* port not found */); - } - } - - mBufPtr = mNextPtr; - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - /* replenish with the special buffer again if it is received - * and update the rxState - * This section is protected because the portDisable context - * run an identical code, so the system keeps replenishing at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*rxState == RECEIVE) - { - IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr; - *rxState = REPLENISH; - IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback); - - /* try to replenish with the buffer used in portDisable - * if seen in Rx - */ - ixEthAccPortDisableTryReplenish(portId); -} - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the portDisable receive callback */ - (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false); -} - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - while (*mBufPtr) - { - /* call the portDisable receive callback with one buffer at a time */ - (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true); - } -} - -IxEthAccStatus -ixEthAccPortDisablePriv(IxEthAccPortId portId) -{ - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - int key; - int retry, retryTimeout; - volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing */ - if (!ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - - *state = DISABLED; - - /* disable MAC receive first */ - ixEthAccPortRxDisablePriv(portId); - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* disable ethernet database for this port - It is done now to avoid - * issuing ELT maintenance after requesting 'port disable' in an NPE - */ - if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0); - } -#endif - - /* enter the critical section */ - key = ixOsalIrqLock(); - - /* swap the Rx and TxDone callbacks */ - ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn; - ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn; - ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag; - ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag; - ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn; - ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag; - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - - /* register temporary callbacks */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId; - - /* initialise the Rx state and Tx states */ - *txState = TRANSMIT_DONE; - *rxState = RECEIVE; - - /* exit the critical section */ - ixOsalIrqUnlock(key); - - /* enable a NPE loopback */ - if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - retry = 0; - - /* Step 1 : Drain Tx traffic and TxDone queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * - * (the receive callback keeps replenishing, so once we see - * the special Tx buffer, we can be sure that Tx drain is complete) - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* Step 2 : Drain Rx traffic, RxFree and Rx queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * (the transmit callback keeps transmitting, and when we see - * the special Rx buffer, we can be sure that rxFree drain - * is complete) - * - * The nested loop helps to retry if the user was keeping - * replenishing or transmitting during portDisable. - * - * The 2 nested loops ensure more retries if user traffic is - * seen during portDisable : the user should not replenish - * or transmit while portDisable is running. However, because of - * the queueing possibilities in ethAcc dataplane, it is possible - * that a lot of traffic is left in the queues (e.g. when - * transmitting over a low speed link) and therefore, more - * retries are allowed to help flushing the buffers out. - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDoneAndSubmit; - - do - { - do - { - ixEthAccPortDisableUserBufferCount[portId] = 0; - - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((ixEthAccPortDisableUserBufferCount[portId] != 0) - || (*rxState == REPLENISH))); - - /* After the first iteration, change the receive callbacks, - * to process only 1 buffer at a time - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - /* repeat the whole process while user traffic is seen in TxDone - * - * The conditions to stop the loop are - * - Xscale has both Rx and Tx special buffers - * (txState = transmit, rxState = receive) - * - any error in txSubmit or rxReplenish - * - no user traffic seen - * - an excessive amount of retries - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* check the loop exit conditions. The NPE should not hold - * the special buffers. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - /* Step 3 : Replenish without transmitting until a timeout - * occurs, in order to drain the internal NPE fifos - * - * we can expect a few frames srill held - * in the NPE. - * - * The 2 nested loops take care about the NPE dropping traffic - * (including loopback traffic) when the Rx queue is full. - * - * The timeout value is very conservative - * since the loopback used keeps replenishhing. - * - */ - do - { - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortDisableUserBufferCount[portId] = 0; - retryTimeout = 0; - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - - /* Step 4 : Transmit once. Stop replenish - * - * After the Rx timeout, we are sure that the NPE does not - * hold any frame in its internal NPE fifos. - * - * At this point, the NPE still holds the last rxFree buffer. - * By transmitting a single frame, this should unblock the - * last rxFree buffer. This code just transmit once and - * wait for both frames seen in TxDone and in rxFree. - * - */ - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - status = ixEthAccPortDisableTryTransmit(portId); - - /* the NPE should immediatelyt release - * the last Rx buffer and the last transmitted buffer - * unless the last Tx frame was dropped (rx queue full) - */ - if (status == IX_ETH_ACC_SUCCESS) - { - retryTimeout = 0; - do - { - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - while ((*rxState == REPLENISH) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - } - - /* the NPE may have dropped the traffic because of Rx - * queue being full. This code ensures that the last - * Tx and Rx frames are both received. - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((*txState == TRANSMIT) - || (*rxState == REPLENISH) - || (ixEthAccPortDisableUserBufferCount[portId] != 0))); - - /* Step 5 : check the final states : the NPE has - * no buffer left, nor in Tx , nor in Rx directions. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* now all the buffers are drained, disable NPE loopback - * This is done regardless of the logic to drain the queues and - * the internal buffers held by the NPE. - */ - if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* disable MAC Tx and Rx services */ - ixEthAccMacState[portId].enabled = false; - ixEthAccMacStateUpdate(portId); - - /* restore the Rx and TxDone callbacks (within a critical section) */ - key = ixOsalIrqLock(); - - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId]; - - ixOsalIrqUnlock(key); - - /* the MAC core rx/tx disable may left the MAC hardware in an - * unpredictable state. A hw reset is executed before resetting - * all the MAC parameters to a known value. - */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return status; -} - -IxEthAccStatus -ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - *enabled = ixEthAccMacState[portId].enabled; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMacResetPriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackEnable(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN); - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n", - (UINT32) portId, 0, 0, 0, 0, 0); - - return; - } -#endif - - /* unlock message reception mutex */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock); -} - -IxEthAccStatus -ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* enable NPE loopback (lsb of the message contains the value 1) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL) - | 0x01; - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackDisable(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*disable MAC loopabck */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* disable NPE loopback (lsb of the message contains the value 0) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL); - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*set bit 5 of Rx control 1 - enable address filtering*/ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = false; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* - * Set bit 5 of Rx control 1 - We enable address filtering even in - * promiscuous mode because we want the MAC to set the appropriate - * bits in m_flags which doesn't happen if we turn off filtering. - */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ) - { - /* This is a multicast/broadcast address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] == 0 && - macAddr->macAddress[1] == 0 && - macAddr->macAddress[2] == 0 && - macAddr->macAddress[3] == 0 && - macAddr->macAddress[4] == 0 && - macAddr->macAddress[5] == 0 ) - { - /* This is an invalid mac address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* update the MAC address in the ethernet database */ - if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } -#endif - - /*Set the Unicast MAC to the specified value*/ - for(i=0;imacAddress[i]); - } - ixEthAccMacState[portId].initDone = true; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Unicast MAC from h/w - for the specified port*/ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */ - for(i=0;imacAddress[i] = 0; - } - return IX_ETH_ACC_SUCCESS ; - } - - if(!ixEthAccMacState[portId].initDone) - { - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - /* Check that this is a multicast address */ - if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT)) - { - return IX_ETH_ACC_FAIL; - } - - /* We don't add the Broadcast address */ - if(ixEthAccMacEqual(&broadcastAddr, macAddr)) - { - return IX_ETH_ACC_FAIL; - } - - for (i = 0; - i= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES) - { - return IX_ETH_ACC_FAIL; - } - - /*First add the address to the multicast table for the - specified port*/ - i=ixEthAccMacState[portId].mcastAddrIndex; - - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i], - &macAddr->macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - /*Increment the index into the table, this must be done here - as MulticastAddressSet below needs to know about the latest - entry. - */ - ixEthAccMacState[portId].mcastAddrIndex++; - - /*Then calculate the new value to be written to the address and - address mask registers*/ - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId) -{ - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* remove all entries from the database and - * insert a multicast entry - */ - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0], - &mcastMacAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - ixEthAccMacState[portId].mcastAddrIndex = 1; - ixEthAccMacState[portId].joinAll = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - /* Remove this mac address from the mask for the specified port - * we copy down all entries above the blanked entry, and - * decrement the index - */ - i=0; - - while(i= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock); - -} - -PRIVATE void -ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats) -{ - /* endianness conversion */ - - /* Rx stats */ - retStats->dot3StatsAlignmentErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors); - retStats->dot3StatsFCSErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors); - retStats->dot3StatsInternalMacReceiveErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors); - retStats->RxOverrunDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards); - retStats->RxLearnedEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards); - retStats->RxLargeFramesDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards); - retStats->RxSTPBlockedDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards); - retStats->RxVLANTypeFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards); - retStats->RxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards); - retStats->RxInvalidSourceDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards); - retStats->RxBlackListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards); - retStats->RxWhiteListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards); - retStats->RxUnderflowEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards); - - /* Tx stats */ - retStats->dot3StatsSingleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames); - retStats->dot3StatsMultipleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames); - retStats->dot3StatsDeferredTransmissions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions); - retStats->dot3StatsLateCollisions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions); - retStats->dot3StatsExcessiveCollsions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions); - retStats->dot3StatsInternalMacTransmitErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors); - retStats->dot3StatsCarrierSenseErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors); - retStats->TxLargeFrameDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards); - retStats->TxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards); -} - -IxEthAccStatus -ixEthAccMibIIStatsGet (IxEthAccPortId portId, - IxEthEthObjStats *retStats ) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get operation - at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_GETSTATS, - ixEthAccMacNpeStatsMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - printf("EthAcc: (Mac) StatsGet failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to - this request - we need this mutex in order to ensure - that the return from this function is synchronous */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* Permit other tasks to perform MIB statistics Get operation */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixEthAccMibIIStatsEndianConvert (retStats); - - return IX_ETH_ACC_SUCCESS; -} - - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get & reset call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock); - -} - - - -IxEthAccStatus -ixEthAccMibIIStatsGetClear (IxEthAccPortId portId, - IxEthEthObjStats *retStats) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get-Reset operation at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_RESETSTATS, - ixEthAccMacNpeStatsResetMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to this request */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* permit other tasks to get and reset MIB stats*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixEthAccMibIIStatsEndianConvert(retStats); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccMibIIStatsClear (IxEthAccPortId portId) -{ - static IxEthEthObjStats retStats; - IxEthAccStatus status; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - /* there is no reset operation without a corresponding Get */ - status = ixEthAccMibIIStatsGetClear(portId, &retStats); - - return status; -} - -/* Initialize the ethernet MAC settings */ -IxEthAccStatus -ixEthAccMacInit(IxEthAccPortId portId) -{ - IX_OSAL_MBUF_POOL* portDisablePool; - UINT8 *data; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if(ixEthAccMacState[portId].macInitialised == false) - { - ixEthAccMacState[portId].fullDuplex = true; - ixEthAccMacState[portId].rxFCSAppend = true; - ixEthAccMacState[portId].txFCSAppend = true; - ixEthAccMacState[portId].txPADAppend = true; - ixEthAccMacState[portId].enabled = false; - ixEthAccMacState[portId].promiscuous = true; - ixEthAccMacState[portId].joinAll = false; - ixEthAccMacState[portId].initDone = false; - ixEthAccMacState[portId].macInitialised = true; - - /* initialize MIB stats mutexes */ - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock); - - ixEthAccMacState[portId].portDisableRxMbufPtr = NULL; - ixEthAccMacState[portId].portDisableTxMbufPtr = NULL; - - portDisablePool = IX_OSAL_MBUF_POOL_INIT(2, - IX_ETHACC_RX_MBUF_MIN_SIZE, - "portDisable Pool"); - - IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool"); - - ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL, - "Pool allocation failed"); - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL, - "Pool allocation failed"); - /* fill the payload of the Rx mbuf used in portDisable */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - - memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr), - 0xAA, - IX_ETHACC_RX_MBUF_MIN_SIZE); - - /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - - data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr); - memset(data, 0xBB, 64); - data[0] = 0x00; /* unicast destination MAC address */ - data[6] = 0x00; /* unicast source MAC address */ - data[12] = 0x08; /* typelength : IP frame */ - data[13] = 0x00; /* typelength : IP frame */ - - IX_OSAL_CACHE_FLUSH(data, 64); - } - - IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* PRIVATE Functions*/ - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId) -{ - UINT32 regval; - - if ( ixEthAccMacState[portId].enabled == false ) - { - /* Just disable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN); - } - - if(ixEthAccMacState[portId].fullDuplex) - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX); - } - else - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX); - } - - if(ixEthAccMacState[portId].rxFCSAppend) - { - ixEthAccPortRxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortRxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txFCSAppend) - { - ixEthAccPortTxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txPADAppend) - { - ixEthAccPortTxFrameAppendPaddingEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendPaddingDisablePriv (portId); - } - - if(ixEthAccMacState[portId].promiscuous) - { - ixEthAccPortPromiscuousModeSetPriv(portId); - } - else - { - ixEthAccPortPromiscuousModeClearPriv(portId); - } - - if ( ixEthAccMacState[portId].enabled == true ) - { - /* Enable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - } -} - - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2) -{ - UINT32 i; - for(i=0;imacAddress[i] != macAddr2->macAddress[i]) - { - return false; - } - } - return true; -} - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m) -{ - printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", - m->macAddress[0], m->macAddress[1], - m->macAddress[2], m->macAddress[3], - m->macAddress[4], m->macAddress[5]); -} - -/* Set the multicast address and address mask registers - * - * A bit in the address mask register must be set if - * all multicast addresses always have that bit set, or if - * all multicast addresses always have that bit cleared. - * - * A bit in the address register must be set if all multicast - * addresses have that bit set, otherwise, it should be cleared - */ - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId) -{ - UINT32 i; - UINT32 j; - IxEthAccMacAddr addressMask; - IxEthAccMacAddr address; - IxEthAccMacAddr alwaysClearBits; - IxEthAccMacAddr alwaysSetBits; - - /* calculate alwaysClearBits and alwaysSetBits: - * alwaysClearBits is calculated by ORing all - * multicast addresses, those bits that are always - * clear are clear in the result - * - * alwaysSetBits is calculated by ANDing all - * multicast addresses, those bits that are always set - * are set in the result - */ - - if (ixEthAccMacState[portId].promiscuous == true) - { - /* Promiscuous Mode is set, and filtering - * allow all packets, and enable the mcast and - * bcast detection. - */ - memset(&addressMask.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(&address.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - if(ixEthAccMacState[portId].joinAll == true) - { - /* Join all is set. The mask and address are - * the multicast settings. - */ - IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - memcpy(addressMask.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - memcpy(address.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else if(ixEthAccMacState[portId].mcastAddrIndex == 0) - { - /* No entry in the filtering database, - * Promiscuous Mode is cleared, Broadcast filtering - * is configured. - */ - memset(addressMask.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(address.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - /* build a mask and an address which mix all entreis - * from the list of multicast addresses - */ - memset(alwaysClearBits.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(alwaysSetBits.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - - for(i=0;i> 8) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - (mdioCommand >> 16) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - (mdioCommand >> 24) & 0xff); -} - -PRIVATE void -ixEthAccMdioCmdRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - -PRIVATE void -ixEthAccMdioStatusRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - - -/******************************************************************** - * ixEthAccMiiInit - */ -IxEthAccStatus -ixEthAccMiiInit() -{ - if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE); - - if (miiBaseAddressVirt == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MII I/O mapped memory\n", - 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMiiUnload(void) -{ - IX_OSAL_MEM_UNMAP(miiBaseAddressVirt); - - miiBaseAddressVirt = 0; -} - -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount) -{ - if (retryCount < 1) return IX_ETH_ACC_FAIL; - - ixEthAccMiiRetryCount = retryCount; - ixEthAccMiiAccessTimeout = timeout; - - return IX_ETH_ACC_SUCCESS; -} - -/********************************************************************* - * ixEthAccMiiReadRtn - read a 16 bit value from a PHY - */ -IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - if (value == NULL) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL; - mdioCommand |= IX_ETH_ACC_MII_GO; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - - - if(miiTimeout == 0) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - - ixEthAccMdioStatusRead(®val); - if(regval & IX_ETH_ACC_MII_READ_FAIL) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - *value = regval & 0xffff; - ixOsalMutexUnlock(&miiAccessLock); - return IX_ETH_ACC_SUCCESS; - -} - - -/********************************************************************* - * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY - */ -IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT16 readVal; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - /* ensure that a PHY is present at this address */ - if(ixEthAccMiiReadRtn(phyAddr, - IX_ETH_ACC_MII_CTRL_REG, - &readVal) != IX_ETH_ACC_SUCCESS) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ; - mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - /*The "GO" bit is reset to 0 when the write completes*/ - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - ixOsalMutexUnlock(&miiAccessLock); - if(miiTimeout == 0) - { - return IX_ETH_ACC_FAIL; - } - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Phy query functions - * - */ -IxEthAccStatus -ixEthAccMiiStatsShow (UINT32 phyAddr) -{ - UINT16 regval; - printf("Regisers on PHY at address 0x%x\n", phyAddr); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val); - printf(" Control Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val); - printf(" Status Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val); - printf(" PHY ID1 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val); - printf(" PHY ID2 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val); - printf(" Auto Neg ADS Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val); - printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val); - printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val); - printf(" Auto Neg Next Register : 0x%4.4x\n", regval); - - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Interface query functions - * - */ -IxEthAccStatus -ixEthAccMdioShow (void) -{ - UINT32 regval; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioCmdRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO command register\n"); - printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26); - printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f); - printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f); - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioStatusRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO status register\n"); - printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff); - - return IX_ETH_ACC_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c deleted file mode 100644 index 023cf50248..0000000000 --- a/drivers/net/npe/IxEthDBAPI.c +++ /dev/null @@ -1,424 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxFeatureCtrl.h" - -extern HashTable dbHashtable; -extern IxEthDBPortMap overflowUpdatePortList; -extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, true); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, false); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - ixEthDBReleaseHashNode(searchResult); - - /* build a remove event and place it on the event queue */ - return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID); -} - -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance() -{ - HashIterator iterator; - UINT32 portIndex; - BOOL agingRequired = false; - - /* ports who will have deleted records and therefore will need updating */ - IxEthDBPortMap triggerPorts; - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED != - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - return; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* check if there's at least a port that needs aging */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled) - { - agingRequired = true; - } - } - - if (agingRequired) - { - /* ask each NPE port to write back the database for aging inspection */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE - && ixEthDBPortInfo[portIndex].agingEnabled - && ixEthDBPortInfo[portIndex].enabled) - { - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* unused */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex); - } - else - { - ixEthDBPortInfo[portIndex].agingEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.userControlled = true; - - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n", - portIndex, 0, 0, 0, 0, 0); - - ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES); - } - } - } - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - UINT32 *age = NULL; - BOOL staticEntry = true; - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - age = &descriptor->recordData.filteringData.age; - staticEntry = descriptor->recordData.filteringData.staticEntry; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - age = &descriptor->recordData.filteringVlanData.age; - staticEntry = descriptor->recordData.filteringVlanData.staticEntry; - } - else - { - staticEntry = true; - } - - if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false)) - { - /* manually increment the age if the port has no such capability */ - if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0) - { - *age += (IX_ETH_DB_MAINTENANCE_TIME / 60); - } - - /* age entry if it exceeded the maximum time to live */ - if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60)) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - } -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) -{ - IxEthDBPortMap triggerPorts; - HashIterator iterator; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* check if the user passes some extra bits */ - if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES) - { - return IX_ETH_DB_INVALID_ARG; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS)) - && ((descriptor->type & recordType) != 0)) - { - /* add to trigger if automatic updates are required */ - if (ixEthDBPortUpdateRequired[descriptor->type]) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - } - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - if (((MacDescriptor *) (searchResult->data))->portID == portID) - { - result = IX_ETH_DB_SUCCESS; /* address and port match */ - } - - ixEthDBReleaseHashNode(searchResult); - - return result; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* return the port ID */ - *portID = ((MacDescriptor *) searchResult->data)->portID; - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = false; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = true; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* return the port ID */ - *portID = descriptor->portID; - - /* reset entry age */ - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = 0; - } - else - { - descriptor->recordData.filteringVlanData.age = 0; - } - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - /* force bit at offset 255 to 0 (reserved) */ - dependencyPortMap[31] &= 0xFE; - - COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c deleted file mode 100644 index c265d942e0..0000000000 --- a/drivers/net/npe/IxEthDBAPISupport.c +++ /dev/null @@ -1,651 +0,0 @@ -/** - * @file IxEthDBAPISupport.c - * - * @brief Public API support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include - -#include "IxEthDB_p.h" -#include "IxEthDBMessages_p.h" -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -#ifdef IX_UNIT_TEST - -int dbAccessCounter = 0; -int overflowEvent = 0; - -#endif - -/* - * External declaration - */ -extern HashTable dbHashtable; - -/* - * Internal declaration - */ -IX_ETH_DB_PUBLIC -PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -IX_ETH_DB_PRIVATE -struct -{ - BOOL saved; - IxEthDBPriorityTable priorityTable; - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - IxEthDBFirewallMode firewallMode; - BOOL stpBlocked; - BOOL srcAddressFilterEnabled; - UINT32 maxRxFrameSize; - UINT32 maxTxFrameSize; -} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS]; - -#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518) - -/** - * @brief initializes a port - * - * @param portID ID of the port to be initialized - * - * Note that redundant initializations are silently - * dealt with and do not constitute an error - * - * This function is fully documented in the main - * header file, IxEthDB.h - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID) -{ - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) - { - WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID); - - return; - } - - if (portInfo->initialized) - { - /* redundant */ - return; - } - - /* initialize core fields */ - portInfo->portID = portID; - SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID); - - /* default values */ - portInfo->agingEnabled = false; - portInfo->enabled = false; - portInfo->macAddressUploaded = false; - portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - - /* default update control values */ - portInfo->updateMethod.searchTree = NULL; - portInfo->updateMethod.searchTreePendingWrite = false; - portInfo->updateMethod.treeInitialized = false; - portInfo->updateMethod.updateEnabled = false; - portInfo->updateMethod.userControlled = false; - - /* default WiFi parameters */ - memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid)); - portInfo->frameControlDurationID = 0; - - /* Ethernet NPE-specific initializations */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* update handler */ - portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler; - } - - /* initialize state save */ - ixEthDBPortState[portID].saved = false; - - portInfo->initialized = true; -} - -/** - * @brief enables a port - * - * @param portID ID of the port to enable - * - * This function is fully documented in the main - * header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if enabling was - * accomplished, or a meaningful error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) -{ - IxEthDBPortMap triggerPorts; - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - SET_DEPENDENCY_MAP(triggerPorts, portID); - - /* mark as enabled */ - portInfo->enabled = true; - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID); - - /* must use UnicastAddressSet() before enabling an NPE port */ - return IX_ETH_DB_MAC_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID); - - if (!portInfo->updateMethod.userControlled - && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)) - { - portInfo->updateMethod.updateEnabled = true; - } - - /* if this is first time initialization then we already have - write access to the tree and can AccessRelease directly */ - if (!portInfo->updateMethod.treeInitialized) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID); - - /* create an initial tree and release access into it */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - /* mark tree as being initialized */ - portInfo->updateMethod.treeInitialized = true; - } - } - - if (ixEthDBPortState[portID].saved) - { - /* previous configuration data stored, restore state */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode); - ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled); - } - -#if 0 /* test-only */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter); - ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction); - - ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo); - ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership); - - ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable); - } -#endif - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked); - } - - ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize); - ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize); - - /* discard previous save */ - ixEthDBPortState[portID].saved = false; - } - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief disables a port - * - * @param portID ID of the port to disable - * - * This function is fully documented in the - * main header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if disabling was - * successful or an appropriate error message - * otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) -{ - HashIterator iterator; - IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */ - BOOL result; - PortInfo *portInfo; - IxEthDBFeature learningEnabled; -#if 0 /* test-only */ - IxEthDBPriorityTable classZeroTable; -#endif - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (!portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* save filtering state */ - ixEthDBPortState[portID].firewallMode = portInfo->firewallMode; - ixEthDBPortState[portID].frameFilter = portInfo->frameFilter; - ixEthDBPortState[portID].taggingAction = portInfo->taggingAction; - ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked; - ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled; - ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize; - ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize; - - memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable)); - - ixEthDBPortState[portID].saved = true; - - /* now turn off all EthDB filtering features on the port */ - -#if 0 /* test-only */ - /* VLAN & QoS */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false); - ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH); - - memset(classZeroTable, 0, sizeof (classZeroTable)); - ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable); - } -#endif - - /* STP */ - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false); - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - ixEthDBFirewallTableDownload((IxEthDBPortId) portID); - ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false); - } - - /* Frame size filter */ - ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE); - - /* WiFi */ - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID); - } - - /* save and disable the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - portInfo->featureStatus &= ~IX_ETH_DB_LEARNING; - } - else - { - /* save the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - ixEthDBUpdateLock(); - - /* wipe out current entries for this port */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - /* check if the port match. If so, remove the entry */ - if (descriptor->portID == portID - && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - && !descriptor->recordData.filteringData.staticEntry) - { - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, portID); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (portInfo->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree); - portInfo->updateMethod.searchTree = NULL; - } - - ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD); - } - - /* mark as disabled */ - portInfo->enabled = false; - - /* disable updates unless the user has specifically altered the default behavior */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (!portInfo->updateMethod.userControlled) - { - portInfo->updateMethod.updateEnabled = false; - } - - /* make sure we re-initialize the NPE learning tree when the port is re-enabled */ - portInfo->updateMethod.treeInitialized = false; - } - - ixEthDBUpdateUnlock(); - - /* restore learning feature bit */ - portInfo->featureStatus |= learningEnabled; - - /* if we've removed any records or lost any events make sure to force an update */ - IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts); - - if (!result) - { - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends the updated maximum Tx/Rx frame lengths to the NPE - * - * @param portID ID of the port to update - * - * @return IX_ETH_DB_SUCCESS if the update completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IX_STATUS result; - - FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the port maximum Rx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumRxFrameSize maximum Rx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumTxFrameSize maximum Tx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx and Rx frame sizes - * - * @param portID ID of the port to set the frame size on - * @param maximumFrameSize maximum Tx and Rx frame sizes - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * Note that both the maximum Tx and Rx frame size are set - * to the same value. This function is kept for compatibility - * reasons. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize; - ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the MAC address of an NPE port - * - * @param portID port ID to set the MAC address on - * @param macAddr pointer to the 6-byte MAC address - * - * This function is called by the EthAcc - * ixEthAccUnicastMacAddressSet() and should not be - * manually invoked unless required by special circumstances. - * - * @return IX_ETH_DB_SUCCESS if the operation succeeded - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* use this macro instead CHECK_PORT - as the port doesn't need to be enabled */ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - /* exit if the port is not an Ethernet NPE */ - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* populate message */ - FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress); - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID); - - /* send a SetPortAddress message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - ixEthDBPortInfo[portID].macAddressUploaded = true; - } - - return result; -} diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c deleted file mode 100644 index 3d3050d5ce..0000000000 --- a/drivers/net/npe/IxEthDBCore.c +++ /dev/null @@ -1,439 +0,0 @@ -/** - * @file IxEthDBDBCore.c - * - * @brief Database support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* list of database hashtables */ -IX_ETH_DB_PUBLIC HashTable dbHashtable; -IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1]; -IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -/* private initialization flag */ -IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false; - -/** - * @brief initializes EthDB - * - * This function must be called to initialize the component. - * - * It does the following things: - * - checks the port definition structure - * - scans the capabilities of the NPE images and sets the - * capabilities of the ports accordingly - * - initializes the memory pools internally used in EthDB - * for storing database records and handling data - * - registers automatic update handlers for add and remove - * operations - * - registers hashing match functions, depending on key sets - * - initializes the main database hashtable - * - allocates contiguous memory zones to be used for NPE - * updates - * - registers the serialize methods used to convert data - * into NPE-readable format - * - starts the event processor - * - * Note that this function is documented in the public - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS or an appropriate error if the - * component failed to initialize correctly - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void) -{ - IxEthDBStatus result; - - if (ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* trap an invalid port definition structure */ - IX_ETH_DB_PORTS_ASSERTION; - - /* memory management */ - ixEthDBInitMemoryPools(); - - /* register hashing search methods */ - ixEthDBMatchMethodsRegister(matchFunctions); - - /* register type-based automatic port updates */ - ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired); - - /* register record to key type mappings */ - ixEthDBKeyTypeRegister(ixEthDBKeyType); - - /* hash table */ - ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor); - - /* NPE update zones */ - ixEthDBNPEUpdateAreasInit(); - - /* register record serialization methods */ - ixEthDBRecordSerializeMethodsRegister(); - - /* start the event processor */ - result = ixEthDBEventProcessorInit(); - - /* scan NPE features */ - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBFeatureCapabilityScan(); - } - - ethDBInitializationComplete = true; - - return result; -} - -/** - * @brief prepares EthDB for unloading - * - * This function must be called before removing the - * EthDB component from memory (e.g. doing rmmod in - * Linux) if the component is to be re-initialized again - * without rebooting the platform. - * - * All the EthDB ports must be disabled before this - * function is to be called. Failure to disable all - * the ports will return the IX_ETH_DB_BUSY error. - * - * This function will destroy mutexes, deallocate - * memory and stop the event processor. - * - * Note that this function is fully documented in the - * main component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if de-initialization - * completed successfully or an appropriate error - * message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void) -{ - IxEthDBPortId portIndex; - - if (!ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* check if any ports are enabled */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].enabled) - { - return IX_ETH_DB_BUSY; - } - } - - /* free port resources */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock); - } - - ixEthDBPortInfo[portIndex].initialized = false; - } - - /* shutdown event processor */ - ixEthDBStopLearningFunction(); - - /* deallocate NPE update zones */ - ixEthDBNPEUpdateAreasUnload(); - - ethDBInitializationComplete = false; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a new entry to the Ethernet database - * - * @param newRecordTemplate address of the record template to use - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * Creates a new database entry, populates it with the data - * copied from the given template and adds the record to the - * database hash table. - * It also checks whether the new record type is registered to trigger - * automatic updates; if it is, the update trigger will contain the - * port on which the record insertion was performed, as well as the - * old port in case the addition was a record migration (from one port - * to the other). The caller can use the updateTrigger to trigger - * automatic updates on the ports changed as a result of this addition. - * - * @retval IX_ETH_DB_SUCCESS addition successful - * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool - * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - MacDescriptor *newDescriptor; - IxEthDBPortId originalPortID; - HashNode *node = NULL; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node)); - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (node == NULL) - { - /* not found, create a new one */ - newDescriptor = ixEthDBAllocMacDescriptor(); - - if (newDescriptor == NULL) - { - return IX_ETH_DB_NOMEM; /* no memory */ - } - - /* old port does not exist, avoid unnecessary updates */ - originalPortID = newRecordTemplate->portID; - } - else - { - /* a node with the same key exists, will update node */ - newDescriptor = (MacDescriptor *) node->data; - - /* save original port id */ - originalPortID = newDescriptor->portID; - } - - /* copy/update fields into new record */ - memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr)); - memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData)); - - newDescriptor->type = newRecordTemplate->type; - newDescriptor->portID = newRecordTemplate->portID; - newDescriptor->user = newRecordTemplate->user; - - if (node == NULL) - { - /* new record, insert into hashtable */ - BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result); - - if (result != IX_ETH_DB_SUCCESS) - { - ixEthDBFreeMacDescriptor(newDescriptor); - - return result; /* insertion failed */ - } - } - - if (node != NULL) - { - /* release access */ - ixEthDBReleaseHashNode(node); - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL && - ixEthDBPortUpdateRequired[newRecordTemplate->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID); - - /* check if record has moved, we'll need to update the old port as well */ - if (originalPortID != newDescriptor->portID) - { - JOIN_PORT_TO_MAP(updateTrigger, originalPortID); - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief remove a record from the Ethernet database - * - * @param templateRecord template record used to determine - * what record is to be removed - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * This function will examine the template record it receives - * and attempts to delete a record of the same type and containing - * the same keys as the template record. If deletion is successful - * and the record type is registered for automatic port updates the - * port will also be set in the updateTrigger port map, so that the - * client can perform an update of the port. - * - * @retval IX_ETH_DB_SUCCESS removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found - * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result); - - if (result != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL - &&ixEthDBPortUpdateRequired[templateRecord->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief register record key types - * - * This function registers the appropriate key types, - * depending on record types. - * - * All filtering records use the MAC address as the key. - * WiFi and Firewall records use a compound key consisting - * in both the MAC address and the port ID. - * - * @return the number of registered record types - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType) -{ - /* safety */ - memset(keyType, 0, sizeof (keyType)); - - /* register all known record types */ - keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - - return 5; -} - -/** - * @brief Sets a user-defined field into a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) -{ - HashNode *result = NULL; - - if (macAddr == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - ((MacDescriptor *) result->data)->user = field; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief Retrieves a user-defined field from a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) -{ - HashNode *result = NULL; - - if (macAddr == NULL || field == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - *field = ((MacDescriptor *) result->data)->user; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c deleted file mode 100644 index 5b3be0b6c1..0000000000 --- a/drivers/net/npe/IxEthDBEvents.c +++ /dev/null @@ -1,496 +0,0 @@ -/** - * @file IxEthDBEvents.c - * - * @brief Implementation of the event processor component - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); - -/* data */ -IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore; -IX_ETH_DB_PRIVATE PortEventQueue eventQueue; -IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock; -IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock; - -IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false; -IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false; - -/* imported data */ -extern HashTable dbHashtable; - -/** - * @brief initializes the event processor - * - * Initializes the event processor queue and processing thread. - * Called from ixEthDBInit() DB-subcomponent master init function. - * - * @warning do not call directly - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure) - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEventProcessorInit(void) -{ - if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - - /* start processor loop thread */ - if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief initializes the event queue and the event processor - * - * This function is called by the component initialization - * function, ixEthDBInit(). - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStartLearningFunction(void) -{ - IxOsalThread eventProcessorThread; - IxOsalThreadAttr threadAttr; - - threadAttr.name = "EthDB event thread"; - threadAttr.stackSize = 32 * 1024; /* 32kbytes */ - threadAttr.priority = 128; - - /* reset event queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - RESET_QUEUE(&eventQueue); - - ixOsalMutexUnlock(&eventQueueLock); - - /* init event queue semaphore */ - if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - ixEthDBLearningShutdown = false; - - /* create processor loop thread */ - if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - /* start event processor */ - ixOsalThreadStart(&eventProcessorThread); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief stops the event processor - * - * Stops the event processor and frees the event queue semaphore - * Called by the component de-initialization function, ixEthDBUnload() - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise; - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStopLearningFunction(void) -{ - ixEthDBLearningShutdown = true; - - /* wake up event processing loop to actually process the shutdown event */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief default NPE event processing callback - * - * @param npeID ID of the NPE that generated the event - * @param msg NPE message (encapsulated event) - * - * Creates an event object on the Ethernet event processor queue - * and signals the new event by incrementing the event queue semaphore. - * Events are processed by @ref ixEthDBEventProcessorLoop() which runs - * at user level. - * - * @see ixEthDBEventProcessorLoop() - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - PortEvent *local_event; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0); - - if (CAN_ENQUEUE(&eventQueue)) - { - TEST_FIXTURE_LOCK_EVENT_QUEUE; - - local_event = QUEUE_HEAD(&eventQueue); - - /* create event structure on queue */ - local_event->eventType = NPE_MSG_ID(msg); - local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - - /* update queue */ - PUSH_UPDATE_QUEUE(&eventQueue); - - TEST_FIXTURE_UNLOCK_EVENT_QUEUE; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0); - - /* increment event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - } - else - { - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0); - } -} - -/** - * @brief Ethernet event processor loop - * - * Extracts at most EVENT_PROCESSING_LIMIT batches of events and - * sends them for processing to @ref ixEthDBProcessEvent(). - * Triggers port updates which normally follow learning events. - * - * @warning do not call directly, executes in separate thread - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBEventProcessorLoop(void *unused1) -{ - IxEthDBPortMap triggerPorts; - IxEthDBPortId portIndex; - - ixEthDBEventProcessorRunning = true; - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); - - while (!ixEthDBLearningShutdown) - { - BOOL keepProcessing = true; - UINT32 processedEvents = 0; - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); - - ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER); - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n"); - - if (!ixEthDBLearningShutdown) - { - /* port update handling */ - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - while (keepProcessing) - { - PortEvent local_event; - UINT32 intLockKey; - - /* lock queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - /* lock NPE interrupts */ - intLockKey = ixOsalIrqLock(); - - /* extract event */ - local_event = *(QUEUE_TAIL(&eventQueue)); - - SHIFT_UPDATE_QUEUE(&eventQueue); - - ixOsalIrqUnlock(intLockKey); - - ixOsalMutexUnlock(&eventQueueLock); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType); - - ixEthDBProcessEvent(&local_event, triggerPorts); - - processedEvents++; - - if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ - || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ - { - keepProcessing = false; - } - } - - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - } - - /* turn off automatic updates */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - } - - ixEthDBEventProcessorRunning = false; -} - -/** - * @brief event processor routine - * - * @param event event to be processed - * @param triggerPorts port map accumulating ports to be updated - * - * Processes learning events by synchronizing the database with - * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop(). - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts) -{ - MacDescriptor recordTemplate; - - switch (local_event->eventType) - { - case IX_ETH_DB_ADD_FILTERING_RECORD: - /* add record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD; - recordTemplate.portID = local_event->portID; - recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry; - - ixEthDBAdd(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID); - - break; - - case IX_ETH_DB_REMOVE_FILTERING_RECORD: - /* remove record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD; - - ixEthDBRemove(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID); - - break; - - default: - /* can't handle/not interested in this event type */ - ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType); - - return; - } -} - -/** - * @brief asynchronously adds a filtering record - * by posting an ADD_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the new record - * @param portID port ID of the new record - * @param staticEntry true if record is static, false if dynamic - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - /* fill search fields */ - memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS; - - if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS) - { - /* already have an identical record */ - return IX_ETH_DB_SUCCESS; - } - else - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry); - } -} - -/** - * @brief asynchronously removes a filtering record - * by posting a REMOVE_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the record to remove - * @param portID port ID of the record to remove - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID) -{ - if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR) - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false); - } - else - { - return IX_ETH_DB_NO_SUCH_ADDR; - } -} - -/** - * @brief adds an ADD or REMOVE event to the main event queue - * - * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD - * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a - * record. - * - * @return IX_ETH_DB_SUCCESS if the event was successfully - * sent or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - UINT32 intLockKey; - - /* lock interrupts to protect queue */ - intLockKey = ixOsalIrqLock(); - - if (CAN_ENQUEUE(&eventQueue)) - { - PortEvent *queueEvent = QUEUE_HEAD(&eventQueue); - - /* update fields on the queue */ - memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr)); - - queueEvent->eventType = eventType; - queueEvent->portID = portID; - queueEvent->staticEntry = staticEntry; - - PUSH_UPDATE_QUEUE(&eventQueue); - - /* imcrement event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_SUCCESS; - } - else /* event queue full */ - { - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_BUSY; - } -} - -/** - * @brief Locks learning tree updates and port disable - * - * - * This function locks portUpdateLock single mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateLock(void) -{ - ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER); -} - -/** - * @brief Unlocks learning tree updates and port disable - * - * - * This function unlocks a portUpdateLock mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateUnlock(void) -{ - ixOsalMutexUnlock(&portUpdateLock); -} - diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c deleted file mode 100644 index 1f7624016a..0000000000 --- a/drivers/net/npe/IxEthDBFeatures.c +++ /dev/null @@ -1,638 +0,0 @@ -/** - * @file IxEthDBFeatures.c - * - * @brief Implementation of the EthDB feature control API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeDl.h" -#include "IxEthDBQoS.h" -#include "IxEthDB_p.h" - -/** - * @brief scans the capabilities of the loaded NPE images - * - * This function MUST be called by the ixEthDBInit() function. - * No EthDB features (including learning and filtering) are enabled - * before this function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFeatureCapabilityScan(void) -{ - IxNpeDlImageId imageId, npeAImageId; - IxEthDBPortId portIndex; - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IX_STATUS result; - UINT32 queueIndex; - UINT32 queueStructureIndex; - UINT32 trafficClassDefinitionIndex; - - /* read version of NPE A - required to set the AQM queues for B and C */ - npeAImageId.functionalityId = 0; - ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - IxNpeMhMessage msg; - - portInfo = &ixEthDBPortInfo[portIndex]; - - /* check and bypass if NPE B or C is fused out */ - if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue; - - /* all ports are capable of LEARNING by default */ - portInfo->featureCapability |= IX_ETH_DB_LEARNING; - portInfo->featureStatus |= IX_ETH_DB_LEARNING; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - - if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex); - } - else - { - /* initialize and empty NPE response mutex */ - ixOsalMutexInit(&portInfo->npeAckLock); - ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER); - - /* check NPE response to GetStatus */ - msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24; - msg.data[1] = 0; - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result); - if (result != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n"); - continue; - } - - - if (imageId.functionalityId == 0x00 - || imageId.functionalityId == 0x03 - || imageId.functionalityId == 0x04 - || imageId.functionalityId == 0x80) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - } - else if (imageId.functionalityId == 0x01 - || imageId.functionalityId == 0x81) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - else if (imageId.functionalityId == 0x02 - || imageId.functionalityId == 0x82) - { - portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - - /* reset AQM queues */ - memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments)); - - /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */ - IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h"); - - /* find the traffic class definition index compatible with the current NPE A functionality ID */ - for (trafficClassDefinitionIndex = 0 ; - trafficClassDefinitionIndex < ARRAY_SIZE(ixEthDBTrafficClassDefinitions); - trafficClassDefinitionIndex++) - { - if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId) - { - /* found it */ - break; - } - } - - /* select the default case if we went over the array boundary */ - if (trafficClassDefinitionIndex == ARRAY_SIZE(ixEthDBTrafficClassDefinitions)) - { - trafficClassDefinitionIndex = 0; /* the first record is the default case */ - } - - /* select queue assignment structure based on the traffic class configuration index */ - queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX]; - - /* only traffic class 0 is active at initialization time */ - portInfo->ixEthDBTrafficClassCount = 1; - - /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */ - portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus |= IX_ETH_DB_FIREWALL; - portInfo->enabled = true; - -#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* set VLAN initial configuration (permissive) */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */ - { - /* QoS capable */ - portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX]; - - /* set AQM queues */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex]; - } - - /* set default PVID (0) and default traffic class 0 */ - ixEthDBPortVlanTagSet(portIndex, 0); - - /* enable reception of all frames */ - ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES); - - /* clear full VLAN membership */ - ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - - /* clear TTI table - no VLAN tagged frames will be transmitted */ - ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false); - - /* set membership on 0, otherwise no Tx or Rx is working */ - ixEthDBPortVlanMembershipAdd(portIndex, 0); - } - else /* QoS not available in this image */ -#endif /* test-only */ - { - /* initialize traffic class availability (only class 0 is available) */ - portInfo->ixEthDBTrafficClassAvailable = 1; - - /* point all AQM queues to traffic class 0 */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = - ixEthDBQueueAssignments[queueStructureIndex][0]; - } - } - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* download priority mapping table and Rx queue configuration */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable); -#endif - - /* by default we turn off invalid source MAC address filtering */ - ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false); - - /* disable port, VLAN, Firewall feature bits */ - portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL; - portInfo->enabled = false; - - /* enable filtering by default if present */ - if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0) - { - portInfo->featureStatus |= IX_ETH_DB_FILTERING; - } - } - } - } -} - -/** - * @brief returns the capability of a port - * - * @param portID ID of the port - * @param featureSet location to store the port capability in - * - * This function will save the capability set of the given port - * into the given location. Capabilities are bit-ORed, each representing - * a bit of the feature set. - * - * Note that this function is documented in the main component - * public header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_INVALID_PORT if the given port is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) -{ - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - IX_ETH_DB_CHECK_REFERENCE(featureSet); - - *featureSet = ixEthDBPortInfo[portID].featureCapability; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables a port capability - * - * @param portID ID of the port - * @param feature feature to enable or disable - * @param enabled true to enable the selected feature or false to disable it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable) -{ - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IxEthDBVlanSet vlanSet; - IxEthDBStatus status = IX_ETH_DB_SUCCESS; - BOOL portEnabled; - - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - portInfo = &ixEthDBPortInfo[portID]; - portEnabled = portInfo->enabled; - - /* check that only one feature is selected */ - if (!ixEthDBCheckSingleBitValue(feature)) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* port capable of this feature? */ - if ((portInfo->featureCapability & feature) == 0) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* mutual exclusion between learning and WiFi header conversion */ - if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* learning must be enabled before filtering */ - if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* filtering must be disabled before learning */ - if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* redundant enabling or disabling */ - if ((!enable && ((portInfo->featureStatus & feature) == 0)) - || (enable && ((portInfo->featureStatus & feature) != 0))) - { - /* do nothing */ - return IX_ETH_DB_SUCCESS; - } - - /* force port enabled */ - portInfo->enabled = true; - - if (enable) - { - /* turn on enable bit */ - portInfo->featureStatus |= feature; - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* if this is VLAN/QoS set the default priority table */ - if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn on VLAN/QoS (most permissive mode): - - set default 802.1Q priority mapping table, in accordance to the - availability of traffic classes - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - set full VLAN membership list - - set full TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - enable TPID port extraction - */ - - portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable; - - /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */ - memcpy (defaultPriorityTable, - (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1], - sizeof (defaultPriorityTable)); - - /* update priority mapping and AQM queue assignments */ - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* set membership and TTI tables */ - memset (vlanSet, 0xFF, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* enable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, true); - } - } - else if (feature == IX_ETH_DB_FIREWALL) -#endif - { - /* firewall starts in black-list mode unless otherwise configured before * - * note that invalid source MAC address filtering is disabled by default */ - if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST - && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - } - } - - if (status != IX_ETH_DB_SUCCESS) - { - /* checks failed, disable */ - portInfo->featureStatus &= ~feature; - } - } - else - { - /* turn off features */ - if (feature == IX_ETH_DB_FIREWALL) - { - /* turning off the firewall is equivalent to: - - set to black-list mode - - clear all the entries and download the new table - - turn off the invalid source address checking - */ - - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallTableDownload(portID); - } - } - else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION) - { - /* turn off header conversion */ - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBWiFiConversionTableDownload(portID); - } - } -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - else if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn off VLAN/QoS: - - set a priority mapping table with one traffic class - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - clear the VLAN membership list - - clear the TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - disable TPID port extraction - */ - - /* initialize all => traffic class 0 priority mapping table */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - portInfo->ixEthDBTrafficClassCount = 1; - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* clear membership and TTI tables */ - memset (vlanSet, 0, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* disable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, false); - } - } -#endif - - if (status == IX_ETH_DB_SUCCESS) - { - /* checks passed, disable */ - portInfo->featureStatus &= ~feature; - } - } - - /* restore port enabled state */ - portInfo->enabled = portEnabled; - - return status; -} - -/** - * @brief returns the status of a feature - * - * @param portID port ID - * @param present location to store a boolean value indicating - * if the feature is present (true) or not (false) - * @param enabled location to store a booleam value indicating - * if the feature is present (true) or not (false) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_REFERENCE(present); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - portInfo = &ixEthDBPortInfo[portID]; - - *present = (portInfo->featureCapability & feature) != 0; - *enabled = (portInfo->featureStatus & feature) != 0; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief returns the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param type location to store the property type into - * @param value location to store the property value into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(type); - - IX_ETH_DB_CHECK_REFERENCE(value); - - if (feature == IX_ETH_DB_VLAN_QOS) - { - if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY) - { - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY - && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY) - { - UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - - if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_FAIL; - } - - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta]; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief sets the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param value location containing the property value - * - * This function implements a private property intended - * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE - * property (the value is ignored), the availability of traffic classes is - * frozen to whatever traffic class structure is currently in use. - * This means that if VLAN_QOS has been enabled before EthAcc - * initialization then all the defined traffic classes will be available; - * otherwise only one traffic class (0) will be available. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h as not accepting any parameters. The - * current implementation is only intended for the private use of EthAcc. - * - * Also note that once this function is called the effect is irreversible, - * unless EthDB is complete unloaded and re-initialized. - * - * @return IX_ETH_DB_INVALID_ARG (no read-write properties are - * supported in this release) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE)) - { - ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - - return IX_ETH_DB_SUCCESS; - } - - return IX_ETH_DB_INVALID_ARG; -} diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c deleted file mode 100644 index c0ae5624ff..0000000000 --- a/drivers/net/npe/IxEthDBFirewall.c +++ /dev/null @@ -1,242 +0,0 @@ -/** - * @file IxEthDBFirewall.c - * - * @brief Implementation of the firewall API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief updates the NPE firewall operating mode and - * firewall address table - * - * @param portID ID of the port - * @param epDelta initial entry point for binary searches (NPE optimization) - * @param address address of the firewall MAC address table - * - * This function will send a message to the NPE configuring the - * firewall mode (white list or black list), invalid source - * address filtering and downloading a new MAC address database - * to be used for firewall matching. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 mode = 0; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - - mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); - - FILL_SETFIREWALLMODE_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, - mode, - IX_OSAL_MMU_VIRT_TO_PHYS(address)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief configures the firewall white list/black list - * access mode - * - * @param portID ID of the port - * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST - * or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST - && mode != IX_ETH_DB_FIREWALL_BLACK_LIST) - { - return IX_ETH_DB_INVALID_ARG; - } - - ixEthDBPortInfo[portID].firewallMode = mode; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief enables or disables the invalid source MAC address filter - * - * @param portID ID of the port - * @param enable true to enable invalid source MAC address filtering - * or false to disable it - * - * The invalid source MAC address filter will discard, when enabled, - * frames whose source MAC address is a multicast or the broadcast MAC - * address. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief adds a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the new record - * - * This function will add a new firewall record - * on the specified port, using the specified - * MAC address. If the record already exists this - * function will silently return IX_ETH_DB_SUCCESS, - * although no duplicate records are added. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief removes a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * This function will attempt to remove a firewall - * record from the given port, using the specified - * MAC address. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully of an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief downloads the firewall address table to an NPE - * - * @param portID ID of the port - * - * This function will download the firewall address table to - * an NPE port. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - IxEthDBStatus result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE); - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD); - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c deleted file mode 100644 index 9493a5b48b..0000000000 --- a/drivers/net/npe/IxEthDBHashtable.c +++ /dev/null @@ -1,618 +0,0 @@ -/** - * @file ethHash.c - * - * @brief Hashtable implementation - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" -#include "IxEthDBLocks_p.h" - -/** - * @addtogroup EthDB - * - * @{ - */ - -/** - * @brief initializes a hash table object - * - * @param hashTable uninitialized hash table structure - * @param numBuckets number of buckets to use - * @param entryHashFunction hash function used - * to hash entire hash node data block (for adding) - * @param matchFunctions array of match functions, indexed on type, - * used to differentiate records with the same hash value - * @param freeFunction function used to free node data blocks - * - * Initializes the given hash table object. - * - * @internal - */ -void ixEthDBInitHash(HashTable *hashTable, - UINT32 numBuckets, - HashFunction entryHashFunction, - MatchFunction *matchFunctions, - FreeFunction freeFunction) -{ - UINT32 bucketIndex; - UINT32 hashSize = numBuckets * sizeof(HashNode *); - - /* entry hashing, matching and freeing methods */ - hashTable->entryHashFunction = entryHashFunction; - hashTable->matchFunctions = matchFunctions; - hashTable->freeFunction = freeFunction; - - /* buckets */ - hashTable->numBuckets = numBuckets; - - /* set to 0 all buckets */ - memset(hashTable->hashBuckets, 0, hashSize); - - /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/ - for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++) - { - ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]); - } -} - -/** - * @brief adds an entry to the hash table - * - * @param hashTable hash table to add the entry to - * @param entry entry to add - * - * The entry will be hashed using the entry hashing function and added to the - * hash table, unless a locking blockage occurs, in which case the caller - * should retry. - * - * @retval IX_ETH_DB_SUCCESS if adding entry has succeeded - * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool - * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path - * - * @internal - */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry) -{ - UINT32 hashValue = hashTable->entryHashFunction(entry); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *bucket = hashTable->hashBuckets[bucketIndex]; - HashNode *newNode; - - LockStack locks; - - INIT_STACK(&locks); - - /* lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - /* lock insertion element (first in chain), if any */ - if (bucket != NULL) - { - PUSH_LOCK(&locks, &bucket->lock); - } - - /* get new node */ - newNode = ixEthDBAllocHashNode(); - - if (newNode == NULL) - { - /* unlock everything */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_NOMEM; - } - - /* init lock - note that mutexes are unlocked after MutexInit */ - ixOsalFastMutexInit(&newNode->lock); - - /* populate new link */ - newNode->data = entry; - - /* add to bucket */ - newNode->next = bucket; - hashTable->hashBuckets[bucketIndex] = newNode; - - /* unlock bucket and insertion point */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief removes an entry from the hashtable - * - * @param hashTable hash table to remove entry from - * @param keyType type of record key used for matching - * @param reference reference key used to identify the entry - * - * The reference key will be hashed using the key hashing function, - * the entry is searched using the hashed value and then examined - * against the reference entry using the match function. A positive - * match will trigger the deletion of the entry. - * Locking failures are reported and the caller should retry. - * - * @retval IX_ETH_DB_SUCCESS if the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found - * @retval IX_ETH_DB_BUSY if a locking failure occured during the process - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue = hashTable->entryHashFunction(reference); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *node = hashTable->hashBuckets[bucketIndex]; - HashNode *previousNode = NULL; - - LockStack locks; - - INIT_STACK(&locks); - - while (node != NULL) - { - /* try to lock node */ - PUSH_LOCK(&locks, &node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - /* found entry */ - if (node->next != NULL) - { - PUSH_LOCK(&locks, &node->next->lock); - } - - if (previousNode == NULL) - { - /* node is head of chain */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - hashTable->hashBuckets[bucketIndex] = node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - previousNode->next = node->next; - } - - UNROLL_STACK(&locks); - - /* free node */ - hashTable->freeFunction(node->data); - ixEthDBFreeHashNode(node); - - return IX_ETH_DB_SUCCESS; - } - else - { - if (previousNode != NULL) - { - /* unlock previous node */ - SHIFT_STACK(&locks); - } - - /* advance to next element in chain */ - previousNode = node; - node = node->next; - } - } - - UNROLL_STACK(&locks); - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief retrieves an entry from the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * @param searchResult pointer where a reference to the located hash node - * is placed - * - * Searches the entry with the same key as reference and places the - * pointer to the resulting node in searchResult. - * An implicit write access lock is granted after a search, which gives the - * caller the opportunity to modify the entry. - * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode(). - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @warning unless the return value is IX_ETH_DB_SUCCESS the searchResult - * location is NOT modified and therefore using a NULL comparison test when the - * value was not properly initialized would be an error - * - * @internal - */ -IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - *searchResult = node; - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief reports the existence of an entry in the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * - * Searches the entry with the same key as reference. - * No implicit write access lock is granted after a search, hence the - * caller cannot access or modify the entry. The result is only temporary. - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @internal - */ -IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - UNLOCK(&node->lock); - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief releases the write access lock - * - * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry() - * - * @see ixEthDBSearchHashEntry() - * - * @internal - */ -void ixEthDBReleaseHashNode(HashNode *node) -{ - UNLOCK(&node->lock); -} - -/** - * @brief initializes a hash iterator - * - * @param hashTable hash table to be iterated - * @param iterator iterator object - * - * If the initialization is successful the iterator will point to the - * first hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points - * to the first valid table node - * @retval IX_ETH_DB_FAIL if the table is empty - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - iterator->bucketIndex = 0; - iterator->node = NULL; - iterator->previousNode = NULL; - - return ixEthDBIncrementHashIterator(hashTable, iterator); -} - -/** - * @brief releases the write access locks of the iterator nodes - * - * @warning use of this function is required only when the caller terminates an iteration - * before reaching the end of the table - * - * @see ixEthDBInitHashIterator() - * @see ixEthDBIncrementHashIterator() - * - * @param iterator iterator whose node(s) should be unlocked - * - * @internal - */ -void ixEthDBReleaseHashIterator(HashIterator *iterator) -{ - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - } -} - -/** - * @brief incremenents an iterator so that it points to the next valid entry of the table - * (if any) - * - * @param hashTable hash table to iterate - * @param iterator iterator object - * - * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator() - * - * If the increment operation is successful the iterator will point to the - * next hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is re-incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * Is is guaranteed that no other thread can remove or change the iterated entry until - * the iterator is incremented successfully. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points - * to the next valid table node - * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - /* unless iterator is just initialized... */ - if (iterator->node != NULL) - { - /* try next in chain */ - if (iterator->node->next != NULL) - { - TRY_LOCK(&iterator->node->next->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->previousNode = iterator->node; - iterator->node = iterator->node->next; - - return IX_ETH_DB_SUCCESS; - } - else - { - /* last in chain, prepare for next bucket */ - iterator->bucketIndex++; - } - } - - /* try next used bucket */ - for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++) - { - HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]); - HashNode *node = *nodePtr; -#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) && - (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD))) - { - /* preload next cache line (2 cache line ahead) */ - nodePtr += IX_ETHDB_BUCKETPTR_AHEAD; - __asm__ ("pld [%0];\n": : "r" (nodePtr)); - } -#endif - if (node != NULL) - { - TRY_LOCK(&node->lock); - - /* unlock last one or two nodes in the previous chain */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* redirect iterator */ - iterator->previousNode = NULL; - iterator->node = node; - - return IX_ETH_DB_SUCCESS; - } - } - - /* could not advance iterator */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->node = NULL; - } - - return IX_ETH_DB_END; -} - -/** - * @brief removes an entry pointed by an iterator - * - * @param hashTable iterated hash table - * @param iterator iterator object - * - * Removes the entry currently pointed by the iterator and repositions the iterator - * on the next valid entry (if any). Handles locking issues automatically and - * implicitely grants write access lock to the new pointed entry. - * Failures due to concurrent threads having write access locks in the same region - * preserve the state of the database and the iterator object, leaving the caller - * free to retry without loss of access. It is guaranteed that only the thread owning - * the iterator can remove the object pointed by the iterator. - * - * @retval IX_ETH_DB_SUCCESS if removal has succeeded - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - HashIterator nextIteratorPos; - LockStack locks; - - INIT_STACK(&locks); - - /* set initial bucket index for next position */ - nextIteratorPos.bucketIndex = iterator->bucketIndex; - - /* compute iterator position before removing anything and lock ahead */ - if (iterator->node->next != NULL) - { - PUSH_LOCK(&locks, &iterator->node->next->lock); - - /* reposition on the next node in the chain */ - nextIteratorPos.node = iterator->node->next; - nextIteratorPos.previousNode = iterator->previousNode; - } - else - { - /* try next chain - don't know yet if we'll find anything */ - nextIteratorPos.node = NULL; - - /* if we find something it's a chain head */ - nextIteratorPos.previousNode = NULL; - - /* browse up in the buckets to find a non-null chain */ - while (++nextIteratorPos.bucketIndex < hashTable->numBuckets) - { - nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex]; - - if (nextIteratorPos.node != NULL) - { - /* found a non-empty chain, try to lock head */ - PUSH_LOCK(&locks, &nextIteratorPos.node->lock); - - break; - } - } - } - - /* restore links over the to-be-deleted item */ - if (iterator->previousNode == NULL) - { - /* first in chain, lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]); - - hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - iterator->previousNode->next = iterator->node->next; - - /* unlock last remaining node in current chain when moving between chains */ - if (iterator->node->next == NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* delete entry */ - hashTable->freeFunction(iterator->node->data); - ixEthDBFreeHashNode(iterator->node); - - /* reposition iterator */ - *iterator = nextIteratorPos; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @} - */ diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c deleted file mode 100644 index 1080d112de..0000000000 --- a/drivers/net/npe/IxEthDBLearning.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * @file IxEthDBLearning.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/** - * @brief hashes the mac address in a mac descriptor with a XOR function - * - * @param entry pointer to a mac descriptor to be hashed - * - * This function only extracts the mac address and employs ixEthDBKeyXORHash() - * to do the actual hashing. - * Used only to add a whole entry to a hash table, as opposed to searching which - * takes only a key and uses the key hashing directly. - * - * @see ixEthDBKeyXORHash() - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBEntryXORHash(void *entry) -{ - MacDescriptor *descriptor = (MacDescriptor *) entry; - - return ixEthDBKeyXORHash(descriptor->macAddress); -} - -/** - * @brief hashes a mac address - * - * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer) - * to be hashed - * - * Given a 6 bytes MAC address, the hash used is: - * - * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5] - * - * Used by the hash table to search and remove entries based - * solely on their keys (mac addresses). - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBKeyXORHash(void *key) -{ - UINT32 hashValue; - UINT8 *value = (UINT8 *) key; - - hashValue = (value[5] << 8) | value[4]; - hashValue ^= (value[3] << 8) | value[2]; - hashValue ^= (value[1] << 8) | value[0]; - - return hashValue; -} - -/** - * @brief mac descriptor match function - * - * @param reference mac address (typically an IxEthDBMacAddr pointer) structure - * @param entry pointer to a mac descriptor whose key (mac address) is to be - * matched against the reference key - * - * Used by the hash table to retrieve entries. Hashing entries can produce - * collisions, i.e. descriptors with different mac addresses and the same - * hash value, where this function is used to differentiate entries. - * - * @retval true if the entry matches the reference key (equal addresses) - * @retval false if the entry does not match the reference key - * - * @internal - */ -BOOL ixEthDBAddressMatch(void *reference, void *entry) -{ - return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0); -} - -/** - * @brief compares two mac addresses - * - * @param mac1 first mac address to compare - * @param mac2 second mac address to compare - * - * This comparison works in a similar way to strcmp, producing similar results. - * Used to insert values keyed on mac addresses into binary search trees. - * - * @retval -1 if mac1 < mac2 - * @retval 0 if ma1 == mac2 - * @retval 1 if mac1 > mac2 - */ -UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2) -{ - UINT32 local_index; - - for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++) - { - if (mac1[local_index] > mac2[local_index]) - { - return 1; - } - else if (mac1[local_index] < mac2[local_index]) - { - return -1; - } - } - - return 0; -} - diff --git a/drivers/net/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c deleted file mode 100644 index 78fce4bd92..0000000000 --- a/drivers/net/npe/IxEthDBMem.c +++ /dev/null @@ -1,625 +0,0 @@ -/** - * @file IxEthDBDBMem.c - * - * @brief Memory handling routines for the MAC address database - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -IX_ETH_DB_PRIVATE HashNode *nodePool = NULL; -IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL; -IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL; - -IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE]; - -IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock; - -#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); } - -#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); } - -#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); } - -/* private function prototypes */ -IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void); -IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor); - -/** - * @addtogroup EthMemoryManagement - * - * @{ - */ - -/** - * @brief initializes the memory pools used by the ethernet database component - * - * Initializes the hash table node, mac descriptor and mac tree node pools. - * Called at initialization time by @ref ixEthDBInit(). - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBInitMemoryPools(void) -{ - int local_index; - - /* HashNode pool */ - ixOsalMutexInit(&nodePoolLock); - - for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++) - { - HashNode *freeNode = &nodePoolArea[local_index]; - - freeNode->nextFree = nodePool; - nodePool = freeNode; - } - - /* MacDescriptor pool */ - ixOsalMutexInit(&macPoolLock); - - for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++) - { - MacDescriptor *freeDescriptor = &macPoolArea[local_index]; - - freeDescriptor->nextFree = macPool; - macPool = freeDescriptor; - } - - /* MacTreeNode pool */ - ixOsalMutexInit(&treePoolLock); - - for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++) - { - MacTreeNode *freeNode = &treePoolArea[local_index]; - - freeNode->nextFree = treePool; - treePool = freeNode; - } -} - -/** - * @brief allocates a hash node from the pool - * - * Allocates a hash node and resets its value. - * - * @return the allocated hash node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBAllocHashNode(void) -{ - HashNode *allocatedNode = NULL; - - if (nodePool != NULL) - { - LOCK_NODE_POOL; - - allocatedNode = nodePool; - nodePool = nodePool->nextFree; - - UNLOCK_NODE_POOL; - - memset(allocatedNode, 0, sizeof(HashNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a hash node into the pool - * - * @param hashNode node to be freed - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeHashNode(HashNode *hashNode) -{ - if (hashNode != NULL) - { - LOCK_NODE_POOL; - - hashNode->nextFree = nodePool; - nodePool = hashNode; - - UNLOCK_NODE_POOL; - } -} - -/** - * @brief allocates a mac descriptor from the pool - * - * Allocates a mac descriptor and resets its value. - * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor() - * is used, which keeps track of the pointer reference count. - * - * @see ixEthDBAllocMacDescriptor() - * - * @warning this function is not used directly by any other function - * apart from ixEthDBAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacDescriptor* ixEthDBPoolAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = NULL; - - if (macPool != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor = macPool; - macPool = macPool->nextFree; - - UNLOCK_MAC_POOL; - - memset(allocatedDescriptor, 0, sizeof(MacDescriptor)); - } - - return allocatedDescriptor; -} - -/** - * @brief allocates and initializes a mac descriptor smart pointer - * - * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor - * from the pool and initializes its reference count. - * - * @see ixEthDBPoolAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor(); - - if (allocatedDescriptor != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor->refCount++; - - UNLOCK_MAC_POOL; - } - - return allocatedDescriptor; -} - -/** - * @brief frees a mac descriptor back into the pool - * - * @param macDescriptor mac descriptor to be freed - * - * @warning this function is not to be called by anyone but - * ixEthDBFreeMacDescriptor() - * - * @see ixEthDBFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - macDescriptor->nextFree = macPool; - macPool = macDescriptor; - - UNLOCK_MAC_POOL; -} - -/** - * @brief frees or reduces the usage count of a mac descriptor smart pointer - * - * If the reference count reaches 0 (structure is no longer used anywhere) - * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor(). - * - * @see ixEthDBPoolFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - if (macDescriptor != NULL) - { - LOCK_MAC_POOL; - - if (macDescriptor->refCount > 0) - { - macDescriptor->refCount--; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - ixEthDBPoolFreeMacDescriptor(macDescriptor); - } - else - { - UNLOCK_MAC_POOL; - } - } - else - { - UNLOCK_MAC_POOL; - } - } -} - -/** - * @brief clones a mac descriptor smart pointer - * - * @param macDescriptor mac descriptor to clone - * - * Increments the usage count of the smart pointer - * - * @returns the cloned smart pointer - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - return NULL; - } - - macDescriptor->refCount++; - - UNLOCK_MAC_POOL; - - return macDescriptor; -} - -/** - * @brief allocates a mac tree node from the pool - * - * Allocates and initializes a mac tree node from the pool. - * - * @return the allocated mac tree node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBAllocMacTreeNode(void) -{ - MacTreeNode *allocatedNode = NULL; - - if (treePool != NULL) - { - LOCK_TREE_POOL; - - allocatedNode = treePool; - treePool = treePool->nextFree; - - UNLOCK_TREE_POOL; - - memset(allocatedNode, 0, sizeof(MacTreeNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a mac tree node back into the pool - * - * @param macNode mac tree node to be freed - * - * @warning not to be used except from ixEthDBFreeMacTreeNode(). - * - * @see ixEthDBFreeMacTreeNode() - * - * @internal - */ -void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - LOCK_TREE_POOL; - - macNode->nextFree = treePool; - treePool = macNode; - - UNLOCK_TREE_POOL; - } -} - -/** - * @brief frees or reduces the usage count of a mac tree node smart pointer - * - * @param macNode mac tree node to free - * - * Reduces the usage count of the given mac node. If the usage count - * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode->descriptor != NULL) - { - ixEthDBFreeMacDescriptor(macNode->descriptor); - } - - if (macNode->left != NULL) - { - ixEthDBFreeMacTreeNode(macNode->left); - } - - if (macNode->right != NULL) - { - ixEthDBFreeMacTreeNode(macNode->right); - } - - ixEthDBPoolFreeMacTreeNode(macNode); -} - -/** - * @brief clones a mac tree node - * - * @param macNode mac tree node to be cloned - * - * Increments the usage count of the node, its associated descriptor - * and recursively of all its child nodes. - * - * @warning this function is recursive and clones whole trees/subtrees, use only for - * root nodes - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode(); - - if (clonedMacNode != NULL) - { - if (macNode->right != NULL) - { - clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right); - } - - if (macNode->left != NULL) - { - clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left); - } - - if (macNode->descriptor != NULL) - { - clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor); - } - } - - return clonedMacNode; - } - else - { - return NULL; - } -} - -#ifndef NDEBUG -/* Debug statistical functions for memory usage */ - -extern HashTable dbHashtable; -int ixEthDBNumHashElements(void); - -int ixEthDBNumHashElements(void) -{ - UINT32 bucketIndex; - int numElements = 0; - HashTable *hashTable = &dbHashtable; - - for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++) - { - if (hashTable->hashBuckets[bucketIndex] != NULL) - { - HashNode *node = hashTable->hashBuckets[bucketIndex]; - - while (node != NULL) - { - numElements++; - - node = node->next; - } - } - } - - return numElements; -} - -UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree) -{ - if (tree == NULL) - { - return 0; - } - else - { - return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right); - } -} - -int ixEthDBShowMemoryStatus(void) -{ - MacDescriptor *mac; - MacTreeNode *tree; - HashNode *node; - - int macCounter = 0; - int treeCounter = 0; - int nodeCounter = 0; - - int totalTreeUsage = 0; - int totalDescriptorUsage = 0; - int totalCloneDescriptorUsage = 0; - int totalNodeUsage = 0; - - UINT32 portIndex; - - LOCK_NODE_POOL; - LOCK_MAC_POOL; - LOCK_TREE_POOL; - - mac = macPool; - tree = treePool; - node = nodePool; - - while (mac != NULL) - { - macCounter++; - - mac = mac->nextFree; - - if (macCounter > MAC_POOL_SIZE) - { - break; - } - } - - while (tree != NULL) - { - treeCounter++; - - tree = tree->nextFree; - - if (treeCounter > TREE_POOL_SIZE) - { - break; - } - } - - while (node != NULL) - { - nodeCounter++; - - node = node->nextFree; - - if (nodeCounter > NODE_POOL_SIZE) - { - break; - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree); - - totalTreeUsage += treeUsage; - totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */ - } - - totalNodeUsage = ixEthDBNumHashElements(); - totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */ - - UNLOCK_NODE_POOL; - UNLOCK_MAC_POOL; - UNLOCK_TREE_POOL; - - printf("Ethernet database memory usage stats:\n\n"); - - if (macCounter <= MAC_POOL_SIZE) - { - printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE); - } - else - { - printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE); - } - - if (treeCounter <= TREE_POOL_SIZE) - { - printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE); - } - else - { - printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE); - } - - if (nodeCounter <= NODE_POOL_SIZE) - { - printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE); - } - else - { - printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE); - } - - printf("\n"); - printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage); - printf("\tTree node usage : %d entries\n", totalTreeUsage); - printf("\tHash node usage : %d entries\n", totalNodeUsage); - printf("\n"); - - /* search for duplicate nodes in the mac pool */ - { - MacDescriptor *reference = macPool; - - while (reference != NULL) - { - MacDescriptor *comparison = reference->nextFree; - - while (comparison != NULL) - { - if (reference == comparison) - { - printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference); - - return 1; - } - - comparison = comparison->nextFree; - } - - reference = reference->nextFree; - } - } - - printf("No duplicates found in the MAC pool (sanity check ok)\n"); - - return 0; -} - -#endif /* NDEBUG */ - -/** - * @} EthMemoryManagement - */ diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c deleted file mode 100644 index 30e1f61ab9..0000000000 --- a/drivers/net/npe/IxEthDBNPEAdaptor.c +++ /dev/null @@ -1,695 +0,0 @@ -/** - * @file IxEthDBDBNPEAdaptor.c - * - * @brief Routines that read and write learning/search trees in NPE-specific format - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void); - -/* data */ -UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS]; -UINT32 dumpEltSize; - -/* private data */ -IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */ -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; - -/** - * @brief allocates non-cached or contiguous NPE tree update areas for all the ports - * - * This function is called only once at initialization time from - * @ref ixEthDBInit(). - * - * @warning do not call manually - * - * @see ixEthDBInit() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasInit(void) -{ - UINT32 portIndex; - PortUpdateMethod *update; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - update = &ixEthDBPortInfo[portIndex].updateMethod; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE); - update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE); - update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE); - - if (update->npeUpdateZone == NULL - || update->npeGwUpdateZone == NULL - || update->vlanUpdateZone == NULL) - { - ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n"); - } - else - { - memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE); - memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE); - memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE); - } - } - else - { - /* unused */ - update->npeUpdateZone = NULL; - update->npeGwUpdateZone = NULL; - update->vlanUpdateZone = NULL; - } - } -} - -/** - * @brief deallocates the NPE update areas for all the ports - * - * This function is called at component de-initialization time - * by @ref ixEthDBUnload(). - * - * @warning do not call manually - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasUnload(void) -{ - UINT32 portIndex; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone); - } - } -} - -/** - * @brief general-purpose NPE callback function - * - * @param npeID NPE ID - * @param msg NPE message - * - * This function will unblock the caller by unlocking - * the npeAckLock mutex defined for each NPE port - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - /* invalid port */ - return; - } - - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - /* not an NPE */ - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - ixOsalMutexUnlock(&portInfo->npeAckLock); -} - -/** - * @brief synchronizes the database with tree - * - * @param portID port ID of the NPE whose tree is to be scanned - * @param eltBaseAddress memory base address of the NPE serialized tree - * @param eltSize size in bytes of the NPE serialized tree - * - * Scans the NPE learning tree and resets the age of active database records. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize) -{ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - /* debug */ - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n"); - } - else if (eltEntryOffset == ELT_ROOT_OFFSET) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n"); - } - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* check only active entries belonging to this port */ - if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID) - && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0)) - { - /* search record */ - HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress)); - - /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */ - if (!descriptor->recordData.filteringData.staticEntry) - { - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = AGE_RESET; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - descriptor->recordData.filteringVlanData.age = AGE_RESET; - } - } - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - } - else - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID); - } - } - } -} - -/** - * @brief writes a search tree in NPE format - * - * @param type type of records to be written into the NPE update zone - * @param totalSize maximum size of the linearized tree - * @param baseAddress memory base address where to write the NPE tree into - * @param tree search tree to write in NPE format - * @param blocks number of written 64-byte blocks - * @param startIndex optimal binary search start index - * - * Serializes the given tree in NPE linear format - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks) -{ - MacTreeNodeStack *stack; - UINT32 maxOffset = 0; - UINT32 emptyOffset; - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n"); - return; - } - - /* zero out empty root */ - memset(baseAddress, 0, ELT_ENTRY_SIZE); - - NODE_STACK_INIT(stack); - - if (tree != NULL) - { - /* push tree root at offset 1 */ - NODE_STACK_PUSH(stack, tree, 1); - - maxOffset = 1; - } - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* update maximum offset */ - if (offset > maxOffset) - { - maxOffset = offset; - } - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset); - - /* add node to NPE ELT at position indicated by offset */ - if (offset < MAX_ELT_SIZE) - { - ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node); - } - - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - } - - emptyOffset = maxOffset + 1; - - /* zero out rest of the tree */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n", - emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - - if (emptyOffset < MAX_ELT_SIZE - 1) - { - memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - } - - /* flush cache */ - IX_OSAL_CACHE_FLUSH(baseAddress, totalSize); - - /* debug */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n", - (UINT32) baseAddress, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE); - - /* compute number of 64-byte blocks */ - if (blocks != NULL) - { - *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0; - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks); - } - - /* compute epDelta - start index for binary search */ - if (epDelta != NULL) - { - UINT32 deltaIndex = 0; - - *epDelta = 0; - - for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++) - { - if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset) - { - *epDelta = ixEthDBEPDelta[type][deltaIndex]; - break; - } - } - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset); - } - - ixOsalCacheDmaFree(stack); -} - -/** - * @brief implements a dummy node serialization function - * - * @param address address of where the node is to be serialized (unused) - * @param node tree node to be serialized (unused) - * - * This function is registered for safety reasons and should - * never be called. It will display an error message if this - * function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNullSerialize(void *address, MacTreeNode *node) -{ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n"); -} - -/** - * @brief writes a filtering entry in NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy port ID */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID); - - /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1)); -} - -/** - * @brief writes a WiFi header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy index */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex; - - /* copy flags (type and valid) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID; -} - -/** - * @brief writes a WiFi gateway header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* set reserved field, two bytes */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0; -} - -/** - * @brief writes a firewall record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node) -{ - /* set reserved field */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - - /* set flags */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID; - - /* copy mac address */ - memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); -} - -/** - * @brief registers the NPE serialization methods - * - * This functions registers NPE serialization methods - * for writing the following types of records in NPE - * readable linear format: - * - filtering records - * - WiFi header conversion records - * - WiFi gateway header conversion records - * - firewall records - * - * Note that this function should be called by the - * component initialization function. - * - * @return number of registered record types - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBRecordSerializeMethodsRegister() -{ - int i; - - /* safety - register a blank method for everybody first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++) - { - ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize; - } - - /* register real methods */ - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite; - - /* EP Delta arrays */ - memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset)); - memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta)); - - /* filtering records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14; - - /* wifi records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14; - - /* firewall records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37; - - return 5; /* 5 methods registered */ -} - -#ifndef IX_NDEBUG - -IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0; - -/** - * When compiled in DEBUG mode, this function can be used to display - * the history of messages sent to the NPEs (up to 100). - */ -IX_ETH_DB_PUBLIC -void ixEthDBShowNpeMsgHistory() -{ - UINT32 i = 0; - UINT32 base, len; - - if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH) - { - base = 0; - len = npeMsgHistoryLen; - } - else - { - base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - } - - printf("NPE message history [last %d messages, from least to most recent]:\n", len); - - for (; i < len ; i++) - { - UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]); - } -} - -IX_ETH_DB_PUBLIC -void ixEthDBELTShow(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* reserved */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone; - UINT32 eltSize = FULL_ELT_BYTE_SIZE; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize); - - printf("Listing records in main learning tree for port %d\n", portID); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - HashNode *node; - - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* search record */ - node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES); - - printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID, - IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive"); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - printf("- %s ", - descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" : - descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" : - descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)"); - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ", - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ", - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - descriptor->recordData.filteringVlanData.ieee802_1qTag); - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - else - { - printf("- not synced"); - } - - printf("\n"); - } - } - } - else - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (ShowELT) Could not complete action (communication failure)\n", - portID, 0, 0, 0, 0, 0); - } -} - -#endif diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c deleted file mode 100644 index 92af331a54..0000000000 --- a/drivers/net/npe/IxEthDBPortUpdate.c +++ /dev/null @@ -1,716 +0,0 @@ -/** - * @file IxEthDBDBPortUpdate.c - * - * @brief Implementation of dependency and port update handling - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor); -IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts); -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count); -IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x); - -extern HashTable dbHashtable; - -/** - * @brief register types requiring automatic updates - * - * @param typeArray array indexed on record types, each - * element indicating whether the record type requires an - * automatic update (true) or not (false) - * - * Automatic updates are done for registered record types - * upon adding, updating (that is, updating the record portID) - * and removing records. Whenever an automatic update is triggered - * the appropriate ports will be provided with new database - * information. - * - * It is assumed that the typeArray parameter is allocated large - * enough to hold all the user defined types. Also, the type - * array should be initialized to false as this function only - * caters for types which do require automatic updates. - * - * Note that this function should be called by the component - * initialization function. - * - * @return number of record types registered for automatic - * updates - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray) -{ - typeArray[IX_ETH_DB_FILTERING_RECORD] = true; - typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true; - - return 2; -} - -/** - * @brief computes dependencies and triggers port learning tree updates - * - * @param triggerPorts port map consisting in the ports which triggered the update - * - * This function browses through all the ports and determines how to waterfall the update - * event from the trigger ports to all other ports depending on them. - * - * Once the list of ports to be updated is determined this function - * calls @ref ixEthDBCreateTrees. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts) -{ - IxEthDBPortMap updatePorts; - UINT32 portIndex; - - ixEthDBUpdateLock(); - - SET_EMPTY_DEPENDENCY_MAP(updatePorts); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *port = &ixEthDBPortInfo[portIndex]; - BOOL mapsCollide; - - MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap); - - if (mapsCollide /* do triggers influence this port? */ - && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */ - && port->updateMethod.updateEnabled) /* and we're allowed to update it */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex); - - JOIN_PORT_TO_MAP(updatePorts, portIndex); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex); - - if (!mapsCollide) - { - IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex); - } - - if (IS_PORT_INCLUDED(portIndex, updatePorts)) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex); - } - - if (!port->updateMethod.updateEnabled) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex); - } - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n"); - - ixEthDBCreateTrees(updatePorts); - - ixEthDBUpdateUnlock(); -} - -/** - * @brief creates learning trees and calls the port update handlers - * - * @param updatePorts set of ports in need of learning trees - * - * This function determines the optimal method of creating learning - * trees using a minimal number of database queries, keeping in mind - * that different ports can either use the same learning trees or they - * can partially share them. The actual tree building routine is - * @ref ixEthDBQuery. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) -{ - UINT32 portIndex; - BOOL result; - BOOL portsLeft = true; - - while (portsLeft) - { - /* get port with minimal dependency map and NULL search tree */ - UINT32 minPortIndex = MAX_PORT_SIZE; - UINT32 minimalSize = MAX_PORT_SIZE; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - UINT32 size; - PortInfo *port = &ixEthDBPortInfo[portIndex]; - - /* generate trees only for ports that need them */ - if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts)) - { - GET_MAP_SIZE(port->dependencyPortMap, size); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n", - portIndex, size); - - if (size < minimalSize) - { - minPortIndex = portIndex; - minimalSize = size; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex, - port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query"); - } - } - - /* if a port was found than minimalSize is not MAX_PORT_SIZE */ - if (minimalSize != MAX_PORT_SIZE) - { - /* minPortIndex is the port we seek */ - PortInfo *port = &ixEthDBPortInfo[minPortIndex]; - - IxEthDBPortMap query; - MacTreeNode *baseTree; - - /* now try to find a port with minimal map difference */ - PortInfo *minimalDiffPort = NULL; - UINT32 minimalDiff = MAX_PORT_SIZE; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *diffPort = &ixEthDBPortInfo[portIndex]; - BOOL mapIsSubset; - - IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap); - - - if (portIndex != minPortIndex - && diffPort->updateMethod.searchTree != NULL - && mapIsSubset) - { - /* compute size and pick only minimal size difference */ - UINT32 diffPortSize; - UINT32 sizeDifference; - - GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex); - - sizeDifference = minimalSize - diffPortSize; - - if (sizeDifference < minimalDiff) - { - minimalDiffPort = diffPort; - minimalDiff = sizeDifference; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n", - minimalDiff, portIndex); - } - } - } - - /* check if filtering is enabled on this port */ - if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0) - { - /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */ - if (minimalDiff != MAX_PORT_SIZE) - { - baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree); - DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n", - minimalDiffPort->portID); - } - else /* .. otherwise no similar port was found, build tree from scratch */ - { - baseTree = NULL; - - COPY_DEPENDENCY_MAP(query, port->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n"); - } - - IS_EMPTY_DEPENDENCY_MAP(result, query); - - if (!result) /* otherwise we don't need anything more on top of the cloned tree */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex); - - /* build learning tree */ - port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n"); - - port->updateMethod.searchTree = baseTree; - } - } - else - { - /* filtering is not enabled, will download an empty tree */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - port->updateMethod.searchTree = NULL; - } - - /* mark tree as valid */ - port->updateMethod.searchTreePendingWrite = true; - } - else - { - portsLeft = false; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n"); - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *updatePort = &ixEthDBPortInfo[portIndex]; - - if (updatePort->updateMethod.searchTreePendingWrite) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n", - updatePort->updateMethod.searchTree != NULL ? "not " : "", - portIndex); - - updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD); - } - } -} - -/** - * @brief standard NPE update handler - * - * @param portID id of the port to be updated - * @param type record type to be pushed during this update - * - * The NPE update handler manages updating the NPE databases - * given a certain record type. - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type) -{ - UINT32 epDelta, blockCount; - IxNpeMhMessage message; - UINT32 treeSize = 0; - PortInfo *port = &ixEthDBPortInfo[portID]; - - /* size selection and type check */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - treeSize = FULL_ELT_BYTE_SIZE; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - treeSize = FULL_FW_BYTE_SIZE; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - /* serialize tree into memory */ - ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount); - - /* free internal copy */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - /* forget last used search tree */ - port->updateMethod.searchTree = NULL; - port->updateMethod.searchTreePendingWrite = false; - - /* dependending on the update type we do different things */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - IX_STATUS result; - - FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, blockCount, - IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID); - } - else - { - ixEthDBPortInfo[portID].agingEnabled = false; - ixEthDBPortInfo[portID].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID); - - ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES); - - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta); - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief queries the database for a set of records to be inserted into a given tree - * - * @param searchTree pointer to a tree where insertions will be performed; can be NULL - * @param query set of ports that a database record must match to be inserted into the tree - * - * The query method browses through the database, extracts all the descriptors matching - * the given query parameter and inserts them into the given learning tree. - * Note that this is an append procedure, the given tree needs not to be empty. - * A "descriptor matching the query" is a descriptor whose port id is in the query map. - * If the given tree is empty (NULL) a new tree is created and returned. - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries) -{ - HashIterator iterator; - UINT32 entryCount = 0; - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ", - mac2string(descriptor->macAddress), - descriptor->portID); - - if ((descriptor->type & recordFilter) != 0 - && IS_PORT_INCLUDED(descriptor->portID, query)) - { - MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor); - - IX_ETH_DB_UPDATE_TRACE("match\n"); - - if (descriptorClone != NULL) - { - /* add descriptor to tree */ - searchTree = ixEthDBTreeInsert(searchTree, descriptorClone); - - entryCount++; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("no match\n"); - } - - if (entryCount < maxEntries) - { - /* advance to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - else - { - /* the NPE won't accept more entries so we can stop now */ - ixEthDBReleaseHashIterator(&iterator); - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n"); - - break; - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount); - - return ixEthDBTreeRebalance(searchTree); -} - -/** - * @brief inserts a mac descriptor into an tree - * - * @param searchTree tree where the insertion is to be performed (may be NULL) - * @param descriptor descriptor to insert into tree - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor) -{ - MacTreeNode *currentNode = searchTree; - MacTreeNode *insertLocation = NULL; - MacTreeNode *newNode; - INT32 insertPosition = RIGHT; - - if (descriptor == NULL) - { - return searchTree; - } - - /* create a new node */ - newNode = ixEthDBAllocMacTreeNode(); - - if (newNode == NULL) - { - /* out of memory */ - ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__); - - ixEthDBFreeMacDescriptor(descriptor); - - return NULL; - } - - /* populate node */ - newNode->descriptor = descriptor; - - /* an empty initial tree is a special case */ - if (searchTree == NULL) - { - return newNode; - } - - /* get insertion location */ - while (insertLocation == NULL) - { - MacTreeNode *nextNode; - - /* compare given key with current node key */ - insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress); - - /* navigate down */ - if (insertPosition == RIGHT) - { - nextNode = currentNode->right; - } - else if (insertPosition == LEFT) - { - nextNode = currentNode->left; - } - else - { - /* error, duplicate key */ - ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n"); - - /* this will free the MAC descriptor as well */ - ixEthDBFreeMacTreeNode(newNode); - - return searchTree; - } - - /* when we can no longer dive through the tree we found the insertion place */ - if (nextNode != NULL) - { - currentNode = nextNode; - } - else - { - insertLocation = currentNode; - } - } - - /* insert node */ - if (insertPosition == RIGHT) - { - insertLocation->right = newNode; - } - else - { - insertLocation->left = newNode; - } - - return searchTree; -} - -/** - * @brief balance a tree - * - * @param searchTree tree to balance - * - * Converts a tree into a balanced tree and returns the root of - * the balanced tree. The resulting tree is route balanced - * not perfectly balanced. This makes no difference to the - * average tree search time which is the same in both cases, O(log2(n)). - * - * @return root of the balanced tree or NULL if there's no memory left - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree) -{ - MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode(); - UINT32 size; - - if (pseudoRoot == NULL) - { - /* out of memory */ - return NULL; - } - - pseudoRoot->right = searchTree; - - ixEthDBRebalanceTreeToVine(pseudoRoot, &size); - ixEthDBRebalanceVineToTree(pseudoRoot, size); - - searchTree = pseudoRoot->right; - - /* remove pseudoRoot right branch, otherwise it will free the entire tree */ - pseudoRoot->right = NULL; - - ixEthDBFreeMacTreeNode(pseudoRoot); - - return searchTree; -} - -/** - * @brief converts a tree into a vine - * - * @param root root of tree to convert - * @param size depth of vine (equal to the number of nodes in the tree) - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size) -{ - MacTreeNode *vineTail = root; - MacTreeNode *remainder = vineTail->right; - MacTreeNode *tempPtr; - - *size = 0; - - while (remainder != NULL) - { - if (remainder->left == NULL) - { - /* move tail down one */ - vineTail = remainder; - remainder = remainder->right; - (*size)++; - } - else - { - /* rotate around remainder */ - tempPtr = remainder->left; - remainder->left = tempPtr->right; - tempPtr->right = remainder; - remainder = tempPtr; - vineTail->right = tempPtr; - } - } -} - -/** - * @brief converts a vine into a balanced tree - * - * @param root vine to convert - * @param size depth of vine - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size) -{ - UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1)); - - ixEthDBRebalanceCompression(root, leafCount); - - size = size - leafCount; - - while (size > 1) - { - ixEthDBRebalanceCompression(root, size / 2); - - size /= 2; - } -} - -/** - * @brief compresses a vine/tree stage into a more balanced vine/tree - * - * @param root root of the tree to compress - * @param count number of "spine" nodes - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count) -{ - MacTreeNode *scanner = root; - MacTreeNode *child; - UINT32 local_index; - - for (local_index = 0 ; local_index < count ; local_index++) - { - child = scanner->right; - scanner->right = child->right; - scanner = scanner->right; - child->right = scanner->left; - scanner->left = child; - } -} - -/** - * @brief computes |_log2(x)_| (a.k.a. floor(log2(x))) - * - * @param x number to compute |_log2(x)_| for - * - * @return |_log2(x)_| - * - * @internal - */ -IX_ETH_DB_PRIVATE -UINT32 ixEthDBRebalanceLog2Floor(UINT32 x) -{ - UINT32 log = 0; - UINT32 val = 1; - - while (val < x) - { - log++; - val <<= 1; - } - - return val == x ? log : log - 1; -} - diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c deleted file mode 100644 index d74f1215fd..0000000000 --- a/drivers/net/npe/IxEthDBReports.c +++ /dev/null @@ -1,628 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; -IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map); - -/** - * @brief displays a port dependency map - * - * @param portID ID of the port - * @param map port map to display - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map) -{ - UINT32 portIndex; - BOOL mapSelf = true, mapNone = true, firstPort = true; - - /* dependency port maps */ - printf("Dependency port map: "); - - /* browse the port map */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (IS_PORT_INCLUDED(portIndex, map)) - { - mapNone = false; - - if (portIndex != portID) - { - mapSelf = false; - } - - printf("%s%d", firstPort ? "{" : ", ", portIndex); - - firstPort = false; - } - } - - if (mapNone) - { - mapSelf = false; - } - - printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group"); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to a port - * - * @param portID ID of the port to display - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) -{ - IxEthDBStatus local_result; - HashIterator iterator; - PortInfo *portInfo; - UINT32 recordCount = 0; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - /* display table header */ - printf("Ethernet database records for port ID [%d]\n", portID); - - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf("updates disabled (not an NPE)\n\n"); - } - - printf(" MAC address | Age | Type \n"); - printf("___________________________________\n"); - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - recordCount++; - - /* display entry */ - printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - return IX_ETH_DB_FAIL; - } - } - - /* display number of records */ - printf("\nFound %d records\n", recordCount); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to all the ports - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll() -{ - IxEthDBPortId portIndex; - - printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBFilteringDatabaseShow(portIndex); - - if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1) - { - printf("\n"); - } - } -} - -/** - * @brief displays one record in a format depending on the record filter - * - * @param descriptor pointer to the record - * @param recordFilter format filter - * - * This function will display the fields in a record depending on the - * selected record filter. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address \n"); - printf("__________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic"); - } - else if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else - { - printf("invalid record filter\n"); - } -} - -/** - * @brief displays the status, records and configuration information of a port - * - * @param portID ID of the port - * @param recordFilter record filter to display - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT32 recordCount = 0; - HashIterator iterator; - IxEthDBStatus local_result; - - /* display port status */ - printf("== Port ID %d ==\n", portID); - - /* display capabilities */ - printf("- Capabilities: "); - - if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0) - { - printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off"); - } - - printf("\n"); - - /* dependency map */ - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - /* NPE dynamic updates */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - dynamic update disabled (not an NPE)\n"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - /* WiFi header conversion */ - if ((portInfo->frameControlDurationID - + portInfo->bbsid[0] - + portInfo->bbsid[1] - + portInfo->bbsid[2] - + portInfo->bbsid[3] - + portInfo->bbsid[4] - + portInfo->bbsid[5]) == 0) - { - printf(" - WiFi header conversion not configured\n"); - } - else - { - printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n", - portInfo->bbsid[0], - portInfo->bbsid[1], - portInfo->bbsid[2], - portInfo->bbsid[3], - portInfo->bbsid[4], - portInfo->bbsid[5], - portInfo->frameControlDurationID >> 16, - portInfo->frameControlDurationID & 0xFFFF); - } - } - else - { - printf(" - WiFi header conversion not enabled\n"); - } - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) - { - printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white"); - printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - Firewall not enabled\n"); - } - } - - /* browse database if asked to display records */ - if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE) - { - printf("\n"); - ixEthDBHeaderShow(recordFilter); - - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0) - { - recordCount++; - - /* display entry */ - ixEthDBRecordShow(descriptor, recordFilter); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - printf("EthDB (API): Error, database browser failed (no access), giving up\n"); - } - } - - printf("\nFound %d records\n\n", recordCount); - } -} - -/** - * @brief displays a record header - * - * @param recordFilter record type filter - * - * This function displays a record header, depending on - * the given record type filter. It is useful when used - * in conjunction with ixEthDBRecordShow which will display - * record fields formatted for the header, provided the same - * record filter is used. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter - * parameter is invalid or not supported - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header */ - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header */ - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header */ - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header */ - printf(" MAC address \n"); - printf("__________________\n"); - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header */ - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays database information (records and port information) - * - * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only - * port information) - * - * Note that this function is documented in the main component header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully or - * an appropriate error code otherwise - * - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - IxEthDBPortId currentPort; - BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS); - - IX_ETH_DB_CHECK_PORT_ALL(portID); - - printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1); - - currentPort = showAllPorts ? 0 : portID; - - while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS) - { - /* display port info */ - ixEthDBPortInfoShow(currentPort, recordFilter); - - /* next port */ - currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS; - } - - return IX_ETH_DB_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c deleted file mode 100644 index 4fd28da080..0000000000 --- a/drivers/net/npe/IxEthDBSearch.c +++ /dev/null @@ -1,303 +0,0 @@ -/** - * @file IxEthDBSearch.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; - -/** - * @brief matches two database records based on their MAC addresses - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and VLAN IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) == - IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and port IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (entry->portID == reference->portID) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief dummy matching function, registered for safety - * - * @param reference record to match against (unused) - * @param entry record to match (unused) - * - * This function is registered in the matching functions - * array on invalid types. Calling it will display an - * error message, indicating an error in the component logic. - * - * @return false - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBNullMatch(void *reference, void *entry) -{ - /* display an error message */ - - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0); - - - return false; -} - -/** - * @brief registers hash matching methods - * - * @param matchFunctions table of match functions to be populated - * - * This function registers the available record matching functions - * by indexing them on record types into the given function array. - * - * Note that it is compulsory to call this in ixEthDBInit(), - * otherwise hashtable searching and removal will not work - * - * @return number of registered functions - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions) -{ - UINT32 i; - - /* safety first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++) - { - matchFunctions[i] = ixEthDBNullMatch; - } - - /* register MAC search method */ - matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch; - - /* register MAC/PortID search method */ - matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch; - - /* register MAC/VLAN ID search method */ - matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch; - - return 3; /* three methods */ -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult)); - - return searchResult; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - MacDescriptor reference; - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference); - - return result; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param portID port ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/port ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult)); - - return searchResult; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param vlanID VLAN ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/VLAN ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.recordData.filteringVlanData.ieee802_1qTag = - IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult)); - - return searchResult; -} diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c deleted file mode 100644 index e12be0d884..0000000000 --- a/drivers/net/npe/IxEthDBSpanningTree.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * @file IxEthDBSpanningTree.c - * - * @brief Implementation of the STP API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief sets the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked true to block the port or false to unblock it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - ixEthDBPortInfo[portID].stpBlocked = blocked; - - FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked address to write the blocked status into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - IX_ETH_DB_CHECK_REFERENCE(blocked); - - *blocked = ixEthDBPortInfo[portID].stpBlocked; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c deleted file mode 100644 index 40d4470bef..0000000000 --- a/drivers/net/npe/IxEthDBUtil.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file ethUtil.c - * - * @brief Utility functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxFeatureCtrl.h" -#include "IxEthDB_p.h" - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID) -{ - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((portID == 0) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 1) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 2) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -BOOL ixEthDBCheckSingleBitValue(UINT32 value) -{ -#if (CPU != SIMSPARCSOLARIS) && !defined (__wince) - UINT32 shift; - - /* use the count-leading-zeros XScale instruction */ - __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value)); - - return ((value << shift) == 0x80000000UL); - -#else - - while (value != 0) - { - if (value == 1) return true; - else if ((value & 1) == 1) return false; - - value >>= 1; - } - - return false; - -#endif -} - -const char *mac2string(const unsigned char *mac) -{ - static char str[19]; - - if (mac == NULL) - { - return NULL; - } - - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - return str; -} diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c deleted file mode 100644 index 483e348934..0000000000 --- a/drivers/net/npe/IxEthDBVlan.c +++ /dev/null @@ -1,1155 +0,0 @@ -/** - * @file IxEthDBVlan.c - * - * @brief Implementation of the VLAN API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB.h" -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex); -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* contants used by various functions as "action" parameter */ -#define ADD_VLAN (0x1) -#define REMOVE_VLAN (0x2) - -/** - * @brief adds or removes a VLAN from a VLAN set - * - * @param vlanID VLAN ID to add or remove - * @param table VLAN set to add into or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffset; - - /* add/remove VID to membership table */ - setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */ - - if (action == ADD_VLAN) - { - table[setOffset] |= 1 << VLAN_SET_MASK(vlanID); - } - else if (action == REMOVE_VLAN) - { - table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID)); - } -} - -/** - * @brief updates a set of 8 VLANs in an NPE - * - * @param portID ID of the port - * @param setOffset offset of the 8 VLANs - * - * This function updates the VLAN membership table - * and Transmit Tagging Info table for 8 consecutive - * VLAN IDs indexed by setOffset. - * - * For example, a setOffset of 0 indexes VLAN IDs 0 - * through 7, 1 indexes VLAN IDs 8 through 9 etc. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - 2 * setOffset, - portInfo->vlanMembership[setOffset], - portInfo->transmitTaggingInfo[setOffset]); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates a VLAN range in an NPE - * - * @param portID ID of the port - * - * This function is similar to @ref ixEthDBVlanTableEntryUpdate - * except that it can update more than one VLAN set (up to - * the entire VLAN membership and TTI tables if the offset is 0 - * and length is sizeof (IxEthDBVlanSet) (512 bytes). - * - * Updating the NPE via this method is slower as it requires - * a memory copy from SDRAM, hence it is recommended that the - * ixEthDBVlanTableEntryUpdate function is used where possible. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone; - IxNpeMhMessage message; - UINT32 setIndex; - IX_STATUS result; - - /* copy membership info and transmit tagging into into exchange area */ - for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++) - { - /* membership and TTI data are interleaved */ - vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex]; - vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex]; - } - - IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE); - - /* build NPE message */ - FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0, - IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone)); - - /* send message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief adds or removes a VLAN from a port's VLAN membership table - * or Transmit Tagging Information table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add or remove - * @param table to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action) -{ - /* change VLAN in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanID, table, action); - - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID)); -} - -/** - * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag port VLAN tag (802.1Q tag) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* add VLAN ID to local membership table */ - ixEthDBPortVlanMembershipChange(portID, - vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK, - ixEthDBPortInfo[portID].vlanMembership, - ADD_VLAN); - - /* set tag in portInfo */ - ixEthDBPortInfo[portID].vlanTag = vlanTag; - - /* build VLAN_SetDefaultRxVID message */ - FILL_SETDEFAULTRXVID_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - IX_IEEE802_1Q_VLAN_TPID, - vlanTag); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag address to write the port VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - *vlanTag = ixEthDBPortInfo[portID].vlanTag; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a - * database filtering record - * - * @param portID ID of the port - * @param vlanTag VLAN tag (802.1Q tag) - * - * Important: filtering records are automatically converted to - * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* set record type to VLAN if not already set */ - descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD; - - /* add vlan tag */ - descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a - * database VLAN filtering record - * - * @param portID ID of the port - * @param vlanTag address to write the VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* get vlan tag */ - *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a VLAN to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to remove - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */ - vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* check we're not asked to remove the default port VID */ - if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief adds or removes a VLAN range from a port's - * VLAN membership table or TTI table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * @param table VLAN set to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffsetMin, setOffsetMax; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax); - - /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */ - vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK; - vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* is this a range? */ - if (vlanIDMax < vlanIDMin) - { - return IX_ETH_DB_INVALID_VLAN; - } - - /* check that we're not specifically asked to remove the default port VID */ - if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* compute set offsets */ - setOffsetMin = VLAN_SET_OFFSET(vlanIDMin); - setOffsetMax = VLAN_SET_OFFSET(vlanIDMax); - - /* change VLAN range */ - for (; vlanIDMin <= vlanIDMax ; vlanIDMin++) - { - /* change vlan in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action); - } - - /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */ - if (setOffsetMin == setOffsetMax) - { - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin); - } - else - { - /* update a zone of the membership/transmit tag info table */ - return ixEthDBVlanTableRangeUpdate(portID); - } -} - -/** - * @brief adds a VLAN range to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN range from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief sets a port's VLAN membership table or TTI table and - * updates the NPE VLAN configuration - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to set - * @param vlanSet new set contents - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet)); - - return ixEthDBVlanTableRangeUpdate(portID); -} - -/** - * @brief retireves a port's VLAN membership table or TTI table - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to retrieve - * @param vlanSet address to - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet new VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the bit corresponding to the PVID just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief retrieves a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet location to store the port's VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief enables or disables Egress tagging for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to enable or disable Egress tagging on - * @param enabled true to enable and false to disable tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief retrieves the Egress tagging status for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to retrieve the tagging status for - * @param enabled location to store the tagging status - * (true - tagging enabled, false - tagging disabled) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables Egress VLAN tagging for a VLAN range - * - * @param portID ID of the port - * @param vlanIDMin start of VLAN range - * @param vlanIDMax end of VLAN range - * @param enabled true to enable or false to disable VLAN tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief sets the Egress VLAN tagging table (the Transmit Tagging - * Information table) - * - * @param portID ID of the port - * @param vlanSet new TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the PVID bit just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief retrieves the Egress VLAN tagging table (the Transmit - * Tagging Information table) - * - * @param portID ID of the port - * @param vlanSet location to store the port's TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief sends the NPE the updated frame filter and default - * Ingress tagging - * - * @param portID ID of the port - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction); - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the default Ingress tagging behavior - * - * @param portID ID of the port - * @param taggingAction default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - portInfo = &ixEthDBPortInfo[portID]; - - if (taggingAction == IX_ETH_DB_PASS_THROUGH) - { - portInfo->npeTaggingAction = 0x00; - } - else if (taggingAction == IX_ETH_DB_ADD_TAG) - { - portInfo->npeTaggingAction = 0x02; - } - else if (taggingAction == IX_ETH_DB_REMOVE_TAG) - { - portInfo->npeTaggingAction = 0x01; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo->taggingAction = taggingAction; - - return ixEthDBIngressVlanModeUpdate(portID); -} - -/** - * @brief retrieves the default Ingress tagging behavior of a port - * - * @param portID ID of the port - * @param taggingAction location to save the default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(taggingAction); - - *taggingAction = ixEthDBPortInfo[portID].taggingAction; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the Ingress acceptable frame type filter - * - * @param portID ID of the port - * @param frameFilter acceptable frame type filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) -{ - PortInfo *portInfo; - IxEthDBStatus result = IX_ETH_DB_SUCCESS; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check parameter range - the ORed value of the valid values is 0x7 - a value having extra bits is invalid */ - if ((frameFilter | 0x7) != 0x7 || frameFilter == 0) - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo = &ixEthDBPortInfo[portID]; - - portInfo->frameFilter = frameFilter; - portInfo->npeFrameFilter = 0; /* allow all by default */ - - /* if accepting priority tagged but not all VLAN tagged - set the membership table to contain only VLAN ID 0 - hence remove vlans 1-4094 and add VLAN ID 0 */ - if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0) - && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0)) - { - result = ixEthDBPortVlanMembershipRangeChange(portID, - 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN); - - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN); - result = ixEthDBVlanTableRangeUpdate(portID); - } - } - - /* untagged only? */ - if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES) - { - portInfo->npeFrameFilter = 0x01; - } - - /* tagged only? */ - if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0) - { - portInfo->npeFrameFilter = 0x02; - } - - if (result == IX_ETH_DB_SUCCESS) - { - result = ixEthDBIngressVlanModeUpdate(portID); - } - - return result; -} - -/** - * @brief retrieves the acceptable frame type filter for a port - * - * @param portID ID of the port - * @param frameFilter location to store the frame filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(frameFilter); - - *frameFilter = ixEthDBPortInfo[portID].frameFilter; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends an NPE the updated configuration related - * to one QoS priority (associated traffic class and AQM mapping) - * - * @param portID ID of the port - * @param classIndex QoS priority (traffic class index) - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex]; - UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass]; - - FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the priority mapping table - * - * @param portID ID of the port - * @param priorityTable new priority mapping table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - UINT32 classIndex; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - /* check range */ - if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - } - - /* set new traffic classes */ - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex]; - - if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; - } - -/** - * @brief retrieves a port's priority mapping table - * - * @param portID ID of the port - * @param priorityTable location to store the priority table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check ranges for userPriority and trafficClass */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass; - - return ixEthDBUpdateTrafficClass(portID, userPriority); -} - -/** - * @brief retrieves one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass location to store the associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(trafficClass); - - /* check userPriority range */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority]; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables the source port extraction - * from the VLAN TPID field - * - * @param portID ID of the port - * @param enable true to enable or false to disable - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} diff --git a/drivers/net/npe/IxEthDBWiFi.c b/drivers/net/npe/IxEthDBWiFi.c deleted file mode 100644 index 44edd47f2f..0000000000 --- a/drivers/net/npe/IxEthDBWiFi.c +++ /dev/null @@ -1,456 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations); - -/** - * @brief sets the BBSID value for the WiFi header conversion feature - * - * @param portID ID of the port - * @param bbsid pointer to the 6-byte BBSID value - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - IX_ETH_DB_CHECK_REFERENCE(bbsid); - - memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr)); - - FILL_SETBBSID_MSG(message, portID, bbsid); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates the Frame Control and Duration/ID WiFi header - * conversion parameters in an NPE - * - * @param portID ID of the port - * - * This function will send a message to the NPE updating the - * frame conversion parameters for 802.3 => 802.11 header conversion. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the Duration/ID WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Duration/ID parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID; - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief sets the Frame Control WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Frame Control parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16); - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief removes a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway (or - * NULL if this is a station record) - * - * This function adds a record of type AP_TO_AP (gateway is not NULL) - * or AP_TO_STA (gateway is NULL) in the main database as a - * WiFi header conversion record. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - if (gatewayMacAddr != NULL) - { - memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP; - } - else - { - memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA; - } - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway - * - * This function adds a record of type AP_TO_AP - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr); - - return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * - * This function adds a record of type AP_TO_STA - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - return ixEthDBWiFiEntryAdd(portID, macAddr, NULL); -} - -/** - * @brief selects a set of gateways from a tree of - * WiFi header conversion records - * - * @param stations binary tree containing pointers to WiFi header - * conversion records - * - * This function browses through the input binary tree, identifies - * records of type AP_TO_AP, clones these records and appends them - * to a vine (a single right-branch binary tree) which is returned - * as result. A maximum of MAX_GW_SIZE entries containing gateways - * will be cloned from the original tree. - * - * @return vine (linear binary tree) containing record - * clones of AP_TO_AP type, which have a gateway field - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations) -{ - MacTreeNodeStack *stack; - MacTreeNode *gateways, *insertionPlace; - UINT32 gwIndex = 1; /* skip the empty root */ - - if (stations == NULL) - { - return NULL; - } - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n"); - return NULL; - } - - /* initialize root node */ - gateways = insertionPlace = NULL; - - /* start browsing the station tree */ - NODE_STACK_INIT(stack); - - /* initialize stack by pushing the tree root at offset 0 */ - NODE_STACK_PUSH(stack, stations, 0); - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */ - if (offset > (MAX_GW_SIZE - 1)) break; - - /* check if this record has a gateway address */ - if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* found a record, create an insertion place */ - if (insertionPlace != NULL) - { - insertionPlace->right = ixEthDBAllocMacTreeNode(); - insertionPlace = insertionPlace->right; - } - else - { - gateways = ixEthDBAllocMacTreeNode(); - insertionPlace = gateways; - } - - if (insertionPlace == NULL) - { - /* no nodes left, bail out with what we have */ - ixOsalCacheDmaFree(stack); - return gateways; - } - - /* clone the original record for the gateway tree */ - insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor); - - /* insert and update the offset in the original record */ - node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++; - } - - /* browse the tree */ - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - } - - ixOsalCacheDmaFree(stack); - return gateways; -} - -/** - * @brief downloads the WiFi header conversion table to an NPE - * - * @param portID ID of the port - * - * This function prepares the WiFi header conversion tables and - * downloads them to the specified NPE port. - * - * The header conversion tables consist in the main table of - * addresses and the secondary table of gateways. AP_TO_AP records - * from the first table contain index fields into the second table - * for gateway selection. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL; - IxNpeMhMessage message; - PortInfo *portInfo; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - portInfo = &ixEthDBPortInfo[portID]; - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE); - gateways = ixEthDBGatewaySelect(stations); - - /* clean up gw area */ - memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0); - - /* write all gateways */ - gateway = gateways; - - while (gateway != NULL) - { - ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone) - + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE), - gateway); - - gateway = gateway->right; - } - - /* free the gateway tree */ - if (gateways != NULL) - { - ixEthDBFreeMacTreeNode(gateways); - } - - FILL_SETAPMACTABLE_MSG(message, - IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* update the main tree (the stations tree) */ - portInfo->updateMethod.searchTree = stations; - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD); - } - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c deleted file mode 100644 index 27f3548ce0..0000000000 --- a/drivers/net/npe/IxEthMii.c +++ /dev/null @@ -1,473 +0,0 @@ -/** - * @file IxEthMii.c - * - * @author Intel Corporation - * @date - * - * @brief MII control functions - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include "IxEthAcc.h" -#include "IxEthMii_p.h" - -#ifdef __wince -#include "IxOsPrintf.h" -#endif - -/* Array to store the phy IDs of the discovered phys */ -PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; - -/********************************************************* - * - * Scan for PHYs on the MII bus. This function returns - * an array of booleans, one for each PHY address. - * If a PHY is found at a particular address, the - * corresponding entry in the array is set to true. - * - */ - -PUBLIC IX_STATUS -ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) -{ - UINT32 i; - UINT16 regval, regvalId1, regvalId2; - - /*Search for PHYs on the MII*/ - /*Search for existant phys on the MDIO bus*/ - - if ((phyPresent == NULL) || - (maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR)) - { - return IX_FAIL; - } - - /* fill the array */ - for(i=0; - i 0 && i= IX_ETH_MII_RESET_DELAY_MS) - { - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_FAIL; - } - - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID) - { - /* reset bit is reserved, just reset the control register */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } - else - { - /* unknown PHY, set the control register reset bit, - * wait 2 s. and clear the control register. - */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_RESET); - - ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS); - - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - return IX_FAIL; -} - -/***************************************************************** - * - * Link state query functions - */ - -PUBLIC IX_STATUS -ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) -{ - UINT16 ctrlRegval, statRegval, regval, regval4, regval5; - - /* check the parameters */ - if ((linkUp == NULL) || - (speed100 == NULL) || - (fullDuplex == NULL) || - (autoneg == NULL)) - { - return IX_FAIL; - } - - *linkUp = false; - *speed100 = false; - *fullDuplex = false; - *autoneg = false; - - if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && - (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) - { - if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID) - ) - { - /* --------------------------------------------------*/ - /* Retrieve information from PHY specific register */ - /* --------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_STAT2_REG, - ®val) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0); - *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0); - *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0); - *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0); - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else - { - /* ----------------------------------------------------*/ - /* Retrieve information from status and ctrl registers */ - /* ----------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_CTRL_REG, - &ctrlRegval) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval); - - *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0); - if (*linkUp) - { - *autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0); - - if (*autoneg) - { - /* mask the current stat values with the capabilities */ - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5); - /* merge the flags from the 3 registers */ - regval = (statRegval & ((regval4 & regval5) << 6)); - /* initialise from status register values */ - if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) - { - /* 100 Base X full dplx */ - *speed100 = true; - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) - { - /* 100 Base X half dplx */ - *speed100 = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) - { - /* 10 mb full dplx */ - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) - { - /* 10 mb half dplx */ - return IX_SUCCESS; - } - } /* end of if(autoneg) */ - else - { - /* autonegotiate not complete, return setup parameters */ - *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0); - *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0); - } - } /* end of if(linkUp) */ - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - else - { - return IX_FAIL; - } /* end of if-else(phyAddr) */ - return IX_SUCCESS; -} - -/***************************************************************** - * - * Link state display functions - */ - -PUBLIC IX_STATUS -ixEthMiiPhyShow (UINT32 phyAddr) -{ - BOOL linkUp, speed100, fullDuplex, autoneg; - UINT16 cregval; - UINT16 sregval; - - - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval); - - /* get link information */ - if (ixEthMiiLinkStatus(phyAddr, - &linkUp, - &speed100, - &fullDuplex, - &autoneg) != IX_ETH_ACC_SUCCESS) - { - printf("PHY Status unknown\n"); - return IX_FAIL; - } - - printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]); - printf( " Status reg: %4.4x\n",sregval); - printf( " control reg: %4.4x\n",cregval); - /* display link information */ - printf("PHY Status:\n"); - printf(" Link is %s\n", - (linkUp ? "Up" : "Down")); - if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0) - { - printf(" Remote fault detected\n"); - } - printf(" Auto Negotiation %s\n", - (autoneg ? "Completed" : "Not Completed")); - - printf("PHY Configuration:\n"); - printf(" Speed %sMb/s\n", - (speed100 ? "100" : "10")); - printf(" %s Duplex\n", - (fullDuplex ? "Full" : "Half")); - printf(" Auto Negotiation %s\n", - (autoneg ? "Enabled" : "Disabled")); - return IX_SUCCESS; -} - diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c deleted file mode 100644 index 0b6807d9d7..0000000000 --- a/drivers/net/npe/IxFeatureCtrl.c +++ /dev/null @@ -1,398 +0,0 @@ -/** - * @file IxFeatureCtrl.c - * - * @author Intel Corporation - * @date 29-Jan-2003 - * - * @brief Feature Control Public API Implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -#include "IxOsal.h" -#include "IxVersionId.h" -#include "IxFeatureCtrl.h" - -/* Macro to read from the Feature Control Register */ -#define IX_FEATURE_CTRL_READ(result) \ -do { \ -ixFeatureCtrlExpMap(); \ -(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \ -} while (0) - -/* Macro to write to the Feature Control Register */ -#define IX_FEATURE_CTRL_WRITE(value) \ -do { \ -ixFeatureCtrlExpMap(); \ -IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \ -} while (0) - -/* - * This is the offset of the feature register relative to the base of the - * Expansion Bus Controller MMR. - */ -#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028) - - -/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */ -PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false; - -/* Pointer holding the virtual address of the Feature Control Register */ -PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; - -/* Place holder to store the software configuration */ -PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX]; - -/* Flag to control swConfiguration[] is initialized once */ -PRIVATE BOOL swConfigurationFlag = false ; - -/* Array containing component mask values */ -#ifdef __ixp42X -UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = { - (0x1<> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET) - & IX_FEATURE_CTRL_DEVICE_TYPE_MASK); -} /* End function ixFeatureCtrlDeviceRead */ - - -/** - * Function definition: ixFeatureCtrlSwConfigurationCheck - */ -IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return IX_FEATURE_CTRL_SWCONFIG_DISABLED; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Check and return software configuration */ - return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); -} - -/** - * Function definition: ixFeatureCtrlSwConfigurationWrite - */ -void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Write software configuration */ - swConfiguration[(UINT32)swConfigType]=enabled ; -} - -/** - * Function definition: ixFeatureCtrlIxp400SwVersionShow - */ -void -ixFeatureCtrlIxp400SwVersionShow (void) -{ - printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID); - -} - -/** - * Function definition: ixFeatureCtrlSoftwareBuildGet - */ -IxFeatureCtrlBuildDevice -ixFeatureCtrlSoftwareBuildGet (void) -{ - #ifdef __ixp42X - return IX_FEATURE_CTRL_SW_BUILD_IXP42X; - #else - return IX_FEATURE_CTRL_SW_BUILD_IXP46X; - #endif -} diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c deleted file mode 100644 index 0e5c428323..0000000000 --- a/drivers/net/npe/IxNpeDl.c +++ /dev/null @@ -1,916 +0,0 @@ -/** - * @file IxNpeDl.c - * - * @author Intel Corporation - * @date 08 January 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Downloader component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required - */ - -/* - * Put the user defined include files required - */ -#include "IxNpeDl.h" -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" -/* - * #defines used in this file - */ - #define IMAGEID_MAJOR_NUMBER_DEFAULT 0 - #define IMAGEID_MINOR_NUMBER_DEFAULT 0 - -/* - * Typedefs whose scope is limited to this file. - */ -typedef struct -{ - BOOL validImage; - IxNpeDlImageId imageId; -} IxNpeDlNpeState; - -/* module statistics counters */ -typedef struct -{ - UINT32 attemptedDownloads; - UINT32 successfulDownloads; - UINT32 criticalFailDownloads; -} IxNpeDlStats; - -/* - * Variable declarations global to this file only. Externs are followed - * by static variables. - */ -static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] = -{ - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} -}; - -static IxNpeDlStats ixNpeDlStats; - -/* - * Software guard to prevent NPE from being started multiple times. - */ -static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId); - -/* - * Function definition: ixNpeDlImageDownload - */ -PUBLIC IX_STATUS -ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, - BOOL verify) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = imageIdPtr->npeId; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageDownload\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n"); - } - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/ - - /* stop and reset the NPE */ - if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId)) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return IX_FAIL; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr, - &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, - verify); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageDownload : status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesCountGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesCountGet\n"); - - /* Check input parameters */ - if (numImagesPtr == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - " - "invalid parameter\n"); - } - else - { - /* - * Use ImageMgr module to get no. of images listed in Image Library Header. - * If NULL is passed as imageListPtr parameter to following function, - * it will only fill number of images into numImagesPtr - */ - status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr); - } /* end of if-else(numImagesPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesCountGet : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesListGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr, - UINT32 *listSizePtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesListGet\n"); - - /* Check input parameters */ - if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - " - "invalid parameter\n"); - } - else - { - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrImageListExtract (imageIdListPtr, - listSizePtr); - } /* end of if-else(imageIdListPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesListGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLoadedImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLoadedImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n"); - } - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - if (ixNpeDlNpeState[npeId].validImage) - { - /* use npeId to get imageId from list of currently loaded - images */ - *imageIdPtr = ixNpeDlNpeState[npeId].imageId; - } - else - { - status = IX_FAIL; - } /* end of if-else(ixNpeDlNpeState) */ - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLoadedImageGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLatestImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLatestImageGet ( - IxNpeDlNpeId npeId, - IxNpeDlFunctionalityId functionalityId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLatestImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || - (npeId < 0) || - (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - " - "invalid parameter\n"); - } /* end of if(npeId) */ - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - imageIdPtr->npeId = npeId; - imageIdPtr->functionalityId = functionalityId; - imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT; - imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT; - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr); - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLatestImageGet : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeStopAndReset - */ -PUBLIC IX_STATUS -ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeStopAndReset\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - if (status == IX_SUCCESS) - { - /* call NpeMgr function to reset the NPE */ - status = ixNpeDlNpeMgrNpeReset (npeId); - } - } /* end of if(status) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStart\n"); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n"); - return IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (true == ixNpeDlNpeStarted[npeId]) - { - /* NPE has been started. */ - return IX_SUCCESS ; - } - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* call NpeMgr function to start the NPE */ - status = ixNpeDlNpeMgrNpeStart (npeId); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has started */ - ixNpeDlNpeStarted[npeId] = true ; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStart : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStop - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStop\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42X-AO Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStop : status = %d\n", - status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlUnload - */ -PUBLIC IX_STATUS -ixNpeDlUnload (void) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlUnload\n"); - - status = ixNpeDlNpeMgrUninit(); - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlUnload : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlStatsShow - */ -PUBLIC void -ixNpeDlStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlStatsShow:\n" - "\tDownloads Attempted by user: %u\n" - "\tSuccessful Downloads: %u\n" - "\tFailed Downloads (due to Critical Error): %u\n\n", - ixNpeDlStats.attemptedDownloads, - ixNpeDlStats.successfulDownloads, - ixNpeDlStats.criticalFailDownloads, - 0,0,0); - - ixNpeDlImageMgrStatsShow (); - ixNpeDlNpeMgrStatsShow (); -} - -/* - * Function definition: ixNpeDlStatsReset - */ -PUBLIC void -ixNpeDlStatsReset (void) -{ - ixNpeDlStats.attemptedDownloads = 0; - ixNpeDlStats.successfulDownloads = 0; - ixNpeDlStats.criticalFailDownloads = 0; - - ixNpeDlImageMgrStatsReset (); - ixNpeDlNpeMgrStatsReset (); -} - -/* - * Function definition: ixNpeDlNpeInitAndStartInternal - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, - UINT32 imageId) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId); - IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeInitAndStartInternal\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameter device correctness */ - if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) || - (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } /* End valid device id checking */ - - /* Check input parameters */ - else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } - - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* Checking if image being loaded is meant for device that is running. - * Image is forward compatible. i.e Image built for IXP42X should run - * on IXP46X but not vice versa.*/ - if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "Device type mismatch. NPE Image not " - "meant for device in use \n"); - return IX_NPEDL_DEVICE_ERR; - }/* if statement - matching image device and current device */ - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if not IXP42X-A0 Silicon */ - - /* stop and reset the NPE */ - status = ixNpeDlNpeStopAndReset (npeId); - if (IX_SUCCESS != status) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return status; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageFind (imageLibrary, imageId, - &imageCodePtr, &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - - /* NOTE - The following section of code is here to support - * a deprecated function ixNpeDlLoadedImageGet(). When that - * function is removed from the API, this code should be revised. - */ - ixNpeDlNpeState[npeId].imageId.npeId = npeId; - ixNpeDlNpeState[npeId].imageId.functionalityId = - IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.major = - IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.minor = - IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId); - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeInitAndStartInternal : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlCustomImageNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary, - UINT32 imageId) -{ - IX_STATUS status; - - if (imageLibrary == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart " - "- invalid parameter\n"); - } - else - { - status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId); - } /* end of if-else(imageLibrary) */ - - return status; -} - -/* - * Function definition: ixNpeDlNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeInitAndStart (UINT32 imageId) -{ - return ixNpeDlNpeInitAndStartInternal (NULL, imageId); -} - -/* - * Function definition: ixNpeDlLoadedImageFunctionalityGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId, - UINT8 *functionalityId) -{ - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - if (functionalityId == NULL) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - - if (ixNpeDlNpeState[npeId].validImage) - { - *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId; - return IX_SUCCESS; - } - else - { - return IX_FAIL; - } -} diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c deleted file mode 100644 index 52f73d7ad8..0000000000 --- a/drivers/net/npe/IxNpeDlImageMgr.c +++ /dev/null @@ -1,663 +0,0 @@ -/** - * @file IxNpeDlImageMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader ImageMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#include "IxOsal.h" - -/* - * Put the user defined include files required. - */ -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * define the flag which toggles the firmare inclusion - */ -#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1 -#include "IxNpeMicrocode.h" - -/* - * Indicates the start of an NPE Image, in new NPE Image Library format. - * 2 consecutive occurances indicates the end of the NPE Image Library - */ -#define NPE_IMAGE_MARKER 0xfeedf00d - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 size; - UINT32 offset; - UINT32 id; -} IxNpeDlImageMgrImageEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef union -{ - IxNpeDlImageMgrImageEntry image; - UINT32 eohMarker; -} IxNpeDlImageMgrHeaderEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 signature; - /* 1st entry in the header (there may be more than one) */ - IxNpeDlImageMgrHeaderEntry entry[1]; -} IxNpeDlImageMgrImageLibraryHeader; - - -/* - * NPE Image Header definition, used in new NPE Image Library format - */ -typedef struct -{ - UINT32 marker; - UINT32 id; - UINT32 size; -} IxNpeDlImageMgrImageHeader; - -/* module statistics counters */ -typedef struct -{ - UINT32 invalidSignature; - UINT32 imageIdListOverflow; - UINT32 imageIdNotFound; -} IxNpeDlImageMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; - -static UINT32* getIxNpeMicroCodeImageLibrary(void) -{ - char *s; - - if ((s = getenv("npe_ucode")) != NULL) - return (UINT32*) simple_strtoul(s, NULL, 16); - else - return NULL; -} - -/* - * static function prototypes. - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary); - -PRIVATE void -ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId); - -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -#if 0 -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize); - -/* - * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrMicrocodeImageLibraryOverride ( - UINT32 *clientImageLibrary) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n"); - - if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary)) - { - IxNpeMicroCodeImageLibrary = clientImageLibrary; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: " - "Client-supplied image has invalid signature\n"); - status = IX_FAIL; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n", - status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageListExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageListExtract ( - IxNpeDlImageId *imageListPtr, - UINT32 *numImages) -{ - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_SUCCESS; - UINT32 imageCount = 0; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageListExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - /* - * if the image list container from calling function has capacity, - * add the image id to the list - */ - if ((imageListPtr != NULL) && (imageCount < *numImages)) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - imageListPtr[imageCount] = formattedImageId; - } - /* imageCount reflects no. of image entries in image library header */ - imageCount++; - } - - /* - * if image list container from calling function was too small to - * contain all image ids in the header, set return status to FAIL - */ - if ((imageListPtr != NULL) && (imageCount > *numImages)) - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "number of Ids found exceeds list capacity\n"); - ixNpeDlImageMgrStats.imageIdListOverflow++; - } - /* return number of image ids found in image library header */ - *numImages = imageCount; - } - else - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "invalid signature in image\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlImageMgrImageLocate - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageLocate ( - IxNpeDlImageId *imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageLocate\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* if a match for imageId is found in the image library header... */ - if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId)) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - UINT32 *tmp=getIxNpeMicroCodeImageLibrary(); - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &tmp[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - break; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrLatestImageExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId) -{ - UINT32 imageCount = 0; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrLatestImageExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* - * if a match for the npe Id and functionality Id of the imageId is - * found in the image library header... - */ - if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId)) - { - if(imageId->major <= formattedImageId.major) - { - if(imageId->minor < formattedImageId.minor) - { - imageId->minor = formattedImageId.minor; - } - imageId->major = formattedImageId.major; - } - status = IX_SUCCESS; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrSignatureCheck - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) -{ - IxNpeDlImageMgrImageLibraryHeader *header = - (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = true; - - if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) - { - result = false; - ixNpeDlImageMgrStats.invalidSignature++; - } - - return result; -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdFormat - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE void -ixNpeDlImageMgrImageIdFormat ( - UINT32 rawImageId, - IxNpeDlImageId *imageId) -{ - imageId->npeId = (rawImageId >> - IX_NPEDL_IMAGEID_NPEID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->functionalityId = (rawImageId >> - IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->major = (rawImageId >> - IX_NPEDL_IMAGEID_MAJOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->minor = (rawImageId >> - IX_NPEDL_IMAGEID_MINOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId) && - (imageIdA->major == imageIdB->major) && - (imageIdA->minor == imageIdB->minor)) - { - return true; - } - else - { - return false; - } -} - -/* - * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId)) - { - return true; - } - else - { - return false; - } -} - - -/* - * Function definition: ixNpeDlImageMgrStatsShow - */ -void -ixNpeDlImageMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlImageMgrStatsShow:\n" - "\tInvalid Image Signatures: %u\n" - "\tImage Id List capacity too small: %u\n" - "\tImage Id not found: %u\n\n", - ixNpeDlImageMgrStats.invalidSignature, - ixNpeDlImageMgrStats.imageIdListOverflow, - ixNpeDlImageMgrStats.imageIdNotFound, - 0,0,0); -} - - -/* - * Function definition: ixNpeDlImageMgrStatsReset - */ -void -ixNpeDlImageMgrStatsReset (void) -{ - ixNpeDlImageMgrStats.invalidSignature = 0; - ixNpeDlImageMgrStats.imageIdListOverflow = 0; - ixNpeDlImageMgrStats.imageIdNotFound = 0; -} - - -#if 0 -/* - * Function definition: ixNpeDlImageMgrImageFind_legacy - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = false; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageFind\n"); - - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { - imageLibrary = IxNpeMicroCodeImageLibrary; - } - - if (ixNpeDlImageMgrSignatureCheck (imageLibrary)) - { - header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary; - - /* for each image entry in the image library header ... */ - while ((header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound)) - { - /* if a match for imageId is found in the image library header... */ - if (imageId == header->entry[imageCount].image.id) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &imageLibrary[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - imageFound = true; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageFind - */ -IX_STATUS -ixNpeDlImageMgrImageFind ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - IxNpeDlImageMgrImageHeader *image; - UINT32 offset = 0; - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { -#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE - if (ixNpeMicrocode_binaryArray == NULL) - { - printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } - else - { - imageLibrary = ixNpeMicrocode_binaryArray; - } -#else - imageLibrary = getIxNpeMicroCodeImageLibrary(); - if (imageLibrary == NULL) - { - printf ("npe: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } -#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ - } - -#if 0 - /* For backward's compatibility with previous image format */ - if (ixNpeDlImageMgrSignatureCheck(imageLibrary)) - { - return ixNpeDlImageMgrImageFind_legacy(imageLibrary, - imageId, - imagePtr, - imageSize); - } -#endif - - while (*(imageLibrary+offset) == NPE_IMAGE_MARKER) - { - image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset); - offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32); - - if (image->id == imageId) - { - *imagePtr = imageLibrary + offset; - *imageSize = image->size; - return IX_SUCCESS; - } - /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ - else if (image->id == NPE_IMAGE_MARKER) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - /* reached end of library, image not found */ - return IX_FAIL; - } - offset += image->size; - } - - /* If we get here, our image library may be corrupted */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "image library format may be invalid or corrupted\n"); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c deleted file mode 100644 index 8d94dfac3d..0000000000 --- a/drivers/net/npe/IxNpeDlNpeMgr.c +++ /dev/null @@ -1,907 +0,0 @@ -/** - * @file IxNpeDlNpeMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPEDL_BYTES_PER_WORD 4 - -/* used to read download map from version in microcode image */ -#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000 -#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001 -#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002 -#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F - -/* - * masks used to extract address info from State information context - * register addresses as read from microcode image - */ -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 - -/* LSB offset of Context Number field in State-Info Context Address */ -#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4 - -/* size (in words) of single State Information entry (ctxt reg address|data) */ -#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2 - - - #define IX_NPEDL_RESET_NPE_PARITY 0x0800 - #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF - #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF - - -/* - * Typedefs whose scope is limited to this file. - */ - -typedef struct -{ - UINT32 type; - UINT32 offset; -} IxNpeDlNpeMgrDownloadMapBlockEntry; - -typedef union -{ - IxNpeDlNpeMgrDownloadMapBlockEntry block; - UINT32 eodmMarker; -} IxNpeDlNpeMgrDownloadMapEntry; - -typedef struct -{ - /* 1st entry in the download map (there may be more than one) */ - IxNpeDlNpeMgrDownloadMapEntry entry[1]; -} IxNpeDlNpeMgrDownloadMap; - - -/* used to access an instruction or data block in a microcode image */ -typedef struct -{ - UINT32 npeMemAddress; - UINT32 size; - UINT32 data[1]; -} IxNpeDlNpeMgrCodeBlock; - -/* used to access each Context Reg entry state-information block */ -typedef struct -{ - UINT32 addressInfo; - UINT32 value; -} IxNpeDlNpeMgrStateInfoCtxtRegEntry; - -/* used to access a state-information block in a microcode image */ -typedef struct -{ - UINT32 size; - IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; -} IxNpeDlNpeMgrStateInfoBlock; - -/* used to store some useful NPE information for easy access */ -typedef struct -{ - UINT32 baseAddress; - UINT32 insMemSize; - UINT32 dataMemSize; -} IxNpeDlNpeInfo; - -/* used to distinguish instruction and data memory operations */ -typedef enum -{ - IX_NPEDL_MEM_TYPE_INSTRUCTION = 0, - IX_NPEDL_MEM_TYPE_DATA -} IxNpeDlNpeMemType; - -/* used to hold a reset value for a particular ECS register */ -typedef struct -{ - UINT32 regAddr; - UINT32 regResetVal; -} IxNpeDlEcsRegResetValue; - -/* prototype of function to write either Instruction or Data memory */ -typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress, - UINT32 npeMemAddress, - UINT32 npeMemData, - BOOL verify); - -/* module statistics counters */ -typedef struct -{ - UINT32 instructionBlocksLoaded; - UINT32 dataBlocksLoaded; - UINT32 stateInfoBlocksLoaded; - UINT32 criticalNpeErrors; - UINT32 criticalMicrocodeErrors; - UINT32 npeStarts; - UINT32 npeStops; - UINT32 npeResets; -} IxNpeDlNpeMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlNpeInfo ixNpeDlNpeInfo[] = -{ - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEA, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEB, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEC, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC - } -}; - -/* contains Reset values for Context Store Registers */ -static UINT32 ixNpeDlCtxtRegResetValues[] = -{ - IX_NPEDL_CTXT_REG_RESET_STEVT, - IX_NPEDL_CTXT_REG_RESET_STARTPC, - IX_NPEDL_CTXT_REG_RESET_REGMAP, - IX_NPEDL_CTXT_REG_RESET_CINDEX, -}; - -/* contains Reset values for Context Store Registers */ -static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] = -{ - {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET} -}; - -static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats; - -/* Set when NPE register memory has been mapped */ -static BOOL ixNpeDlMemInitialised = false; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *codeBlockPtr, - BOOL verify, IxNpeDlNpeMemType npeMemType); -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr, - BOOL verify); -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset, - UINT32 expectedBitsSet); - -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId); - -/* - * Function definition: ixNpeDlNpeMgrBaseAddressGet - */ -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId) -{ - IX_OSAL_ASSERT (ixNpeDlMemInitialised); - return ixNpeDlNpeInfo[npeId].baseAddress; -} - - -/* - * Function definition: ixNpeDlNpeMgrInit - */ -void -ixNpeDlNpeMgrInit (void) -{ - /* Only map the memory once */ - if (!ixNpeDlMemInitialised) - { - UINT32 virtAddr; - - /* map the register memory for NPE-A */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr; - - /* map the register memory for NPE-B */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr; - - /* map the register memory for NPE-C */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr; - - ixNpeDlMemInitialised = true; - } -} - - -/* - * Function definition: ixNpeDlNpeMgrUninit - */ -IX_STATUS -ixNpeDlNpeMgrUninit (void) -{ - if (!ixNpeDlMemInitialised) - { - return IX_FAIL; - } - - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress); - - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0; - - ixNpeDlMemInitialised = false; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeDlNpeMgrImageLoad - */ -IX_STATUS -ixNpeDlNpeMgrImageLoad ( - IxNpeDlNpeId npeId, - UINT32 *imageCodePtr, - BOOL verify) -{ - UINT32 npeBaseAddress; - IxNpeDlNpeMgrDownloadMap *downloadMap; - UINT32 *blockPtr; - UINT32 mapIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrImageLoad\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* check execution status of NPE to verify NPE Stop was successful */ - if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - " - "NPE was not stopped before download\n"); - status = IX_FAIL; - } - else - { - /* - * Read Download Map, checking each block type and calling - * appropriate function to perform download - */ - downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr; - while ((downloadMap->entry[mapIndex].eodmMarker != - IX_NPEDL_END_OF_DOWNLOAD_MAP) - && (status == IX_SUCCESS)) - { - /* calculate pointer to block to be downloaded */ - blockPtr = imageCodePtr + - downloadMap->entry[mapIndex].block.offset; - - switch (downloadMap->entry[mapIndex].block.type) - { - case IX_NPEDL_BLOCK_TYPE_INSTRUCTION: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, - IX_NPEDL_MEM_TYPE_INSTRUCTION); - break; - case IX_NPEDL_BLOCK_TYPE_DATA: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, IX_NPEDL_MEM_TYPE_DATA); - break; - case IX_NPEDL_BLOCK_TYPE_STATE: - status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress, - (IxNpeDlNpeMgrStateInfoBlock *) blockPtr, - verify); - break; - default: - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: " - "unknown block type in download map\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; - } - mapIndex++; - }/* loop: for each entry in download map, while status == SUCCESS */ - }/* condition: NPE stopped before attempting download */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrMemLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad ( - IxNpeDlNpeId npeId, - UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *blockPtr, - BOOL verify, - IxNpeDlNpeMemType npeMemType) -{ - UINT32 npeMemAddress; - UINT32 blockSize; - UINT32 memSize = 0; - IxNpeDlNpeMgrMemWrite memWriteFunc = NULL; - UINT32 localIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrMemLoad\n"); - - /* - * select NPE EXCTL reg read/write commands depending on memory - * type (instruction/data) to be accessed - */ - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - memSize = ixNpeDlNpeInfo[npeId].insMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - memSize = ixNpeDlNpeInfo[npeId].dataMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite; - } - - /* - * NPE memory is loaded contiguously from each block, so only address - * of 1st word in block is needed - */ - npeMemAddress = blockPtr->npeMemAddress; - /* number of words of instruction/data microcode in block to download */ - blockSize = blockPtr->size; - if ((npeMemAddress + blockSize) > memSize) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "Block size too big for NPE memory\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - } - else - { - for (localIndex = 0; localIndex < blockSize; localIndex++) - { - status = memWriteFunc (npeBaseAddress, npeMemAddress, - blockPtr->data[localIndex], verify); - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "write to NPE memory failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - /* increment target (word)address in NPE memory */ - npeMemAddress++; - } - }/* condition: block size will fit in NPE memory */ - - if (status == IX_SUCCESS) - { - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - ixNpeDlNpeMgrStats.instructionBlocksLoaded++; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - ixNpeDlNpeMgrStats.dataBlocksLoaded++; - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrStateInfoLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad ( - UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *blockPtr, - BOOL verify) -{ - UINT32 blockSize; - UINT32 ctxtRegAddrInfo; - UINT32 ctxtRegVal; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 i; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrStateInfoLoad\n"); - - /* block size contains number of words of state-info in block */ - blockSize = blockPtr->size; - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* for each state-info context register entry in block */ - for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++) - { - /* each state-info entry is 2 words (address, value) in length */ - ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo; - ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value; - - ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG); - ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> - IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM; - - /* error-check Context Register No. and Context Number values */ - /* NOTE that there is no STEVT register for Context 0 */ - if ((ctxtReg < 0) || - (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) || - (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) || - ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "invalid Context Register Address\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; /* abort download */ - } - - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg, - ctxtRegVal, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "write of state-info to NPE failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - }/* loop: for each context reg entry in State Info block */ - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - if (status == IX_SUCCESS) - { - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeReset - */ -IX_STATUS -ixNpeDlNpeMgrNpeReset ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 regAddr; - UINT32 regVal; - UINT32 localIndex; - UINT32 indexMax; - IX_STATUS status = IX_SUCCESS; - IxFeatureCtrlReg unitFuseReg; - UINT32 ixNpeConfigCtrlRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeReset\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* pre-store the NPE Config Control Register Value */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal); - - ixNpeConfigCtrlRegVal |= 0x3F000000; - - /* disable the parity interrupt */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK)); - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* - * clear the FIFOs - */ - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_WFIFO, - IX_NPEDL_MASK_WFIFO_VALID)) - { - /* read from the Watch-point FIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_OFNE)) - { - /* read from the outFIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_IFNE)) - { - /* - * step execution of the NPE intruction to read inFIFO using - * the Debug Executing Context stack - */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RD_FIFO, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - } - - /* - * Reset the mailbox reg - */ - /* ...from XScale side */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST, - IX_NPEDL_REG_RESET_MBST); - /* ...from NPE side */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RESET_MBOX, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - /* - * Reset the physical registers in the NPE register file: - * Note: no need to save/restore REGMAP for Context 0 here - * since all Context Store regs are reset in subsequent code - */ - for (regAddr = 0; - (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL); - regAddr++) - { - /* for each physical register in the NPE reg file, write 0 : */ - status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr, - 0, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - - - /* - * Reset the context store: - */ - for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN; - ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++) - { - /* set each context's Context Store registers to reset values: */ - for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) - { - /* NOTE that there is no STEVT register for Context 0 */ - if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, - ctxtReg, regVal, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - } - } - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - /* write Reset values to Execution Context Stack registers */ - indexMax = sizeof (ixNpeDlEcsRegResetValues) / - sizeof (IxNpeDlEcsRegResetValue); - for (localIndex = 0; localIndex < indexMax; localIndex++) - { - regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr; - regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal); - } - - /* clear the profile counter */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT); - - /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ - for (regAddr = IX_NPEDL_REG_OFFSET_EXCT; - regAddr <= IX_NPEDL_REG_OFFSET_AP3; - regAddr += IX_NPEDL_BYTES_PER_WORD) - { - IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0); - } - - /* Reset the Watch-count register */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0); - - /* - * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation - */ - - /* - * Call the feature control API to fused out and reset the NPE and its - * coprocessor - to reset internal states and remove parity error - */ - unitFuseReg = ixFeatureCtrlRead (); - unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId); - ixFeatureCtrlWrite (unitFuseReg); - - /* call the feature control API to un-fused and un-reset the NPE & COP */ - unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId)); - ixFeatureCtrlWrite (unitFuseReg); - - /* - * Call NpeMgr function to stop the NPE again after the Feature Control - * has unfused and Un-Reset the NPE and its associated Coprocessors - */ - status = ixNpeDlNpeMgrNpeStop (npeId); - - /* restore NPE configuration bus Control Register - Parity Settings */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, - (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK)); - - ixNpeDlNpeMgrStats.npeResets++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStart - */ -IX_STATUS -ixNpeDlNpeMgrNpeStart ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - UINT32 ecsRegVal; - BOOL npeRunning; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStart\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* - * ensure only Background Context Stack Level is Active by turning off - * the Active bit in each of the other Executing Context Stack levels - */ - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_1_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_2_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* start NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START); - - /* - * check execution status of NPE to verify NPE Start operation was - * successful - */ - npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_RUN); - if (npeRunning) - { - ixNpeDlNpeMgrStats.npeStarts++; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: " - "failed to start NPE execution\n"); - status = IX_FAIL; - } - - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStop - */ -IX_STATUS -ixNpeDlNpeMgrNpeStop ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStop\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* stop NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP); - - /* verify that NPE Stop was successful */ - if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: " - "failed to stop NPE execution\n"); - status = IX_FAIL; - } - - ixNpeDlNpeMgrStats.npeStops++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrBitsSetCheck - */ -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck ( - UINT32 npeBaseAddress, - UINT32 regOffset, - UINT32 expectedBitsSet) -{ - UINT32 regVal; - IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val); - - return expectedBitsSet == (expectedBitsSet & regVal); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsShow - */ -void -ixNpeDlNpeMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrStatsShow:\n" - "\tInstruction Blocks loaded: %u\n" - "\tData Blocks loaded: %u\n" - "\tState Information Blocks loaded: %u\n" - "\tCritical NPE errors: %u\n" - "\tCritical Microcode errors: %u\n", - ixNpeDlNpeMgrStats.instructionBlocksLoaded, - ixNpeDlNpeMgrStats.dataBlocksLoaded, - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded, - ixNpeDlNpeMgrStats.criticalNpeErrors, - ixNpeDlNpeMgrStats.criticalMicrocodeErrors, - 0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tSuccessful NPE Starts: %u\n" - "\tSuccessful NPE Stops: %u\n" - "\tSuccessful NPE Resets: %u\n\n", - ixNpeDlNpeMgrStats.npeStarts, - ixNpeDlNpeMgrStats.npeStops, - ixNpeDlNpeMgrStats.npeResets, - 0,0,0); - - ixNpeDlNpeMgrUtilsStatsShow (); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsReset - */ -void -ixNpeDlNpeMgrStatsReset (void) -{ - ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0; - ixNpeDlNpeMgrStats.dataBlocksLoaded = 0; - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0; - ixNpeDlNpeMgrStats.criticalNpeErrors = 0; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0; - ixNpeDlNpeMgrStats.npeStarts = 0; - ixNpeDlNpeMgrStats.npeStops = 0; - ixNpeDlNpeMgrStats.npeResets = 0; - - ixNpeDlNpeMgrUtilsStatsReset (); -} diff --git a/drivers/net/npe/IxNpeDlNpeMgrUtils.c b/drivers/net/npe/IxNpeDlNpeMgrUtils.c deleted file mode 100644 index db50d22d1b..0000000000 --- a/drivers/net/npe/IxNpeDlNpeMgrUtils.c +++ /dev/null @@ -1,782 +0,0 @@ -/** - * @file IxNpeDlNpeMgrUtils.c - * - * @author Intel Corporation - * @date 18 February 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr Utils module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * #defines and macros used in this file. - */ - -/* used to bit-mask a number of bytes */ -#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF -#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF -#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF - -#define IX_NPEDL_BYTES_PER_WORD 4 -#define IX_NPEDL_BYTES_PER_SHORT 2 - -#define IX_NPEDL_REG_SIZE_BYTE 8 -#define IX_NPEDL_REG_SIZE_SHORT 16 -#define IX_NPEDL_REG_SIZE_WORD 32 - -/* - * Introduce extra read cycles after issuing read command to NPE - * so that we read the register after the NPE has updated it - * This is to overcome race condition between XScale and NPE - */ -#define IX_NPEDL_DELAY_READ_CYCLES 2 -/* - * To mask top three MSBs of 32bit word to download into NPE IMEM - */ -#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF; - - -/* - * typedefs - */ -typedef struct -{ - UINT32 regAddress; - UINT32 regSize; -} IxNpeDlCtxtRegAccessInfo; - -/* module statistics counters */ -typedef struct -{ - UINT32 insMemWrites; - UINT32 insMemWriteFails; - UINT32 dataMemWrites; - UINT32 dataMemWriteFails; - UINT32 ecsRegWrites; - UINT32 ecsRegReads; - UINT32 dbgInstructionExecs; - UINT32 contextRegWrites; - UINT32 physicalRegWrites; - UINT32 nextPcWrites; -} IxNpeDlNpeMgrUtilsStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * contains useful address and function pointers to read/write Context Regs, - * eliminating some switch or if-else statements in places - */ -static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] = -{ - { - IX_NPEDL_CTXT_REG_ADDR_STEVT, - IX_NPEDL_REG_SIZE_BYTE - }, - { - IX_NPEDL_CTXT_REG_ADDR_STARTPC, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_CINDEX, - IX_NPEDL_REG_SIZE_BYTE - } -}; - -static UINT32 ixNpeDlSavedExecCount = 0; -static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0; - -static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats; - - -/* - * static function prototypes. - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, - UINT32 addr, UINT32 data); - -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regVal, UINT32 regSize, - UINT32 ctxtNum, BOOL verify); - -/* - * Function definition: ixNpeDlNpeMgrWriteCommandIssue - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr, - UINT32 data) -{ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); -} - - -/* - * Function definition: ixNpeDlNpeMgrReadCommandIssue - */ -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr) -{ - UINT32 data = 0; - int i; - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); - for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++) - { - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data); - } - - return data; -} - -/* - * Function definition: ixNpeDlNpeMgrInsMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrInsMemWrite ( - UINT32 npeBaseAddress, - UINT32 insMemAddress, - UINT32 insMemData, - BOOL verify) -{ - UINT32 insMemDataRtn; - - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_INS_MEM, - insMemAddress, insMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, - ~insMemData); - - /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/ - insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_INS_MEM, - insMemAddress); - - insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - if (insMemData != insMemDataRtn) - { - ixNpeDlNpeMgrUtilsStats.insMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.insMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrDataMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrDataMemWrite ( - UINT32 npeBaseAddress, - UINT32 dataMemAddress, - UINT32 dataMemData, - BOOL verify) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, - dataMemAddress, dataMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData); - - if (dataMemData != - ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, - dataMemAddress)) - { - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.dataMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegWrite - */ -void -ixNpeDlNpeMgrExecAccRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddress, - UINT32 regData) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_ECS_REG, - regAddress, regData); - ixNpeDlNpeMgrUtilsStats.ecsRegWrites++; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegRead - */ -UINT32 -ixNpeDlNpeMgrExecAccRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddress) -{ - ixNpeDlNpeMgrUtilsStats.ecsRegReads++; - return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_ECS_REG, - regAddress); -} - - -/* - * Function definition: ixNpeDlNpeMgrCommandIssue - */ -void -ixNpeDlNpeMgrCommandIssue ( - UINT32 npeBaseAddress, - UINT32 command) -{ - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCommandIssue\n"); - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCommandIssue\n"); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec - */ -void -ixNpeDlNpeMgrDebugInstructionPreExec( - UINT32 npeBaseAddress) -{ - /* turn off the halt bit by clearing Execution Count register. */ - /* save reg contents 1st and restore later */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - &ixNpeDlSavedExecCount); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0); - - /* ensure that IF and IE are on (temporarily), so that we don't end up - * stepping forever */ - ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_2); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - (ixNpeDlSavedEcsDbgCtxtReg2 | - IX_NPEDL_MASK_ECS_DBG_REG_2_IF | - IX_NPEDL_MASK_ECS_DBG_REG_2_IE)); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionExec - */ -IX_STATUS -ixNpeDlNpeMgrDebugInstructionExec( - UINT32 npeBaseAddress, - UINT32 npeInstruction, - UINT32 ctxtNum, - UINT32 ldur) -{ - UINT32 ecsDbgRegVal; - UINT32 oldWatchcount, newWatchcount; - UINT32 retriesCount = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrDebugInstructionExec\n"); - - /* set the Active bit, and the LDUR, in the debug level */ - ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE | - (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsDbgRegVal); - - /* - * set CCTXT at ECS DEBUG L3 to specify in which context to execute the - * instruction, and set SELCTXT at ECS DEBUG Level to specify which context - * store to access. - * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number - */ - ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) | - (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1, - ecsDbgRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* load NPE instruction into the instruction register */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG, - npeInstruction); - - /* we need this value later to wait for completion of NPE execution step */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount); - - /* issue a Step One command via the Execution Control register */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP); - - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - /* - * force the XScale to wait until the NPE has finished execution step - * NOTE that this delay will be very small, just long enough to allow a - * single NPE instruction to complete execution; if instruction execution - * is not completed before timeout retries, exit the while loop - */ - while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - && (newWatchcount == oldWatchcount)) - { - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - retriesCount++; - } - - if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - { - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++; - } - else - { - /* Return timeout status as the instruction has not been executed - * after maximum retries */ - status = IX_NPEDL_CRITICAL_NPE_ERR; - } - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrDebugInstructionExec\n"); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec - */ -void -ixNpeDlNpeMgrDebugInstructionPostExec( - UINT32 npeBaseAddress) -{ - /* clear active bit in debug level */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - 0); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* restore Execution Count register contents. */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - ixNpeDlSavedExecCount); - - /* restore IF and IE bits to original values */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - ixNpeDlSavedEcsDbgCtxtReg2); -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegRead - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regSize, - UINT32 ctxtNum, - UINT32 *regVal) -{ - IX_STATUS status = IX_SUCCESS; - UINT32 npeInstruction = 0; - UINT32 mask = 0; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegRead\n"); - - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - case IX_NPEDL_REG_SIZE_WORD: - npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD; - mask = IX_NPEDL_MASK_FULL_WORD; break; - } - - /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | - (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* step execution of NPE intruction using Debug Executing Context stack */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_RD_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - - /* read value of register from Execution Data register */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal); - - /* align value from left to right */ - *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegRead\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegWrite - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regVal, - UINT32 regSize, - UINT32 ctxtNum, - BOOL verify) -{ - UINT32 npeInstruction = 0; - UINT32 mask = 0; - IX_STATUS status = IX_SUCCESS; - UINT32 retRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegWrite\n"); - - if (regSize == IX_NPEDL_REG_SIZE_WORD) - { - /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ - /* Write upper half-word (short) to |d0|d1| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, - regVal >> IX_NPEDL_REG_SIZE_SHORT, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - - /* Write lower half-word (short) to |d2|d3| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - regAddr + IX_NPEDL_BYTES_PER_SHORT, - regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - } - else - { - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - } - /* mask out any redundant bits, so verify will work later */ - regVal &= mask; - - /* fill dest operand field of instruction with destination reg addr */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* fill src operand field of instruction with least-sig 5 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << - IX_NPEDL_OFFSET_INSTR_SRC); - - /* fill coprocessor field of instruction with most-sig 11 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << - IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); - - /* step execution of NPE intruction using Debug ECS */ - status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_WR_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */ - - if (verify) - { - status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, - regSize, ctxtNum, &retRegVal); - - if (IX_SUCCESS == status) - { - if (regVal != retRegVal) - { - status = IX_FAIL; - } - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrPhysicalRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrPhysicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regValue, - BOOL verify) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrPhysicalRegWrite\n"); - -/* - * There are 32 physical registers used in an NPE. These are - * treated as 16 pairs of 32-bit registers. To write one of the pair, - * write the pair number (0-16) to the REGMAP for Context 0. Then write - * the value to register 0 or 4 in the regfile, depending on which - * register of the pair is to be written - */ - - /* - * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) - * of physical registers to write - */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - (regAddr >> - IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP), - IX_NPEDL_REG_SIZE_SHORT, 0, verify); - if (status == IX_SUCCESS) - { - /* regAddr = 0 or 4 */ - regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * - IX_NPEDL_BYTES_PER_WORD; - - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue, - IX_NPEDL_REG_SIZE_WORD, 0, verify); - } - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: " - "error writing to physical register\n"); - } - - ixNpeDlNpeMgrUtilsStats.physicalRegWrites++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrCtxtRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrCtxtRegWrite ( - UINT32 npeBaseAddress, - UINT32 ctxtNum, - IxNpeDlCtxtRegNum ctxtReg, - UINT32 ctxtRegVal, - BOOL verify) -{ - UINT32 tempRegVal; - UINT32 ctxtRegAddr; - UINT32 ctxtRegSize; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCtxtRegWrite\n"); - - /* - * Context 0 has no STARTPC. Instead, this value is used to set - * NextPC for Background ECS, to set where NPE starts executing code - */ - if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC)) - { - /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ - tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0); - tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) & - IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal); - - ixNpeDlNpeMgrUtilsStats.nextPcWrites++; - } - else - { - ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress; - ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize; - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr, - ctxtRegVal, ctxtRegSize, - ctxtNum, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: " - "error writing to context store register\n"); - } - - ixNpeDlNpeMgrUtilsStats.contextRegWrites++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsShow - */ -void -ixNpeDlNpeMgrUtilsStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrUtilsStatsShow:\n" - "\tInstruction Memory writes: %u\n" - "\tInstruction Memory writes failed: %u\n" - "\tData Memory writes: %u\n" - "\tData Memory writes failed: %u\n", - ixNpeDlNpeMgrUtilsStats.insMemWrites, - ixNpeDlNpeMgrUtilsStats.insMemWriteFails, - ixNpeDlNpeMgrUtilsStats.dataMemWrites, - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails, - 0,0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tExecuting Context Stack Register writes: %u\n" - "\tExecuting Context Stack Register reads: %u\n" - "\tPhysical Register writes: %u\n" - "\tContext Store Register writes: %u\n" - "\tExecution Backgound Context NextPC writes: %u\n" - "\tDebug Instructions Executed: %u\n\n", - ixNpeDlNpeMgrUtilsStats.ecsRegWrites, - ixNpeDlNpeMgrUtilsStats.ecsRegReads, - ixNpeDlNpeMgrUtilsStats.physicalRegWrites, - ixNpeDlNpeMgrUtilsStats.contextRegWrites, - ixNpeDlNpeMgrUtilsStats.nextPcWrites, - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs); -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsReset - */ -void -ixNpeDlNpeMgrUtilsStatsReset (void) -{ - ixNpeDlNpeMgrUtilsStats.insMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0; - ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0; - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0; -} diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c deleted file mode 100644 index 5adabd82fc..0000000000 --- a/drivers/net/npe/IxNpeMh.c +++ /dev/null @@ -1,558 +0,0 @@ -/** - * @file IxNpeMh.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Message Handler component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMh.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE BOOL ixNpeMhInitialized = false; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhInitialize - */ - -PUBLIC IX_STATUS ixNpeMhInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhInitialize\n"); - - /* check the npeInterrupts parameter */ - if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) && - (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES)) - { - IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* initialize the Receive module */ - ixNpeMhReceiveInitialize (); - - /* initialize the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrInitialize (); - - /* initialize the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrInitialize (); - - /* initialize the Configuration module - * - * NOTE: This module was originally configured before the - * others, but the sequence was changed so that interrupts - * would only be enabled after the handler functions were - * set up. The above modules need to be initialised to - * handle the NPE interrupts. See SCR #2231. - */ - ixNpeMhConfigInitialize (npeInterrupts); - - ixNpeMhInitialized = true; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhInitialize\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnload - */ - -PUBLIC IX_STATUS ixNpeMhUnload (void) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnload\n"); - - if (!ixNpeMhInitialized) - { - return IX_FAIL; - } - - /* Uninitialize the Configuration module */ - ixNpeMhConfigUninit (); - - ixNpeMhInitialized = false; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnload\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeMhUnsolicitedCallbackRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId messageId, - IxNpeMhCallback unsolicitedCallback) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the messageId parameter */ - if ((messageId < IX_NPEMH_MIN_MESSAGE_ID) - || (messageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId minMessageId, - IxNpeMhMessageId maxMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhMessageId messageId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the minMessageId parameter */ - if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n"); - return IX_FAIL; - } - - /* check the maxMessageId parameter */ - if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n"); - return IX_FAIL; - } - - /* check the semantics of the message range parameters */ - if (minMessageId > maxMessageId) - { - IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message " - "ID\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* for each message ID in the range ... */ - for (messageId = minMessageId; messageId <= maxMessageId; messageId++) - { - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhMessageSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessageWithResponseSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - IxNpeMhCallback unsolicitedCallback = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageWithResponseSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* the solicitecCallback parameter is allowed to be NULL. this */ - /* signifies the client is not interested in the response message */ - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter */ - if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter. if an unsolicited */ - /* callback has been registered for the specified message ID then */ - /* report an error and return failure */ - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, solicitedMessageId, &unsolicitedCallback); - if (unsolicitedCallback != NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with " - "unsolicited message ID\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageWithResponseSend ( - npeId, message, solicitedMessageId, solicitedCallback, - maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageWithResponseSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessagesReceive - */ - -PUBLIC IX_STATUS ixNpeMhMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessagesReceive\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* receive messages from the NPE */ - status = ixNpeMhReceiveMessagesReceive (npeId); - - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to receive message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessagesReceive" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhShow - */ - -PUBLIC IX_STATUS ixNpeMhShow ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShow\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as printing the statistics */ - /* to a console may take some time and we don't want to impact */ - /* system performance. this means that the statistics displayed */ - /* may be in a state of flux and make not represent a consistent */ - /* snapshot. */ - - /* display a header */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0); - - /* show the current state of each module */ - - /* show the current state of the Configuration module */ - ixNpeMhConfigShow (npeId); - - /* show the current state of the Receive module */ - ixNpeMhReceiveShow (npeId); - - /* show the current state of the Send module */ - ixNpeMhSendShow (npeId); - - /* show the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShow (npeId); - - /* show the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShow (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShow\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhShowReset - */ - -PUBLIC IX_STATUS ixNpeMhShowReset ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShowReset\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as resetting the statistics */ - /* shouldn't impact system performance. */ - - /* reset the current state of each module */ - - /* reset the current state of the Configuration module */ - ixNpeMhConfigShowReset (npeId); - - /* reset the current state of the Receive module */ - ixNpeMhReceiveShowReset (npeId); - - /* reset the current state of the Send module */ - ixNpeMhSendShowReset (npeId); - - /* reset the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShowReset (npeId); - - /* reset the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShowReset (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShowReset\n"); - - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c deleted file mode 100644 index eaa9a21ad7..0000000000 --- a/drivers/net/npe/IxNpeMhConfig.c +++ /dev/null @@ -1,584 +0,0 @@ -/** - * @file IxNpeMhConfig.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Configuration module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhConfigStats - * - * @brief This structure is used to maintain statistics for the - * Configuration module. - */ - -typedef struct -{ - UINT32 outFifoReads; /**< outFifo reads */ - UINT32 inFifoWrites; /**< inFifo writes */ - UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */ - UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */ -} IxNpeMhConfigStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = -{ - { - 0, - IX_NPEMH_NPEA_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEB_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEC_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - } -}; - -PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhConfigIsr (void *parameter); - -/* - * Function definition: ixNpeMhConfigIsr - */ - -PRIVATE -void ixNpeMhConfigIsr (void *parameter) -{ - IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter; - UINT32 ofint; - volatile UINT32 *statusReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsr\n"); - - /* get the OFINT (OutFifo interrupt) bit of the status register */ - IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT); - - /* if the OFINT status bit is set */ - if (ofint) - { - /* if there is an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - /* invoke the ISR routine */ - ixNpeMhConfigNpeInfo[npeId].isr (npeId); - } - else - { - /* if we don't service the interrupt the NPE will continue */ - /* to trigger the interrupt indefinitely */ - IX_NPEMH_ERROR_REPORT ("No ISR registered to service " - "interrupt\n"); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsr\n"); -} - -/* - * Function definition: ixNpeMhConfigInitialize - */ - -void ixNpeMhConfigInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IxNpeMhNpeId npeId; - UINT32 virtualAddr[IX_NPEMH_NUM_NPES]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigInitialize\n"); - - /* Request a mapping for the NPE-A config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEA] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]); - - /* Request a mapping for the NPE-B config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEB] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]); - - /* Request a mapping for the NPE-C config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEC] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* store the virtual addresses of the NPE registers for later use */ - npeInfo->virtualRegisterBase = virtualAddr[npeId]; - npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET; - npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET; - npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - - /* for test purposes - to verify the register addresses */ - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = " - "0x%08X\n", npeId, npeInfo->statusRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = " - "0x%08X\n", npeId, npeInfo->controlRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = " - "0x%08X\n", npeId, npeInfo->inFifoRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = " - "0x%08X\n", npeId, npeInfo->outFifoRegister); - - /* connect our ISR to the NPE interrupt */ - (void) ixOsalIrqBind ( - npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId); - - /* initialise a mutex for this NPE */ - (void) ixOsalMutexInit (&npeInfo->mutex); - - /* if we should service the NPE's "outFIFO not empty" interrupt */ - if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptEnable (npeId); - } - else - { - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptDisable (npeId); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigInitialize\n"); -} - -/* - * Function definition: ixNpeMhConfigUninit - */ - -void ixNpeMhConfigUninit (void) -{ - IxNpeMhNpeId npeId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigUninit\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* disconnect ISR */ - ixOsalIrqUnbind(npeInfo->interruptId); - - /* destroy mutex associated with this NPE */ - ixOsalMutexDestroy(&npeInfo->mutex); - - IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase); - - npeInfo->virtualRegisterBase = 0; - npeInfo->statusRegister = 0; - npeInfo->controlRegister = 0; - npeInfo->inFifoRegister = 0; - npeInfo->outFifoRegister = 0; - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigUninit\n"); -} - -/* - * Function definition: ixNpeMhConfigIsrRegister - */ - -void ixNpeMhConfigIsrRegister ( - IxNpeMhNpeId npeId, - IxNpeMhConfigIsr isr) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsrRegister\n"); - - /* check if there is already an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n"); - } - - /* save the ISR routine with the NPE info */ - ixNpeMhConfigNpeInfo[npeId].isr = isr; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsrRegister\n"); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptEnable - */ - -BOOL ixNpeMhConfigNpeInterruptEnable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is disabled then we must enable it */ - if (!ofe) - { - /* set the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptDisable - */ - -BOOL ixNpeMhConfigNpeInterruptDisable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is enabled then we must disable it */ - if (ofe) - { - /* unset the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (0 | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigMessageIdGet - */ - -IxNpeMhMessageId ixNpeMhConfigMessageIdGet ( - IxNpeMhMessage message) -{ - /* return the most-significant byte of the first word of the */ - /* message */ - return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF)); -} - -/* - * Function definition: ixNpeMhConfigNpeIdIsValid - */ - -BOOL ixNpeMhConfigNpeIdIsValid ( - IxNpeMhNpeId npeId) -{ - /* check that the npeId parameter is within the range of valid IDs */ - return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES); -} - -/* - * Function definition: ixNpeMhConfigLockGet - */ - -void ixNpeMhConfigLockGet ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockGet\n"); - - /* lock the mutex for this NPE */ - (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, - IX_OSAL_WAIT_FOREVER); - - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptDisable (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockGet\n"); -} - -/* - * Function definition: ixNpeMhConfigLockRelease - */ - -void ixNpeMhConfigLockRelease ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockRelease\n"); - - /* if the interrupt was previously enabled */ - if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptEnable (npeId); - } - - /* unlock the mutex for this NPE */ - (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockRelease\n"); -} - -/* - * Function definition: ixNpeMhConfigInFifoWrite - */ - -IX_STATUS ixNpeMhConfigInFifoWrite ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message) -{ - volatile UINT32 *npeInFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister; - UINT32 retriesCount = 0; - - /* write the first word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]); - - /* need to wait for room to write second word - see SCR #493, - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigInFifoIsFull (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* write the second word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].inFifoWrites++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigOutFifoRead - */ - -IX_STATUS ixNpeMhConfigOutFifoRead ( - IxNpeMhNpeId npeId, - IxNpeMhMessage *message) -{ - volatile UINT32 *npeOutFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister; - UINT32 retriesCount = 0; - - /* read the first word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]); - - /* need to wait for NPE to write second word - see SCR #493 - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* read the second word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].outFifoReads++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigShow - */ - -void ixNpeMhConfigShow ( - IxNpeMhNpeId npeId) -{ - /* show the message fifo read counter */ - IX_NPEMH_SHOW ("Message FIFO reads", - ixNpeMhConfigStats[npeId].outFifoReads); - - /* show the message fifo write counter */ - IX_NPEMH_SHOW ("Message FIFO writes", - ixNpeMhConfigStats[npeId].inFifoWrites); - - /* show the max retries performed when inFIFO full */ - IX_NPEMH_SHOW ("Max inFIFO Full retries", - ixNpeMhConfigStats[npeId].maxInFifoFullRetries); - - /* show the max retries performed when outFIFO empty */ - IX_NPEMH_SHOW ("Max outFIFO Empty retries", - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries); - - /* show the current status of the inFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "InFifo is %s and %s\n", - (ixNpeMhConfigInFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigInFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); - - /* show the current status of the outFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "OutFifo is %s and %s\n", - (ixNpeMhConfigOutFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigOutFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); -} - -/* - * Function definition: ixNpeMhConfigShowReset - */ - -void ixNpeMhConfigShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message fifo read counter */ - ixNpeMhConfigStats[npeId].outFifoReads = 0; - - /* reset the message fifo write counter */ - ixNpeMhConfigStats[npeId].inFifoWrites = 0; - - /* reset the max inFIFO Full retries counter */ - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0; - - /* reset the max outFIFO empty retries counter */ - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0; -} - - diff --git a/drivers/net/npe/IxNpeMhReceive.c b/drivers/net/npe/IxNpeMhReceive.c deleted file mode 100644 index 273c3733f3..0000000000 --- a/drivers/net/npe/IxNpeMhReceive.c +++ /dev/null @@ -1,296 +0,0 @@ -/** - * @file IxNpeMhReceive.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Receive module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhReceiveStats - * - * @brief This structure is used to maintain statistics for the Receive - * module. - */ - -typedef struct -{ - UINT32 isrs; /**< receive ISR invocations */ - UINT32 receives; /**< receive messages invocations */ - UINT32 messages; /**< messages received */ - UINT32 solicited; /**< solicited messages received */ - UINT32 unsolicited; /**< unsolicited messages received */ - UINT32 callbacks; /**< callbacks invoked */ -} IxNpeMhReceiveStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhReceiveIsr (int npeId); - -PRIVATE -void ixNpeMhReceiveIsr (int npeId) -{ - int lockKey; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveIsr\n"); - - lockKey = ixOsalIrqLock (); - - /* invoke the message receive routine to get messages from the NPE */ - ixNpeMhReceiveMessagesReceive (npeId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].isrs++; - - ixOsalIrqUnlock (lockKey); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveIsr\n"); -} - -/* - * Function definition: ixNpeMhReceiveInitialize - */ - -void ixNpeMhReceiveInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* register our internal ISR for the NPE to handle "outFIFO not */ - /* empty" interrupts */ - ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveInitialize\n"); -} - -/* - * Function definition: ixNpeMhReceiveMessagesReceive - */ - -IX_STATUS ixNpeMhReceiveMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IxNpeMhMessage message = { { 0, 0 } }; - IxNpeMhMessageId messageId = 0; - IxNpeMhCallback callback = NULL; - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveMessagesReceive\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].receives++; - - /* while the NPE has messages in its outFIFO */ - while (!ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - /* read a message from the NPE's outFIFO */ - status = ixNpeMhConfigOutFifoRead (npeId, &message); - - if (IX_SUCCESS != status) - { - return status; - } - - /* get the ID of the message */ - messageId = ixNpeMhConfigMessageIdGet (message); - - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, - "Received message from NPE %d with ID 0x%02X\n", - npeId, messageId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].messages++; - - /* try to find a matching unsolicited callback for this message. */ - - /* we assume the message is unsolicited. only if there is no */ - /* unsolicited callback for this message type do we assume the */ - /* message is solicited. it is much faster to check for an */ - /* unsolicited callback, so doing this check first should result */ - /* in better performance. */ - - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching unsolicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].unsolicited++; - } - - /* if no unsolicited callback was found try to find a matching */ - /* solicited callback for this message */ - if (callback == NULL) - { - ixNpeMhSolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching solicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].solicited++; - } - } - - /* if a callback (either unsolicited or solicited) was found */ - if (callback != NULL) - { - /* invoke the callback to pass the message back to the client */ - callback (npeId, message); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].callbacks++; - } - else /* no callback (neither unsolicited nor solicited) was found */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_WARNING, - "No matching callback for NPE %d" - " and ID 0x%02X, discarding message\n", - npeId, messageId); - - /* the message will be discarded. this is normal behaviour */ - /* if the client passes a NULL solicited callback when */ - /* sending a message. this indicates that the client is not */ - /* interested in receiving the response. alternatively a */ - /* NULL callback here may signify an unsolicited message */ - /* with no appropriate registered callback. */ - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveMessagesReceive\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhReceiveShow - */ - -void ixNpeMhReceiveShow ( - IxNpeMhNpeId npeId) -{ - /* show the ISR invocation counter */ - IX_NPEMH_SHOW ("Receive ISR invocations", - ixNpeMhReceiveStats[npeId].isrs); - - /* show the receive message invocation counter */ - IX_NPEMH_SHOW ("Receive messages invocations", - ixNpeMhReceiveStats[npeId].receives); - - /* show the message received counter */ - IX_NPEMH_SHOW ("Messages received", - ixNpeMhReceiveStats[npeId].messages); - - /* show the solicited message counter */ - IX_NPEMH_SHOW ("Solicited messages received", - ixNpeMhReceiveStats[npeId].solicited); - - /* show the unsolicited message counter */ - IX_NPEMH_SHOW ("Unsolicited messages received", - ixNpeMhReceiveStats[npeId].unsolicited); - - /* show the callback invoked counter */ - IX_NPEMH_SHOW ("Callbacks invoked", - ixNpeMhReceiveStats[npeId].callbacks); - - /* show the message discarded counter */ - IX_NPEMH_SHOW ("Received messages discarded", - (ixNpeMhReceiveStats[npeId].messages - - ixNpeMhReceiveStats[npeId].callbacks)); -} - -/* - * Function definition: ixNpeMhReceiveShowReset - */ - -void ixNpeMhReceiveShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the ISR invocation counter */ - ixNpeMhReceiveStats[npeId].isrs = 0; - - /* reset the receive message invocation counter */ - ixNpeMhReceiveStats[npeId].receives = 0; - - /* reset the message received counter */ - ixNpeMhReceiveStats[npeId].messages = 0; - - /* reset the solicited message counter */ - ixNpeMhReceiveStats[npeId].solicited = 0; - - /* reset the unsolicited message counter */ - ixNpeMhReceiveStats[npeId].unsolicited = 0; - - /* reset the callback invoked counter */ - ixNpeMhReceiveStats[npeId].callbacks = 0; -} diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c deleted file mode 100644 index 8b7038870a..0000000000 --- a/drivers/net/npe/IxNpeMhSend.c +++ /dev/null @@ -1,283 +0,0 @@ -/** - * @file IxNpeMhSend.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Send module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_NPEMH_INFIFO_RETRY_DELAY_US - * - * @brief Amount of time (uSecs) to delay between retries - * while inFIFO is Full when attempting to send a message - */ -#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1) - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSendStats - * - * @brief This structure is used to maintain statistics for the Send - * module. - */ - -typedef struct -{ - UINT32 sends; /**< send invocations */ - UINT32 sendWithResponses; /**< send with response invocations */ - UINT32 queueFulls; /**< fifo queue full occurrences */ - UINT32 queueFullRetries; /**< fifo queue full retry occurrences */ - UINT32 maxQueueFullRetries; /**< max fifo queue full retries */ - UINT32 callbackFulls; /**< callback list full occurrences */ -} IxNpeMhSendStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries); - -/* - * Function definition: ixNpeMhSendInFifoIsFull - */ - -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries) -{ - BOOL isFull = false; - UINT32 numRetries = 0; - - /* check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* we retry a few times, just to give the NPE a chance to read from */ - /* the FIFO if the FIFO is currently full */ - while (isFull && (numRetries++ < maxSendRetries)) - { - if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT) - { - /* Delay here for as short a time as possible (1 us). */ - /* Adding a delay here should ensure we are not hogging */ - /* the AHB bus while we are retrying */ - ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - } - - /* re-check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFullRetries++; - } - - /* record the highest number of retries that occurred */ - if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries) - { - ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries; - } - - if (isFull) - { - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFulls++; - } - - return isFull; -} - -/* - * Function definition: ixNpeMhSendMessageSend - */ - -IX_STATUS ixNpeMhSendMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sends++; - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendMessageWithResponseSend - */ - -IX_STATUS ixNpeMhSendMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageWithResponseSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sendWithResponses++; - - /* sr: this sleep will call the receive routine (no interrupts used!!!) */ - ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* save the solicited callback */ - status = ixNpeMhSolicitedCbMgrCallbackSave ( - npeId, solicitedMessageId, solicitedCallback); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].callbackFulls++; - - return status; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageWithResponseSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendShow - */ - -void ixNpeMhSendShow ( - IxNpeMhNpeId npeId) -{ - /* show the message send invocation counter */ - IX_NPEMH_SHOW ("Send invocations", - ixNpeMhSendStats[npeId].sends); - - /* show the message send with response invocation counter */ - IX_NPEMH_SHOW ("Send with response invocations", - ixNpeMhSendStats[npeId].sendWithResponses); - - /* show the fifo queue full occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full occurrences", - ixNpeMhSendStats[npeId].queueFulls); - - /* show the fifo queue full retry occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full retry occurrences", - ixNpeMhSendStats[npeId].queueFullRetries); - - /* show the fifo queue full maximum retries counter */ - IX_NPEMH_SHOW ("Maximum fifo queue full retries", - ixNpeMhSendStats[npeId].maxQueueFullRetries); - - /* show the callback list full occurrence counter */ - IX_NPEMH_SHOW ("Solicited callback list full occurrences", - ixNpeMhSendStats[npeId].callbackFulls); -} - -/* - * Function definition: ixNpeMhSendShowReset - */ - -void ixNpeMhSendShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message send invocation counter */ - ixNpeMhSendStats[npeId].sends = 0; - - /* reset the message send with response invocation counter */ - ixNpeMhSendStats[npeId].sendWithResponses = 0; - - /* reset the fifo queue full occurrence counter */ - ixNpeMhSendStats[npeId].queueFulls = 0; - - /* reset the fifo queue full retry occurrence counter */ - ixNpeMhSendStats[npeId].queueFullRetries = 0; - - /* reset the max fifo queue full retries counter */ - ixNpeMhSendStats[npeId].maxQueueFullRetries = 0; - - /* reset the callback list full occurrence counter */ - ixNpeMhSendStats[npeId].callbackFulls = 0; -} diff --git a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c b/drivers/net/npe/IxNpeMhSolicitedCbMgr.c deleted file mode 100644 index c539d09071..0000000000 --- a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c +++ /dev/null @@ -1,334 +0,0 @@ -/** - * @file IxNpeMhSolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Solicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ -#ifndef IXNPEMHCONFIG_P_H -# define IXNPEMHSOLICITEDCBMGR_C -#else -# error "Error, IxNpeMhConfig_p.h should not be included before this definition." -#endif - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhConfig_p.h" -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSolicitedCallbackListEntry - * - * @brief This structure is used to store the information associated with - * an entry in the callback list. This consists of the ID of the send - * message (which indicates the ID of the corresponding response message) - * and the callback function pointer itself. - * - */ - -typedef struct IxNpeMhSolicitedCallbackListEntry -{ - /** message ID */ - IxNpeMhMessageId messageId; - - /** callback function pointer */ - IxNpeMhCallback callback; - - /** pointer to next entry in the list */ - struct IxNpeMhSolicitedCallbackListEntry *next; -} IxNpeMhSolicitedCallbackListEntry; - -/** - * @struct IxNpeMhSolicitedCallbackList - * - * @brief This structure is used to maintain the list of response - * callbacks. The number of entries in this list will be variable, and - * they will be stored in a linked list fashion for ease of addition and - * removal. The entries themselves are statically allocated, and are - * organised into a "free" list and a "callback" list. Adding an entry - * means taking an entry from the "free" list and adding it to the - * "callback" list. Removing an entry means removing it from the - * "callback" list and returning it to the "free" list. - */ - -typedef struct -{ - /** pointer to the head of the free list */ - IxNpeMhSolicitedCallbackListEntry *freeHead; - - /** pointer to the head of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackHead; - - /** pointer to the tail of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackTail; - - /** array of entries - the first entry is used as a dummy entry to */ - /* avoid the scenario of having an empty list, hence '+ 1' */ - IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1]; -} IxNpeMhSolicitedCallbackList; - -/** - * @struct IxNpeMhSolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Solicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback list saves */ - UINT32 retrieves; /**< callback list retrieves */ -} IxNpeMhSolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSolicitedCallbackList -ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhSolicitedCbMgrStats -ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhSolicitedCbMgrInitialize - */ - -void ixNpeMhSolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId; - UINT32 localIndex; - IxNpeMhSolicitedCallbackList *list = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* for each entry in the list, after the dummy entry ... */ - for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++) - { - /* initialise the entry */ - list->entries[localIndex].messageId = 0x00; - list->entries[localIndex].callback = NULL; - - /* if this entry is before the last entry */ - if (localIndex < IX_NPEMH_MAX_CALLBACKS) - { - /* chain this entry to the following entry */ - list->entries[localIndex].next = &(list->entries[localIndex + 1]); - } - else /* this entry is the last entry */ - { - /* the last entry isn't chained to anything */ - list->entries[localIndex].next = NULL; - } - } - - /* set the free list pointer to point to the first real entry */ - /* (all real entries begin chained together on the free list) */ - list->freeHead = &(list->entries[1]); - - /* set the callback list pointers to point to the dummy entry */ - /* (the callback list is initially empty) */ - list->callbackHead = &(list->entries[0]); - list->callbackTail = &(list->entries[0]); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackSave - */ - -IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* check to see if there are any entries in the free list */ - if (list->freeHead == NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n"); - return IX_FAIL; - } - - /* there is an entry in the free list we can use */ - - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].saves++; - - /* remove a callback entry from the start of the free list */ - callbackEntry = list->freeHead; - list->freeHead = callbackEntry->next; - - /* fill in the callback entry with the new data */ - callbackEntry->messageId = solicitedMessageId; - callbackEntry->callback = solicitedCallback; - - /* the new callback entry will be added to the tail of the callback */ - /* list, so it isn't chained to anything */ - callbackEntry->next = NULL; - - /* chain new callback entry to the last entry of the callback list */ - list->callbackTail->next = callbackEntry; - list->callbackTail = callbackEntry; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhSolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback *solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL; - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* initialise the callback entry to the first entry of the callback */ - /* list - we must skip over the dummy entry, which is the previous */ - callbackEntry = list->callbackHead->next; - previousEntry = list->callbackHead; - - /* traverse the callback list looking for an entry with a matching */ - /* message ID. note we also save the previous entry's pointer to */ - /* allow us to unchain the matching entry from the callback list */ - while ((callbackEntry != NULL) && - (callbackEntry->messageId != solicitedMessageId)) - { - previousEntry = callbackEntry; - callbackEntry = callbackEntry->next; - } - - /* if we didn't find a matching callback entry */ - if (callbackEntry == NULL) - { - /* return a NULL callback in the outgoing parameter */ - *solicitedCallback = NULL; - } - else /* we found a matching callback entry */ - { - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves++; - - /* return the callback in the outgoing parameter */ - *solicitedCallback = callbackEntry->callback; - - /* unchain callback entry by chaining previous entry to next */ - previousEntry->next = callbackEntry->next; - - /* if the callback entry is at the tail of the list */ - if (list->callbackTail == callbackEntry) - { - /* update the tail of the callback list */ - list->callbackTail = previousEntry; - } - - /* re-initialise the callback entry */ - callbackEntry->messageId = 0x00; - callbackEntry->callback = NULL; - - /* add the callback entry to the start of the free list */ - callbackEntry->next = list->freeHead; - list->freeHead = callbackEntry; - } -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShow - */ - -void ixNpeMhSolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the solicited callback list save counter */ - IX_NPEMH_SHOW ("Solicited callback list saves", - ixNpeMhSolicitedCbMgrStats[npeId].saves); - - /* show the solicited callback list retrieve counter */ - IX_NPEMH_SHOW ("Solicited callback list retrieves", - ixNpeMhSolicitedCbMgrStats[npeId].retrieves); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShowReset - */ - -void ixNpeMhSolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the solicited callback list save counter */ - ixNpeMhSolicitedCbMgrStats[npeId].saves = 0; - - /* reset the solicited callback list retrieve counter */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0; -} diff --git a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c b/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c deleted file mode 100644 index 082f677e62..0000000000 --- a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c +++ /dev/null @@ -1,222 +0,0 @@ -/** - * @file IxNpeMhUnsolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for - * the Unsolicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhUnsolicitedCbMgr_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhUnsolicitedCallbackTable - * - * @brief This structure is used to maintain the list of registered - * callbacks. One entry exists for each message ID, and a NULL entry will - * signify that no callback has been registered for that ID. - */ - -typedef struct -{ - /** array of entries */ - IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1]; -} IxNpeMhUnsolicitedCallbackTable; - -/** - * @struct IxNpeMhUnsolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Unsolicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback table saves */ - UINT32 overwrites; /**< callback table overwrites */ -} IxNpeMhUnsolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhUnsolicitedCallbackTable -ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhUnsolicitedCbMgrStats -ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrInitialize - */ - -void ixNpeMhUnsolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - IxNpeMhUnsolicitedCallbackTable *table = NULL; - IxNpeMhMessageId messageId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* for each message ID ... */ - for (messageId = IX_NPEMH_MIN_MESSAGE_ID; - messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++) - { - /* initialise the callback for this message ID to NULL */ - table->entries[messageId] = NULL; - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave - */ - -void ixNpeMhUnsolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves++; - - /* check if there is a callback already registered for this NPE and */ - /* message ID */ - if (table->entries[unsolicitedMessageId] != NULL) - { - /* if we are overwriting an existing callback */ - if (unsolicitedCallback != NULL) - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback " - "overwriting existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - else /* if we are clearing an existing callback */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback " - "clearing existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++; - } - - /* save the callback into the table */ - table->entries[unsolicitedMessageId] = unsolicitedCallback; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback *unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* retrieve the callback from the table */ - *unsolicitedCallback = table->entries[unsolicitedMessageId]; -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShow - */ - -void ixNpeMhUnsolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the unsolicited callback table save counter */ - IX_NPEMH_SHOW ("Unsolicited callback table saves", - ixNpeMhUnsolicitedCbMgrStats[npeId].saves); - - /* show the unsolicited callback table overwrite counter */ - IX_NPEMH_SHOW ("Unsolicited callback table overwrites", - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShowReset - */ - -void ixNpeMhUnsolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the unsolicited callback table save counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0; - - /* reset the unsolicited callback table overwrite counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0; -} diff --git a/drivers/net/npe/IxOsalBufferMgt.c b/drivers/net/npe/IxOsalBufferMgt.c deleted file mode 100644 index f70ba05d9e..0000000000 --- a/drivers/net/npe/IxOsalBufferMgt.c +++ /dev/null @@ -1,776 +0,0 @@ -/** - * @file IxOsalBufferMgt.c - * - * @brief Default buffer pool management and buffer management - * Implementation. - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* - * OS may choose to use default bufferMgt by defining - * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h - */ - -#include "IxOsal.h" - -#define IX_OSAL_BUFFER_FREE_PROTECTION /* Define this to enable Illegal MBuf Freed Protection*/ - -/* - * The implementation is only used when the following - * is defined. - */ -#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT - - -#define IX_OSAL_MBUF_SYS_SIGNATURE (0x8BADF00D) -#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK (0xEFFFFFFF) -#define IX_OSAL_MBUF_USED_FLAG (0x10000000) -#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE - -/* -* This implementation is protect, the buffer pool management's ixOsalMBufFree -* against an invalid MBUF pointer argument that already has been freed earlier -* or in other words resides in the free pool of MBUFs. This added feature, -* checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed -* back to the Buffer Pool. -* Disable this feature for performance reasons by undef -* IX_OSAL_BUFFER_FREE_PROTECTION macro. -*/ -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) ) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) do { \ - IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\ - IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE; \ - }while(0) - -#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG) - -#else - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE - -#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * A unit of 32, used to provide bit-shift for pool - * management. Needs some work if users want more than 32 pools. - */ -#define IX_OSAL_BUFF_FREE_BITS 32 - -PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS / - IX_OSAL_BUFF_FREE_BITS]; - -PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS]; - -static int ixOsalBuffPoolsInUse = 0; - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr); -#endif - -PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void); - -/* - * Function definition: ixOsalPoolAlloc - */ - -/****************************/ - -PRIVATE IX_OSAL_MBUF_POOL * -ixOsalPoolAlloc (void) -{ - register unsigned int i = 0; - - /* - * Scan for the first free buffer. Free buffers are indicated by 0 - * on the corrsponding bit in ixOsalBuffFreePools. - */ - if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS) - { - /* - * Fail to grab a ptr this time - */ - return NULL; - } - - while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] & - (1 << (i % IX_OSAL_BUFF_FREE_BITS))) - i++; - /* - * Free buffer found. Mark it as busy and initialize. - */ - ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |= - (1 << (i % IX_OSAL_BUFF_FREE_BITS)); - - memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL)); - - ixOsalBuffPools[i].poolIdx = i; - ixOsalBuffPoolsInUse++; - - return &ixOsalBuffPools[i]; -} - - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr) -{ - UINT8 *dataPtr; - IX_OSAL_MBUF *realMbufPtr; - /* Allocate cache-aligned memory for mbuf header */ - realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned); - IX_OSAL_ASSERT (realMbufPtr != NULL); - memset (realMbufPtr, 0, mbufSizeAligned); - - /* Allocate cache-aligned memory for mbuf data */ - dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned); - IX_OSAL_ASSERT (dataPtr != NULL); - memset (dataPtr, 0, dataSizeAligned); - - /* Fill in mbuf header fields */ - IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr; - - IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned; - - IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr); - - /* update some statistical information */ - poolPtr->mbufMemSize += mbufSizeAligned; - poolPtr->dataMemSize += dataSizeAligned; - - return realMbufPtr; -} -#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - -/* - * Function definition: ixOsalBuffPoolInit - */ - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalPoolInit (UINT32 count, UINT32 size, const char *name) -{ - - /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY - * is defined . - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i, mbufSizeAligned, dataSizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; -#else - void *poolBufPtr; - void *poolDataPtr; - int mbufMemSize; - int dataMemSize; -#endif - - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - -/* OS can choose whether to allocate all buffers all together (if it - * can handle a huge single alloc request), or to allocate buffers - * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY. - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - /* Get a pool Ptr */ - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size); - - poolPtr->nextFreeBuf = NULL; - poolPtr->mbufMemPtr = NULL; - poolPtr->dataMemPtr = NULL; - poolPtr->bufDataSize = dataSizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - strcpy (poolPtr->name, name); - - - for (i = 0; i < count; i++) - { - /* create an mbuf */ - currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned, - dataSizeAligned, - poolPtr); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION -/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail. - ixOsalMbufFree used here is in a special case whereby, it's - used to add MBUF to the Pool. By specification, ixOsalMbufFree - deallocates an allocated MBUF from Pool. -*/ - IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr); -#endif - /* Add it to the pool */ - ixOsalMbufFree (currentMbufPtr); - - /* flush the pool information to RAM */ - IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned); - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - -#else -/* Otherwise allocate buffers in a continuous block fashion */ - poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize); - IX_OSAL_ASSERT (poolBufPtr != NULL); - poolDataPtr = - IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize); - IX_OSAL_ASSERT (poolDataPtr != NULL); - - poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr, - count, size, name); - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - -#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - return poolPtr; -} - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalNoAllocPoolInit (void *poolBufPtr, - void *poolDataPtr, UINT32 count, UINT32 size, const char *name) -{ - UINT32 i, mbufSizeAligned, sizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; - IX_OSAL_MBUF *nextMbufPtr = NULL; - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - /* - * check parameters - */ - if (poolBufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - count must > 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL name ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - return NULL; - } - - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - mbufSizeAligned = - IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - /* - * clear the mbuf memory area - */ - memset (poolBufPtr, 0, mbufSizeAligned * count); - - if (poolDataPtr != NULL) - { - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - /* - * clear the data memory area - */ - memset (poolDataPtr, 0, sizeAligned * count); - } - else - { - sizeAligned = 0; - } - - /* - * initialise pool fields - */ - strcpy ((poolPtr)->name, name); - - poolPtr->dataMemPtr = poolDataPtr; - poolPtr->mbufMemPtr = poolBufPtr; - poolPtr->bufDataSize = sizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->mbufMemSize = mbufSizeAligned * count; - poolPtr->dataMemSize = sizeAligned * count; - - currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr; - - poolPtr->nextFreeBuf = currentMbufPtr; - - for (i = 0; i < count; i++) - { - if (i < (count - 1)) - { - nextMbufPtr = - (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr + - mbufSizeAligned); - } - else - { /* last mbuf in chain */ - nextMbufPtr = NULL; - } - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr; - IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr); - - if (poolDataPtr != NULL) - { - IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr; - - IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned; - - poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned); - } - - currentMbufPtr = nextMbufPtr; - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC; - - return poolPtr; -} - -/* - * Get a mbuf ptr from the pool - */ -PUBLIC IX_OSAL_MBUF * -ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr) -{ - int lock; - IX_OSAL_MBUF *newBufPtr = NULL; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufAlloc(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - lock = ixOsalIrqLock (); - - newBufPtr = poolPtr->nextFreeBuf; - if (newBufPtr) - { - poolPtr->nextFreeBuf = - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool--; - } - else - { - /* Return NULL to indicate to caller that request is denied. */ - ixOsalIrqUnlock (lock); - - return NULL; - } - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - /* Set Buffer Used Flag to indicate state.*/ - IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr); -#endif - - ixOsalIrqUnlock (lock); - - return newBufPtr; -} - -PUBLIC IX_OSAL_MBUF * -ixOsalMbufFree (IX_OSAL_MBUF * bufPtr) -{ - int lock; - IX_OSAL_MBUF_POOL *poolPtr; - - IX_OSAL_MBUF *nextBufPtr = NULL; - - /* - * check parameters - */ - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufFree(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - - - lock = ixOsalIrqLock (); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - - /* Prevention for Buffer freed more than once*/ - if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr)) - { - return NULL; - } - IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr); -#endif - - poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr); - - /* - * check the mbuf wrapper signature (if mbuf wrapper was used) - */ - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE), - "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature."); - } - - nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr); - - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf; - poolPtr->nextFreeBuf = bufPtr; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool++; - - ixOsalIrqUnlock (lock); - - return nextBufPtr; -} - -PUBLIC void -ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr) -{ - while ((bufPtr = ixOsalMbufFree (bufPtr))); -} - -/* - * Function definition: ixOsalBuffPoolShow - */ -PUBLIC void -ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr) -{ - IX_OSAL_MBUF *nextBufPtr; - int count = 0; - int lock; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolShow(): " - "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0); - /* - * return IX_FAIL; - */ - return; - } - - lock = ixOsalIrqLock (); - count = poolPtr->freeBufsInPool; - nextBufPtr = poolPtr->nextFreeBuf; - ixOsalIrqUnlock (lock); - - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0, - 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Name: %s\n", - (unsigned int) poolPtr->name, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Allocation Type: %d\n", - (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Mbuf Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Data Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Data Capacity (bytes): %d\n", - (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Total Mbufs in Pool: %d\n", - (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Available Mbufs: %d\n", (unsigned int) count, 0, - 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr, - 0, 0, 0, 0, 0); - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Mem Area Start address: %p\n", - (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Data Mem Area Start address: %p\n", - (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0); - } -} - -PUBLIC void -ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr) -{ - IX_OSAL_MBUF_POOL *poolPtr; - UINT8 *poolDataPtr; - - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return; - } - - poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr); - poolDataPtr = poolPtr->dataMemPtr; - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": invalid mbuf, cannot reset mData pointer\n", 0, 0, - 0, 0, 0, 0); - return; - } - IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr); - } - else - { - if (poolDataPtr) - { - unsigned int bufSize = poolPtr->bufDataSize; - unsigned int bufDataAddr = - (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr); - unsigned int poolDataAddr = (unsigned int) poolDataPtr; - - /* - * the pointer is still pointing somewhere in the mbuf payload. - * This operation moves the pointer to the beginning of the - * mbuf payload - */ - bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize; - IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr]; - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": cannot be used if user supplied NULL pointer for pool data area " - "when pool was created\n", 0, 0, 0, 0, 0, 0); - return; - } - } - -} - -/* - * Function definition: ixOsalBuffPoolUninit - */ -PUBLIC IX_STATUS -ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool) -{ - if (!pool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->freeBufsInPool != pool->totalBufsInPool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n", - 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i; - IX_OSAL_MBUF* pBuf; - - pBuf = pool->nextFreeBuf; - /* Freed the Buffer one by one till all the Memory is freed*/ - for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){ - IX_OSAL_MBUF* pBufTemp; - pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf); - /* Freed MBUF Data Memory area*/ - IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) ); - /* Freed MBUF Struct Memory area*/ - IX_OSAL_CACHE_DMA_FREE(pBuf); - pBuf = pBufTemp; - } - -#else - IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr); - IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr); -#endif - } - - ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &= - ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS)); - ixOsalBuffPoolsInUse--; - return IX_SUCCESS; -} - -/* - * Function definition: ixOsalBuffPoolDataAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolDataAreaSizeGet (int count, int size) -{ - UINT32 memorySize; - memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolMbufAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolMbufAreaSizeGet (int count) -{ - UINT32 memorySize; - memorySize = - count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolFreeCountGet - */ -PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr) - -{ - - return poolPtr->freeBufsInPool; - -} - -#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */ diff --git a/drivers/net/npe/IxOsalIoMem.c b/drivers/net/npe/IxOsalIoMem.c deleted file mode 100644 index bf3acdc10c..0000000000 --- a/drivers/net/npe/IxOsalIoMem.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - * @file IxOsalIoMem.c - * - * @brief OS-independent IO/Mem implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* Access to the global mem map is only allowed in this file */ -#define IxOsalIoMem_C - -#include "IxOsal.h" - -#define SEARCH_PHYSICAL_ADDRESS (1) -#define SEARCH_VIRTUAL_ADDRESS (2) - -/* - * Searches for map using one of the following criteria: - * - * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping) - * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping) - * - correct coherency - * - * Returns a pointer to the map or NULL if a suitable map is not found. - */ -PRIVATE IxOsalMemoryMap * -ixOsalMemMapFind (UINT32 requestedAddress, - UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType) -{ - UINT32 mapIndex; - - UINT32 numMapElements = ARRAY_SIZE(ixOsalGlobalMemoryMap); - - for (mapIndex = 0; mapIndex < numMapElements; mapIndex++) - { - IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex]; - - if (searchCriteria == SEARCH_PHYSICAL_ADDRESS - && requestedAddress >= map->physicalAddress - && (requestedAddress + size) <= (map->physicalAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS - && requestedAddress >= map->virtualAddress - && requestedAddress <= (map->virtualAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS) - { - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n", - map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0); - } - } - - /* - * not found - */ - return NULL; -} - -/* - * This function maps an I/O mapped physical memory zone of the given size - * into a virtual memory zone accessible by the caller and returns a cookie - - * the start address of the virtual memory zone. - * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned - * virtual address. - * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has - * finished using this zone (e.g. on driver unload) using the cookie as - * parameter. - * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write - * the mapped memory, adding the necessary offsets to the address cookie. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP - * instead. - */ -PUBLIC void * -ixOsalIoMemMap (UINT32 requestedAddress, - UINT32 size, IxOsalMapEndianessType requestedEndianType) -{ - IxOsalMemoryMap *map; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - if (requestedEndianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return (NULL); - } - map = ixOsalMemMapFind (requestedAddress, - size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType); - if (map != NULL) - { - UINT32 offset = requestedAddress - map->physicalAddress; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n", - map->physicalAddress, map->virtualAddress, - map->size, map->refCount, map->mapEndianType, 0); - - if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0) - { - if (map->mapFunction != NULL) - { - map->mapFunction (map); - - if (map->virtualAddress == 0) - { - /* - * failed - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; - } - } - else - { - /* - * error, no map function for a dynamic map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No map function for a dynamic map - " - "[addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - return NULL; - } - } - - /* - * increment reference count - */ - map->refCount++; - - return (void *) (map->virtualAddress + offset); - } - - /* - * requested address is not described in the global memory map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; -} - -/* - * This function unmaps a previously mapped I/O memory zone using - * the cookie obtained in the mapping operation. The memory zone in question - * becomes unavailable to the caller once unmapped and the cookie should be - * discarded. - * - * This function cannot fail if the given parameter is correct and does not - * return a value. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP - * instead. - */ -PUBLIC void -ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) -{ - IxOsalMemoryMap *map; - - if (endianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return; - } - - if (requestedAddress == 0) - { - /* - * invalid virtual address - */ - return; - } - - map = - ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS, - endianType); - - if (map != NULL) - { - if (map->refCount > 0) - { - /* - * decrement reference count - */ - map->refCount--; - - if (map->refCount == 0) - { - /* - * no longer used, deallocate - */ - if (map->type == IX_OSAL_DYNAMIC_MAP - && map->unmapFunction != NULL) - { - map->unmapFunction (map); - } - } - } - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: ixOsServMemUnmap didn't find the requested map " - "[virt addr 0x%x: endianType %d], ignoring call\n", - requestedAddress, endianType, 0, 0, 0, 0); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->physicalAddress + virtualAddress - map->virtualAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->virtualAddress + physicalAddress - map->physicalAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress); - } -} diff --git a/drivers/net/npe/IxOsalOsCacheMMU.c b/drivers/net/npe/IxOsalOsCacheMMU.c deleted file mode 100644 index 72d22e5882..0000000000 --- a/drivers/net/npe/IxOsalOsCacheMMU.c +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file IxOsalOsCacheMMU.c (linux) - * - * @brief Cache MemAlloc and MemFree. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include - -/* - * Allocate on a cache line boundary (null pointers are - * not affected by this operation). This operation is NOT cache safe. - */ -void * -ixOsalCacheDmaMalloc (UINT32 n) -{ - return malloc(n); -} - -/* - * - */ -void -ixOsalCacheDmaFree (void *ptr) -{ - free(ptr); -} diff --git a/drivers/net/npe/IxOsalOsMsgQ.c b/drivers/net/npe/IxOsalOsMsgQ.c deleted file mode 100644 index 5fe368bdaf..0000000000 --- a/drivers/net/npe/IxOsalOsMsgQ.c +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file IxOsalOsMsgQ.c (eCos) - * - * @brief OS-specific Message Queue implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/******************************* - * Public functions - *******************************/ -PUBLIC IX_STATUS -ixOsalMessageQueueCreate (IxOsalMessageQueue * queue, - UINT32 msgCount, UINT32 msgLen) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueDelete (IxOsalMessageQueue * queue) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c deleted file mode 100644 index 33de7f6e42..0000000000 --- a/drivers/net/npe/IxOsalOsSemaphore.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - * @file IxOsalOsSemaphore.c (eCos) - * - * @brief Implementation for semaphore and mutex. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMhReceive_p.h" - -/* Define a large number */ -#define IX_OSAL_MAX_LONG (0x7FFFFFFF) - -/* Max timeout in MS, used to guard against possible overflow */ -#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ) - - -PUBLIC IX_STATUS -ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/** - * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked. - * If the semaphore is 'full', it is taken and control is returned - * to the caller. If the time indicated in 'timeout' is reached, - * the thread will unblock and return an error indication. If the - * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block; - * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until - * the semaphore is available. - * - * - */ - - -PUBLIC IX_STATUS -ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/* - * Attempt to get semaphore, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalSemaphoreTryWait (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/** - * - * DESCRIPTION: This function causes the next available thread in the pend queue - * to be unblocked. If no thread is pending on this semaphore, the - * semaphore becomes 'full'. - */ -PUBLIC IX_STATUS -ixOsalSemaphorePost (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreDestroy (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/**************************** - * Mutex - ****************************/ - -static void drv_mutex_init(IxOsalMutex *mutex) -{ - *mutex = 0; -} - -static void drv_mutex_destroy(IxOsalMutex *mutex) -{ - *mutex = -1; -} - -static int drv_mutex_trylock(IxOsalMutex *mutex) -{ - int result = true; - - if (*mutex == 1) - result = false; - - return result; -} - -static void drv_mutex_unlock(IxOsalMutex *mutex) -{ - if (*mutex == 1) - printf("Trying to unlock unlocked mutex!"); - - *mutex = 0; -} - -PUBLIC IX_STATUS -ixOsalMutexInit (IxOsalMutex * mutex) -{ - drv_mutex_init(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout) -{ - int tries; - - if (timeout == IX_OSAL_WAIT_NONE) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - else - return IX_FAIL; - } - - tries = (timeout * 1000) / 50; - while (1) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0) - break; - udelay(50); - } - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexUnlock (IxOsalMutex * mutex) -{ - drv_mutex_unlock(mutex); - return IX_SUCCESS; -} - -/* - * Attempt to get mutex, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalMutexTryLock (IxOsalMutex * mutex) -{ - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexDestroy (IxOsalMutex * mutex) -{ - drv_mutex_destroy(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalFastMutexInit (IxOsalFastMutex * mutex) -{ - return ixOsalMutexInit(mutex); -} - -PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex) -{ - return ixOsalMutexTryLock(mutex); -} - - -PUBLIC IX_STATUS -ixOsalFastMutexUnlock (IxOsalFastMutex * mutex) -{ - return ixOsalMutexUnlock(mutex); -} - -PUBLIC IX_STATUS -ixOsalFastMutexDestroy (IxOsalFastMutex * mutex) -{ - return ixOsalMutexDestroy(mutex); -} diff --git a/drivers/net/npe/IxOsalOsServices.c b/drivers/net/npe/IxOsalOsServices.c deleted file mode 100644 index a9aa36804b..0000000000 --- a/drivers/net/npe/IxOsalOsServices.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file IxOsalOsServices.c (linux) - * - * @brief Implementation for Irq, Mem, sleep. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include "IxOsal.h" -#include -#include -#include -#include -#include - -static char *traceHeaders[] = { - "", - "[fatal] ", - "[error] ", - "[warning] ", - "[message] ", - "[debug1] ", - "[debug2] ", - "[debug3] ", - "[all]" -}; - -/* by default trace all but debug message */ -PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE; - -/************************************** - * Irq services - *************************************/ - -PUBLIC IX_STATUS -ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter) -{ - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalIrqUnbind (UINT32 vector) -{ - return IX_FAIL; -} - -PUBLIC UINT32 -ixOsalIrqLock () -{ - return 0; -} - -/* Enable interrupts and task scheduling, - * input parameter: irqEnable status returned - * by ixOsalIrqLock(). - */ -PUBLIC void -ixOsalIrqUnlock (UINT32 lockKey) -{ -} - -PUBLIC UINT32 -ixOsalIrqLevelSet (UINT32 level) -{ - return IX_FAIL; -} - -PUBLIC void -ixOsalIrqEnable (UINT32 irqLevel) -{ -} - -PUBLIC void -ixOsalIrqDisable (UINT32 irqLevel) -{ -} - -/********************* - * Log function - *********************/ - -INT32 -ixOsalLog (IxOsalLogLevel level, - IxOsalLogDevice device, - char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) -{ - /* - * Return -1 for custom display devices - */ - if ((device != IX_OSAL_LOG_DEV_STDOUT) - && (device != IX_OSAL_LOG_DEV_STDERR)) - { - debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n"); - return (IX_OSAL_LOG_ERROR); - } - - if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE) - { -#if 0 /* sr: U-Boots printf or debug doesn't return a length */ - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]); - - return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6); -#else - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]); - - return headerByteCount + strlen(format); -#endif - } - else - { - /* - * Return error - */ - return (IX_OSAL_LOG_ERROR); - } -} - -PUBLIC UINT32 -ixOsalLogLevelSet (UINT32 level) -{ - UINT32 oldLevel; - - /* - * Check value first - */ - if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL)) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalLogLevelSet: Log Level is between %d and%d \n", - IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0); - return IX_OSAL_LOG_LVL_NONE; - } - oldLevel = ixOsalCurrLogLevel; - - ixOsalCurrLogLevel = level; - - return oldLevel; -} - -/************************************** - * Task services - *************************************/ - -PUBLIC void -ixOsalBusySleep (UINT32 microseconds) -{ - udelay(microseconds); -} - -PUBLIC void -ixOsalSleep (UINT32 milliseconds) -{ - if (milliseconds != 0) { -#if 1 - /* - * sr: We poll while we wait because interrupts are off in U-Boot - * and CSR expects messages, etc to be dispatched while sleeping. - */ - int i; - IxQMgrDispatcherFuncPtr qDispatcherFunc; - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - while (milliseconds--) { - for (i = 1; i <= 2; i++) - ixNpeMhMessagesReceive(i); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - - udelay(1000); - } -#endif - } -} - -/************************************** - * Memory functions - *************************************/ - -void * -ixOsalMemAlloc (UINT32 size) -{ - return (void *)0; -} - -void -ixOsalMemFree (void *ptr) -{ -} - -/* - * Copy count bytes from src to dest , - * returns pointer to the dest mem zone. - */ -void * -ixOsalMemCopy (void *dest, void *src, UINT32 count) -{ - IX_OSAL_ASSERT (dest != NULL); - IX_OSAL_ASSERT (src != NULL); - return (memcpy (dest, src, count)); -} - -/* - * Fills a memory zone with a given constant byte, - * returns pointer to the memory zone. - */ -void * -ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count) -{ - IX_OSAL_ASSERT (ptr != NULL); - return (memset (ptr, filler, count)); -} diff --git a/drivers/net/npe/IxOsalOsThread.c b/drivers/net/npe/IxOsalOsThread.c deleted file mode 100644 index b3caae19b1..0000000000 --- a/drivers/net/npe/IxOsalOsThread.c +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file IxOsalOsThread.c (eCos) - * - * @brief OS-specific thread implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/* Thread attribute is ignored */ -PUBLIC IX_STATUS -ixOsalThreadCreate (IxOsalThread * ptrTid, - IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg) -{ - return IX_SUCCESS; -} - -/* - * Start thread after given its thread handle - */ -PUBLIC IX_STATUS -ixOsalThreadStart (IxOsalThread * tId) -{ - /* Thread already started upon creation */ - return IX_SUCCESS; -} - -/* - * In Linux threadKill does not actually destroy the thread, - * it will stop the signal handling. - */ -PUBLIC IX_STATUS -ixOsalThreadKill (IxOsalThread * tid) -{ - return IX_SUCCESS; -} - -PUBLIC void -ixOsalThreadExit (void) -{ -} - -PUBLIC IX_STATUS -ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority) -{ - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalThreadSuspend (IxOsalThread * tId) -{ - return IX_SUCCESS; - -} - -PUBLIC IX_STATUS -ixOsalThreadResume (IxOsalThread * tId) -{ - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrAqmIf.c b/drivers/net/npe/IxQMgrAqmIf.c deleted file mode 100644 index 69138ccded..0000000000 --- a/drivers/net/npe/IxQMgrAqmIf.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - * @file: IxQMgrAqmIf.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This component provides a set of functions for - * perfoming I/O on the AQM hardware. - * - * Design Notes: - * These functions are intended to be as fast as possible - * and as a result perform NO PARAMETER CHECKING. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h - */ -#ifndef IXQMGRAQMIF_P_H -# define IXQMGRAQMIF_C -#else -# error -#endif - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrLog_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* These defines are the bit offsets of the various fields of - * the queue configuration register - */ -#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00 -#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07 -#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E -#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16 -#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18 -#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A -#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D - -#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 0x40 -#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 0x6 - -#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF -#define IX_QMGR_NE_MASK 0x7 -#define IX_QMGR_NF_MASK 0x7 -#define IX_QMGR_SIZE_MASK 0x3 -#define IX_QMGR_ENTRY_SIZE_MASK 0x3 -#define IX_QMGR_BADDR_MASK 0x003FC000 -#define IX_QMGR_RDPTR_MASK 0x7F -#define IX_QMGR_WRPTR_MASK 0x7F -#define IX_QMGR_RDWRPTR_MASK 0x00003FFF - -#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000 - -/* Base address of AQM SRAM */ -#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \ -((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE)) - -/* Min buffer size used for generating buffer size in QUECONFIG */ -#define IX_QMGR_MIN_BUFFER_SIZE 16 - -/* Reset values of QMgr hardware registers */ -#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333 -#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000 -#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000 - -#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE - -#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) - -#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7 -#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\ - (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\ - IX_QMGR_QUECONFIG_BASE_OFFSET) - -#define IX_QMGR_ENTRY1_OFFSET 0 -#define IX_QMGR_ENTRY2_OFFSET 1 -#define IX_QMGR_ENTRY4_OFFSET 3 - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ -UINT32 aqmBaseAddress = 0; -/* Store addresses and bit-masks for certain queue access and status registers. - * This is to facilitate inlining of QRead, QWrite and QStatusGet functions - * in IxQMgr,h - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; -UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES]; -UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsMask; -UINT32 ixQMgrAqmIfQueUppStat0RegAddr; -UINT32 ixQMgrAqmIfQueUppStat1RegAddr; -UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID]; - -/* - * Fast mutexes, one for each queue, used to protect peek & poke functions - */ -IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * Function prototypes - */ -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ); - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize); - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords); - -PRIVATE void -ixQMgrAqmIfRegistersReset (void); - -PRIVATE void -ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex, - UINT32 configRegWord, - unsigned int qEntrySizeInwords, - unsigned int qSizeInWords, - UINT32 **address); -/* - * Function definitions - */ -void -ixQMgrAqmIfInit (void) -{ - UINT32 aqmVirtualAddr; - int i; - - /* The value of aqmBaseAddress depends on the logical address - * assigned by the MMU. - */ - aqmVirtualAddr = - (UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS, - IX_OSAL_IXP400_QMGR_MAP_SIZE); - IX_OSAL_ASSERT (aqmVirtualAddr); - - ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr); - - ixQMgrAqmIfRegistersReset (); - - for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]); - - /******************************************************************** - * Register addresses and bit masks are calculated and stored here to - * facilitate inlining of QRead, QWrite and QStatusGet functions in - * IxQMgr.h. - * These calculations are normally performed dynamically in inlined - * functions in IxQMgrAqmIf_p.h, and their semantics are reused here. - */ - - /* AQM Queue access reg addresses, per queue */ - ixQMgrAqmIfQueAccRegAddr[i] = - (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - - - ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i)); - - /* AQM Queue lower-group (0-31), only */ - if (i < IX_QMGR_MIN_QUEUPP_QID) - { - /* AQM Q underflow/overflow status register addresses, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr = - (volatile UINT32 *)(aqmBaseAddress + - IX_QMGR_QUEUOSTAT0_OFFSET + - ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* AQM Q underflow status bit masks for status register per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask = - (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q overflow status bit masks for status register, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask = - (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q lower-group (0-31) status register addresses, per queue */ - ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress + - IX_QMGR_QUELOWSTAT0_OFFSET + - ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD); - - /* AQM Q lower-group (0-31) status register bit offset */ - ixQMgrAqmIfQueLowStatBitsOffset[i] = - (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD); - } - else /* AQM Q upper-group (32-63), only */ - { - /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */ - ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - - /* AQM Q upper-group (32-63) Full status register bit masks */ - ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - } - } - - /* AQM Q lower-group (0-31) status register bit mask */ - ixQMgrAqmIfQueLowStatBitsMask = (1 << - (BITS_PER_WORD / - IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1; - - /* AQM Q upper-group (32-63) Nearly Empty status register address */ - ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET; - - /* AQM Q upper-group (32-63) Full status register address */ - ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET; -} - -/* - * Uninitialise the AqmIf module by unmapping memory, etc - */ -void -ixQMgrAqmIfUninit (void) -{ - UINT32 virtAddr; - - ixQMgrAqmIfBaseAddressGet (&virtAddr); - IX_OSAL_MEM_UNMAP (virtAddr); - ixQMgrAqmIfBaseAddressSet (0); -} - -/* - * Set the the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressSet (UINT32 address) -{ - aqmBaseAddress = address; -} - -/* - * Get the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress; -} - -/* - * Get the logical base address of AQM SRAM - */ -void -ixQMgrAqmIfSramBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress + - IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET; -} - -/* - * This function will write the status bits of a queue - * specified by qId. - */ -void -ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, - UINT32 registerBaseAddrOffset, - unsigned queuesPerRegWord, - UINT32 value) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 statusBitsMask; - UINT32 bitsPerQueue; - - bitsPerQueue = BITS_PER_WORD / queuesPerRegWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - - if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) && - (qId == IX_QMGR_QUEUE_0) ) - { - statusBitsMask = 0x7 ; - - /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */ - value &= 0x7 ; - } - else - { - /* Calculate the mask for the status bits for this queue. */ - statusBitsMask = ((1 << bitsPerQueue) - 1); - statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - - /* Mask out bits in value that would overwrite other q data */ - value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - value &= statusBitsMask; - } - - /* Mask out bits to write to */ - registerWord &= ~statusBitsMask; - - - /* Set the write bits */ - registerWord |= value; - - /* - * Write the data - */ - ixQMgrAqmIfWordWrite (registerAddress, registerWord); -} - -/* - * This function generates the parameters that can be used to - * check if a Qs status matches the specified source select. - * It calculates which status word to check (statusWordOffset), - * the value to check the status against (checkValue) and the - * mask (mask) to mask out all but the bits to check in the status word. - */ -void -ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId, - IxQMgrSourceId srcSel, - unsigned int *statusWordOffset, - UINT32 *checkValue, - UINT32 *mask) -{ - UINT32 shiftVal; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - switch (srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - *checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - *checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - *checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_F: - *checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - default: - /* Should never hit */ - IX_OSAL_ASSERT(0); - break; - } - - /* One nibble of status per queue so need to shift the - * check value and mask out to the correct position. - */ - shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_QUELOWSTAT_BITS_PER_Q; - - /* Calculate the which status word to check from the qId, - * 8 Qs status per word - */ - *statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD; - - *checkValue <<= shiftVal; - *mask <<= shiftVal; - } - else - { - /* One status word */ - *statusWordOffset = 0; - /* Single bits per queue and int source bit hardwired NE, - * Qs start at 32. - */ - *mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID); - *checkValue = *mask; - } -} - -void -ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset)); -} - -void -ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); -} - -void -ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords entrySizeInWords, - UINT32 freeSRAMAddress) -{ - volatile UINT32 *cfgAddress = NULL; - UINT32 qCfg = 0; - UINT32 baseAddress = 0; - unsigned aqmEntrySize = 0; - unsigned aqmBufferSize = 0; - - /* Build config register */ - aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords); - qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) << - IX_QMGR_Q_CONFIG_ESIZE_OFFSET; - - aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords); - qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET; - - /* baseAddress, calculated relative to aqmBaseAddress and start address */ - baseAddress = freeSRAMAddress - - (aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Verify base address aligned to a 16 word boundary */ - if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0) - { - IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n"); - } - /* Now convert it to a 16 word pointer as required by QUECONFIG register */ - baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - - - qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET); - - - cfgAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - - - /* NOTE: High and Low watermarks are set to zero */ - ixQMgrAqmIfWordWrite (cfgAddress, qCfg); -} - -void -ixQMgrAqmIfQueCfgRead (IxQMgrQId qId, - unsigned int numEntries, - UINT32 *baseAddress, - unsigned int *ne, - unsigned int *nf, - UINT32 *readPtr, - UINT32 *writePtr) -{ - UINT32 qcfg; - UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - UINT32 *readPtr_ = NULL; - - /* Read the queue configuration register */ - ixQMgrAqmIfWordRead (cfgAddress, &qcfg); - - /* Extract the base address */ - *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET; - - /* - * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries...... - * If ne > 0 ==> neInEntries = 2^(ne - 1) - * If ne == 0 ==> neInEntries = 0 - * The same applies. - */ - *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK; - *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK; - - if (0 != *ne) - { - *ne = 1 << (*ne - 1); - } - if (0 != *nf) - { - *nf = 1 << (*nf - 1); - } - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/, - qcfg, - qEntrySizeInwords, - qSizeInWords, - &readPtr_); - *readPtr = (UINT32)readPtr_; - *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */ - - *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK; - *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD)); - return; -} - -unsigned -ixQMgrAqmIfLog2 (unsigned number) -{ - unsigned count = 0; - - /* - * N.B. this function will return 0 - * for ixQMgrAqmIfLog2 (0) - */ - while (number/2) - { - number /=2; - count++; - } - - return count; -} - -void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void) -{ - - volatile UINT32 *registerAddress; - UINT32 registerWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_INT0SRCSELREG0_OFFSET); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - /* Set the write bits */ - registerWord |= (1<> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Extract the read pointer. Read pointer is a word pointer */ - readPtr = (UINT32)((configRegWord >> - IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK); - - /* Read/Write pointers(word pointers) are offsets from the queue buffer space base address. - * Calculate the absolute read pointer address. NOTE: Queues are circular buffers. - */ - readPtr = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */ - *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD))); - - switch (qEntrySizeInwords) - { - case IX_QMGR_Q_ENTRY_SIZE1: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE2: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE4: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram); - break; - default: - IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet"); - break; - } - -} - -IX_STATUS -ixQMgrAqmIfQPeek (IxQMgrQId qId, - unsigned int entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordRead (entryAddress++, entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAqmIfQPoke (IxQMgrQId qId, - unsigned entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - /* Else read the entry directly from SRAM. This will not move the read pointer */ - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordWrite (entryAddress++, *entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ) -{ - unsigned aqmWatermark = 0; - - /* - * Watermarks 0("000"),1("001"),2("010"),4("011"), - * 8("100"),16("101"),32("110"),64("111") - */ - aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2); - - return aqmWatermark; -} - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize) -{ - /* entrySize 1("00"),2("01"),4("10") */ - return (ixQMgrAqmIfLog2 (entrySize)); -} - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords) -{ - /* bufferSize 16("00"),32("01),64("10"),128("11") */ - return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE)); -} - -/* - * Reset AQM registers to default values. - */ -PRIVATE void -ixQMgrAqmIfRegistersReset (void) -{ - volatile UINT32 *qConfigWordAddress = NULL; - unsigned int i; - - /* - * Need to initialize AQM hardware registers to an initial - * value as init may have been called as a result of a soft - * reset. i.e. soft reset does not reset hardware registers. - */ - - /* Reset queues 0..31 status registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - - /* Reset underflow/overflow status registers 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - - /* Reset queues 32..63 nearly empty status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET), - IX_QMGR_QUEUPPSTAT0_RESET_VALUE); - - /* Reset queues 32..63 full status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET), - IX_QMGR_QUEUPPSTAT1_RESET_VALUE); - - /* Reset int0 status flag source select registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - - /* Reset queue interrupt enable register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - - /* Reset queue interrupt register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - - /* Reset queue configuration words 0..63 */ - qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++) - { - ixQMgrAqmIfWordWrite(qConfigWordAddress, - IX_QMGR_QUECONFIG_RESET_VALUE); - /* Next word */ - qConfigWordAddress++; - } -} - diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c deleted file mode 100644 index 2baeaafeb1..0000000000 --- a/drivers/net/npe/IxQMgrDispatcher.c +++ /dev/null @@ -1,1320 +0,0 @@ -/** - * @file IxQMgrDispatcher.c - * - * @author Intel Corporation - * @date 20-Dec-2001 - * - * @brief This file contains the implementation of the Dispatcher sub component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrDefines_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" - - - -/* - * #defines and macros used in this file. - */ - - -/* - * This constant is used to indicate the number of priority levels supported - */ -#define IX_QMGR_NUM_PRIORITY_LEVELS 3 - -/* - * This constant is used to set the size of the array of status words - */ -#define MAX_Q_STATUS_WORDS 4 - -/* - * This macro is used to check if a given priority is valid - */ -#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \ -(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2)) - -/* - * This macto is used to check that a given interrupt source is valid - */ -#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \ -(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F)) - -/* - * Number of times a dummy callback is called before logging a trace - * message - */ -#define LOG_THROTTLE_COUNT 1000000 - -/* Priority tables limits */ -#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0) -#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16) -#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31) -#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32) -#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48) -#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63) - -/* - * This macro is used to check if a given callback type is valid - */ -#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \ - (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \ - ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC)) - -/* - * define max index in lower queue to use in loops - */ -#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Information on a queue needed by the Dispatcher - */ -typedef struct -{ - IxQMgrCallback callback; /* Notification callback */ - IxQMgrCallbackId callbackId; /* Notification callback identifier */ - unsigned dummyCallbackCount; /* Number of times runs of dummy callback */ - IxQMgrPriority priority; /* Dispatch priority */ - unsigned int statusWordOffset; /* Offset to the status word to check */ - UINT32 statusMask; /* Status mask */ - UINT32 statusCheckValue; /* Status check value */ - UINT32 intRegCheckMask; /* Interrupt register check mask */ -} IxQMgrQInfo; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -/* - * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit() - * is called. This is needed because it is possible that a client might - * change whether the live lock prevention dispatcher is used between - * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet(). - */ -PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED; - -/* - * keep record of Q types - not in IxQMgrQInfo for performance as - * it is only used with ixQMgrDispatcherLoopRunB0LLP() - */ -PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This array contains a list of queue identifiers ordered by priority. The table - * is split logically between queue identifiers 0-31 and 32-63. - */ -static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This flag indicates to the dispatcher that the priority table needs to be rebuilt. - */ -static BOOL rebuildTable = false; - -/* Dispatcher statistics */ -static IxQMgrDispatcherStats dispatcherStats; - -/* Table of queue information */ -static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* Masks use to identify the first queues in the priority tables -* when comparing with the interrupt register -*/ -static unsigned int lowPriorityTableFirstHalfMask; -static unsigned int uppPriorityTableFirstHalfMask; - -/* - * Static function prototypes - */ - -/* - * This function is the default callback for all queues - */ -PRIVATE void -dummyCallback (IxQMgrQId qId, - IxQMgrCallbackId cbId); - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void); - -/* - * Function definitions. - */ -void -ixQMgrDispatcherInit (void) -{ - int i; - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - BOOL stickyIntSilicon = true; - - /* Set default priorities */ - for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - dispatchQInfo[i].callback = dummyCallback; - dispatchQInfo[i].callbackId = 0; - dispatchQInfo[i].dummyCallbackCount = 0; - dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2; - dispatchQInfo[i].statusWordOffset = 0; - dispatchQInfo[i].statusCheckValue = 0; - dispatchQInfo[i].statusMask = 0; - /* - * There are two interrupt registers, 32 bits each. One for the lower - * queues(0-31) and one for the upper queues(32-63). Therefore need to - * mod by 32 i.e the min upper queue identifier. - */ - dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID))); - - /* - * Set the Q types - will only be used with livelock - */ - ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER; - - /* Reset queue statistics */ - dispatcherStats.queueStats[i].callbackCnt = 0; - dispatcherStats.queueStats[i].priorityChangeCnt = 0; - dispatcherStats.queueStats[i].intNoCallbackCnt = 0; - dispatcherStats.queueStats[i].intLostCallbackCnt = 0; - dispatcherStats.queueStats[i].notificationEnabled = false; - dispatcherStats.queueStats[i].srcSel = 0; - - } - - /* Priority table. Order the table from queue 0 to 63 */ - ixQMgrDispatcherReBuildPriorityTable(); - - /* Reset statistics */ - dispatcherStats.loopRunCnt = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead(); - - /* - * Check featureCtrl to see if Livelock prevention is required - */ - ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck( - IX_FEATURECTRL_ORIGB0_DISPATCHER); - - /* - * Check if the silicon supports the sticky interrupt feature. - * IF (IXP42X AND A0) -> No sticky interrupt feature supported - */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - stickyIntSilicon = false; - } - - /* - * IF user wants livelock prev option AND silicon supports sticky interrupt - * feature -> enable the sticky interrupt bit - */ - if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) && - stickyIntSilicon) - { - ixQMgrStickyInterruptRegEnable(); - } -} - -IX_STATUS -ixQMgrDispatcherPrioritySet (IxQMgrQId qId, - IxQMgrPriority priority) -{ - int ixQMgrLockKey; - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority)) - { - return IX_QMGR_Q_INVALID_PRIORITY; - } - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Change priority */ - dispatchQInfo[qId].priority = priority; - /* Set flag */ - rebuildTable = true; - - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qId].priorityChangeCnt++; -#endif - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationCallbackSet (IxQMgrQId qId, - IxQMgrCallback callback, - IxQMgrCallbackId callbackId) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (NULL == callback) - { - /* Reset to dummy callback */ - dispatchQInfo[qId].callback = dummyCallback; - dispatchQInfo[qId].dummyCallbackCount = 0; - dispatchQInfo[qId].callbackId = 0; - } - else - { - dispatchQInfo[qId].callback = callback; - dispatchQInfo[qId].callbackId = callbackId; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationEnable (IxQMgrQId qId, - IxQMgrSourceId srcSel) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - int ixQMgrLockKey; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if ((qId < IX_QMGR_MIN_QUEUPP_QID) && - !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel)) - { - /* QId 0-31 source id invalid */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } - - if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) && - (qId >= IX_QMGR_MIN_QUEUPP_QID)) - { - /* - * For queues 32-63 the interrupt source is fixed to the Nearly - * Empty status flag and therefore should have a srcSel of NE. - */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } -#endif - -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = true; - dispatcherStats.queueStats[qId].srcSel = srcSel; -#endif - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Calculate the checkMask and checkValue for this q */ - ixQMgrAqmIfQStatusCheckValsCalc (qId, - srcSel, - &dispatchQInfo[qId].statusWordOffset, - &dispatchQInfo[qId].statusCheckValue, - &dispatchQInfo[qId].statusMask); - - - /* Set the interrupt source is this queue is in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); - } - - /* Enable the interrupt */ - ixQMgrAqmIfQInterruptEnable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - - -IX_STATUS -ixQMgrNotificationDisable (IxQMgrQId qId) -{ - int ixQMgrLockKey; - -#ifndef NDEBUG - /* Validate parameters */ - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = false; -#endif - - ixQMgrLockKey = ixOsalIrqLock(); - - ixQMgrAqmIfQInterruptDisable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - return IX_SUCCESS; -} - -void -ixQMgrStickyInterruptRegEnable(void) -{ - /* Use Aqm If function to set Interrupt Register0 Bit-3 */ - ixQMgrAqmIfIntSrcSelReg0Bit3Set (); -} - -#if !defined __XSCALE__ || defined __linux - -/* Count the number of leading zero bits in a word, - * and return the same value than the CLZ instruction. - * - * word (in) return value (out) - * 0x80000000 0 - * 0x40000000 1 - * ,,, ,,, - * 0x00000002 30 - * 0x00000001 31 - * 0x00000000 32 - * - * The C version of this function is used as a replacement - * for system not providing the equivalent of the CLZ - * assembly language instruction. - * - * Note that this version is big-endian - */ -unsigned int -ixQMgrCountLeadingZeros(UINT32 word) -{ - unsigned int leadingZerosCount = 0; - - if (word == 0) - { - return 32; - } - /* search the first bit set by testing the MSB and shifting the input word */ - while ((word & 0x80000000) == 0) - { - word <<= 1; - leadingZerosCount++; - } - return leadingZerosCount; -} -#endif /* not __XSCALE__ or __linux */ - -void -ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr) -{ - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead (); - - /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - /*For IXP42X A0 silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ; - } - else /*For IXP42X B0 or IXP46X silicon*/ - { - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher) - { - /* Default for IXP42X B0 and IXP46X silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0; - } - else - { - /* FeatureCtrl indicated that livelock dispatcher be used */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP; - } - } -} - -void -ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegValAfterWrite; /* Interrupt reg val after writing back */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS]; /* Status b4 interrupt write */ - UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */ - IxQMgrQInfo *currDispatchQInfo; - BOOL statusChangeFlag; - - int priorityTableIndex;/* Priority table index */ - int qIndex; /* Current queue being processed */ - int endIndex; /* Index of last queue to process */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read Q status registers before interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write); - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* No bit set : nothing to process (the reaminder of the algorithm is - * based on the fact that the interrupt register value contains at - * least one bit set - */ - if (intRegVal == 0) - { -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - - return; - } - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* Read Q status registers after interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - /* check if any change occured during hw register modifications */ - if (IX_QMGR_QUELOW_GROUP == group) - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) || - (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) || - (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) || - (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]); - } - else - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]); - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - if (statusChangeFlag == false) - { - /* check if the interrupt register contains - * only 1 bit set (happy day scenario) - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } - } - else - { - /* A change in queue status occured during the hw interrupt - * register update. To maintain the interrupt consistency, it - * is necessary to iterate through all queues of the queue group. - */ - - /* Read interrupt status again */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite); - - if (IX_QMGR_QUELOW_GROUP == group) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX; - } - - for ( ; priorityTableIndex<=endIndex; priorityTableIndex++) - { - qIndex = priorityTable[priorityTableIndex]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - } /* if (intRegVal .. */ - - /* - * If interrupt bit is set in intRegValAfterWrite don't - * proceed as this will be caught in next interrupt - */ - else if ((intRegValAfterWrite & intRegCheckMask) == 0) - { - /* Check if an interrupt was lost for this Q */ - if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write, - qStatusWordsAfterWrite, - currDispatchQInfo->statusWordOffset, - currDispatchQInfo->statusCheckValue, - currDispatchQInfo->statusMask)) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - dispatchQInfo[qIndex].callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; - dispatcherStats.queueStats[qIndex].intLostCallbackCnt++; -#endif - } /* if ixQMgrAqmIfQStatusCheck(.. */ - } /* else if ((intRegValAfterWrite ... */ - } /* for (priorityTableIndex=0 ... */ - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif -} - - - -void -ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -void -ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal =0; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - - UINT32 intRegValCopy = 0; - UINT32 intEnableRegVal = 0; - UINT8 i = 0; - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* - * mask any interrupts that are not enabled - */ - ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal); - intRegVal &= intEnableRegVal; - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - if (IX_QMGR_QUELOW_GROUP == group) - { - /* - * As the sticky bit is set, the interrupt register will - * not clear if write back at this point because the condition - * has not been cleared. Take a copy and write back later after - * the condition has been cleared - */ - intRegValCopy = intRegVal; - } - else - { - /* no sticky for upper Q's, so write back now */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - } - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic. There can only be one - * periodic queue, so the sporadics are only disabled once. - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == - ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); - /* - * remove from intRegVal as we don't want - * to service any sporadics now - */ - intRegVal &= ~dispatchQInfo[i].intRegCheckMask; -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group)) - { - /* - * lower groups (therefore sticky) AND at least one enabled interrupt - * Write back to clear the interrupt - */ - ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy); - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void) -{ - UINT32 qIndex; - UINT32 priority; - int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - - /* Reset the rebuild flag */ - rebuildTable = false; - - /* initialize the mak used to identify the queues in the first half - * of the priority table - */ - lowPriorityTableFirstHalfMask = 0; - uppPriorityTableFirstHalfMask = 0; - - /* For each priority level */ - for(priority=0; priority dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId); - } - dispatchQInfo[qId].dummyCallbackCount++; - -#ifndef NDEBUG - /* Update statistcs */ - dispatcherStats.queueStats[qId].intNoCallbackCnt++; -#endif -} -void -ixQMgrLLPShow (int resetStats) -{ -#ifndef NDEBUG - UINT8 i = 0; - UINT32 intEnableRegVal = 0; - - printf ("Livelock statistics are printed on the fly.\n"); - printf ("qId Type EnableCnt DisableCnt IntEnableState Callbacks\n"); - printf ("=== ======== ========= ========== ============== =========\n"); - - for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER) - { - printf (" %2d ", i); - - if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC) - { - printf ("Sporadic"); - } - else - { - printf ("Periodic"); - } - - - ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP, - &intEnableRegVal); - - - intEnableRegVal &= dispatchQInfo[i].intRegCheckMask; - intEnableRegVal = intEnableRegVal >> i; - - printf (" %10d %10d %10d %10d\n", - dispatcherStats.queueStats[i].enableCount, - dispatcherStats.queueStats[i].disableCount, - intEnableRegVal, - dispatcherStats.queueStats[i].callbackCnt); - - if (resetStats) - { - dispatcherStats.queueStats[i].enableCount = - dispatcherStats.queueStats[i].disableCount = - dispatcherStats.queueStats[i].callbackCnt = 0; - } - } - } -#else - IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n"); -#endif -} - -void -ixQMgrPeriodicDone (void) -{ - UINT32 i = 0; - UINT32 ixQMgrLockKey = 0; - - /* - * for the lower queues - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - /* - * check for sporadics - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - /* - * enable any sporadics - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(i); - ixOsalIrqUnlock(ixQMgrLockKey); -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[i].enableCount++; - dispatcherStats.queueStats[i].notificationEnabled = true; -#endif - } - } -} -IX_STATUS -ixQMgrCallbackTypeSet (IxQMgrQId qId, - IxQMgrType type) -{ - UINT32 ixQMgrLockKey = 0; - IxQMgrType ixQMgrOldType =0; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type)) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - ixQMgrOldType = ixQMgrQTypes[qId]; - ixQMgrQTypes[qId] = type; - - /* - * check if Q has been changed from type SPORADIC - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType) - { - /* - * previously Q was a SPORADIC, this means that LLP - * might have had it disabled. enable it now. - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(qId); - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[qId].enableCount++; -#endif - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrCallbackTypeGet (IxQMgrQId qId, - IxQMgrType *type) -{ -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(type == NULL) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - *type = ixQMgrQTypes[qId]; - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c deleted file mode 100644 index 14687e61af..0000000000 --- a/drivers/net/npe/IxQMgrInit.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - * @file IxQMgrInit.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief: Provided initialization of the QMgr component and its subcomponents. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrDefines_p.h" -#include "IxQMgrAqmIf_p.h" - -/* - * Set to true if initialized - * N.B. global so integration/unit tests can reinitialize - */ -BOOL qMgrIsInitialized = false; - -/* - * Function definitions. - */ -IX_STATUS -ixQMgrInit (void) -{ - if (qMgrIsInitialized) - { - IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n"); - return IX_FAIL; - } - - /* Initialise the QCfg component */ - ixQMgrQCfgInit (); - - /* Initialise the Dispatcher component */ - ixQMgrDispatcherInit (); - - /* Initialise the Access component */ - ixQMgrQAccessInit (); - - /* Initialization complete */ - qMgrIsInitialized = true; - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrUnload (void) -{ - if (!qMgrIsInitialized) - { - return IX_FAIL; - } - - /* Uninitialise the QCfg component */ - ixQMgrQCfgUninit (); - - /* Uninitialization complete */ - qMgrIsInitialized = false; - - return IX_SUCCESS; -} - -void -ixQMgrShow (void) -{ - IxQMgrQCfgStats *qCfgStats = NULL; - IxQMgrDispatcherStats *dispatcherStats = NULL; - int i; - UINT32 lowIntRegRead, upIntRegRead; - - qCfgStats = ixQMgrQCfgStatsGet (); - dispatcherStats = ixQMgrDispatcherStatsGet (); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead); - printf("Generic Stats........\n"); - printf("=====================\n"); - printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt); - printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt); - printf("===========================================\n"); - printf("On the fly Interrupt Register Stats........\n"); - printf("===========================================\n"); - printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead); - printf("Upper Interrupt Register............0x%08x\n",upIntRegRead); - printf("==============================================\n"); - printf("Queue Specific Stats........\n"); - printf("============================\n"); - - for (i=0; iqStats[qId].qName); - printf(" Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords); - printf(" Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords); - printf(" Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne); - printf(" Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf); - printf(" Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries); - printf(" Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress); - printf(" Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr); - printf(" Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr); - -#ifndef NDEBUG - if (dispatcherStats->queueStats[qId].notificationEnabled) - { - char *localEvent = "none ????"; - switch (dispatcherStats->queueStats[qId].srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - localEvent = "Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - localEvent = "Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - localEvent = "Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_F: - localEvent = "Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - localEvent = "Not Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - localEvent = "Not Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - localEvent = "Not Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - localEvent = "Not Full"; - break; - default : - break; - } - printf(" Notifications localEvent...... %s\n", localEvent); - } - else - { - printf(" Notifications............ not enabled\n"); - } - printf(" IxQMgrDispatcher Stats\n"); - printf(" Callback count................%d\n", - dispatcherStats->queueStats[qId].callbackCnt); - printf(" Priority change count.........%d\n", - dispatcherStats->queueStats[qId].priorityChangeCnt); - printf(" Interrupt no callback count...%d\n", - dispatcherStats->queueStats[qId].intNoCallbackCnt); - printf(" Interrupt lost callback count...%d\n", - dispatcherStats->queueStats[qId].intLostCallbackCnt); -#endif - - return IX_SUCCESS; -} - - - - diff --git a/drivers/net/npe/IxQMgrQAccess.c b/drivers/net/npe/IxQMgrQAccess.c deleted file mode 100644 index 13ee0f4f11..0000000000 --- a/drivers/net/npe/IxQMgrQAccess.c +++ /dev/null @@ -1,772 +0,0 @@ -/** - * @file IxQMgrQAccess.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This file contains functions for putting entries on a queue and - * removing entries from a queue. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgr.h" - */ -#ifndef IXQMGR_H -# define IXQMGRQACCESS_C -#else -# error -#endif - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * Global variables and extern definitions - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - -/* - * Function definitions. - */ -void -ixQMgrQAccessInit (void) -{ -} - -IX_STATUS -ixQMgrQReadWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPop (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries) - { - infoPtr->qReadCount = 0; - } - - /* Check if underflow occurred on the read */ - if (ixQMgrAqmIfUnderflowCheck (qId)) - { - return IX_QMGR_Q_UNDERFLOW; - } - - return IX_SUCCESS; -} - -/* this function reads the remaining of the q entry - * for queues configured with many words. - * (the first word of the entry is already read - * in the inlined function and the entry pointer already - * incremented - */ -IX_STATUS -ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize = infoPtr->qEntrySizeInWords; - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - while (--entrySize) - { - /* read the entry and accumulate the result */ - *(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr); - } - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQWriteWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPush (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries) - { - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write*/ - if (ixQMgrAqmIfOverflowCheck (qId)) - { - return IX_QMGR_Q_OVERFLOW; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQPeek (IxQMgrQId qId, - unsigned int entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (entryIndex >= numEntries) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPeek (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQPoke (IxQMgrQId qId, - unsigned entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex > 128)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPoke (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQStatusGetWithChecks (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - if (NULL == qStatus) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - ixQMgrAqmIfQueStatRead (qId, qStatus); - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQNumEntriesGet (IxQMgrQId qId, - unsigned *numEntriesPtr) -{ - UINT32 qPtrs; - UINT32 qStatus; - unsigned numEntries; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - -#ifndef NDEBUG - if (NULL == numEntriesPtr) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* get fast access data */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - - /* get snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (numEntries == 0) - { - /* - * Could mean either full or empty queue - * so look at status - */ - ixQMgrAqmIfQueStatRead (qId, &qStatus); - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) - { - /* Empty */ - *numEntriesPtr = 0; - } - else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* Full */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* - * Queue status and read/write pointers are volatile. - * The queue state has changed since we took the - * snapshot of the read and write pointers. - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - else /* It is an upper queue which does not have an empty status bit maintained */ - { - if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* The queue is Full at the time of snapshot. */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* The queue is either empty, either moving, - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - } - else - { - *numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1); - } - - return IX_SUCCESS; -} - -#if defined(__wince) && defined(NO_INLINE_APIS) - -PUBLIC IX_STATUS -ixQMgrQRead (IxQMgrQId qId, - UINT32 *entryPtr) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entry, entrySize; - - /* get a new entry */ - entrySize = infoPtr->qEntrySizeInWords; - entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - *entryPtr = entry; - /* process the remaining part of the entry */ - return ixQMgrQReadMWordsMinus1(qId, entryPtr); - } - - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* the counter of queue entries is decremented. In happy - * day scenario there are many entries in the queue - * and the counter does not reach zero. - */ - if (infoPtr->qReadCount-- == 0) - { - /* There is maybe no entry in the queue - * qReadCount is now negative, but will be corrected before - * the function returns. - */ - UINT32 qPtrs; /* queue internal pointers */ - - /* when a queue is empty, the hw guarantees to return - * a null value. If the value is not null, the queue is - * not empty. - */ - if (entry == 0) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - *entryPtr = 0; - infoPtr->qReadCount = 0; - return IX_QMGR_Q_UNDERFLOW; - } - } - /* store the result */ - *entryPtr = entry; - - /* No underflow occured : someone is filling the queue - * or the queue contains null entries. - * The current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get snapshot of queue pointers */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* no entry in the queue */ - infoPtr->qReadCount = 0; - } - else - { - /* convert the number of words inside the queue - * to a number of entries - */ - infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1); - } - return IX_SUCCESS; - } - } - *entryPtr = entry; - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstRead (IxQMgrQId qId, - UINT32 numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 nullCheckEntry; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - /* the code is optimized to take care of data dependencies: - * Durig a read, there are a few cycles needed to get the - * read complete. During these cycles, it is poossible to - * do some CPU, e.g. increment pointers and decrement - * counters. - */ - - /* fetch a queue entry */ - nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - /* iterate the specified number of queue entries */ - while (--numEntries) - { - /* check the result of the previous read */ - if (nullCheckEntry == 0) - { - /* if we read a NULL entry, stop. We have underflowed */ - break; - } - else - { - /* write the entry */ - *entries = nullCheckEntry; - /* fetch next entry */ - nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr); - /* increment the write address */ - entries++; - } - } - /* write the pre-fetched entry */ - *entries = nullCheckEntry; - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - /* read the specified number of queue entries */ - nullCheckEntry = 0; - while (numEntries--) - { - int i; - - for (i = 0; i < entrySizeInWords; i++) - { - *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i); - nullCheckEntry |= *entries++; - } - - /* if we read a NULL entry, stop. We have underflowed */ - if (nullCheckEntry == 0) - { - break; - } - nullCheckEntry = 0; - } - } - - /* reset the current read count : next access to the read function - * will force a underflow status check - */ - infoPtr->qWriteCount = 0; - - /* Check if underflow occurred on the read */ - if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - if (status & infoPtr->qUflowStatBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQWrite (IxQMgrQId qId, - UINT32 *entry) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize; - - /* write the entry */ - IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry); - entrySize = infoPtr->qEntrySizeInWords; - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - /* process the remaining part of the entry */ - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (--entrySize) - { - ++entry; - IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry); - } - entrySize = infoPtr->qEntrySizeInWords; - } - - /* overflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - UINT32 qSize = infoPtr->qSizeInEntries; - /* increment the current number of entries in the queue - * and check for overflow - */ - if (infoPtr->qWriteCount++ == qSize) - { - /* the queue may have overflow */ - UINT32 qPtrs; /* queue internal pointers */ - - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be immediately ready after the write operation - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* the queue is full, clear the overflow status - * bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - return IX_QMGR_Q_OVERFLOW; - } - /* No overflow occured : someone is draining the queue - * and the current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get q pointer snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* the queue may be full at the time of the - * snapshot. Next access will check - * the overflow status again. - */ - infoPtr->qWriteCount = qSize; - } - else - { - /* convert the number of words to a number of entries */ - if (entrySize == IX_QMGR_Q_ENTRY_SIZE1) - { - infoPtr->qWriteCount = qPtrs & (qSize - 1); - } - else - { - infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1); - } - } - } - } - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstWrite (IxQMgrQId qId, - unsigned numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 status; - - /* update the current write count */ - infoPtr->qWriteCount += numEntries; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (numEntries--) - { - IX_OSAL_WRITE_LONG(qAccRegAddr, *entries); - entries++; - } - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - int i; - - /* write each queue entry */ - while (numEntries--) - { - /* write the queueEntrySize number of words for each entry */ - for (i = 0; i < entrySizeInWords; i++) - { - IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries); - entries++; - } - } - } - - /* check if the write count overflows */ - if (infoPtr->qWriteCount > infoPtr->qSizeInEntries) - { - /* reset the current write count */ - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write operation */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be ready at the time of the write - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - return IX_QMGR_Q_OVERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQStatusGet (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - /* read the status of a queue in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsMask; - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId]; - volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr; - - UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId]; - UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask; - UINT32 underflowBitMask = infoPtr->qUflowStatBitMask; - UINT32 overflowBitMask = infoPtr->qOflowStatBitMask; - - /* read the status register for this queue */ - *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr); - /* mask out the status bits relevant only to this queue */ - *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask; - - /* Check if the queue has overflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask) - { - /* clear the overflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~overflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK; - } - - /* Check if the queue has underflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~underflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK; - } - } - else /* read status of a queue in the range 32-63 */ - { - extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[]; - extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[]; - - volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr; - volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr; - int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID; - UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex]; - UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex]; - - /* Reset the status bits */ - *qStatus = 0; - - /* Check if the queue is nearly empty */ - if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK; - } - - /* Check if the queue is full */ - if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK; - } - } - return IX_SUCCESS; -} -#endif /* def NO_INLINE_APIS */ diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c deleted file mode 100644 index b64bb2dd90..0000000000 --- a/drivers/net/npe/IxQMgrQCfg.c +++ /dev/null @@ -1,519 +0,0 @@ -/** - * @file QMgrQCfg.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This modules provides an interface for setting up the static - * configuration of AQM queues.This file contains the following - * functions: - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * #defines and macros used in this file. - */ - -#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 - -/* Total size of SRAM */ -#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 - -/* - * Check that qId is a valid queue identifier. This is provided to - * make the code easier to read. - */ -#define IX_QMGR_QID_IS_VALID(qId) \ -(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID))) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * This struct describes an AQM queue. - * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue - * as these are requested by Access in the data path. sizeInEntries is - * not required by the data path so it can be calculated dynamically. - * - */ -typedef struct -{ - char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ - IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ - IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ - BOOL isConfigured; /* This flag is true if the queue has - * been configured - */ -} IxQMgrCfgQ; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; - -/* Store data required to inline read and write access - */ -IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES]; - -static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* This pointer holds the starting address of AQM SRAM not used by - * the AQM queues. - */ -static UINT32 freeSramAddress=0; - -/* 4 words of zeroed memory for inline access */ -static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; - -static BOOL cfgInitialized = false; - -static IxOsalMutex ixQMgrQCfgMutex; - -/* - * Statistics - */ -static IxQMgrQCfgStats stats; - -/* - * Function declarations - */ -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level); - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize); - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize); - -/* - * Function definitions. - */ -void -ixQMgrQCfgInit (void) -{ - int loopIndex; - - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - /* info for code inlining */ - ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder; - - /* info for code inlining */ - ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder; - } - - /* Initialise the AqmIf component */ - ixQMgrAqmIfInit (); - - /* Reset all queues to have queue name = NULL, entry size = 0 and - * isConfigured = false - */ - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - strcpy (cfgQueueInfo[loopIndex].qName, ""); - cfgQueueInfo[loopIndex].qSizeInWords = 0; - cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; - cfgQueueInfo[loopIndex].isConfigured = false; - - /* Statistics */ - stats.qStats[loopIndex].isConfigured = false; - stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; - } - - /* Statistics */ - stats.wmSetCnt = 0; - - ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress); - - ixOsalMutexInit(&ixQMgrQCfgMutex); - - cfgInitialized = true; -} - -void -ixQMgrQCfgUninit (void) -{ - cfgInitialized = false; - - /* Uninitialise the AqmIf component */ - ixQMgrAqmIfUninit (); -} - -IX_STATUS -ixQMgrQConfig (char *qName, - IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords qEntrySizeInWords) -{ - UINT32 aqmLocalBaseAddress; - - if (!cfgInitialized) - { - return IX_FAIL; - } - - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return IX_QMGR_INVALID_Q_ID; - } - - else if (NULL == qName) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (!qSizeInWordsIsOk (qSizeInWords)) - { - return IX_QMGR_INVALID_QSIZE; - } - - else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords)) - { - return IX_QMGR_INVALID_Q_ENTRY_SIZE; - } - - else if (cfgQueueInfo[qId].isConfigured) - { - return IX_QMGR_Q_ALREADY_CONFIGURED; - } - - ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER); - - /* Write the config register */ - ixQMgrAqmIfQueCfgWrite (qId, - qSizeInWords, - qEntrySizeInWords, - freeSramAddress); - - - strcpy (cfgQueueInfo[qId].qName, qName); - cfgQueueInfo[qId].qSizeInWords = qSizeInWords; - cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - - /* store pre-computed information in the same cache line - * to facilitate inlining of QRead and QWrite functions - * in IxQMgr.h - */ - ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = - (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords; - - /* Calculate the new freeSramAddress from the size of the queue - * currently being configured. - */ - freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD); - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <= - IX_QMGR_QUE_BUFFER_SPACE_SIZE); - - /* The queue is now configured */ - cfgQueueInfo[qId].isConfigured = true; - - ixOsalMutexUnlock(&ixQMgrQCfgMutex); - -#ifndef NDEBUG - /* Update statistics */ - stats.qStats[qId].isConfigured = true; - stats.qStats[qId].qName = cfgQueueInfo[qId].qName; -#endif - return IX_SUCCESS; -} - -IxQMgrQSizeInWords -ixQMgrQSizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qSizeInWords); -} - -IX_STATUS -ixQMgrQSizeInEntriesGet (IxQMgrQId qId, - unsigned *qSizeInEntries) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if(NULL == qSizeInEntries) - { - return IX_QMGR_PARAMETER_ERROR; - } - - *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) / - (UINT32)cfgQueueInfo[qId].qEntrySizeInWords; - - return IX_SUCCESS; -} - -IxQMgrQEntrySizeInWords -ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qEntrySizeInWords); -} - -IX_STATUS -ixQMgrWatermarkSet (IxQMgrQId qId, - IxQMgrWMLevel ne, - IxQMgrWMLevel nf) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!watermarkLevelIsOk (qId, ne)) - { - return IX_QMGR_INVALID_Q_WM; - } - - if (!watermarkLevelIsOk (qId, nf)) - { - return IX_QMGR_INVALID_Q_WM; - } - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - -#ifndef NDEBUG - /* Update statistics */ - stats.wmSetCnt++; -#endif - - ixQMgrAqmIfWatermarkSet (qId, - ne, - nf); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAvailableSramAddressGet (UINT32 *address, - unsigned *sizeOfFreeRam) -{ - UINT32 aqmLocalBaseAddress; - - if ((NULL == address)||(NULL == sizeOfFreeRam)) - { - return IX_QMGR_PARAMETER_ERROR; - } - if (!cfgInitialized) - { - return IX_FAIL; - } - - *address = freeSramAddress; - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - /* - * Calculate the size in bytes of free sram - * i.e. current free SRAM virtual pointer from - * (base + total size) - */ - *sizeOfFreeRam = - (aqmLocalBaseAddress + - IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) - - freeSramAddress; - - if (0 == *sizeOfFreeRam) - { - return IX_QMGR_NO_AVAILABLE_SRAM; - } - - return IX_SUCCESS; -} - -BOOL -ixQMgrQIsConfigured (IxQMgrQId qId) -{ - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return false; - } - - return cfgQueueInfo[qId].isConfigured; -} - -IxQMgrQCfgStats* -ixQMgrQCfgStatsGet (void) -{ - return &stats; -} - -IxQMgrQCfgStats* -ixQMgrQCfgQStatsGet (IxQMgrQId qId) -{ - unsigned int ne; - unsigned int nf; - UINT32 baseAddress; - UINT32 readPtr; - UINT32 writePtr; - - stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords; - stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords; - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId); - } - } - - ixQMgrAqmIfQueCfgRead (qId, - stats.qStats[qId].numEntries, - &baseAddress, - &ne, - &nf, - &readPtr, - &writePtr); - - stats.qStats[qId].baseAddress = baseAddress; - stats.qStats[qId].ne = ne; - stats.qStats[qId].nf = nf; - stats.qStats[qId].readPtr = readPtr; - stats.qStats[qId].writePtr = writePtr; - - return &stats; -} - -/* - * Static function definitions - */ - -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) -{ - unsigned qSizeInEntries; - - switch (level) - { - case IX_QMGR_Q_WM_LEVEL0: - case IX_QMGR_Q_WM_LEVEL1: - case IX_QMGR_Q_WM_LEVEL2: - case IX_QMGR_Q_WM_LEVEL4: - case IX_QMGR_Q_WM_LEVEL8: - case IX_QMGR_Q_WM_LEVEL16: - case IX_QMGR_Q_WM_LEVEL32: - case IX_QMGR_Q_WM_LEVEL64: - break; - default: - return false; - } - - /* Check watermark is not bigger than the qSizeInEntries */ - ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries); - - if ((unsigned)level > qSizeInEntries) - { - return false; - } - - return true; -} - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) -{ - BOOL status; - - switch (qSize) - { - case IX_QMGR_Q_SIZE16: - case IX_QMGR_Q_SIZE32: - case IX_QMGR_Q_SIZE64: - case IX_QMGR_Q_SIZE128: - status = true; - break; - default: - status = false; - break; - } - - return status; -} - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) -{ - BOOL status; - - switch (entrySize) - { - case IX_QMGR_Q_ENTRY_SIZE1: - case IX_QMGR_Q_ENTRY_SIZE2: - case IX_QMGR_Q_ENTRY_SIZE4: - status = true; - break; - default: - status = false; - break; - } - - return status; -} diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile deleted file mode 100644 index 0779255216..0000000000 --- a/drivers/net/npe/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux -CFLAGS += $(LOCAL_CFLAGS) -CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend - -obj-y := npe.o \ - miiphy.o \ - IxOsalBufferMgt.o \ - IxOsalIoMem.o \ - IxOsalOsCacheMMU.o \ - IxOsalOsMsgQ.o \ - IxOsalOsSemaphore.o \ - IxOsalOsServices.o \ - IxOsalOsThread.o \ - IxEthAcc.o \ - IxEthAccCommon.o \ - IxEthAccControlInterface.o \ - IxEthAccDataPlane.o \ - IxEthAccMac.o \ - IxEthAccMii.o \ - IxEthDBAPI.o \ - IxEthDBAPISupport.o \ - IxEthDBCore.o \ - IxEthDBEvents.o \ - IxEthDBFeatures.o \ - IxEthDBFirewall.o \ - IxEthDBHashtable.o \ - IxEthDBLearning.o \ - IxEthDBMem.o \ - IxEthDBNPEAdaptor.o \ - IxEthDBPortUpdate.o \ - IxEthDBReports.o \ - IxEthDBSearch.o \ - IxEthDBSpanningTree.o \ - IxEthDBUtil.o \ - IxEthDBVlan.o \ - IxEthDBWiFi.o \ - IxEthMii.o \ - IxQMgrAqmIf.o \ - IxQMgrDispatcher.o \ - IxQMgrInit.o \ - IxQMgrQAccess.o \ - IxQMgrQCfg.o \ - IxFeatureCtrl.o \ - IxNpeDl.o \ - IxNpeDlImageMgr.o \ - IxNpeDlNpeMgr.o \ - IxNpeDlNpeMgrUtils.o \ - IxNpeMh.o \ - IxNpeMhConfig.o \ - IxNpeMhReceive.o \ - IxNpeMhSend.o \ - IxNpeMhSolicitedCbMgr.o \ - IxNpeMhUnsolicitedCbMgr.o diff --git a/drivers/net/npe/include/IxAssert.h b/drivers/net/npe/include/IxAssert.h deleted file mode 100644 index 8be0cafc44..0000000000 --- a/drivers/net/npe/include/IxAssert.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file IxAssert.h - * - * @date 21-MAR-2002 (replaced by OSAL) - * - * @brief This file contains assert and ensure macros used by the IXP400 software - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API - * - * @brief Assertion support - * - * @{ - */ - -#ifndef IXASSERT_H - -#ifndef __doxygen_HIDE -#define IXASSERT_H -#endif /* __doxygen_HIDE */ - -#include "IxOsalBackward.h" - -#endif /* IXASSERT_H */ - -/** - * @} addtogroup IxAssert - */ - - - diff --git a/drivers/net/npe/include/IxAtmSch.h b/drivers/net/npe/include/IxAtmSch.h deleted file mode 100644 index 7d74771c28..0000000000 --- a/drivers/net/npe/include/IxAtmSch.h +++ /dev/null @@ -1,480 +0,0 @@ -/** - * @file IxAtmSch.h - * - * @date 23-NOV-2001 - * - * @brief Header file for the IXP400 ATM Traffic Shaper - * - * This component demonstrates an ATM Traffic Shaper implementation. It - * will perform shaping on upto 12 ports and total of 44 VCs accross all ports, - * 32 are intended for AAL0/5 and 12 for OAM (1 per port). - * The supported traffic types are;1 rt-VBR VC where PCR = SCR. - * (Effectively CBR) and Up-to 44 VBR VCs. - * - * This component models the ATM ports and VCs and is capable of producing - * a schedule of ATM cells per port which can be supplied to IxAtmdAcc - * for execution on the data path. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - * @sa IxAtmm.h - * - */ - -/** - * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API - * - * @brief IXP400 ATM scheduler component Public API - * - * @{ - */ - -#ifndef IXATMSCH_H -#define IXATMSCH_H - -#include "IxOsalTypes.h" -#include "IxAtmTypes.h" - -/* - * #defines and macros used in this file. - */ - -/* Return codes */ - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_NOT_ADMITTED - * @brief Indicates that CAC function has rejected VC registration due - * to insufficient line capacity. -*/ -#define IX_ATMSCH_RET_NOT_ADMITTED 2 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_FULL - * @brief Indicates that the VC queue is full, no more demand can be - * queued at this time. - */ -#define IX_ATMSCH_RET_QUEUE_FULL 3 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_EMPTY - * @brief Indicates that all VC queues on this port are empty and - * therefore there are no cells to be scheduled at this time. - */ -#define IX_ATMSCH_RET_QUEUE_EMPTY 4 - -/* - * Function declarations - */ - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchInit(void) - * - * @brief This function is used to initialize the ixAtmSch component. It - * should be called before any other IxAtmSch API function. - * - * @param None - * - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler component has been successfully initialized. - * -# The scheduler is ready to accept Port modelling requests. - * - IX_FAIL : Some internal error has prevented the scheduler component - * from initialising. - */ -PUBLIC IX_STATUS -ixAtmSchInit(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule) - * - * @brief This function shall be called first to initialize an ATM port before - * any other ixAtmSch API calls may be made for that port. - * - * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize. Valid - * values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a - * maximum of IX_UTOPIA_MAX_PORTS possible ports. - * - * @param portRate unsigned int [in] - Value indicating the upstream capacity - * of the indicated port. The value should be supplied in - * units of ATM (53 bytes) cells per second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum - * number of cells which the scheduler will put in a schedule - * table for this port. This value sets the worst case CDVT for VCs - * on this port i.e. CDVT = 1*minCellsToSchedule/portRate. - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler has been successfully initialized. - * -# The requested port model has been established. - * -# The scheduler is ready to accept VC modelling requests - * on the ATM port. - * - IX_FAIL : indicates the requested port could not be - * initialized. */ -PUBLIC IX_STATUS -ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate) - * - * @brief This function is called to modify the portRate on a - * previously initialized port, typically in the event that - * the line condition of the port changes. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be - * modified. - * - * @param portRate unsigned int [in] - Value indicating the new upstream - * capacity for this port in cells/second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @return - * - IX_SUCCESS : The port rate has been successfully modified.
- * - IX_FAIL : The port rate could not be modified, either - * because the input data was invalid, or the new port rate is - * insufficient to support established ATM VC contracts on this - * port. - * - * @warning The IxAtmSch component will validate the supplied port - * rate is sufficient to support all established VC - * contracts on the port. If the new port rate is - * insufficient to support all established contracts then - * the request to modify the port rate will be rejected. - * In this event, the user is expected to remove - * established contracts using the ixAtmSchVcModelRemove - * interface and then retry this interface. - * - * @sa ixAtmSchVcModelRemove() */ -PUBLIC IX_STATUS -ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate); - - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId) - * - * @brief A client calls this interface to set up an upstream - * (transmitting) virtual connection model (VC) on the - * specified ATM port. This function also provides the - * virtual * connection admission control (CAC) service to the - * client. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is to be established. - * - * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure - * describing the requested traffic contract of the VC to be - * established. This structure contains the typical ATM - * traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.) - * defined by the ATM standard. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the - * port-unique identifier for this virtual connection. A - * valid identification is a non-negative number. - * - * @return - * - IX_SUCCESS : The VC has been successfully established on - * this port. The client may begin to submit demand on this VC. - * - IX_ATMSCH_RET_NOT_ADMITTED : The VC cannot be established - * on this port because there is insufficient upstream capacity - * available to support the requested traffic contract descriptor - * - IX_FAIL :Input data are invalid. VC has not been - * established. - */ -PUBLIC IX_STATUS -ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId) - * - * @brief A client calls this interface to set the vcUserConnId for a VC on - * the specified ATM port. This vcUserConnId will default to - * IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC. - * Hence if the client does not call this function for a VC then only idle - * cells will be scheduled for this VC. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is has been established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual - * connection. A valid identification is a non-negative number and is - * all ports. - * - * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule - * table entries. It is treated as the Id by which the scheduler client - * knows the VC. It is used in any communicatations from the Scheduler - * to the scheduler user e.g. schedule table entries. - * - * @return - * - IX_SUCCESS : The id has successfully been set. - * - IX_FAIL :Input data are invalid. connId id is not established. - */ -PUBLIC IX_STATUS -ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief Interface called by the client to remove a previously - * established VC on a particular port. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * removed is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC has been successfully removed from - * this port. It is no longer modelled on this port. - * - IX_FAIL :Input data are invalid. The VC is still being modeled - * by the traffic shaper. - * - * @sa ixAtmSchVcModelSetup() - */ -PUBLIC IX_STATUS -ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells) - * - * @brief The client calls this function to notify IxAtmSch that the - * user of a VC has submitted cells for transmission. - * - * This information is stored, aggregated from a number of calls to - * ixAtmSchVcQueueUpdate and eventually used in the call to - * ixAtmSchTableUpdate. - * - * Normally IxAtmSch will update the VC queue by adding the number of - * cells to the current queue length. However, if IxAtmSch - * determines that the user has over-submitted for the VC and - * exceeded its transmission quota the queue request can be rejected. - * The user should resubmit the request later when the queue has been - * depleted. - * - * This implementation of ixAtmSchVcQueueUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an interrupt handler. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueUpdate callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * updated is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should - * be added to the queue for this VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully updated. - * - IX_ATMSCH_RET_QUEUE_FULL : The VC queue has reached a - * preset limit. This indicates the client has over-submitted - * and exceeded its transmission quota. The request is - * rejected. The VC queue is not updated. The VC user is - * advised to resubmit the request later. - * - IX_FAIL : The input are invalid. No VC queue is updated. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief The client calls this function to remove all currently - * queued cells from a registered VC. The pending cell count - * for the specified VC is reset to zero. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueClear callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * cleared is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully cleared. - * - IX_FAIL : The input are invalid. No VC queue is modified. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable) - * - * @brief The client calls this function to request an update of the - * schedule table for a particular ATM port. - * - * This is called when the client decides it needs a new sequence of - * cells to send (probably because the transmit queue is near to - * empty for this ATM port). The scheduler will use its stored - * information on the cells submitted for transmit (i.e. data - * supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic - * descriptor information of all established VCs on the ATM port to - * decide the sequence of cells to be sent and fill the schedule - * table for a period of time into the future. - * - * IxAtmSch will guarantee a minimum of minCellsToSchedule if there - * is at least one cell ready to send. If there are no cells then - * IX_ATMSCH_RET_QUEUE_EMPTY is returned. - * - * This implementation of ixAtmSchTableUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an FIQ - * interrupt handler. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested - * schedule table is to be generated. - * - * @param maxCells unsigned [in] - Specifies the maximum number of cells - * that must be scheduled in the supplied table during any - * call to the interface. - * - * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of - * storage is returned which contains the generated - * schedule table. The client should not modify the - * contents of this table. - * - * @return - * - IX_SUCCESS : The schedule table has been published. - * Currently there is at least one VC queue that is nonempty. - * - IX_ATMSCH_RET_QUEUE_EMPTY : Currently all VC queues on - * this port are empty. The schedule table returned is set to - * NULL. The client is not expected to invoke this function - * again until more cells have been submitted on this port - * through the @ref ixAtmSchVcQueueUpdate function. - * - IX_FAIL : The input are invalid. No action is taken. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @warning Subsequent calls to this function for the same port will - * overwrite the contents of previously supplied schedule - * tables. The client must be completely finished with the - * previously supplied schedule table before calling this - * function again for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchShow(void) - * - * @brief Utility function which will print statistics on the current - * and accumulated state of VCs and traffic in the ATM - * scheduler component. Output is sent to the default output - * device. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchShow(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchStatsClear(void) - * - * @brief Utility function which will reset all counter statistics in - * the ATM scheduler to zero. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchStatsClear(void); - -#endif -/* IXATMSCH_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxAtmTypes.h b/drivers/net/npe/include/IxAtmTypes.h deleted file mode 100644 index 6c8d12f394..0000000000 --- a/drivers/net/npe/include/IxAtmTypes.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - * @file IxAtmTypes.h - * - * @date 24-MAR-2002 - * - * @brief This file contains Atm types common to a number of Atm components. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes) - * - * @brief The common set of types used in many Atm components - * - * @{ */ - -#ifndef IXATMTYPES_H -#define IXATMTYPES_H - -#include "IxNpeA.h" - -/** - * @enum IxAtmLogicalPort - * - * @brief Logical Port Definitions : - * - * Only 1 port is available in SPHY configuration - * 12 ports are enabled in MPHY configuration - * - */ -typedef enum -{ - IX_UTOPIA_PORT_0 = 0, /**< Port 0 */ -#ifdef IX_NPE_MPHYMULTIPORT - IX_UTOPIA_PORT_1, /**< Port 1 */ - IX_UTOPIA_PORT_2, /**< Port 2 */ - IX_UTOPIA_PORT_3, /**< Port 3 */ - IX_UTOPIA_PORT_4, /**< Port 4 */ - IX_UTOPIA_PORT_5, /**< Port 5 */ - IX_UTOPIA_PORT_6, /**< Port 6 */ - IX_UTOPIA_PORT_7, /**< Port 7 */ - IX_UTOPIA_PORT_8, /**< Port 8 */ - IX_UTOPIA_PORT_9, /**< Port 9 */ - IX_UTOPIA_PORT_10, /**< Port 10 */ - IX_UTOPIA_PORT_11, /**< Port 11 */ -#endif /* IX_NPE_MPHY */ - IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the - * maximum possible ports - */ -} IxAtmLogicalPort; - -/** - * @def IX_ATM_CELL_PAYLOAD_SIZE - * @brief Size of a ATM cell payload - */ -#define IX_ATM_CELL_PAYLOAD_SIZE (48) - -/** - * @def IX_ATM_CELL_SIZE - * @brief Size of a ATM cell, including header - */ -#define IX_ATM_CELL_SIZE (53) - -/** - * @def IX_ATM_CELL_SIZE_NO_HEC - * @brief Size of a ATM cell, excluding HEC byte - */ -#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1) - -/** - * @def IX_ATM_OAM_CELL_SIZE_NO_HEC - * @brief Size of a OAM cell, excluding HEC byte - */ -#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - -/** - * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE - * @brief Size of a AAL0 48 Cell payload - */ -#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE - * @brief Size of a AAL5 Cell payload - */ -#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC - * @brief Size of a AAL0 52 Cell, excluding HEC byte - */ -#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - - -/** - * @def IX_ATM_MAX_VPI - * @brief Maximum value of an ATM VPI - */ -#define IX_ATM_MAX_VPI 255 - -/** - * @def IX_ATM_MAX_VCI - * @brief Maximum value of an ATM VCI - */ -#define IX_ATM_MAX_VCI 65535 - - /** - * @def IX_ATM_MAX_NUM_AAL_VCS - * @brief Maximum number of active AAL5/AAL0 VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_VCS 32 - -/** - * @def IX_ATM_MAX_NUM_VC - * @brief Maximum number of active AAL5/AAL0 VCs in the system - * The use of this macro is depreciated, it is retained for - * backward compatiblity. For current software release - * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used. - */ -#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS - - - -/** - * @def IX_ATM_MAX_NUM_OAM_TX_VCS - * @brief Maximum number of active OAM Tx VCs in the system, - * 1 OAM VC per port - */ -#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS - -/** - * @def IX_ATM_MAX_NUM_OAM_RX_VCS - * @brief Maximum number of active OAM Rx VCs in the system, - * 1 OAM VC shared accross all ports - */ -#define IX_ATM_MAX_NUM_OAM_RX_VCS 1 - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS) - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS) - -/** - * @def IX_ATM_IDLE_CELLS_CONNID - * @brief VC Id used to indicate idle cells in the returned schedule table. - */ -#define IX_ATM_IDLE_CELLS_CONNID 0 - - -/** - * @def IX_ATM_CELL_HEADER_VCI_GET - * @brief get the VCI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \ - (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_VPI_GET - * @brief get the VPI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \ - (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_PTI_GET - * @brief get the PTI field from a cell header - */ -#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \ - ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK; - -/** - * @typedef IxAtmCellHeader - * - * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A - */ -typedef unsigned int IxAtmCellHeader; - - -/** - * @enum IxAtmServiceCategory - * - * @brief Enumerated type representing available ATM service categories. - * For more informatoin on these categories, see "Traffic Management - * Specification" v4.1, published by the ATM Forum - - * http://www.atmforum.com - */ -typedef enum -{ - IX_ATM_CBR, /**< Constant Bit Rate */ - IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */ - IX_ATM_VBR, /**< Variable Bit Rate */ - IX_ATM_UBR, /**< Unspecified Bit Rate */ - IX_ATM_ABR /**< Available Bit Rate (not supported) */ - -} IxAtmServiceCategory; - -/** - * - * @enum IxAtmRxQueueId - * - * @brief Rx Queue Type for RX traffic - * - * IxAtmRxQueueId defines the queues involved for receiving data. - * - * There are two queues to facilitate prioritisation handling - * and processing the 2 queues with different algorithms and - * constraints - * - * e.g. : one queue can carry voice (or time-critical traffic), the - * other queue can carry non-voice traffic - * - */ -typedef enum -{ - IX_ATM_RX_A = 0, /**< RX queue A */ - IX_ATM_RX_B, /**< RX queue B */ - IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */ -} IxAtmRxQueueId; - -/** - * @brief Structure describing an ATM traffic contract for a Virtual - * Connection (VC). - * - * Structure is used to specify the requested traffic contract for a - * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup - * interface. - * - * These parameters are defined by the ATM forum working group - * (http://www.atmforum.com). - * - * @note Typical values for a voice channel 64 Kbit/s - * - atmService @a IX_ATM_RTVBR - * - pcr 400 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - scr = pcr - * - * @note Typical values for a data channel 800 Kbit/s - * - atmService @a IX_ATM_UBR - * - pcr 1962 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - */ -typedef struct -{ - IxAtmServiceCategory atmService; /**< ATM service category */ - unsigned pcr; /**< Peak Cell Rate - cells per second */ - unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */ - unsigned scr; /**< Sustained Cell Rate - cells per second */ - unsigned mbs; /**< Max Burst Size - cells */ - unsigned mcr; /**< Minimum Cell Rate - cells per second */ - unsigned mfs; /**< Max Frame Size - cells */ -} IxAtmTrafficDescriptor; - -/** - * @typedef IxAtmConnId - * - * @brief ATM VC data connection identifier. - * - * This is is generated by IxAtmdAcc when a successful connection is - * made on a VC. The is the ID by which IxAtmdAcc knows an active - * VC and should be used in IxAtmdAcc API calls to reference a - * specific VC. - */ -typedef unsigned int IxAtmConnId; - -/** - * @typedef IxAtmSchedulerVcId - * - * @brief ATM VC scheduling connection identifier. - * - * This id is generated and used by ATM Tx controller, generally - * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component - * will request one of these Ids whenever a data connection on - * a Tx VC is requested. This ID will be used in callbacks to - * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a - * particular VC. - */ -typedef int IxAtmSchedulerVcId; - -/** - * @typedef IxAtmNpeRxVcId - * - * @brief ATM Rx VC identifier used by the ATM Npe. - * - * This Id is generated by IxAtmdAcc when a successful data connection - * is made on a rx VC. - */ -typedef unsigned int IxAtmNpeRxVcId; - -/** - * @brief ATM Schedule Table entry - * - * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform - * IxAtmdAcc about the data to transmit (in term of cells per VC) - * - * This structure defines - * @li the number of cells to be transmitted (numberOfCells) - * @li the VC connection to be used for transmission (connId). - * - * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the - * corresponding number of idle cells will be transmitted to the hardware. - * - */ -typedef struct -{ - IxAtmConnId connId; /**< connection Id - * - * Identifier of VC from which cells are to be transmitted. - * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates - * that the system should transmit the specified number - * of idle cells. Unknown connIds result in the transmission - * idle cells. - */ - unsigned int numberOfCells; /**< number of cells to transmit - * - * The number of contiguous cells to schedule from this VC - * at this point. The valid range is from 1 to - * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This - * number can swap over mbufs and pdus. OverSchduling results - * in the transmission of idle cells. - */ -} IxAtmScheduleTableEntry; - -/** - * @brief This structure defines a schedule table which gives details - * on which data (from which VCs) should be transmitted for a - * forthcoming period of time for a particular port and the - * order in which that data should be transmitted. - * - * The schedule table consists of a series of entries each of which - * will schedule one or more cells from a particular registered VC. - * The total number of cells scheduled and the total number of - * entries in the table are also indicated. - * - */ -typedef struct -{ - unsigned tableSize; /**< Number of entries - * - * Indicates the total number of - * entries in the table. - */ - unsigned totalCellSlots; /**< Number of cells - * - * Indicates the total number of ATM - * cells which are scheduled by all the - * entries in the table. - */ - IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries - * - * Pointer to an array - * containing tableSize entries - */ -} IxAtmScheduleTable; - -#endif /* IXATMTYPES_H */ - -/** - * @} defgroup IxAtmTypes - */ - - diff --git a/drivers/net/npe/include/IxAtmdAcc.h b/drivers/net/npe/include/IxAtmdAcc.h deleted file mode 100644 index b37c615029..0000000000 --- a/drivers/net/npe/include/IxAtmdAcc.h +++ /dev/null @@ -1,1169 +0,0 @@ -/** - * @file IxAtmdAcc.h - * - * @date 07-Nov-2001 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * data functions of the component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API - * - * @brief The public API for the IXP400 Atm Driver Data component - * - * IxAtmdAcc is the low level interface by which AAL0/AAL5 and - * OAM data gets transmitted to,and received from the Utopia bus. - * - * For AAL0/AAL5 services transmit and receive connections may - * be established independantly for unique combinations of - * port,VPI,and VCI. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * OAM cells cannot be received over the AAL0 service but instead - * are received over a dedicated OAM service. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values defined below. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. Note that AtmdAcc does not validate the cell headers - * in a submitted OAM PDU. - * - * - * - * This part is related to the User datapath processing - * - * @{ - */ - -#ifndef IXATMDACC_H -#define IXATMDACC_H - -#include "IxAtmTypes.h" - -/* ------------------------------------------------------ - AtmdAcc Data Types definition - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_WARNING - * - * @brief Warning return code - * - * This constant is used to tell IxAtmDAcc user about a special case. - * - */ -#define IX_ATMDACC_WARNING 2 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_BUSY - * - * @brief Busy return code - * - * This constant is used to tell IxAtmDAcc user that the request - * is correct, but cannot be processed because the IxAtmAcc resources - * are already used. The user has to retry its request later - * - */ -#define IX_ATMDACC_BUSY 3 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED - * - * @brief Disconnect return code - * - * This constant is used to tell IxAtmDAcc user that the disconnect - * functions are not complete because the resources used by the driver - * are not yet released. The user has to retry the disconnect call - * later. - * - */ -#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT - * - * @brief Default resources usage for RxVcFree replenish mechanism - * - * This constant is used to tell IxAtmDAcc to allocate and use - * the minimum of resources for rx free replenish. - * - * @sa ixAtmdAccRxVcConnect - */ -#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0 - - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VPI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - * - * - */ -#define IX_ATMDACC_OAM_TX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VCI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_TX_VCI 0 - - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_PORT - * - * @brief The reserved dummy PORT used for all dedicated OAM - * Rx connections. Note that this is not a real port but must - * have a value that lies within the valid range of port values. - */ -#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0 - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VPI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - */ -#define IX_ATMDACC_OAM_RX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VCI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_RX_VCI 0 - - -/** - * @enum IxAtmdAccPduStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc Pdu status : - * - * IxAtmdAccPduStatus is used during a RX operation to indicate - * the status of the received PDU - * - */ - -typedef enum -{ - IX_ATMDACC_AAL0_VALID = 0, /**< aal0 pdu */ - IX_ATMDACC_OAM_VALID, /**< OAM pdu */ - IX_ATMDACC_AAL2_VALID, /**< aal2 pdu @b reserved for future use */ - IX_ATMDACC_AAL5_VALID, /**< aal5 pdu complete and trailer is valid */ - IX_ATMDACC_AAL5_PARTIAL, /**< aal5 pdu not complete, trailer is missing */ - IX_ATMDACC_AAL5_CRC_ERROR, /**< aal5 pdu not complete, crc error/length error */ - IX_ATMDACC_MBUF_RETURN /**< empty buffer returned to the user */ -} IxAtmdAccPduStatus; - - -/** - * - * @enum IxAtmdAccAalType - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc AAL Service Type : - * - * IxAtmdAccAalType defines the type of traffic to run on this VC - * - */ -typedef enum -{ - IX_ATMDACC_AAL5, /**< ITU-T AAL5 */ - IX_ATMDACC_AAL2, /**< ITU-T AAL2 @b reserved for future use */ - IX_ATMDACC_AAL0_48, /**< AAL0 48 byte payloads (cell header is added by NPE)*/ - IX_ATMDACC_AAL0_52, /**< AAL0 52 byte cell data (HEC is added by NPE) */ - IX_ATMDACC_OAM, /**< OAM cell transport service (HEC is added by NPE)*/ - IX_ATMDACC_MAX_SERVICE_TYPE /**< not a service, used for parameter validation */ -} IxAtmdAccAalType; - -/** - * - * @enum IxAtmdAccClpStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc CLP indication - * - * IxAtmdAccClpStatus defines the CLP status of the current PDU - * - */ -typedef enum -{ - IX_ATMDACC_CLP_NOT_SET = 0, /**< CLP indication is not set */ - IX_ATMDACC_CLP_SET = 1 /**< CLP indication is set */ -} IxAtmdAccClpStatus; - -/** - * @typedef IxAtmdAccUserId - * - * @ingroup IxAtmdAccAPI - * - * @brief User-supplied Id - * - * IxAtmdAccUserId is passed through callbacks and allows the - * IxAtmdAcc user to identify the source of a call back. The range of - * this user-owned Id is [0...2^32-1)]. - * - * The user provides this own Ids on a per-channel basis as a parameter - * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect() - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccTxVcConnect - * - */ -typedef unsigned int IxAtmdAccUserId; - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Rx callback prototype - * - * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user - * function called once per PDU to pass a receive Pdu to a user on a - * partilcular connection. The callback is likely to push the mbufs - * to a protocol layer, and recycle the mbufs for a further use. - * - * @note -This function is called ONLY in the context of - * the @a ixAtmdAccRxDispatch() function - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * - * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received - * a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity. - * In the case of AAL0 the only possibile value is - * AAL0_VALID, in this case the client may optionally determine - * that an rx timeout occured by checking if the mbuf is - * compleletly or only partially filled, the later case - * indicating a timeout. - * In the case of OAM the only possible value is OAM valid. - * The status is set to @a IX_ATMDACC_MBUF_RETURN when - * the mbuf is released during a disconnect process. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. - * For AAL5/AAL0_48 this information - * is set if the clp bit of any rx cell is set - * For AAL0-52/OAM the client may inspect the CLP in individual - * cell headers in the PDU, and this parameter is set to 0. - * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to - * an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only), - * that comprises the complete PDU data. - * - * This parameter is guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port, - IxAtmdAccUserId userId, - IxAtmdAccPduStatus status, - IxAtmdAccClpStatus clp, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Callback prototype for free buffer level is low. - * - * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function - * which get called on a per-VC basis, when more mbufs are needed to - * continue the ATM data reception. This function is likely to supply - * more available mbufs by one or many calls to the replenish function - * @a ixAtmdAccRxVcFreeReplenish() - * - * This function is called when the number of available buffers for - * reception is going under the threshold level as defined - * in @a ixAtmdAccRxVcFreeLowCallbackRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * - * @return None - * - */ -typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Buffer callback prototype. - * - * This function is called to relinguish ownership of a transmitted - * buffer chain to the user. - * - * @note -In the case of a chained mbuf the AmtdAcc component can - * chain many user buffers together and pass ownership to the user in - * one function call. - * - * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this - * callback. - * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is - * guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId, - IX_OSAL_MBUF * mbufPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Initialisation - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccInit (void) - * - * @brief Initialise the IxAtmdAcc Component - * - * This function initialise the IxAtmdAcc component. This function shall - * be called before any other function of the API. Its role is to - * initialise all internal resources of the IxAtmdAcc component. - * - * The ixQmgr component needs to be initialized prior the use of - * @a ixAtmdAccInit() - * - * @param none - * - * Failing to initilialize the IxAtmdAcc API before any use of it will - * result in a failed status. - * If the specified component is not present, a success status will still be - * returned, however, a warning indicating the NPE to download to is not - * present will be issued. - * - * @return @li IX_SUCCESS initialisation is complete (in case of component not - * being present, a warning is clearly indicated) - * @return @li IX_FAIL unable to process this request either - * because this IxAtmdAcc is already initialised - * or some unspecified error has occrred. - */ -PUBLIC IX_STATUS ixAtmdAccInit (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccShow (void) - * - * @brief Show IxAtmdAcc configuration on a per port basis - * - * @param none - * - * @return none - * - * @note - Display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsShow (void) - * - * @brief Show all IxAtmdAcc stats - * - * @param none - * - * @return none - * - * @note - Stats display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccStatsShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsReset (void) - * - * @brief Reset all IxAtmdAcc stats - * - * @param none - * - * @return none - * - */ -PUBLIC void -ixAtmdAccStatsReset (void); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ) - * - * @brief Connect to a Aal Pdu receive service for a particular - * port/vpi/vci, and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VCC. - * - * The function will setup VC receive service on the specified rx queue. - * - * This function is blocking and makes use internal locks, and hence - * should not be called from an interrupt context. - * - * On return from @a ixAtmdAccRxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * Calling this function for the same combination of Vpi, Vci and more - * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a - * failure status. - * - * If this function returns success the user should supply receive - * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call - * @a ixAtmdAccRxVcEnable() to begin receiving pdus. - * - * There is a choice of two receive Qs on which the VC pdus could be - * receive. The user must associate the VC with one of these. Essentially - * having two qs allows more flexible system configuration such as have - * high prioriy traffic on one q (e.g. voice) and low priority traffic on - * the other (e.g. data). The high priority Q could be serviced in - * preference to the low priority Q. One queue may be configured to be - * serviced as soon as there is traffic, the other queue may be configured - * to be serviced by a polling mechanism running at idle time. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Received AAL0 PDUs will be be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service and includes an ATM cell header - * (excluding HEC) at the start of each cell. - * - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function prior to enable the port will fail. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcTryDisconnect - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM - * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC - * should use.when icoming traffic is processed - * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to - * the supplied rxCallback. - * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received. - * This parameter cannot be a null pointer. - * @param bufferFreeCallback [in] - function to be called to return - * ownership of buffers to IxAtmdAcc user. - * @param minimumReplenishCount unsigned int [in] - For AAL5/AAL0 the number of free mbufs - * to be used with this channel. Use a high number when the expected traffic - * rate on this channel is high, or when the user's mbufs are small, or when - * the RxVcFreeLow Notification has to be invoked less often. When this - * value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of - * resources will be used. Depending on traffic rate, pdu - * size and mbuf size, rxfree queue size, polling/interrupt rate, this value may - * require to be replaced by a different value in the range 1-128 - * For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored. - * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id - * This parameter cannot be a null pointer. - * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect - * @return @li IX_ATMDACC_BUSY cannot process this request : - * no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr) - * - * @brief Provide free mbufs for data reception on a connection. - * - * This function provides mbufs for data reception by the hardware. This - * function needs to be called by the user on a regular basis to ensure - * no packet loss. Providing free buffers is a connection-based feature; - * each connection can have different requirements in terms of buffer size - * number of buffers, recycling rate. This function could be invoked from - * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback - * for a particular VC - * - * Mbufs provided through this function call can be chained. They will be - * unchained internally. A call to this function with chained mbufs or - * multiple calls with unchained mbufs are equivalent, but calls with - * unchained mbufs are more efficients. - * - * Mbufs provided to this interface need to be able to hold at least one - * full cell payload (48/52 bytes, depending on service type). - * Chained buffers with a size less than the size supported by the hardware - * will be returned through the rx callback provided during the connect step. - * - * Failing to invoke this function prior to enabling the RX traffic - * can result in packet loss. - * - * This function is not reentrant for the same connId. - * - * This function does not use system resources and can be - * invoked from an interrupt context. - * - * @note - Over replenish is detected, and extra mbufs are returned through - * the rx callback provided during the connect step. - * - * @note - Mbuf provided to the replenish function should have a length greater or - * equal to 48/52 bytes according to service type. - * - * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf - * submission. Flushing the Mbuf headers is handled by IxAtmdAcc. - * - * @note - When a chained mbuf is provided, this function process the mbufs - * up to the hardware limit and invokes the user-supplied callback - * to release extra buffers. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data - * reception. The mbuf pointed to by this parameter can be chained - * to an other mbuf. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish() - * and the mbuf is now ready to use for incoming traffic. - * @return @li IX_ATMDACC_BUSY cannot process this request because - * the max number of outstanding free buffers has been reached - * or the internal resources have exhausted for this VC. - * The user is responsible for retrying this request later. - * @return @li IX_FAIL cannot process this request because of parameter - * errors or some unspecified internal error has occurred. - * - * @note - It is not always guaranteed the replenish step to be as fast as the - * hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to - * guarantee that replenish reaches the rxFree threshold level. If the - * threshold level is not reached, the next rxFree low notification for - * this channel will not be triggered. - * The preferred ways to replenish can be as follows (depending on - * applications and implementations) : - * @li Replenish in a rxFree low notification until the function - * ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY - * @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then - * , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue - * level again, and replenish if the threshold is still not reached. - * @li Trigger replenish from an other event source and use rxFree starvation - * to throttle the Rx traffic. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback) - * - * @brief Configure the RX Free threshold value and register a callback - * to handle threshold notifications. - * - * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for - * a particular RX VC. When the number of buffers reaches this threshold - * the callback is invoked. - * - * This function should be called once per VC before RX traffic is - * enabled.This function will fail if the curent level of the free buffers - * is equal or less than the threshold value. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number - * has to be a power of 2, one of the values 0,1,2,4,8,16,32.... - * The maximum value cannot be more than half of the rxFree queue - * size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery() - * before any use of the @a ixAtmdAccRxVcFreeReplenish() function) - * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of - * free buffers has reduced to the threshold value. - * - * @return @li IX_SUCCESS Threshold set successfully. - * @return @li IX_FAIL parameter error or the current number of free buffers - * is less than or equal to the threshold supplied or some - * unspecified error has occrred. - * - * @note - the callback will be called when the threshold level will drop from - * exactly (numberOfMbufs + 1) to (numberOfMbufs). - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr) - * - * @brief Get the number of rx mbufs the system can accept to replenish the - * the rx reception mechanism on a particular channel - * - * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current - * number of available mbuf entries for reception, on a per-VC basis. This - * function can be used to know the number of mbufs which can be provided - * using @a ixAtmdAccRxVcFreeReplenish(). - * - * This function can be used from a timer context, or can be associated - * with a threshold event, or can be used inside an active polling - * mechanism which is under user control. - * - * This function is reentrant and does not use system resources and can - * be invoked from an interrupt context. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries. - * . This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic - * @return @li IX_FAIL invalid parameter - * - * @sa ixAtmdAccRxVcFreeReplenish - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId) - * - * @brief Start the RX service on a VC. - * - * This functions kicks-off the traffic reception for a particular VC. - * Once invoked, incoming PDUs will be made available by the hardware - * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback - * registered for the connection. - * - * If the traffic is already running, this function returns IX_SUCCESS. - * This function can be invoked many times. - * - * IxAtmdAccRxVcFreeLowCallback event will occur only after - * @a ixAtmdAccRxVcEnable() function is invoked. - * - * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function - * has to be used to replenish the RX Free queue. If not, incoming traffic - * may be discarded.and in the case of interrupt driven reception the - * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect - * during a replenish action. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * For an VC connection this function can be called after a call to - * @a ixAtmdAccRxVcDisable() and should not be called after - * @a ixAtmdAccRxVcTryDisconnect() - * - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcFreeReplenish - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable - * @return @li IX_ATMDACC_WARNING the channel is already enabled - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId) - * - * @brief Stop the RX service on a VC. - * - * This functions stops the traffic reception for a particular VC connection. - * - * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus - * pending will be freed to the user - * - * Hence once this function returns no more receive callbacks will be - * called for that VC. However, buffer free callbacks will be invoked - * until such time as all buffers supplied by the user have been freed - * back to the user - * - * Calling this function doe not invalidate the connId. - * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again. - * - * If the traffic is already stopped, this function returns IX_SUCCESS. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a - * IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable(). - * @return @li IX_ATMDACC_WARNING the channel is already disabled - * @return @li IX_FAIL invalid parameters or some unspecified internal error occured - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect a VC from the RX service. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay and - * call again this function many times until a success status is returned. - * - * This function needs internal locks and should not be called from an - * interrupt context - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. - * @return @li IX_FAIL cannot process this request because of a parameter - * error - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr) - * - * @brief Connect to a Aal Pdu transmit service for a particular - * port/vpi/vci and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VC. - * - * The function will setup VC transmit service on the specified on the - * specified port. A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * This function needs internal locks, and hence should not be called - * from an interrupt context. - * - * On return from @a ixAtmdAccTxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * - * Calling this function for the same combination of port, Vpi, Vci and - * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result - * in a failure status. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function before enabling the port will fail. - * - * @sa ixAtmdAccTxVcTryDisconnect - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM - * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related - * to this channel - * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs - * transmission is complete. This parameter cannot be a null - * pointer. - * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect(). - * @return @li IX_ATMDACC_BUSY cannot process this request - * because no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the - * function @a ixAtmdAccPortTxScheduledModeEnable() need to be called - * for this port before any establishing a Tx Connection - */ -PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells) - * - * @brief Submit a Pdu for transmission on connection. - * - * A data user calls this function to submit an mbufs containing a Pdu - * to be transmitted. The buffer supplied can be chained and the Pdu it - * contains must be complete. - * - * The transmission behavior of this call depends on the operational mode - * of the port on which the connection is made. - * - * In unscheduled mode the mbuf will be submitted to the hardware - * immediately if sufficent resource is available. Otherwise the function - * will return failure. - * - * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell - * demand is made known to the traffic shaping entity. Cells from the - * buffers are MUXed onto the port some time later as dictated by the - * traffic shaping entity. The traffic shaping entity does this by sending - * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call. - * - * Note that the dedicated OAM channel is scheduled just like any - * other channel. This means that any OAM traffic relating to an - * active AAL0/AAL5 connection will be scheduled independantly of the - * AAL0/AAL5 traffic for that connection. - * - * When transmission is complete, the TX Done mechanism will give the - * owmnership of these buffers back to the customer. The tx done mechanism - * must be in operation before transmission is attempted. - * - * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data - * size (48/52). AAL0_52 and OAM are raw cell services, and the client - * must format the PDU with an ATM cell header (excluding HEC) at the - * start of each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneDispatch - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit. - * This parameter cannot be a null pointer. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu - * will be sent with the clp bit set - * @param numberOfCells unsigned int [in] - number of cells in the PDU. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit() - * The pdu pointed by the mbufPtr parameter will be - * transmitted - * @return @li IX_ATMDACC_BUSY unable to process this request because - * internal resources are all used. The caller is responsible - * for retrying this request later. - * @return @li IX_FAIL unable to process this request because of error - * in the parameters (wrong connId supplied, - * or wrong mbuf pointer supplied), the total length of all buffers - * in the chain should be a multiple of the cell size - * ( 48/52 depending on the service type ), - * or unspecified error during processing - * - * @note - This function in not re-entrant for the same VC (e.g. : two - * thread cannot send PDUs for the same VC). But two threads can - * safely call this function with a different connection Id - * - * @note - In unscheduled mode, this function is not re-entrant on a per - * port basis. The size of pdus is limited to 8Kb. - * - * @note - 0-length mbufs should be removed from the chain before submission. - * The total length of the pdu (sdu + padding +trailer) has to be - * updated in the header of the first mbuf of a chain of mbufs. - * - * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied - * before submission. - * - * @note - The payload memory cache should be flushed, if needed, prior to - * transmission. Mbuf headers are flushed by IxAtmdAcc - * - * @note - This function does not use system resources and can be used - * inside an interrupt context - */ -PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect from a Aal Pdu transmit service for a particular - * port/vpi/vci. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay - * and call again this function many times until a success status is - * returned. - * - * After its execution, the connection Id is not available. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect() - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. This condition will - * disappear after Tx and TxDone is complete for this channel. - * @return @li IX_FAIL unable to process this request because of errors - * in the parameters (wrong connId supplied) - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not - * clear after a while, this may be linked to a previous problem - * of cell overscheduling. Diabling the port and retry a disconnect - * will free the resources associated with this channel. - * - * @sa ixAtmdAccPortTxProcess - * - */ -PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId); - -#endif /* IXATMDACC_H */ - -/** - * @} defgroup IxAtmdAccAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h deleted file mode 100644 index ecbb0059f5..0000000000 --- a/drivers/net/npe/include/IxAtmdAccCtrl.h +++ /dev/null @@ -1,1933 +0,0 @@ -/** - * @file IxAtmdAccCtrl.h - * - * @date 20-Mar-2002 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * control functions of the component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get transmitted - * to,and received from the Utopia bus - * - * This part is related to the Control configuration - * - * @{ - */ - -#ifndef IXATMDACCCTRL_H -#define IXATMDACCCTRL_H - -#include "IxAtmdAcc.h" - -/* ------------------------------------------------------ - AtmdAccCtrl Data Types definition - ------------------------------------------------------ */ - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS -* -* @brief Port enable return code -* -* This constant is used to tell IxAtmDAcc user that the port disable -* functions are not complete. The user can call ixAtmdAccPortDisableComplete() -* to find out when the disable has finished. The port enable can then proceed. -* -*/ -#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5 - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_ALLPDUS -* -* @brief All PDUs -* -* This constant is used to tell IxAtmDAcc to process all PDUs from -* the RX queue or the TX Done -* -* @sa IxAtmdAccRxDispatcher -* @sa IxAtmdAccTxDoneDispatcher -* -*/ -#define IX_ATMDACC_ALLPDUS 0xffffffff - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for notification of available PDUs for - * an Rx Q. - * - * This a protoype for a function which is called when there is at - * least one Pdu available for processing on a particular Rx Q. - * - * This function should call @a ixAtmdAccRxDispatch() with - * the aprropriate number of parameters to read and process the Rx Q. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxDispatcherRegister - * - * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process. - * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of - * PDUs available to process all PDUs from the queue. - * @param reservedPtr unsigned int* [out] pointer to a int location which can - * be written to, but does not retain written values. This is - * provided to make this prototype compatible - * with @a ixAtmdAccRxDispatch() - * - * @return @li int - ignored. - * - */ -typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for transmitted mbuf when threshold level is - * crossed. - * - * IxAtmdAccTxDoneDispatcher is the prototype of the user function - * which get called when pdus are completely transmitted. This function - * is likely to call the @a ixAtmdAccTxDoneDispatch() function. - * - * This function is called when the number of available pdus for - * reception is crossing the threshold level as defined - * in @a ixAtmdAccTxDoneDispatcherRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set before any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers with @a ixAtmdAccTxDoneDispatch() - * and @a ixAtmdAccTxDoneLevelQuery() functions. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently - * available for recycling - * @param *reservedPtr unsigned int [out] - pointer to a int location which can be - * written to but does not retain written values. This is provided - * to make this prototype compatible - * with @a ixAtmdAccTxDoneDispatch() - * - * @return @li IX_SUCCESS This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * - */ -typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Notification that the threshold number of scheduled cells -* remains in a port's transmit Q. -* -* The is the prototype for of the user notification function which -* gets called on a per-port basis, when the number of remaining -* scheduled cells to be transmitted decreases to the threshold level. -* The number of cells passed as a parameter can be used for scheduling -* purposes as the maximum number of cells that can be passed in a -* schedule table to the @a ixAtmdAccPortTxProcess() function. -* -* @sa ixAtmdAccPortTxCallbackRegister -* @sa ixAtmdAccPortTxProcess -* @sa ixAtmdAccPortTxFreeEntriesQuery -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* @param numberOfAvailableCells unsigned int [in] - number of available -* cell entries.for the port -* -* @note - This functions shall not use system resources when used -* inside an interrupt context. -* -*/ -typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port, - unsigned int numberOfAvailableCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Prototype to submit cells for transmission -* -* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback -* function used by AtmD to notify an ATM Scheduler that the user of -* a VC has submitted cells for transmission. -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated -* is established -* @param vcId int [in] - Identifies the VC to be updated. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added -* to the queue for this VC. -* -* @return @li IX_SUCCESS the function is registering the cell demand for -* this VC. -* @return @li IX_FAIL the function cannot register cell for this VC : the -* scheduler maybe overloaded or misconfigured -* -*/ -typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port, - int vcId, - unsigned int numberOfCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to remove all currently queued cells from a -* registered VC -* -* IxAtmdAccTxVcDemandClearCallback is the prototype of the function -* to remove all currently queued cells from a registered VC. The -* pending cell count for the specified VC is reset to zero. After the -* use of this callback, the scheduler shall not schedule more cells -* for this VC. -* -* This callback function is called during a VC disconnection -* @a ixAtmdAccTxVcTryDisconnect() -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* @sa ixAtmdAccTxVcTryDisconnect -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared -* is established -* @param vcId int [in] - Identifies the VC to be cleared. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* -* @return none -* -*/ -typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port, - int vcId); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to get a scheduler vc id -* -* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get -* a scheduler vcId -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is -* established -* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VPI. -* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VCI. -* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already -* associated with this VC -* @param vcId int* [out] - pointer to a vcId -* -* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this -* VC -* @return @li IX_FAIL the function cannot process scheduling for this VC. -* the contents of vcId is unspecified -* -*/ -typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmConnId connId, - int *vcId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback) - * - * @brief Register a notification callback to be invoked when there is - * at least one entry on a particular Rx queue. - * - * This function registers a callback to be invoked when there is at - * least one entry in a particular queue. The registered callback is - * called every time when the hardware adds one or more pdus to the - * specified Rx queue. - * - * This function cannot be used when a Rx Vc using this queue is - * already existing. - * - * @note -The callback function can be the API function - * @a ixAtmdAccRxDispatch() : every time the threhold level - * of the queue is reached, the ixAtmdAccRxDispatch() is - * invoked to remove all entries from the queue. - * - * @sa ixAtmdAccRxDispatch - * @sa IxAtmdAccRxDispatcher - * - * @param queueId @ref IxAtmRxQueueId [in] RX queue identification - * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming - * traffic. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister() - * @return @li IX_FAIL error in the parameters, or there is an - * already active RX VC for this queue or some unspecified - * internal error occurred. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * - * @brief Control function which executes Rx processing for a particular - * Rx stream. - * - * The @a IxAtmdAccRxDispatch() function is used to process received Pdus - * available from one of the two incoming RX streams. When this function - * is invoked, the incoming traffic (up to the number of PDUs passed as - * a parameter) will be transferred to the IxAtmdAcc users through the - * callback @a IxAtmdAccRxVcRxCallback(), as registered during the - * @a ixAtmdAccRxVcConnect() call. - * - * The user receive callbacks will be executed in the context of this - * function. - * - * Failing to use this function on a regular basis when there is traffic - * will block incoming traffic and can result in Pdus being dropped by - * the hardware. - * - * This should be used to control when received pdus are handed off from - * the hardware to Aal users from a particluar stream. The function can - * be used from a timer context, or can be registered as a callback in - * response to an rx stream threshold event, or can be used inside an - * active polling mechanism which is under user control. - * - * @note - The signature of this function is directly compatible with the - * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister(). - * - * @sa ixAtmdAccRxDispatcherRegister - * @sa IxAtmdAccRxVcRxCallback - * @sa ixAtmdAccRxVcFreeEntriesQuery - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process. - * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to - * remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates - * to process all PDUs from the queue. This includes at least the PDUs - * in the queue when the fuction is invoked. Because of real-time - * constraints, there is no guarantee thatthe queue will be empty - * when the function exits. If this parameter is greater than the - * number of entries of the queues, the function will succeed - * and the parameter numberOfPdusProcessedPtr will reflect the exact - * number of PDUs processed. - * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU - * processed during this call. This parameter cannot be a null - * pointer. - * - * @return @li IX_SUCCESS the number of PDUs as indicated in - * numberOfPdusProcessedPtr are removed from the RX queue and the VC callback - * are called. - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the number of entries in a particular RX queue. - * - * This function is used to retrieve the number of pdus received by - * the hardware and ready for distribution to users. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available - * PDUs in the RX queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of incoming pdus waiting in this queue - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the size of a particular RX queue. - * - * This function is used to retrieve the number of pdus the system is - * able to queue when reception is complete. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus - * the system is able to queue in the RX queue. This parameter - * cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of pdus the system is able to queue. - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr) - * - * @brief Get the number of available cells the system can accept for - * transmission. - * - * The function is used to retrieve the number of cells that can be - * queued for transmission to the hardware. - * - * This number is based on the worst schedule table where one cell - * is stored in one schedule table entry, depending on the pdus size - * and mbuf size and fragmentation. - * - * This function doesn't use system resources and can be used from a - * timer context, or can be associated with a threshold event, or can - * be used inside an active polling mechanism - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCellsPtr unsigned int* [out] - number of available cells. - * This parameter cannot be a null pointer. - * - * @sa ixAtmdAccPortTxProcess - * - * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled - * for this port. - * @return @li IX_FAIL error in the parameters, or some processing error - * occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback) - * - * @brief Configure the Tx port threshold value and register a callback to handle - * threshold notifications. - * - * This function sets the threshold in cells - * - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortTxProcess - * @sa ixAtmdAccPortTxFreeEntriesQuery - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCells unsigned int [in] - threshold value which triggers the callback - * invocation, This number has to be one of the - * values 0,1,2,4,8,16,32 .... - * The maximum value cannot be more than half of the txVc queue - * size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery() - * before any Tx traffic is sent for this port) - * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold - * level is reached. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister() - * @return @li IX_FAIL error in the parameters, Tx channel already set for this port - * threshold level is not correct or within the range regarding the - * queue size:or unspecified error during processing: - * - * @note - This callback function get called when the threshold level drops from - * (numberOfCells+1) cells to (numberOfCells) cells - * - * @note - This function should be called during system initialisation, - * outside an interrupt context - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback) - * - * @brief Put the port into Scheduled Mode - * - * This function puts the specified port into scheduled mode of - * transmission which means an external s/w entity controls the - * transmission of cells on this port. This faciltates traffic shaping on - * the port. - * - * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc. - * The transmission of these buffers to and by the hardware will be driven - * by a transmit schedule submitted regulary in calls to - * @a ixAtmdAccPortTxProcess() by traffic shaping entity. - * - * The transmit schedule is expected to be dynamic in nature based on - * the demand in cells for each VC on the port. Hence the callback - * parameters provided to this function allow IxAtmdAcc to inform the - * shaping entity of demand changes for each VC on the port. - * - * By default a port is in Unscheduled Mode so if this function is not - * called, transmission of data is done without sheduling rules, on a - * first-come, first-out basis. - * - * Once a port is put in scheduled mode it cannot be reverted to - * un-scheduled mode. Note that unscheduled mode is not supported - * in ixp425 1.0 - * - * @note - This function should be called before any VCs have be - * connected on a port. Otherwise this function call will return failure. - * - * @note - This function uses internal locks and should not be called from - * an interrupt context - * - * @sa IxAtmdAccTxVcDemandUpdateCallback - * @sa IxAtmdAccTxVcDemandClearCallback - * @sa IxAtmdAccTxSchVcIdGetCallback - * @sa ixAtmdAccPortTxProcess - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update - * the number of outstanding cells for transmission. This parameter - * cannot be a null pointer. - * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all - * clear the number of outstanding cells for a VC. This parameter - * cannot be a null pointer. - * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc - * Identifiers between IxAtmdAcc and the entity supplying the - * transmit schedule. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS scheduler registration is complete and the port - * is now in scheduled mode. - * @return @li IX_FAIL failed (wrong parameters, or traffic is already - * enabled on this port, possibly without ATM shaping) - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr) - * - * @brief Transmit queue cells to the H/W based on the supplied schedule - * table. - * - * This function @a ixAtmdAccPortTxProcess() process the schedule - * table provided as a parameter to the function. As a result cells are - * sent to the underlaying hardware for transmission. - * - * The schedule table is executed in its entirety or not at all. So the - * onus is on the caller not to submit a table containing more cells than - * can be transmitted at that point. The maximum numbers that can be - * transmitted is guaranteed to be the number of cells as returned by the - * function @a ixAtmdAccPortTxFreeEntriesQuery(). - * - * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the - * minimum number of cells (to ensure the callback will fire again later) - * and the maximum number of cells that @a ixAtmdAccPortTxProcess() - * will be able to process (assuming the ATM scheduler is able - * to produce the worst-case schedule table, i.e. one entry per cell). - * - * When invoked ouside a threshold level, the overall number of cells of - * the schedule table should be less than the number of cells returned - * by the @a ixAtmdAccPortTxFreeEntriesQuery() function. - * - * After invoking the @a ixAtmdAccPortTxProcess() function, it is the - * user choice to query again the queue level with the function - * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell - * number, submit an other schedule table. - * - * IxAtmdAcc will check that the number of cells in the schedule table - * is compatible with the current transmit level. If the - * - * Obsolete or invalid connection Id will be silently discarded. - * - * This function is not reentrant for the same port. - * - * This functions doesn't use system resources and can be used inside an - * interrupt context. - * - * This function is used as a response to the hardware requesting more - * cells to transmit. - * - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortTxFreeEntriesQuery - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The - * content of this table is not modified by this function. This - * parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the schedule table process is complete - * and cells are transmitted to the hardware - * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed - * the hardware capacity If this error is ignored, further traffic - * and schedule will work correctly. - * Overscheduling does not occur when the schedule table does - * not contain more entries that the number of free entries returned - * by @a ixAtmdAccPortTxFreeEntriesQuery(). - * However, Disconnect attempts just after this error will fail permanently - * with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is - * necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect() - * successful. - * @return @li IX_FAIL a wrong parameter is supplied, or the format of - * the schedule table is invalid, or the port is not Enabled, or - * an internal severe error occured. No cells is transmitted to the hardware - * - * @note - If the failure is linked to an overschedule of data cells - * the result is an inconsistency in the output traffic (one or many - * cells may be missing and the traffic contract is not respected). - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * @brief Process a number of pending transmit done pdus from the hardware. - * - * As a by-product of Atm transmit operation buffers which transmission - * is complete need to be recycled to users. This function is invoked - * to service the oustanding list of transmitted buffers and pass them - * to VC users. - * - * Users are handed back pdus by invoking the free callback registered - * during the @a ixAtmdAccTxVcConnect() call. - * - * There is a single Tx done stream servicing all active Atm Tx ports - * which can contain a maximum of 64 entries. If this stream fills port - * transmission will stop so this function must be call sufficently - * frequently to ensure no disruption to the transmit operation. - * - * This function can be used from a timer context, or can be associated - * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ), - * or can be used inside an active polling mechanism under user control. - * - * For ease of use the signature of this function is compatible with the - * TxDone threshold event callback prototype. - * - * This functions can be used inside an interrupt context. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove - * from the TX Done queue - * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from - * the TX Done queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the number of pdus as indicated in - * numberOfPdusToProcess are removed from the TX Done hardware - * and passed to the user through the Tx Done callback registered - * during a call to @a ixAtmdAccTxVcConnect() - * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is - * a null pointer or some unspecified internal error occured. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the current number of transmit pdus ready for - * recycling. - * - * This function is used to get the number of transmitted pdus which - * the hardware is ready to hand back to user. - * - * This function can be used from a timer context, or can be associated - * with a threshold event, on can be used inside an active polling - * mechanism - * - * @sa ixAtmdAccTxDoneDispatch - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted - * at the time of this function call, and ready for recycling - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus - * ready for recycling at the time of this function call - * - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the TxDone queue size. - * - * This function is used to get the number of pdus which - * the hardware is able to store after transmission is complete - * - * The returned value can be used to set a threshold and enable - * a callback to be notified when the number of pdus is going over - * the threshold. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system - * is able to queue after transmission - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of - * pdus the system is able to queue after transmission - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback) - * - * @brief Configure the Tx Done stream threshold value and register a - * callback to handle threshold notifications. - * - * This function sets the threshold level in term of number of pdus at - * which the supplied notification function should be called. - * - * The higher the threshold value is, the less events will be necessary - * to process transmitted buffers. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set prior any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and - * @a ixAtmdAccTxDoneLevelQuery() functions. - * - * This function should be called during system initialisation outside - * an interrupt context - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the - * callback invocation This number has to be a power of 2, one of the - * values 0,1,2,4,8,16,32 ... - * The maximum value cannot be more than half of the txDone queue - * size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery()) - * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This - * parameter can be @a ixAtmdAccTxDoneDispatch()).This - * parameter ust not be a null pointer. - * - * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister - * @return @li IX_FAIL error in the parameters: - * - * @note - The notificationCallback will be called exactly when the threshold level - * will increase from (numberOfPdus) to (numberOfPdus+1) - * - * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will - * be released to the user (when txDone level is permanently under the threshold - * level. One of the preffered way to return resources to the user is to use - * a mix of txDone notifications, used together with a slow - * rate timer and an exclusion mechanism protecting from re-entrancy - * - * @note - The TxDone threshold will only hand back buffers when the threshold level is - * crossed. Setting this threshold to a great number reduce the interrupt rate - * and the cpu load, but also increase the number of outstanding mbufs and has - * a system wide impact when these mbufs are needed by other components. - * - */ -PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Utopia config - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get - * transmitted to,and received from the Utopia bus - * - * This part is related to the UTOPIA configuration. - * - * @{ - */ - -/** - * - * @brief Utopia configuration - * - * This structure is used to set the Utopia parameters - * @li contains the values of Utopia registers, to be set during initialisation - * @li contains debug commands for NPE, to be used during development steps - * - * @note - the exact description of all parameters is done in the Utopia reference - * documents. - * - */ -typedef struct -{ - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxConfig_ - * @brief Utopia Tx Config Register - */ - struct UtTxConfig_ - { - - unsigned int reserved_1:1; /**< [31] These bits are always 0.*/ - unsigned int txInterface:1; /**< [30] Utopia Transmit Interface. The following encoding - * is used to set the Utopia Transmit interface as ATM master - * or PHY slave: - * @li 1 - PHY - * @li 0 - ATM - */ - unsigned int txMode:1; /**< [29] Utopia Transmit Mode. The following encoding is used - * to set the Utopia Transmit mode to SPHY or MPHY: - * @li 1 - SPHY - * @li 0 - MPHY - */ - unsigned int txOctet:1; /**< [28] Utopia Transmit cell transfer protocol. Used to set - * the Utopia cell transfer protocol to Octet-level handshaking. - * Note this is only applicable in SPHY mode. - * @li 1 - Octet-handshaking enabled - * @li 0 - Cell-handshaking enabled - */ - unsigned int txParity:1; /**< [27] Utopia Transmit parity enabled when set. TxEvenParity - * defines the parity format odd/even. - * @li 1 - Enable Parity generation. - * @li 0 - ut_op_prty held low. - */ - unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode - * @li 1 - Even Parity Generated. - * @li 0 - Odd Parity Generated. - */ - unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit - * cell header check byte is calculated and inserted when set. - * @li 1 - Generate HEC. - * @li 0 - Disable HEC generation. - */ - unsigned int txCOSET:1; /**< [24] If enabled the HEC is Exclusive-OR'ed with the value 0x55 before - * being presented on the Utopia bus. - * @li 1 - Enable HEC ExOR with value 0x55 - * @li 0 - Use generated HEC value. - */ - - unsigned int reserved_2:1; /**< [23] These bits are always 0 - */ - unsigned int txCellSize:7; /**< [22:16] Transmit expected cell size. Configures the cell size - * for the transmit module: Values between 52-64 are valid. - */ - unsigned int reserved_3:3; /**< [15:13] These bits are always 0 */ - unsigned int txAddrRange:5; /**< [12:8] When configured as an ATM master in MPHY mode this - * register specifies the upper limit of the PHY polling logical - * range. The number of active PHYs are TxAddrRange + 1. - */ - unsigned int reserved_4:3; /**< [7:5] These bits are always 0 */ - unsigned int txPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } - - utTxConfig; /**< Tx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxStatsConfig_ - * @brief Utopia Tx stats Register - */ - struct UtTxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] or PHY Address[4] */ - - unsigned int pti:3; /**< [3:1] ATM PTI [2:0] or PHY Address[3:1] - @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - - unsigned int clp:1; /**< [0] ATM CLP or PHY Address [0] - @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - } - - utTxStatsConfig; /**< Tx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxDefineIdle_ - * @brief Utopia Tx idle cells Register - */ - struct UtTxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/ - } - - utTxDefineIdle; /**< Tx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxEnableFields_ - * @brief Utopia Tx ienable fields Register - */ - struct UtTxEnableFields_ - { - - unsigned int defineTxIdleGFC:1; /**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineTxIdlePTI:1; /**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int defineTxIdleCLP:1; /**< [29] This register is used to include or - exclude the CLP field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int phyStatsTxEnb:1; /**< [28] This register is used to enable or disable ATM - statistics gathering based on the specified PHY address as defined - in TxStatsConfig register. - @li 1 - Enable statistics for specified transmit PHY address. - @li 0 - Disable statistics for specified transmit PHY address. */ - - unsigned int vcStatsTxEnb:1; /**< [27] This register is used to change the ATM - statistics-gathering mode from the specified logical PHY address - to a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address */ - - unsigned int vcStatsTxGFC:1; /**< [26] This register is used to include or exclude the GFC - field of the ATM header when ATM VPI/VCI statistics are enabled. - GFC is only available at the UNI and uses the first 4-bits of - the VPI field. - @li 1 - GFC field is valid - @li 0 - GFC field ignored.*/ - - unsigned int vcStatsTxPTI:1; /**< [25] This register is used to include or exclude the PTI - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsTxCLP:1; /**< [24] This register is used to include or exclude the CLP - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid - @li 0 - CLP field ignored. */ - - unsigned int reserved_1:3; /**< [23-21] These bits are always 0 */ - - unsigned int txPollStsInt:1; /**< [20] Enable the assertion of the ucp_tx_poll_sts condition - where there is a change in polling status. - @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status - @li 0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available - */ - unsigned int txCellOvrInt:1; /**< [19] Enable TxCellCount overflow CBI Transmit Status condition - assertion. - @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition. - @li 0 - No CBI Transmit Status condition assertion */ - - unsigned int txIdleCellOvrInt:1; /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition - @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition - @li 0 - No CBI Transmit Status condition assertion..*/ - - unsigned int enbIdleCellCnt:1; /**< [17] Enable Transmit Idle Cell Count. - @li 1 - Enable count of Idle cells transmitted. - @li 0 - No count is maintained. */ - - unsigned int enbTxCellCnt:1; /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells - @li 1 - Enable count of valid cells transmitted- non-idle/non-error - @li 0 - No count is maintained.*/ - - unsigned int reserved_2:16; /**< [15:0] These bits are always 0 */ - } utTxEnableFields; /**< Tx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable0_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Tx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Tx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Tx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0.*/ - - unsigned int phy3:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable0; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable1_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable1; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable2_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable2; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable3_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable3; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable4_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable4; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable5_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utTxTransTable5; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxConfig_ - * @brief Utopia Rx config Register - */ - struct UtRxConfig_ - { - - unsigned int rxInterface:1; /**< [31] Utopia Receive Interface. The following encoding is used - to set the Utopia Receive interface as ATM master or PHY slave: - @li 1 - PHY - @li 0 - ATM */ - - unsigned int rxMode:1; /**< [30] Utopia Receive Mode. The following encoding is used to set - the Utopia Receive mode to SPHY or MPHY: - @li 1 - SPHY - @li 0 - MPHY */ - - unsigned int rxOctet:1; /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia - cell transfer protocol to Octet-level handshaking. Note this is only - applicable in SPHY mode. - @li 1 - Octet-handshaking enabled - @li 0 - Cell-handshaking enabled */ - - unsigned int rxParity:1; /**< [28] Utopia Receive Parity Checking enable. - @li 1 - Parity checking enabled - @li 0 - Parity checking disabled */ - - unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode - @li 1 - Check for Even Parity - @li 0 - Check for Odd Parity.*/ - - unsigned int rxHEC:1; /**< [26] RxHEC Header Error Check Mode. Enables/disables cell header - error checking on the received cell header. - @li 1 - HEC checking enabled - @li 0 - HEC checking disabled */ - - unsigned int rxCOSET:1; /**< [25] If enabled the HEC is Exclusive-OR'ed with the value 0x55 - before being tested with the received HEC. - @li 1 - Enable HEC ExOR with value 0x55. - @li 0 - Use generated HEC value.*/ - - unsigned int rxHECpass:1; /**< [24] Specifies if the incoming cell HEC byte should be transferred - after optional processing to the NPE2 Coprocessor Bus Interface or - if it should be discarded. - @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2. - @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/ - - unsigned int reserved_1:1; /**< [23] These bits are always 0 */ - - unsigned int rxCellSize:7; /**< [22:16] Receive cell size. Configures the receive cell size. - Values between 52-64 are valid */ - - unsigned int rxHashEnbGFC:1; /**< [15] Specifies if the VPI field [11:8]/GFC field should be - included in the Hash data input or if the bits should be padded - with 1'b0. - @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation. - @li 0 - VPI [11:8]/GFC field padded with 1'b0 */ - - unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the - incoming cell data should be pre-hashed to allow VPI/VCI header look-up - in a hash table. - @li 1 - Pre-hashing enabled - @li 0 - Pre-hashing disabled */ - - unsigned int reserved_2:1; /**< [13] These bits are always 0 */ - - unsigned int rxAddrRange:5; /**< [12:8] In ATM master, MPHY mode, - * this register specifies the upper - * limit of the PHY polling logical range. The number of active PHYs are - * RxAddrRange + 1. - */ - unsigned int reserved_3:3; /**< [7-5] These bits are always 0 .*/ - unsigned int rxPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } utRxConfig; /**< Rx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxStatsConfig_ - * @brief Utopia Rx stats config Register - */ - struct UtRxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] VCI [15:0] or PHY Address [4] */ - - unsigned int pti:3; /**< [3:1] PTI [2:0] or or PHY Address [3:1] - @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - - unsigned int clp:1; /**< [0] CLP [0] or PHY Address [0] - @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - } utRxStatsConfig; /**< Rx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxDefineIdle_ - * @brief Utopia Rx idle cells config Register - */ - struct UtRxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/ - } utRxDefineIdle; /**< Rx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxEnableFields_ - * @brief Utopia Rx enable Register - */ - struct UtRxEnableFields_ - { - - unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP - field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored.*/ - - unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics - gathering based on the specified PHY address as defined in RxStatsConfig - register. - @li 1 - Enable statistics for specified receive PHY address. - @li 0 - Disable statistics for specified receive PHY address.*/ - - unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics - gathering based on a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address.*/ - - unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field - of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only - available at the UNI and uses the first 4-bits of the VPI field. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored. */ - - unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC. - @li 1 - Discard cells with HEC errors - @li 0 - Cells with HEC errors are passed */ - - unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors. - @li 1 - Discard cells with parity errors - @li 0 - Cells with parity errors are passed */ - - unsigned int discardIdle:1; /**< [21] Discard Idle Cells based on DefineIdle register values - @li 1 - Discard IDLE cells - @li 0 - IDLE cells passed */ - - unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count. - @li 1 - Enable count of received cells containing HEC errors - @li 0 - No count is maintained. */ - - unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count - @li 1 - Enable count of received cells containing Parity errors - @li 0 - No count is maintained. */ - - unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count. - @li 1 - Enable count of Idle cells received. - @li 0 - No count is maintained.*/ - - unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count. - @li 1 - Enable count of received cells of incorrect size - @li 0 - No count is maintained. */ - - unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells. - @li 1 - Enable count of valid cells received - non-idle/non-error - @li 0 - No count is maintained. */ - - unsigned int reserved_1:3; /**< [15:13] These bits are always 0 */ - - unsigned int rxCellOvrInt:1; /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount - register overflows. - @li 1 - CBI Receive Status asserted. - @li 0 - No CBI Receive Status asserted.*/ - - unsigned int invalidHecOvrInt:1; /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount - register overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidParOvrInt:1; /**< [10] Enable CBI Receive Status Condition if the InvalidParCount - register overflows - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidSizeOvrInt:1; /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount - register overflows. - @li 1 - CBI Receive Status Condition asserted. - @li 0 - No CBI Receive Status asserted */ - - unsigned int rxIdleOvrInt:1; /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int reserved_2:3; /**< [7:5] These bits are always 0 */ - - unsigned int rxAddrMask:5; /**< [4:0] This register is used as a mask to allow the user to increase - the PHY receive address range. The register should be programmed with - the address-range limit, i.e. if set to 0x3 the address range increases - to a maximum of 4 addresses. */ - } utRxEnableFields; /**< Rx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable0_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Rx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Rx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Rx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0 */ - - unsigned int phy3:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable0; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable1_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable1; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable2_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable2; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable3_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable3; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable4_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable4; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable5_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utRxTransTable5; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtSysConfig_ - * @brief NPE setup Register - */ - struct UtSysConfig_ - { - - unsigned int reserved_1:2; /**< [31-30] These bits are always 0 */ - unsigned int txEnbFSM:1; /**< [29] Enables the operation ofthe Utopia Transmit FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int rxEnbFSM:1; /**< [28] Enables the operation ofthe Utopia Revieve FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int disablePins:1; /**< [27] Disable Utopia interface I/O pins forcing the signals to an - * inactive state. Note that this bit is set on reset and must be - * de-asserted - * @li 0 - Normal data transfer - * @li 1 - Utopia interface pins are forced inactive - */ - unsigned int tstLoop:1; /**< [26] Test Loop Back Enable. - * @li Note: For loop back to function RxMode and Tx Mode must both be set - * to single PHY mode. - * @li 0 - Loop back - * @li 1 - Normal operating mode - */ - - unsigned int txReset:1; /**< [25] Resets the Utopia Coprocessor transmit module to a known state. - * @li Note: All transmit configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset transmit modules - */ - - unsigned int rxReset:1; /**< [24] Resets the Utopia Coprocessor receive module to a known state. - * @li Note: All receive configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset receive modules - */ - - unsigned int reserved_2:24; /**< [23-0] These bits are always 0 */ - } utSysConfig; /**< NPE debug config */ - -} -IxAtmdAccUtopiaConfig; - -/** -* -* @brief Utopia status -* -* This structure is used to set/get the Utopia status parameters -* @li contains debug cell counters, to be accessed during a read operation -* -* @note - the exact description of all parameters is done in the Utopia reference -* documents. -* -*/ -typedef struct -{ - - unsigned int utTxCellCount; /**< count of cells transmitted */ - - unsigned int utTxIdleCellCount; /**< count of idle cells transmitted */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxCellConditionStatus_ - * @brief Utopia Tx Status Register - */ - struct UtTxCellConditionStatus_ - { - - unsigned int reserved_1:2; /**< [31:30] These bits are always 0 */ - unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO underflow - * error condition. - */ - unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if - * 64-byte Transmit FIFO1 indicates a FIFO - * underflow error condition. - */ - unsigned int txFIFO2Overflow:1; /**< [27] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO overflow - * error condition. - */ - unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte - * Transmit FIFO1 indicates a FIFO overflow - * error condition. - */ - unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the - * TxIdleCellCount register overflows. - */ - unsigned int txCellCountOvr:1; /**< [24] This bit is set if the - * TxCellCount register overflows - */ - unsigned int reserved_2:24; /**< [23:0] These bits are always 0 */ - } utTxCellConditionStatus; /**< Tx cells condition status */ - - unsigned int utRxCellCount; /**< count of cell received */ - unsigned int utRxIdleCellCount; /**< count of idle cell received */ - unsigned int utRxInvalidHECount; /**< count of invalid cell - * received because of HEC errors - */ - unsigned int utRxInvalidParCount; /**< count of invalid cell received - * because of parity errors - */ - unsigned int utRxInvalidSizeCount; /**< count of invalid cell - * received because of cell - * size errors - */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxCellConditionStatus_ - * @brief Utopia Rx Status Register - */ - struct UtRxCellConditionStatus_ - { - - unsigned int reserved_1:3; /**< [31:29] These bits are always 0.*/ - unsigned int rxCellCountOvr:1; /**< [28] This bit is set if the RxCellCount register overflows. */ - unsigned int invalidHecCountOvr:1; /**< [27] This bit is set if the InvalidHecCount register overflows.*/ - unsigned int invalidParCountOvr:1; /**< [26] This bit is set if the InvalidParCount register overflows.*/ - unsigned int invalidSizeCountOvr:1; /**< [25] This bit is set if the InvalidSizeCount register overflows.*/ - unsigned int rxIdleCountOvr:1; /**< [24] This bit is set if the RxIdleCount register overflows.*/ - unsigned int reserved_2:4; /**< [23:20] These bits are always 0 */ - unsigned int rxFIFO2Underflow:1; /**< [19] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO underflow error condition. - */ - unsigned int rxFIFO1Underflow:1; /**< [18] This bit is set if 64-byte Receive - * FIFO1 indicates a FIFO underflow error condition - . */ - unsigned int rxFIFO2Overflow:1; /**< [17] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO overflow error condition. - */ - unsigned int rxFIFO1Overflow:1; /**< [16] This bit is set if 64-byte Receive FIFO1 - * indicates a FIFO overflow error condition. - */ - unsigned int reserved_3:16; /**< [15:0] These bits are always 0. */ - } utRxCellConditionStatus; /**< Rx cells condition status */ - -} IxAtmdAccUtopiaStatus; - -/** - * @} defgroup IxAtmdAccUtopiaCtrlAPI - */ - - /** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr) - * - * @brief Send the configuration structure to the Utopia interface - * - * This function downloads the @a IxAtmdAccUtopiaConfig structure to - * the Utopia and has the following effects - * @li setup the Utopia interface - * @li initialise the NPE - * @li reset the Utopia cell counters and status registers to known values - * - * This action has to be done once at initialisation. A lock is preventing - * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and - * @A ixAtmdAccUtopiaConfigSet() - * - * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to - * Utopia. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful download - * @return @li IX_FAIL error in the parameters, or configuration is not - * complete or failed - * - * @sa ixAtmdAccUtopiaStatusGet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus) - * - * @brief Get the Utopia interface configuration. - * - * This function reads the Utopia registers and the Cell counts - * and fills the @a IxAtmdAccUtopiaStatus structure - * - * A lock is preventing the concurrent - * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet() - * - * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal - * hardware counters. This parameter cannot be a NULL pointer. - * - * @return @li IX_SUCCESS successful read - * @return @li IX_FAIL error in the parameters null pointer, or - * configuration read is not complete or failed - * - * @sa ixAtmdAccUtopiaConfigSet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus); - -/** - * - * @ingroup IxAtmdAcc - * - * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port) - * - * @brief enable a PHY logical port - * - * This function enables the transmission over one port. It should be - * called before accessing any resource from this port and before the - * establishment of a VC. - * - * When a port is enabled, the cell transmission to the Utopia interface - * is started. If there is no traffic already running, idle cells are - * sent over the interface. - * - * This function can be called multiple times. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS enable is complete - * @return @li IX_ATMDACC_WARNING port already enabled - * @return @li IX_FAIL enable failed, wrong parameter, or cannot - * initialise this port (the port is maybe already in use, - * or there is a hardware issue) - * - * @note - This function needs internal locks and should not be - * called from an interrupt context - * - * @sa ixAtmdAccPortDisable - * - */ -PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port) - * - * @brief disable a PHY logical port - * - * This function disable the transmission over one port. - * - * When a port is disabled, the cell transmission to the Utopia interface - * is stopped. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS disable is complete - * @return @li IX_ATMDACC_WARNING port already disabled - * @return @li IX_FAIL disable failed, wrong parameter . - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - The response from hardware is done through the txDone mechanism - * to ensure the synchrnisation with tx resources. Therefore, the - * txDone mechanism needs to be serviced to make a PortDisable complete. - * - * @sa ixAtmdAccPortEnable - * @sa ixAtmdAccPortDisableComplete - * @sa ixAtmdAccTxDoneDispatch - * - */ -PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port) -* -* @brief disable a PHY logical port -* -* This function indicates if the port disable for a port has completed. This -* function will return true if the port has never been enabled. -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* -* @return @li true disable is complete -* @return @li false disable failed, wrong parameter . -* -* @note - This function needs internal locks and should not be called -* from an interrupt context -* -* @sa ixAtmdAccPortEnable -* @sa ixAtmdAccPortDisable -* -*/ -PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port); - -#endif /* IXATMDACCCTRL_H */ - -/** - * @} defgroup IxAtmdAccCtrlAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmm.h b/drivers/net/npe/include/IxAtmm.h deleted file mode 100644 index 805b8c9bd6..0000000000 --- a/drivers/net/npe/include/IxAtmm.h +++ /dev/null @@ -1,771 +0,0 @@ -/** - * @file IxAtmm.h - * - * @date 3-DEC-2001 - * - * @brief Header file for the IXP400 ATM Manager component (IxAtmm) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -/** - * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API - * - * @brief IXP400 ATM Manager component Public API - * - * @{ - */ - -#ifndef IXATMM_H -#define IXATMM_H - -/* - * Put the user defined include files required - */ -#include "IxAtmSch.h" -#include "IxOsalTypes.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_ATMM_RET_ALREADY_INITIALIZED - * - * @brief Component has already been initialized - */ -#define IX_ATMM_RET_ALREADY_INITIALIZED 2 - -/** - * @def IX_ATMM_RET_INVALID_PORT - * - * @brief Specified port does not exist or is out of range */ -#define IX_ATMM_RET_INVALID_PORT 3 - -/** - * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR - * - * @brief The VC description does not adhere to ATM standards */ -#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4 - -/** - * @def IX_ATMM_RET_VC_CONFLICT - * - * @brief The VPI/VCI values supplied are either reserved, or they - * conflict with a previously registered VC on this port */ -#define IX_ATMM_RET_VC_CONFLICT 5 - -/** - * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL - * - * @brief The virtual connection cannot be established on the port - * because the remaining port capacity is not sufficient to - * support it */ -#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6 - -/** - * @def IX_ATMM_RET_NO_SUCH_VC - * - * @brief No registered VC, as described by the supplied VCI/VPI or - * VC identifier values, exists on this port */ -#define IX_ATMM_RET_NO_SUCH_VC 7 - -/** - * @def IX_ATMM_RET_INVALID_VC_ID - * - * @brief The specified VC identifier is out of range. */ -#define IX_ATMM_RET_INVALID_VC_ID 8 - -/** - * @def IX_ATMM_RET_INVALID_PARAM_PTR - * - * @brief A pointer parameter was NULL. */ -#define IX_ATMM_RET_INVALID_PARAM_PTR 9 - -/** - * @def IX_ATMM_UTOPIA_SPHY_ADDR - * - * @brief The phy address when in SPHY mode */ -#define IX_ATMM_UTOPIA_SPHY_ADDR 31 - -/** - * @def IX_ATMM_THREAD_PRI_HIGH - * - * @brief The value of high priority thread */ -#define IX_ATMM_THREAD_PRI_HIGH 90 - -/* - * Typedefs whose scope is limited to this file. - */ - -/** @brief Definition for use in the @ref IxAtmmVc structure. - * Indicates the direction of a VC */ -typedef enum -{ - IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/ - IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/ - IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/ -} IxAtmmVcDirection; - -/** @brief Definition for use with @ref IxAtmmVcChangeCallback - * callback. Indicates that the event type represented by the - * callback for this VC. */ -typedef enum -{ - IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/ - IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/ - IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/ -} IxAtmmVcChangeEvent; - -/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to - * indicate that UTOPIA loopback should be enabled or disabled - * on initialisation. */ -typedef enum -{ - IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/ - IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/ - IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/ -} IxAtmmUtopiaLoopbackMode; - -/** @brief This structure describes the required attributes of a - * virtual connection. -*/ -typedef struct { - unsigned vpi; /**< VPI value of this virtual connection */ - unsigned vci; /**< VCI value of this virtual connection. */ - IxAtmmVcDirection direction; /**< VC direction */ - - /** Traffic descriptor of this virtual connection. This structure - * is defined by the @ref IxAtmSch component. */ - IxAtmTrafficDescriptor trafficDesc; -} IxAtmmVc; - - -/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to - * indicate that UTOPIA multi-phy/single-phy mode is used. - */ -typedef enum -{ - IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/ - IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/ - IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/ -} IxAtmmPhyMode; - - -/** @brief Structure contains port-specific information required to - * initialize IxAtmm, and specifically, the IXP400 UTOPIA - * Level-2 device. */ -typedef struct { - unsigned reserved_1:11; /**< [31:21] Should be zero */ - unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the - * transmit (Tx) PHY for this - * port on the 5-bit UTOPIA - * Level-2 address bus */ - unsigned reserved_2:11; /**< [15:5] Should be zero */ - unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive - * (Rx) PHY for this port on the - * 5-bit UTOPIA Level-2 - * address bus */ -} IxAtmmPortCfg; - -/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface - * Defines a callback type which will be used to notify registered - * users of registration/deregistration events on a particular port - * - * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating - * whether the VC supplied has been added or - * removed - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has - * occurred - * - * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives - * details of the VC which has been added - * or removed on the port - */ -typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType, - IxAtmLogicalPort port, - const IxAtmmVc* vcChanged); - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * Extern function prototypes - */ - -/* - * Function declarations - */ - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmInit (void) - * - * @brief Interface to initialize the IxAtmm software component. Can - * be called once only. - * - * Must be called before any other IxAtmm API is called. - * - * @param "none" - * - * @return @li IX_SUCCESS : IxAtmm has been successfully initialized. - * Calls to other IxAtmm interfaces may now be performed. - * @return @li IX_FAIL : IxAtmm has already been initialized. - */ -PUBLIC IX_STATUS -ixAtmmInit (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode) - * - * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor - * for the specified number of physical ports. The function - * must be called before the ixAtmmPortInitialize interface - * can operate successfully. - * - * @param numPorts unsigned [in] - Indicates the total number of logical - * ports that are active on the device. Up to 12 ports are - * supported. - * - * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY - * or MPHY mode. - * - * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements - * detailing the UTOPIA specific port characteristics. The - * length of the array must be equal to the number of ports - * activated. ATM ports are referred to by the relevant - * offset in this array in all subsequent IxAtmm interface - * calls. - * - * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of - * @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref - * IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether - * loopback should be enabled on the device. Loopback can - * only be supported on a single PHY, therefore the numPorts - * parameter must be 1 if loopback is enabled. - * - * @return @li IX_SUCCESS : Indicates that the UTOPIA device has been - * successfully initialized for the supplied ports. - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has - * already been initialized. - * @return @li IX_FAIL : The supplied parameters are invalid or have been - * rejected by the UTOPIA-NPE device. - * - * @warning - * This interface may only be called once. - * Port identifiers are assumed to range from 0 to (numPorts - 1) in all - * instances. - * In all subsequent calls to interfaces supplied by IxAtmm, the specified - * port value is expected to represent the offset in the portCfgs array - * specified in this interface. i.e. The first port in this array will - * subsequently be represented as port 0, the second port as port 1, - * and so on.*/ -PUBLIC IX_STATUS -ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief The interface is called following @ref ixAtmmUtopiaInit () - * and before calls to any other IxAtmm interface. It serves - * to activate the registered ATM port with IxAtmm. - * - * The transmit and receive port rates are specified in bits per - * second. This translates to ATM cells per second according to the - * following formula: CellsPerSecond = portRate / (53*8) The - * IXP400 device supports only 53 byte cells. The client shall make - * sure that the off-chip physical layer device has already been - * initialized. - * - * IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling - * on the port. - * - * This interface must be called once for each active port in the - * system. The first time the interface is invoked, it will configure - * the mechanism by which the handling of transmit, transmit-done and - * receive are driven with the IxAtmdAcc component. - * - * This function is reentrant. - * - * @note The minimum tx rate that will be accepted is 424 bit/s which equates - * to 1 cell (53 bytes) per second. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in bits/second. - * - * @return @li IX_SUCCESS : The specificed ATM port has been successfully - * initialized. IxAtmm is ready to accept VC registrations on - * this port. - * - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has - * already been called successfully on this port. The current - * call is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not initialize the port because the - * inputs are not understood. - * - * @sa ixAtmmPortEnable, ixAtmmPortDisable - * - */ -PUBLIC IX_STATUS -ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief A client may call this interface to change the existing - * port rate (expressed in bits/second) on an established ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the`` - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in - * bits/second. - * - * @return @li IX_SUCCESS : The indicated ATM port rates have been - * successfully modified. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - - * - * @brief The client may call this interface to request details on - * currently registered transmit and receive rates for an ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the - * rate details are requested. - * - * @param *txPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the transmit port - * rate specified in bits/second. - * - * @param *rxPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the receive port - * rate specified in bits/second. - * - * @return @li IX_SUCCESS : The information requested on the specified - * port has been successfully supplied in the output. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortEnable(IxAtmLogicalPort port) - * - * @brief The client call this interface to enable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is started. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already enabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortDisable */ -PUBLIC IX_STATUS -ixAtmmPortEnable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortDisable(IxAtmLogicalPort port) - * - * @brief The client call this interface to disable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is stopped. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already disabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function call does not stop RX traffic. It is supposed - * that this function is invoked when a serious problem - * is detected (e.g. physical layer broken). Then, the RX traffic - * is not passing. - * - * @note - This function is blocking until the hw acknowledge that the - * transmission is stopped. - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortEnable */ -PUBLIC IX_STATUS -ixAtmmPortDisable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId) - * - * @brief This interface is used to register an ATM Virtual - * Connection on the specified ATM port. - * - * Each call to this interface registers a unidirectional virtual - * connection with the parameters specified. If a bi-directional VC - * is needed, the function should be called twice (once for each - * direction, Tx & Rx) where the VPI and VCI and port parameters in - * each call are identical. - * - * With the addition of each new VC to a port, a series of - * callback functions are invoked by the IxAtmm component to notify - * possible external components of the change. The callback functions - * are registered using the @ref ixAtmmVcChangeCallbackRegister interface. - * - * The IxAtmSch component is notified of the registration of transmit - * VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is - * to be registered. - * - * @param *vcToAdd @ref IxAtmmVc [in] - Pointer to an @ref IxAtmmVc structure - * containing a description of the VC to be registered. The - * client shall fill the vpi, vci and direction and relevant - * trafficDesc members of this structure before calling this - * function. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled - * with the per-port unique identifier value for this VC. - * This identifier will be required when a request is - * made to deregister or change this VC. VC identifiers - * for transmit VCs will have a value between 0-43, - * i.e. 32 data Tx VCs + 12 OAM Tx Port VCs. - * Receive VCs will have a value between 44-66, - * i.e. 32 data Rx VCs + 1 OAM Rx VC. - * - * @return @li IX_SUCCESS : The VC has been successfully registered on - * this port. The VC is ready for a client to configure IxAtmdAcc - * for receive and transmit operations on the VC. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor - * pointed to by vcToAdd is invalid. The registration request - * is rejected. - * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with - * reserved VPI and/or VCI values or with another VC already activated - * on this port. - * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be - * registered in the port becuase the port capacity is - * insufficient to support the requested ATM traffic contract. - * The registration request is rejected. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @warning IxAtmm has no capability of signaling or negotiating a virtual - * connection. Negotiation of the admission of the VC to the network - * is beyond the scope of this function. This is assumed to be - * performed by the calling client, if appropriate, - * before or after this function is called. - */ -PUBLIC IX_STATUS -ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId) - * - * @brief Function called by a client to deregister a VC from the - * system. - * - * With the removal of each new VC from a port, a series of - * registered callback functions are invoked by the IxAtmm component - * to notify possible external components of the change. The callback - * functions are registered using the @ref ixAtmmVcChangeCallbackRegister. - * - * The IxAtmSch component is notified of the removal of transmit VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * removed is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to - * be deregistered. This value was supplied to the client when - the VC was originally registered. This value can also be - queried from the IxAtmm component through the @ref ixAtmmVcQuery - * interface. - * - * @return @li IX_SUCCESS : The specified VC has been successfully - * removed from this port. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_FAIL : There is no registered VC associated with the - * supplied identifier registered on this port. */ -PUBLIC IX_STATUS -ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with the VPI, VCI and - * direction of that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vpi unsigned [in] - ATM VPI value of the requested VC. - * - * @param vci unsigned [in] - ATM VCI value of the requested VC. - * - * @param direction @ref IxAtmmVcDirection [in] - One of @ref - * IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX - * indicating the direction (Tx or Rx) of the requested VC. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be - * filled with the VC identifier value for the requested - * VC (as returned by @ref ixAtmmVcRegister), if it - * exists on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the search criteria (VPI, VCI, direction) - * given. No data is returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - */ -PUBLIC IX_STATUS -ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with a vcId for that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which - * uniquely identifies the requested VC on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the supplied identifier. No data is - * returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - */ -PUBLIC IX_STATUS -ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to supply a function to IxAtmm - * which will be called to notify the client if a new VC is - * registered with IxAtmm or an existing VC is removed. - * - * The callback, when invoked, will run within the context of the call - * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused - * the change of state. - * - * A maximum of 32 calbacks may be registered in with IxAtmm. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will be invoked by IxAtmm with the appropiate - * parameters for the relevant VC when any VC has been - * registered or deregistered with IxAtmm. - * - * @return @li IX_SUCCESS : The specified callback has been registered - * successfully with IxAtmm and will be invoked when appropriate. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * IxAtmm has already registered 32 and connot accommodate - * any further registrations of this type. The request is - * rejected. - * - * @warning The client must not call either the @ref - * ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces - * from within the supplied callback function. */ -PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to deregister a previously supplied - * callback function. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will removed from the table of callbacks. - * - * @return @li IX_SUCCESS : The specified callback has been deregistered - * successfully from IxAtmm. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * is not currently registered with IxAtmm. - */ -PUBLIC IX_STATUS -ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaStatusShow (void) - * - * @brief Display utopia status counters - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaStatusShow (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaCfgShow (void) - * - * @brief Display utopia information(config registers and status registers) - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaCfgShow (void); - -#endif -/* IXATMM_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxDmaAcc.h b/drivers/net/npe/include/IxDmaAcc.h deleted file mode 100644 index a62e72cc1b..0000000000 --- a/drivers/net/npe/include/IxDmaAcc.h +++ /dev/null @@ -1,236 +0,0 @@ -/** - * @file IxDmaAcc.h - * - * @date 15 October 2002 - * - * @brief API of the IXP400 DMA Access Driver Component (IxDma) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/*--------------------------------------------------------------------- - Doxygen group definitions - ---------------------------------------------------------------------*/ - -#ifndef IXDMAACC_H -#define IXDMAACC_H - -#include "IxOsal.h" -#include "IxNpeDl.h" -/** - * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes) - * @brief The common set of types used in the DMA component - * @{ - */ - -/** - * @ingroup IxDmaTypes - * @enum IxDmaReturnStatus - * @brief Dma return status definitions - */ -typedef enum -{ - IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */ - IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */ - IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */ - IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */ - IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */ - IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */ - IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */ -} IxDmaReturnStatus; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferMode - * @brief Dma transfer mode definitions - * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length. - */ -typedef enum -{ - IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/ - IX_DMA_COPY, /**< copy */ - IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */ - IX_DMA_COPY_REVERSE, /**< copy and reverse */ - IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */ -} IxDmaTransferMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaAddressingMode - * @brief Dma addressing mode definitions - * @note Fixed source address to fixed destination address addressing mode is not supported. - */ -typedef enum -{ - IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */ - IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */ -} IxDmaAddressingMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferWidth - * @brief Dma transfer width definitions - * @Note Fixed addresses (either source or destination) do not support burst transfer width. - */ -typedef enum -{ - IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */ - IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */ - IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */ - IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */ - IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */ - IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */ - IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */ - IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */ - IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */ - IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/ - IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address -*/ - IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */ -} IxDmaTransferWidth; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaNpeId - * @brief NpeId numbers to identify NPE A, B or C - */ -typedef enum -{ - IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */ - IX_DMA_NPEID_NPEB, /**< Identifies NPE B */ - IX_DMA_NPEID_NPEC, /**< Identifies NPE C */ - IX_DMA_NPEID_MAX /**< Total Number of NPEs */ -} IxDmaNpeId; -/* @} */ -/** - * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API - * - * @brief The public API for the IXP400 IxDmaAcc component - * - * @{ - */ - -/** - * @ingroup IxDmaAcc - * @brief DMA Request Id type - */ -typedef UINT32 IxDmaAccRequestId; - -/** - * @ingroup IxDmaAcc - * @def IX_DMA_REQUEST_FULL - * @brief DMA request queue is full - * This constant is a return value used to tell the user that the IxDmaAcc - * queue is full. - * - */ -#define IX_DMA_REQUEST_FULL 16 - -/** - * @ingroup IxDmaAcc - * @brief DMA completion notification - * This function is called to notify a client that the DMA has been completed - * @param status @ref IxDmaReturnStatus [out] - reporting to client - * - */ -typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccInit(IxNpeDlNpeId npeId) - * - * @brief Initialise the DMA Access component - * This function will initialise the DMA Access component internals - * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer - * @return @li IX_SUCCESS succesfully initialised the component - * @return @li IX_FAIL Initialisation failed for some unspecified - * internal reason. - */ -PUBLIC IX_STATUS -ixDmaAccInit(IxNpeDlNpeId npeId); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth) - * - * @brief Perform DMA transfer - * This function will perform DMA transfer between devices within the - * IXP400 memory map. - * @note The following are restrictions for IxDmaAccDmaTransfer: - * @li The function is non re-entrant. - * @li The function assumes host devices are operating in big-endian mode. - * @li Fixed address does not suport burst transfer width - * @li Fixed source address to fixed destinatiom address mode is not suported - * @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode - * - * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL. - * @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address. - * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address. - * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte - * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode - * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode - * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width - * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured - * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid - * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range - * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid - * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full - */ -PUBLIC IxDmaReturnStatus -ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth); -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccShow(void) - * - * @brief Display some component information for debug purposes - * Show some internal operation information relating to the DMA service. - * At a minimum the following will show. - * - the number of the DMA pend (in queue) - * @param None - * @return @li None - */ -PUBLIC IX_STATUS -ixDmaAccShow(void); - -#endif /* IXDMAACC_H */ - diff --git a/drivers/net/npe/include/IxEthAcc.h b/drivers/net/npe/include/IxEthAcc.h deleted file mode 100644 index cc7e010667..0000000000 --- a/drivers/net/npe/include/IxEthAcc.h +++ /dev/null @@ -1,2488 +0,0 @@ -/** @file IxEthAcc.h - * - * @brief this file contains the public API of @ref IxEthAcc component - * - * Design notes: - * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must - * be cache aligned (bits[4-0] cleared) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthAcc_H -#define IxEthAcc_H - -#include -#include - -/** - * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API - * - * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs. - * - *@{ - */ - -/** - * @ingroup IxEthAcc - * @brief Definition of the Ethernet Access status - */ -typedef enum /* IxEthAccStatus */ -{ - IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/ - IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/ - IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/ - IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/ - IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/ - IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/ - IX_ETH_TX_Q_FULL, /**< return tx queue is full*/ - IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/ -} IxEthAccStatus; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccPortId - * @brief Definition of the IXP400 Mac Ethernet device. - */ -typedef enum -{ - IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */ - IX_ETH_PORT_2 = 1 /**< Ethernet port 2 */ - ,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */ -} IxEthAccPortId; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETH_ACC_NUMBER_OF_PORTS - * - * @brief Definition of the number of ports - * - */ -#ifdef __ixp46X -#define IX_ETH_ACC_NUMBER_OF_PORTS (3) -#else -#define IX_ETH_ACC_NUMBER_OF_PORTS (2) -#endif - -/** - * @ingroup IxEthAcc - * - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * - * @brief Definition of the size of the MAC address - * - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - - -/** - * - * @brief Definition of the IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * @note - * The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */ -} IxEthAccMacAddr; - -/** - * @ingroup IxEthAcc - * @def IX_ETH_ACC_NUM_TX_PRIORITIES - * @brief Definition of the number of transmit priorities - * - */ -#define IX_ETH_ACC_NUM_TX_PRIORITIES (8) - -/** - * @ingroup IxEthAcc - * @enum IxEthAccTxPriority - * @brief Definition of the relative priority used to transmit a frame - * - */ -typedef enum -{ - IX_ETH_ACC_TX_PRIORITY_0 = 0, /** STA */ - IX_ETHACC_RX_APTYPE = 0x30 /**< 802.11, AP <=> AP */ -} IxEthAccRxFrameType; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccDuplexMode - * @brief Definition to provision the duplex mode of the MAC. - * - */ -typedef enum -{ - IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */ - IX_ETH_ACC_HALF_DUPLEX /**< Half duplex operation of the MAC */ -} IxEthAccDuplexMode; - - -/** - * @ingroup IxEthAcc - * @struct IxEthAccNe - * @brief Definition of service-specific informations. - * - * This structure defines the Ethernet service-specific informations - * and enable QoS and VLAN features. - */ -typedef struct -{ - UINT32 ixReserved_next; /**< reserved for chaining */ - UINT32 ixReserved_lengths; /**< reserved for buffer lengths */ - UINT32 ixReserved_data; /**< reserved for buffer pointer */ - UINT8 ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */ - UINT8 ixSourcePortId; /**< Source portId for this packet */ - UINT16 ixFlags; /**< BitField of option for this frame */ - UINT8 ixQoS; /**< QoS class of the frame */ - UINT8 ixReserved; /**< reserved */ - UINT16 ixVlanTCI; /**< Vlan TCI */ - UINT8 ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */ - UINT8 ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */ -} IxEthAccNe; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORT_UNKNOWN - * - * @brief Contents of the field @a IX_ETHACC_NE_DESTPORTID when no - * destination port can be found by the NPE for this frame. - * - */ -#define IX_ETHACC_NE_PORT_UNKNOWN (0xff) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTMAC - * - * @brief The location of the destination MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEMAC - * - * @brief The location of the source MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANTCI - * - * @brief The VLAN Tag Control Information associated with this frame - * - * The VLAN Tag Control Information associated with this frame. On Rx - * path, this field is extracted from the packet header. - * On Tx path, the value of this field is inserted in the frame when - * the port is configured to insert or replace vlan tags in the - * egress frames. - * - * @sa IX_ETHACC_NE_FLAGS - */ -#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEPORTID - * - * @brief The port where this frame came from. - * - * The port where this frame came from. This field is set on receive - * with the port information. This field is ignored on Transmit path. - */ -#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTPORTID - * - * @brief The destination port where this frame should be sent. - * - * The destination port where this frame should be sent. - * - * @li In the transmit direction, this field contains the destination port - * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set. - * - * @li In the receive direction, this field contains the port where the - * destination MAC addresses has been learned. If the destination - * MAC address is unknown, then this value is set to the reserved value - * @a IX_ETHACC_NE_PORT_UNKNOWN - * - */ -#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_QOS - * - * @brief QualityOfService class (QoS) for this received frame. - * - */ -#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FLAGS - * - * @brief Bit Mask of the different flags associated with a frame - * - * The flags are the bit-oring combination - * of the following different fields : - * - * @li IP flag (Rx @a IX_ETHACC_NE_IPMASK) - * @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK) - * @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK) - * @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK) - * @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK) - * @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK) - * @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK) - * @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK) - * @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK) - * @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK) - * @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK) - * @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK) - */ -#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_BCASTMASK - * - * @brief This mask defines if a received frame is a broadcast frame. - * - * This mask defines if a received frame is a broadcast frame. - * The BCAST flag is set when the destination MAC address of - * a frame is broadcast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_BCASTMASK (0x1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_MCASTMASK - * - * @brief This mask defines if a received frame is a multicast frame. - * - * This mask defines if a received frame is a multicast frame. - * The MCAST flag is set when the destination MAC address of - * a frame is multicast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_MCASTMASK (0x1 << 1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_IPMASK - * - * @brief This mask defines if a received frame is a IP frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received - * frame is a IP frame. The IP flag is set on Rx direction, depending on - * the frame contents. The flag is set when the length/type field of a - * received frame is 0x8000. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_IPMASK (0x1 << 2) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANMASK - * - * @brief This mask defines if a received frame is VLAN tagged. - * - * This mask defines if a received frame is VLAN tagged. - * When set, the Rx frame is VLAN-tagged and the tag value - * is available thru @a IX_ETHACC_NE_VLANID. - * Note that when sending frames which are already tagged - * this flag should be set, to avoid inserting another VLAN tag. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_VLANID - * - */ -#define IX_ETHACC_NE_VLANMASK (0x1 << 3) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_LINKMASK - * - * @brief This mask is the link layer protocol indicator - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * It reflects the state of a frame as it exits an NPE on the Rx path - * or enters an NPE on the Tx path. Its values are as follows: - * @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx) - * @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx) - * @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx) - * @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx) - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_LINKMASK (0x3 << 4) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_STMASK - * - * @brief This mask defines if a received frame is a Spanning Tree frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * On rx direction, it defines if a received if frame is a Spanning Tree frame. - * Setting this fkag on transmit direction overrides the port settings - * regarding the VLAN options and - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_STMASK (0x1 << 6) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FILTERMASK - * - * @brief This bit indicates whether a frame has been filtered by the Rx service. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * Certain frames, which should normally be fully filtered by the NPE to due - * the destination MAC address being on the same segment as the Rx port are - * still forwarded to the XScale (although the payload is invalid) in order - * to learn the MAC address of the transmitting station, if this is unknown. - * Normally EthAcc will filter and recycle these framess internally and no - * frames with the FILTER bit set will be received by the client. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_FILTERMASK (0x1 << 7) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORTMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, a frame - * is transmitted to the destination port as set by the macro - * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port - * is searched using the destination MAC address. - * - * @note This flag is meaningful only for multiport Network Engines. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_DESTPORTID - * - */ -#define IX_ETHACC_NE_PORTOVERMASK (0x1 << 8) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGMODEMASK - * - * @brief This mask defines the tagging rules to apply to a transmit frame. - * - * This mask defines the tagging rules to apply to a transmit frame - * regardless of the default setting for a port. When used together - * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the - * frame will be tagged prior to transmission. When not set, - * the frame will be untagged prior to transmission. This is accomplished - * irrespective of the Egress tagging rules, constituting a per-frame override. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGOVERMASK - * - */ -#define IX_ETHACC_NE_TAGMODEMASK (0x1 << 9) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGOVERMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, the - * default transmit rules of a port are overriden. - * When not set, the default rules as set by @ref IxEthDB should apply. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGMODEMASK - * - */ -#define IX_ETHACC_NE_TAGOVERMASK (0x1 << 10) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANENABLEMASK - * - * @brief This mask defines if a frame is a VLAN frame or not - * - * When set, frames undergo normal VLAN processing on the Tx path - * (membership filtering, tagging, tag removal etc). If this flag is - * not set, the frame is considered to be a regular non-VLAN frame - * and no VLAN processing will be performed. - * - * Note that VLAN-enabled NPE images will always set this flag in all - * Rx frames, and images which are not VLAN enabled will clear this - * flag for all received frames. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_NEWSRCMASK - * - * @brief This mask defines if a received frame has been learned. - * - * This mask defines if the source MAC address of a frame is - * already known. If the bit is set, the source MAC address was - * unknown to the NPE at the time the frame was received. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_NEWSRCMASK (0x1 << 15) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the recommanded minimum size of MBUF's submitted - * to the frame receive service. - * - */ -#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the highest MII address of any attached PHYs - * - * The maximum number for PHY address is 31, add on for range checking. - * - */ -#define IXP425_ETH_ACC_MII_MAX_ADDR 32 - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccInit(void) - * - * @brief Initializes the IXP400 Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per module initialization. - * @pre - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Service has failed to initialize. - * - *

- */ -PUBLIC IxEthAccStatus ixEthAccInit(void); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccUnload(void) - * - * @brief Unload the Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @return void - * - *
- */ -PUBLIC void ixEthAccUnload(void); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortInit( IxEthAccPortId portId) - * - * @brief Initializes an NPE/Ethernet MAC Port. - * - * The NPE/Ethernet port initialisation includes the following steps - * @li Initialize the NPE/Ethernet MAC hardware. - * @li Verify NPE downloaded and operational. - * @li The NPE shall be available for usage once this API returns. - * @li Verify that the Ethernet port is present before initializing - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per mac device. - * The NPE/MAC shall be in disabled state after init. - * - * @pre - * The component must be initialized via @a ixEthAccInit - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued. - * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId); - - -/************************************************************************* - - ##### ## ##### ## ##### ## ##### # # - # # # # # # # # # # # # # # - # # # # # # # # # # # # ###### - # # ###### # ###### ##### ###### # # # - # # # # # # # # # # # # # - ##### # # # # # # # # # # # - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) - * - * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device. - * - * When the frame is transmitted, the buffer shall be returned thru the - * callback @a IxEthAccPortTxDoneCallback. - * - * In case of over-submitting, the order of the frames on the - * network may be modified. - * - * Buffers shall be not queued for transmission if the port is disabled. - * The port can be enabled using @a ixEthAccPortEnable - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @pre - * @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to - * return the buffer to the calling service. - * - * @note - * If the buffer submit fails for any reason the user has retained ownership of the buffer. - * - * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on. - * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored. - * @param priority @ref IxEthAccTxPriority [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Failed to queue frame for transmission. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ - -PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered - * via @a ixEthAccTxBufferDoneCallbackRegister - * - * This function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or during the shutdown of - * the port prior to the transmission of a queued frame. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor. - * - * @return void - * - * @note - * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL. - * - *
- */ -typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer ); - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the transmitted buffers to return to the user. - * - * This function registers the transmit buffer done function callback for a particular port. - * - * The registered callback function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or shutdown of port prior to submission. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * The port must be initialized via @a ixEthAccPortInit - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag); - - - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches frames to the user level - * via the provided function. The invocation shall be made for each - * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if - * the frame length is greater than the supplied mbuf length. - * @param reserved [in] - deprecated parameter The information is passed - * thru the IxEthAccNe header destination port ID field - * (@sa IX_ETHACC_NE_DESTPORTID). For backward - * compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff). - * - * @return void - * - * @note - * Buffers may not be filled up to the length supplied in - * @a ixEthAccPortRxFreeReplenish(). The firmware fills - * them to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * The mbuf header contains the following modified field - * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates - * the total frame size - * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length - * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next - * mbuf, or NULL at the end of a chain. - * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL - * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5 - * set for a multicast packet. Other bits are unmodified. - * - *
- */ -typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches many frames to the user level - * via the provided function. The invocation shall be made for multiple frames - * dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs - * may be chained if - * the frame length is greater than the supplied mbuf length. - * The end of the array contains a zeroed entry (NULL pointer). - * - * @return void - * - * @note The mbufs passed to this callback have the same structure than the - * buffers passed to @a IxEthAccPortRxCallback interfac. - * - * @note The usage of this callback is exclusive with the usage of - * @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ - -typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is received by this service. - * - * If called several times the latest callback shall be registered for a particular port. - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback rxCallbackFn, - UINT32 callbackTag); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is - * received by this service. If many frames are already received, - * the function is called once. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId - Register callback for a particular MAC device. - * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble. - * @param callbackTag - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback rxCallbackFn, - UINT32 callbackTag); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer) - * - * @brief This function provides buffers for the Ethernet receive path. - * - * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it - * via this interface. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC. - * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism. - * Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor - * performances and excessive buffer chaining. Buffers - * larger than this size may be suitable for jumbo frames. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the - * buffer in the receive service. - * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - * @note - * If the buffer replenish operation fails it is the responsibility - * of the user to free the buffer. - * - * @note - * Sufficient buffers must be supplied to the component to maintain - * receive throughput and avoid rx buffer underflow conditions. - * To meet this goal, It is expected that the user preload the - * component with a sufficent number of buffers prior to enabling the - * NPE Ethernet receive path. The recommended minimum number of - * buffers is 8. - * - * @note - * For maximum performances, the mbuf size should be greater - * than the maximum frame size (Ethernet header, payload and FCS) + 64. - * Supplying smaller mbufs to the service results in mbuf - * chaining and degraded performances. The recommended size - * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is - * enough to take care of 802.3 frames and "baby jumbo" frames without - * chaining, and "jumbo" frame within chaining. - * - * @note - * Buffers may not be filled up to their length. The firware fills - * them up to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * - * @warning This function checks the parameters if the NDEBUG - * flag is not defined. Turning on the argument checking (disabled by - * default) results in a lower EthAcc performance as this function - * is part of the data path. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer); - - - -/*************************************************************** - - #### #### # # ##### ##### #### # - # # # # ## # # # # # # # - # # # # # # # # # # # # - # # # # # # # ##### # # # - # # # # # ## # # # # # # - #### #### # # # # # #### ###### - - - ##### # ## # # ###### - # # # # # ## # # - # # # # # # # # ##### - ##### # ###### # # # # - # # # # # ## # - # ###### # # # # ###### - -***************************************************************/ - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnable(IxEthAccPortId portId) - * - * @brief This enables an Ethernet port for both Tx and Rx. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address - * must be set using @a ixEthAccUnicastMacAddressSet before enabling it - * The rx and Tx Done callbacks registration via @a - * ixEthAccPortTxDoneCallbackRegister amd @a ixEthAccPortRxCallbackRegister - * has to be done before enabling the traffic. - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDisable(IxEthAccPortId portId) - * - * @brief This disables an Ethernet port for both Tx and Rx. - * - * Free MBufs are returned to the user via the registered callback when the port is disabled - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this - * function has no effect - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) - * - * @brief Get the enabled state of a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre The port must first be initialized via @a ixEthAccPortInit - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * @param enabled BOOL [out] - location to store the state of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) - * - * @brief Put the Ethernet MAC device in non-promiscuous mode. - * - * In non-promiscuous mode the MAC filters all frames other than - * destination MAC address which matches the following criteria: - * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet - * @li All broadcast frames. - * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeSet - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) - * - * @brief Put the MAC device in promiscuous mode. - * - * If the device is in promiscuous mode then all all received frames shall be forwared - * to the NPE for processing. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeClear - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Configure unicast MAC address for a particular port - * - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Get unicast MAC address for a particular MAC port - * - * @pre - * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet - * If the MAC address has not been set, the function returns a - * IX_ETH_ACC_MAC_UNINITIALIZED status - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized. - * @li @a IX_ETH_ACC_FAIL : macAddr is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Add a multicast address to the MAC address table. - * - * @note - * Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not - * have a multicast destination address which were provisioned via this API may be forwarded - * to the NPE's. This is a result of the hardware comparison algorithm used in the destination mac address logic - * within the Ethernet MAC. - * - * See Also: IXP425 hardware development manual. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId) - * - * @brief Filter all frames with multicast dest. - * - * This function clears the MAC address table, and then sets - * the MAC to forward ALL multicast frames to the NPE. - * Specifically, it forwards all frames whose destination address - * has the LSB of the highest byte set (01:00:00:00:00:00). This - * bit is commonly referred to as the "multicast bit". - * Broadcast frames will still be forwarded. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Remove a multicast address from the MAC address table. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_NO_SUCH_ADDR : Failed if MAC address was not in the table. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId) - * - * @brief This function unconfigures the multicast filtering settings - * - * This function first clears the MAC address table, and then sets - * the MAC as configured by the promiscuous mode current settings. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) - * - * @brief Displays unicast MAC address - * - * Displays unicast address which is configured using - * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used - * to filter multicast frames. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId) - * - * @brief Displays multicast MAC address - * - * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode ) - * - * @brief Set the duplex mode for the MAC. - * - * Configure the IXP400 MAC to either full or half duplex. - * - * @note - * The configuration should match that provisioned on the PHY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param mode @ref IxEthAccDuplexMode [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode ) - * - * @brief Get the duplex mode for the MAC. - * - * return the duplex configuration of the IXP400 MAC. - * - * @note - * The configuration should match that provisioned on the PHY. - * See @a ixEthAccDuplexModeSet - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param *mode @ref IxEthAccDuplexMode [out] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- * - */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId) - * - * @brief Enable padding bytes to be appended to runt frames submitted to - * this port - * - * Enable up to 60 null-bytes padding bytes to be appended to runt frames - * submitted to this port. This is the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @note When Tx padding is enabled, Tx FCS generation is turned on - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendFCSDusable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId) - * - * @brief Disable padding bytes to be appended to runt frames submitted to - * this port - * - * Disable padding bytes to be appended to runt frames - * submitted to this port. This is not the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Enable the appending of Ethernet FCS to all frames submitted to this port - * - * When enabled, the FCS is added to the submitted frames. This is the default - * behavior of the access component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Disable the appending of Ethernet FCS to all frames submitted to this port. - * - * When disabled, the Ethernet FCS is not added to the submitted frames. - * This is not the default - * behavior of the access component. - * - * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the - * component includes a valid FCS at the end of the data, although this will not be validated. - * - * The component shall forward the frame to the Ethernet MAC WITHOUT modification. - * - * Do not change this behaviour while the port is enabled. - * - * @note Tx FCS append is not disabled while Tx padding is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendPaddingEnable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Forward frames with FCS included in the receive buffer. - * - * The FCS is not striped from the receive buffer. - * The received frame length includes the FCS size (4 bytes). ie. - * A minimum sized ethernet frame shall have a length of 64bytes. - * - * Frame FCS validity checks are still carried out on all received frames. - * - * This is not the default - * behavior of the access component. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Do not forward the FCS portion of the received Ethernet frame to the user. - * The FCS is striped from the receive buffer. - * The received frame length does not include the FCS size (4 bytes). - * Frame FCS validity checks are still carried out on all received frames. - * - * This is the default behavior of the component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId); - - - - -/** - * @ingroup IxEthAcc - * - * @enum IxEthAccSchedulerDiscipline - * - * @brief Definition for the port scheduling discipline - * - * Select the port scheduling discipline on receive and transmit path - * @li FIFO : No Priority : In this configuration all frames are processed - * in the access component in the strict order in which - * the component received them. - * @li FIFO : Priority : This shall be a very simple priority mechanism. - * Higher prior-ity frames shall be forwarded - * before lower priority frames. There shall be no - * fairness mechanisms applied across different - * priorities. Higher priority frames could starve - * lower priority frames indefinitely. - */ -typedef enum -{ - FIFO_NO_PRIORITY, /** - */ -PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline sched); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) - * - * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline - * - * The default behavior of the component is @a FIFO_NO_PRIORITY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param sched : @a IxEthAccSchedulerDiscipline - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline. - * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId) - * - * @brief Enable NPE loopback - * - * When this loopback mode is enabled all the transmitted frames are - * received on the same port, without payload. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId : ID of the port - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) - * - * @brief Disable NPE loopback - * - * This function is used to disable the NPE loopback if previously - * enabled using ixEthAccNpeLoopbackEnable. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId) - * - * @brief Enable Tx on the port - * - * This function is the complement of ixEthAccPortTxDisable and should - * be used only after Tx was disabled. A MAC core reset is required before - * this function is called (see @a ixEthAccPortMacReset). - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId) - * - * @brief Disable Tx on the port - * - * This function can be used to disable Tx in the MAC core. - * Tx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable. - * Note that using this function is not recommended, except for shutting - * down Tx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId) - * - * @brief Enable Rx on the port - * - * This function is the complement of ixEthAccPortRxDisable and should - * be used only after Rx was disabled. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId) - * - * @brief Disable Rx on the port - * - * This function can be used to disable Rx in the MAC core. - * Rx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable. - * Note that using this function is not recommended, except for shutting - * down Rx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId) - * - * @brief Reset MAC core on the port - * - * This function will perform a MAC core reset (NPE Ethernet coprocessor). - * This function is inherently unsafe and the NPE recovery is not guaranteed - * after this function is called. The proper manner of performing port disable - * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable. - * - * This function is the recommended usage scenario for hardware failure recovery - * and should never be used for throttling traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : MAC core reset - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId); - -/********************************************************************************* - #### ##### ## ##### # #### ##### # #### #### - # # # # # # # # # # # # - #### # # # # # #### # # # #### - # # ###### # # # # # # # - # # # # # # # # # # # # # # # - #### # # # # # #### # # #### #### -**********************************************************************************/ - - -/** - * - * @brief This struct defines the statistics returned by this component. - * - * The component returns MIB2 EthObj variables which are obtained from the - * hardware or maintained by this component. - * - * - */ -typedef struct -{ - UINT32 dot3StatsAlignmentErrors; /**< link error count (rx) */ - UINT32 dot3StatsFCSErrors; /**< link error count (rx) */ - UINT32 dot3StatsInternalMacReceiveErrors; /**< link error count (rx) */ - UINT32 RxOverrunDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxLearnedEntryDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxLargeFramesDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxSTPBlockedDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxVLANTypeFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxVLANIdFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxInvalidSourceDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxBlackListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxWhiteListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxUnderflowEntryDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 dot3StatsSingleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsMultipleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsDeferredTransmissions; /**< link error count (tx) */ - UINT32 dot3StatsLateCollisions; /**< link error count (tx) */ - UINT32 dot3StatsExcessiveCollsions; /**< link error count (tx) */ - UINT32 dot3StatsInternalMacTransmitErrors; /**< link error count (tx) */ - UINT32 dot3StatsCarrierSenseErrors; /**< link error count (tx) */ - UINT32 TxLargeFrameDiscards; /**< NPE: discarded frames count (tx) */ - UINT32 TxVLANIdFilterDiscards; /**< NPE: discarded frames count (tx) */ - -}IxEthEthObjStats; - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats ) - * - * @brief Returns the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStat - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats) - * - * @brief Returns and clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStats - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId) - * - * @brief Clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMacInit(IxEthAccPortId portId) - * - * @brief Initializes the ethernet MAC settings - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccStatsShow(IxEthAccPortId portId) - * - * - * @brief Displays a ports statistics on the standard io console using printf. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return void - * - *
- */ -PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId); - -/************************************************************************* - - # # # # # # ##### # #### - ## ## # # ## ## # # # # # - # ## # # # # ## # # # # # # - # # # # # # # # # # # - # # # # # # # # # # # - # # # # # # ##### # #### - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) - * - * - * @brief Reads a 16 bit value from a PHY - * - * Reads a 16-bit word from a register of a MII-compliant PHY. Reading - * is performed through the MII management interface. This function returns - * when the read operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to read (0-31) - * @param value UINT16 [in] - the value read from the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to read the register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) - * - * - * @brief Writes a 16 bit value to a PHY - * - * Writes a 16-bit word from a register of a MII-compliant PHY. Writing - * is performed through the MII management interface. This function returns - * when the write operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to write (0-31) - * @param value UINT16 [out] - the value to write to the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to write register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout) - * - * @brief Overrides the default timeout value and retry count when reading or - * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn - * - * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms - * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS - * (declared as 5 in IxEthAccMii_p.h). - * - * The MII read and write functions will attempt to read the status of the register up - * to the retry count times, delaying between each attempt with the timeout value. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param timeout UINT32 [in] - new timeout value, in milliseconds - * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid parameter(s) - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiStatsShow (UINT32 phyAddr) - * - * - * @brief Displays detailed information on a specified PHY - * - * Displays the current values of the first eigth MII registers for a PHY, - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and - * generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr); - - - -/******* BOARD SPECIFIC DEPRECATED API *********/ - -/* The following functions are high level functions which rely - * on the properties and interface of some Ethernet PHYs. The - * implementation is hardware specific and has been moved to - * the hardware-specific component IxEthMii. - */ - - #include "IxEthMii.h" - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyScan - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyScan - * - * @note this feature is board specific - * - */ -#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyConfig - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyConfig - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \ - ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyReset - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyReset - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyReset(phyAddr) \ - ixEthMiiPhyReset(phyAddr) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiLinkStatus - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiLinkStatus - * - * @note this feature is board specific - */ -#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \ - ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) - - - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiShow - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyShow - * - * @note this feature is board specific - */ -#define ixEthAccMiiShow(phyAddr) \ - ixEthMiiPhyShow(phyAddr) - -#endif /* ndef IxEthAcc_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthAccDataPlane_p.h b/drivers/net/npe/include/IxEthAccDataPlane_p.h deleted file mode 100644 index dce43d9a19..0000000000 --- a/drivers/net/npe/include/IxEthAccDataPlane_p.h +++ /dev/null @@ -1,221 +0,0 @@ -/** - * @file IxEthAccDataPlane_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - - -#ifndef IxEthAccDataPlane_p_H -#define IxEthAccDataPlane_p_H - -#include -#include - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* typedefs global to this file*/ - -typedef struct -{ - IX_OSAL_MBUF *pHead; - IX_OSAL_MBUF *pTail; -}IxEthAccDataPlaneQList; - - -/** - * @struct IxEthAccDataPlaneStats - * @brief Statistics data structure associated with the data plane - * - */ -typedef struct -{ - UINT32 addToSwQ; - UINT32 removeFromSwQ; - UINT32 unchainedTxMBufs; - UINT32 chainedTxMBufs; - UINT32 unchainedTxDoneMBufs; - UINT32 chainedTxDoneMBufs; - UINT32 unchainedRxMBufs; - UINT32 chainedRxMBufs; - UINT32 unchainedRxFreeMBufs; - UINT32 chainedRxFreeMBufs; - UINT32 rxCallbackCounter; - UINT32 rxCallbackBurstRead; - UINT32 txDoneCallbackCounter; - UINT32 unexpectedError; -} IxEthAccDataPlaneStats; - -/** - * @fn ixEthAccMbufFromSwQ - * @brief used during disable steps to convert mbufs from - * swq format, ready to be pushed into hw queues for NPE, - * back into XScale format - */ -IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf); - -/** - * @fn ixEthAccDataPlaneShow - * @brief Show function (for data plane statistics - */ -void ixEthAccDataPlaneShow(void); - -/* - * lock dataplane when atomic operation is required - */ -#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock(); -#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg); - -/* - * Use MBUF fields - */ -#define IX_ETHACC_NE_SHARED(mBufPtr) \ - ((IxEthAccNe *)&((mBufPtr)->ix_ne)) - -#if 1 - -#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0] - -/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */ -#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1] - -#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2] - -#else - -#define IX_ETHACC_NE_NEXT(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next - -#define IX_ETHACC_NE_LEN(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths - -#define IX_ETHACC_NE_DATA(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data -#endif - -/* - * Use MBUF next pointer field to chain data. - */ -#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain - - - -#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\ - (mbuf_list.pHead) = (mbuf_to_add); \ - } \ - else { \ - (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while(0) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) == NULL ) \ - { \ - (mbuf_list.pHead) = mbuf_to_add; \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - else { \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - (mbuf_list.pTail) = mbuf_to_add; \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \ - (mbuf_to_rem) = (mbuf_list.pHead) ; \ - (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\ - } \ - else { \ - (mbuf_to_rem) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -/** - * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \ - ixEthAccPortData[(port)].npeId - -#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 )))) - -#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccTxData.txQueue - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue - -#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE)) - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE )) - -/* Flush the mbufs chain and all data pointed to by the mbuf */ - -#ifndef NDEBUG -#define IX_ETH_ACC_STATS_INC(x) (x++) -#else -#define IX_ETH_ACC_STATS_INC(x) -#endif - -#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128 - -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); - -#endif /* IxEthAccDataPlane_p_H */ - - -/** - *@} - */ - diff --git a/drivers/net/npe/include/IxEthAccMac_p.h b/drivers/net/npe/include/IxEthAccMac_p.h deleted file mode 100644 index 4eafab2585..0000000000 --- a/drivers/net/npe/include/IxEthAccMac_p.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -#ifndef IxEthAccMac_p_H -#define IxEthAccMac_p_H - -#include "IxOsal.h" - -#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256 -#define IX_ETH_ACC_NUM_PORTS 3 -#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536 -#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64) -#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64 - -/* - * - * MAC register definitions - * - */ -#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE -#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE -#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE - -#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000 -#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004 -#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010 -#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014 -#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020 -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030 -#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038 -#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040 -#define IX_ETH_ACC_MAC_TX_DEFER 0x050 -#define IX_ETH_ACC_MAC_RX_DEFER 0x054 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064 -#define IX_ETH_ACC_MAC_SLOT_TIME 0x070 -#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080 -#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084 -#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088 -#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c -#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090 -#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094 -#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098 -#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c -#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0 -#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4 -#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8 -#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC -#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0 -#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4 -#define IX_ETH_ACC_MAC_ADDR_1 0x0C0 -#define IX_ETH_ACC_MAC_ADDR_2 0x0C4 -#define IX_ETH_ACC_MAC_ADDR_3 0x0C8 -#define IX_ETH_ACC_MAC_ADDR_4 0x0CC -#define IX_ETH_ACC_MAC_ADDR_5 0x0D0 -#define IX_ETH_ACC_MAC_ADDR_6 0x0D4 -#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0 -#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0 -#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4 -#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8 -#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC -#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100 -#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104 -#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC - - -/* - * - *Bit definitions - * - */ - -/* TX Control Register 1*/ - -#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0) -#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1) -#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2) -#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3) -#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4) -#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5) -#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6) - -/* TX Control Register 2 */ -#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf - -/* RX Control Register 1 */ -#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0) -#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1) -#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2) -#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3) -#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4) -#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5) -#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6) -#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7) - -/* RX Control Register 2 */ -#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0) - - - -/* Core Control Register */ -#define IX_ETH_ACC_CORE_RESET BIT(0) -#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1) -#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2) -#define IX_ETH_ACC_CORE_SEND_JAM BIT(3) -#define IX_ETH_ACC_CORE_MDC_EN BIT(4) - -/* 1st bit of 1st MAC octet */ -#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) - - -/* - * - * Default values - * - */ - - -#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \ - IX_ETH_ACC_TX_CNTRL1_RETRY | \ - IX_ETH_ACC_TX_CNTRL1_FCS_EN | \ - IX_ETH_ACC_TX_CNTRL1_2DEFER | \ - IX_ETH_ACC_TX_CNTRL1_PAD_EN) - -#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f - -#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \ - | IX_ETH_ACC_RX_CNTRL1_RX_EN) - -#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0 - -/* Thresholds determined by NPE firmware FS */ -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12 -#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30 - -/* Number of bytes that must be in the tx fifo before - transmission commences*/ -#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8 - -/* One-part deferral values */ -#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15 -#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16 - -/* Two-part deferral values... */ -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07 - -/* This value applies to MII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80 - -/* This value applies to RMII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1 -/*The following is a value chosen at random*/ -#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8 - -/*By default we must configure the MAC to generate the - MDC clock*/ -#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN) - -#define IXP425_ETH_ACC_MAX_PHY 2 -#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20 -#define IX_ETH_ACC_MAC_RESET_DELAY 1 - -#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF - -#define IX_ETH_ACC_MAC_MSGID_SHL 24 - -#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20 -#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */ -#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3 -#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ - -/*Register access macros*/ -#if (CPU == SIMSPARCSOLARIS) -extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val); -extern UINT32 registerReadStub (UINT32 base, UINT32 offset); - -#define REG_WRITE(b,o,v) registerWriteStub(b, o, v) -#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0) -#else -#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v) -#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o))) - -#endif - -void ixEthAccMacUnload(void); -IxEthAccStatus ixEthAccMacMemInit(void); - -/* MAC core loopback */ -IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId); - -/* MAC core traffic control */ -IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId); - -/* NPE software loopback */ -IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId); - -#endif /*IxEthAccMac_p_H*/ - diff --git a/drivers/net/npe/include/IxEthAccMii_p.h b/drivers/net/npe/include/IxEthAccMii_p.h deleted file mode 100644 index aff30f00af..0000000000 --- a/drivers/net/npe/include/IxEthAccMii_p.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file IxEthAccMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccMii_p_H -#define IxEthAccMii_p_H - -/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/ - -#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */ - -#define IX_ETH_ACC_MII_REG_SHL 16 -#define IX_ETH_ACC_MII_ADDR_SHL 21 - -/* Definitions for MII access routines*/ - -#define IX_ETH_ACC_MII_GO BIT(31) -#define IX_ETH_ACC_MII_WRITE BIT(26) -#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5 -#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100 -#define IX_ETH_ACC_MII_READ_FAIL BIT(31) - -#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ -#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */ -#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */ -#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ - -#ifndef IX_ETH_ACC_MII_MONITOR_DELAY -# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */ -#endif - -/* Register definition */ - -#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -IxEthAccStatus ixEthAccMdioShow (void); -IxEthAccStatus ixEthAccMiiInit(void); -void ixEthAccMiiUnload(void); - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthAccQueueAssign_p.h b/drivers/net/npe/include/IxEthAccQueueAssign_p.h deleted file mode 100644 index 65661a0dd5..0000000000 --- a/drivers/net/npe/include/IxEthAccQueueAssign_p.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file IxEthAccQueueAssign_p.h - * - * @author Intel Corporation - * @date 06-Mar-2002 - * - * @brief Mapping from QMgr Q's to internal assignment - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxQMgr.h" -#include "IxQueueAssignments.h" - -/* Check range of Q's assigned to this component. */ -#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID) -#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated " -#endif - -/** -* -* @typedef IxEthAccQregInfo -* -* @brief -* -*/ -typedef struct -{ - IxQMgrQId qId; - char *qName; - IxQMgrCallback qCallback; - IxQMgrCallbackId callbackTag; - IxQMgrQSizeInWords qSize; - IxQMgrQEntrySizeInWords qWords; - BOOL qNotificationEnableAtStartup; - IxQMgrSourceId qConditionSource; - IxQMgrWMLevel AlmostEmptyThreshold; - IxQMgrWMLevel AlmostFullThreshold; - -} IxEthAccQregInfo; - -/* - * Prototypes for all QM callbacks. - */ - -/* - * Rx Callbacks - */ -IX_ETH_ACC_PUBLIC -void ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId); - -/* - * Tx Callback. - */ -IX_ETH_ACC_PUBLIC -void ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId ); - - -#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */ - -/* - * Queue watermarks - */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h deleted file mode 100644 index 1348f4e3c8..0000000000 --- a/drivers/net/npe/include/IxEthAcc_p.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * @file IxEthAcc_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -#ifndef IxEthAcc_p_H -#define IxEthAcc_p_H - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxNpeDl.h" -#include "IxQMgr.h" - -#include "IxEthNpe.h" - -/* - * Intra module dependancies - */ - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMac_p.h" - - -#define INLINE __inline__ - -#ifdef NDEBUG - -#define IX_ETH_ACC_PRIVATE static - -#else - -#define IX_ETH_ACC_PRIVATE - -#endif /* ndef NDEBUG */ - -#define IX_ETH_ACC_PUBLIC - - -#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false ) - - - -#ifndef NDEBUG -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#else -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {} -#endif - -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries); - -/* prototypes for the private control plane functions (used by the control interface wrapper) */ -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched); - -/** - * @struct ixEthAccRxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 rxFrameClientCallback; - UINT32 rxFreeRepOK; - UINT32 rxFreeRepDelayed; - UINT32 rxFreeRepFromSwQOK; - UINT32 rxFreeRepFromSwQDelayed; - UINT32 rxFreeLateNotificationEnabled; - UINT32 rxFreeLowCallback; - UINT32 rxFreeOverflow; - UINT32 rxFreeLock; - UINT32 rxDuringDisable; - UINT32 rxSwQDuringDisable; - UINT32 rxUnlearnedMacAddress; - UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 rxUnexpectedError; - UINT32 rxFiltered; -} IxEthAccRxDataStats; - -/** - * @struct IxEthAccTxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 txQOK; - UINT32 txQDelayed; - UINT32 txFromSwQOK; - UINT32 txFromSwQDelayed; - UINT32 txLowThreshCallback; - UINT32 txDoneClientCallback; - UINT32 txDoneClientCallbackDisable; - UINT32 txOverflow; - UINT32 txLock; - UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 txLateNotificationEnabled; - UINT32 txDoneDuringDisable; - UINT32 txDoneSwQDuringDisable; - UINT32 txUnexpectedError; -} IxEthAccTxDataStats; - -/* port Disable state machine : list of states */ -typedef enum -{ - /* general port states */ - DISABLED = 0, - ACTIVE, - - /* particular Tx/Rx states */ - REPLENISH, - RECEIVE, - TRANSMIT, - TRANSMIT_DONE -} IxEthAccPortDisableState; - -typedef struct -{ - BOOL fullDuplex; - BOOL rxFCSAppend; - BOOL txFCSAppend; - BOOL txPADAppend; - BOOL enabled; - BOOL promiscuous; - BOOL joinAll; - IxOsalMutex ackMIBStatsLock; - IxOsalMutex ackMIBStatsResetLock; - IxOsalMutex MIBStatsGetAccessLock; - IxOsalMutex MIBStatsGetResetAccessLock; - IxOsalMutex npeLoopbackMessageLock; - IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES]; - UINT32 mcastAddrIndex; - IX_OSAL_MBUF *portDisableTxMbufPtr; - IX_OSAL_MBUF *portDisableRxMbufPtr; - - volatile IxEthAccPortDisableState portDisableState; - volatile IxEthAccPortDisableState rxState; - volatile IxEthAccPortDisableState txState; - - BOOL initDone; - BOOL macInitialised; -} IxEthAccMacState; - -/** - * @struct IxEthAccRxInfo - * @brief System-wide data structures associated with the data plane. - * - */ -typedef struct -{ - IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */ -} IxEthAccInfo; - -/** - * @struct IxEthAccRxDataInfo - * @brief Per Port data structures associated with the receive data plane. - * - */ -typedef struct -{ - IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */ - IxEthAccPortRxCallback rxCallbackFn; - UINT32 rxCallbackTag; - IxEthAccDataPlaneQList freeBufferList; - IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn; - UINT32 rxMultiBufferCallbackTag; - BOOL rxMultiBufferCallbackInUse; - IxEthAccRxDataStats stats; /**< Receive s/w stats */ -} IxEthAccRxDataInfo; - -/** - * @struct IxEthAccTxDataInfo - * @brief Per Port data structures associated with the transmit data plane. - * - */ -typedef struct -{ - IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; - UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ - IxQMgrQId txQueue; /**< txQueue for this port */ - IxEthAccTxDataStats stats; /**< Transmit s/w stats */ -} IxEthAccTxDataInfo; - - -/** - * @struct IxEthAccPortDataInfo - * @brief Per Port data structures associated with the port data plane. - * - */ -typedef struct -{ - BOOL portInitialized; - UINT32 npeId; /**< NpeId for this port */ - IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ -} IxEthAccPortDataInfo; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized) - -extern BOOL ixEthAccServiceInit; -#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true ) - -/* - * Maximum number of frames to consume from the Rx Frame Q. - */ - -#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128) - -/* - * Max number of times to load the Rx Free Q from callback. - */ -#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */ - -/* - * Max number of times to read from the Tx Done Q in one sitting. - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256) - -/* - * Max number of times to take buffers from S/w queues and write them to the H/w Tx - * queues on receipt of a Tx low threshold callback - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16) - - -#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size)) -#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size)) - - -#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size) - -#endif /* ndef IxEthAcc_p_H */ - - - diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h deleted file mode 100644 index 9c4a6a4ec4..0000000000 --- a/drivers/net/npe/include/IxEthDB.h +++ /dev/null @@ -1,2349 +0,0 @@ -/** @file IxEthDB.h - * - * @brief this file contains the public API of @ref IxEthDB component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthDB_H -#define IxEthDB_H - -#include -#include - -/** - * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API - * - * @brief ethDB is a library that does provides a MAC address database learning/filtering capability - * - *@{ - */ - -#define INLINE __inline__ - -#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */ - -#define IX_ETH_DB_PUBLIC PUBLIC - -/** - * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C) - */ -#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1))) - -/** - * @def IX_ETH_DB_NPE_TO_PORT_ID(npe) - * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1))) - -/* temporary define - won't work for Azusa */ -#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4) -#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4)) - -/** - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * @brief The size of the MAC address - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief Number of QoS priorities defined by IEEE802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) - -/** - * @enum IxEthDBStatus - * @brief Ethernet Database API return values - */ -typedef enum /* IxEthDBStatus */ -{ - IX_ETH_DB_SUCCESS = IX_SUCCESS, /**< Success */ - IX_ETH_DB_FAIL = IX_FAIL, /**< Failure */ - IX_ETH_DB_INVALID_PORT, /**< Invalid port */ - IX_ETH_DB_PORT_UNINITIALIZED, /**< Port not initialized */ - IX_ETH_DB_MAC_UNINITIALIZED, /**< MAC not initialized */ - IX_ETH_DB_INVALID_ARG, /**< Invalid argument */ - IX_ETH_DB_NO_SUCH_ADDR, /**< Address not found for search or delete operations */ - IX_ETH_DB_NOMEM, /**< Learning database memory full */ - IX_ETH_DB_BUSY, /**< Learning database cannot complete operation, access temporarily blocked */ - IX_ETH_DB_END, /**< Database browser passed the end of the record set */ - IX_ETH_DB_INVALID_VLAN, /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */ - IX_ETH_DB_INVALID_PRIORITY, /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */ - IX_ETH_DB_NO_PERMISSION, /**< No permission for attempted operation */ - IX_ETH_DB_FEATURE_UNAVAILABLE, /**< Feature not available (or not enabled) */ - IX_ETH_DB_INVALID_KEY, /**< Invalid search key */ - IX_ETH_DB_INVALID_RECORD_TYPE /**< Invalid record type */ -} IxEthDBStatus; - -/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */ -typedef UINT32 IxEthDBVlanId; - -/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */ -typedef UINT32 IxEthDBVlanTag; - -/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */ -typedef UINT32 IxEthDBPriority; - -/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */ -typedef UINT8 IxEthDBPriorityTable[8]; - -/** @brief A 4096 bit array used to map the complete VLAN ID range */ -typedef UINT8 IxEthDBVlanSet[512]; - -#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF) -#define IX_ETH_DB_802_1Q_QOS_MASK (0x7) - -#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE) - -/** - * @def IX_ETH_DB_SET_VLAN_ID - * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID - * - * This macro is used to change the VLAN ID in a 802.1Q tag. - * - * Example: - * - * tag = IX_ETH_DB_SET_VLAN_ID(tag, 32) - * - * inserts the VLAN ID "32" in the given tag. - */ -#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK)) - -/** -* @def IX_ETH_DB_GET_VLAN_ID -* @brief returns the VLAN ID from the given 802.1Q tag -*/ -#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK) - -#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK) - -#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13)) - -#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_IEEE802_1Q_VLAN_TPID (0x8100) - -typedef enum -{ - IX_ETH_DB_UNTAGGED_FRAMES = 0x1, /**< Accepts untagged frames */ - IX_ETH_DB_VLAN_TAGGED_FRAMES = 0x2, /**< Accepts tagged frames */ - IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */ - IX_ETH_DB_ACCEPT_ALL_FRAMES = - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */ -} IxEthDBFrameFilter; - -typedef enum -{ - IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */ - IX_ETH_DB_ADD_TAG = 0x2, /**< Add default port VLAN tag */ - IX_ETH_DB_REMOVE_TAG = 0x3 /**< Remove VLAN tag from frame */ -} IxEthDBTaggingAction; - -typedef enum -{ - IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1, /**< Firewall operates in white-list mode (MAC address based admission) */ - IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2 /**< Firewall operates in black-list mode (MAC address based blocking) */ -} IxEthDBFirewallMode; - -typedef enum -{ - IX_ETH_DB_FILTERING_RECORD = 0x01, /**< - *
Filtering record
MAC address static/dynamic type age - *
- */ - IX_ETH_DB_FILTERING_VLAN_RECORD = 0x02, /**< - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag - *
- */ - IX_ETH_DB_WIFI_RECORD = 0x04, /**< - *
WiFi header conversion record
MAC address optional gateway MAC address - *
- */ - IX_ETH_DB_FIREWALL_RECORD = 0x08, /**< - *
Firewall record
MAC address - *
- */ - IX_ETH_DB_GATEWAY_RECORD = 0x10, /**< For internal use only */ - IX_ETH_DB_MAX_RECORD_TYPE_INDEX = 0x10, /**< For internal use only */ - IX_ETH_DB_NO_RECORD_TYPE = 0, /**< None of the registered record types */ - IX_ETH_DB_ALL_FILTERING_RECORDS = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */ - IX_ETH_DB_ALL_RECORD_TYPES = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | - IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */ -} IxEthDBRecordType; - -typedef enum -{ - IX_ETH_DB_LEARNING = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */ - IX_ETH_DB_FILTERING = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */ - IX_ETH_DB_VLAN_QOS = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */ - IX_ETH_DB_FIREWALL = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */ - IX_ETH_DB_SPANNING_TREE_PROTOCOL = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */ - IX_ETH_DB_WIFI_HEADER_CONVERSION = 0x20 /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */ -} IxEthDBFeature; - -typedef UINT32 IxEthDBProperty; /**< Property ID type */ - -typedef enum -{ - IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */ - IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */ - IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */ - IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */ -} IxEthDBPropertyType; - -/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY (0x01) /**< Property identifying number the supported number of traffic classes */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10) /**< Rx queue assigned to traffic class 0 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11) /**< Rx queue assigned to traffic class 1 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12) /**< Rx queue assigned to traffic class 2 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13) /**< Rx queue assigned to traffic class 3 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14) /**< Rx queue assigned to traffic class 4 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15) /**< Rx queue assigned to traffic class 5 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16) /**< Rx queue assigned to traffic class 6 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17) /**< Rx queue assigned to traffic class 7 */ - -/* private property used by EthAcc to indicate queue configuration complete */ -#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18) - -/** - * - * @brief The IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * - * @note The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; -} IxEthDBMacAddr; - -/** - * @ingroup IxEthDB - * - * @brief Definition of an IXP400 port. - */ -typedef UINT32 IxEthDBPortId; - -/** - * @ingroup IxEthDB - * - * @brief Port dependency map definition - */ -typedef UINT8 IxEthDBPortMap[32]; - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBInit(void) - * - * @brief Initializes the Ethernet learning/filtering database - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUnload(void) - * - * @brief Stops and prepares the EthDB component for unloading. - * - * @retval IX_ETH_DB_SUCCESS de-initialization was successful - * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first - * @retval IX_ETH_DB_FAIL de-initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBPortInit(IxEthDBPortId portID) - * - * @brief Initializes a port - * - * This function is called automatically by the Ethernet Access - * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the two Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) - * - * @brief Enables a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on - * - * @retval IX_ETH_DB_SUCCESS if enabling is successful - * @retval IX_ETH_DB_FAIL if the enabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was - * not initialized (only for Ethernet NPEs) - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events - * for Ethernet NPEs - * - * @see ixEthDBPortAddressSet - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) - * - * @brief Disables processing on a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE. - * After Ethernet NPEs are disabled they are stopped therefore - * when re-enabled they need to be reset, downloaded with microcode and started. - * For learning to restart working the user needs to call again - * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet - * with the respective port MAC address. - * Residual MAC addresses learnt before the port was disabled are deleted as soon - * as the port is disabled. This only applies to dynamic (learnt) entries, static - * entries do not dissapear when the port is disabled. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on - * - * @retval IX_ETH_DB_SUCCESS if disabling is successful - * @retval IX_ETH_DB_FAIL if the disabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @note calling this function multiple times after the first time completed successfully - * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Sets the port MAC address - * - * This function is to be called from the Ethernet Access component top-level - * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port - * until its MAC address has been set. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set - * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address - * - * @retval IX_ETH_DB_SUCCESS MAC address was set successfully - * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure - * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE - * - * @see IxEthDBPortDefs.h for port definitions - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) - * - * @brief Set the maximum frame size supported on the given port ID - * - * This functions set the maximum frame size supported on a specific port ID - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to configure - * @param maximumFrameSize UINT32 [in] - maximum frame size to configure - * - * @retval IX_ETH_DB_SUCCESS the port is configured - * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range - * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note - * This maximum frame size is used to filter the frames based on their - * destination addresses and the capabilities of the destination port. - * The mximum value that can be set for a NPE port is 16320. - * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a static MAC address - * - * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging. - * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address - * - * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal - * aging function, if aging is enabled on its port. - * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address entry from the Ethernet learning/filtering database - * - * @param macAddr IxEthDBMacAddr [in] - MAC address to remove - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database) - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID - * - * This functions searches the database for a specific port ID and MAC address. Both the port ID - * and the MAC address have to match in order for the record to be reported as found. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to search for - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search) - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the filtering database for a MAC address, return the port ID and reset the record age - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record and resets the entry age to 0, if found. - * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the MAC address was found - * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_MAINTENANCE_TIME - * - * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of - * IX_ETH_DB_MAINTENANCE_TIME - * - */ -#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */ - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME - * - * @brief The define specifies the filtering database age entry time. Static entries older than - * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed. - * - */ -#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */ - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) - * - * @brief Disable the aging function for a specific port - * - * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS aging disabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) - * - * @brief Enable the aging function for a specific port - * - * Enables the aging of dynamic MAC address entries stored in the learning/filtering database - * - * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on - * - * @retval IX_ETH_DB_SUCCESS aging enabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBDatabaseMaintenance(void) - * - * @brief Performs a maintenance operation on the Ethernet learning/filtering database - * - * In order to perform a database maintenance this function must be called every - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is - * enabled or not. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function call will be ignored if the learning feature is disabled - */ -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) - * - * @brief This function displays the Mac Ethernet MAC address filtering tables. - * - * It displays the MAC address, port ID, entry type (dynamic/static),and age for - * the given port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBFilteringDatabaseShowAll(void) - * - * @brief Displays the MAC address recorded in the filtering database for all registered - * ports (see IxEthDBPortDefs.h), grouped by port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval void - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) - * - * @brief This function displays per port database records, given a record type filter - * - * The supported record type filters are: - * - * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic) - * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class) - * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records - * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID) - * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list) - * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types - * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed) - * - * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status, - * aging enabled status, group membership and maximum frame size. - * - * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information - * will be displayed for all the ports (grouped by port) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Sets the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included) - * - * This function is used to share filtering information between ports. - * By adding a port into another port's dependency map the target port - * filtering data will import the filtering data from the port it depends on. - * Any changes to filtering data for a port - such as adding, updating or removing records - - * will trigger updates in the filtering information for all the ports depending on - * on the updated port. - * - * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering - * information for port 0 will also include the filtering information from ports 2 and 3. - * Adding a record to port 2 will also trigger an update not only on port 2 but also on - * port 0. - * - * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the - * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding - * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4. - * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically - * cleared by the function). - * - * By default, each port has a dependency port map consisting only of itself, i.e. - * - * @verbatim - IxEthDBPortMap portMap; - - // clear all ports from port map - memset(portMap, 0, sizeof (portMap)); - - // include portID in port map - portMap[portID / 8] = 1 << (portID % 8); - @endverbatim - * - * - Reentrant - no - * - ISR Callable - no - * - * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates - * of filtering information. Setting dependency maps for user-defined ports is not an error - * but will have no actual effect. - * - * @note Including a port in its own dependency map is not compulsory, however note that - * in this case updating the port will not trigger an update on the port itself, which - * might not be the intended behavior - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Retrieves the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap location where the port dependency map is to be copied - * - * This function will copy the port dependency map to a user specified location. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) - * - * @brief Sets the default 802.1Q VLAN tag for a given port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to - * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag - * - * The tag format has 16 bits and it is defined in the IEEE802.1Q specification. - * This tag will be used for tagging untagged frames (if enabled) and classifying - * unexpedited traffic into an internal traffic class (using the user priority field). - * - * - *
802.1Q tag format
3 bits 1 bit 12 bits - *
user priority CFI VID - *
- * - * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines - * the operation for these 3 user priority bits - * - * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for - * compatibility reason between Ethernet type network and Token Ring type network. If a frame received - * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port. - * - * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q. - * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0 - * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN - * configurations are 4,094. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - * - * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN - * @note the value of the cannonical frame indicator (CFI) field is ignored, the - * field being used only in frame tagging operations - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from - * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) - * - * @brief Sets the 802.1Q VLAN tag for a database record - * - * @param macAddr MAC address - * @param vlanTag 802.1Q VLAN tag - * - * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see below). - * - * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records. - * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically - * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never - * revert to a non-VLAN type (unless deleted and re-added). - * - * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by - * this function. - * - * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the - * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification - * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address - * (contained in the ixp_ne_src_mac field of the buffer header). - * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag - * in the ixp_ne_vlan_tci field of the buffer header. This way the NPE will inspect the Egress tagging - * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is - * allowed. Additionally, Egress tagging can be forced by setting the ixp_ne_tx_flags.tag_over and - * ixp_ne_tx_flags.tag_mode flags in the buffer header. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function will not add a filtering record, it can only be used to update an existing one - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address - * - * @param macAddr MAC address - * @param vlanTag location to write the record 802.1Q VLAN tag to - * - * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records - * - * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet). - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or vlanTag pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Adds a VLAN ID to a port's VLAN membership table - * - * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified - * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID is always in its own membership table, hence there - * is no need to explicitly add it using this function (although it is not an error - * to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Adds a VLAN ID range to a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be added to the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames with - * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this - * function will behave as @ref ixEthDBPortVlanMembershipAdd - * - * @note A port's default VLAN ID is always in its own membership table, hence there is no need - * to explicitly add it using this function (although it is not an error to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Removes a VLAN ID from a port's VLAN membership table - * - * Frames tagged with a VLAN ID which is not in a port's VLAN membership table - * will be discarded by the frame filter, if Ingress membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (vlanID was set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID cannot be removed from the port's membership - * table; attempting it will return IX_ETH_DB_NO_PERMISSION - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Removes a VLAN ID range from a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be removed from the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames - * with VLAN IDs in the range will be discarded by the frame filter, if Ingress - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case - * function will behave as @ref ixEthDBPortVlanMembershipRemove - * - * @note If the given range overlaps the default port VLAN ID this function - * will remove all the VLAN IDs in the range except for the port VLAN ID from its - * own membership table. This situation will be silently dealt with (no error message - * will be returned) as long as the range contains more than one value (i.e. at least - * one other value, apart from the default port VLAN ID). If the function is called - * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the - * function will infer that an attempt was specifically made to remove the default port - * VLAN ID from the port membership table, in which case the return value will be - * IX_ETH_DB_NO_PERMISSION. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets a port's VLAN membership table - * - * Sets a port's VLAN membership table from a complete VLAN table containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit must be set if bit 0 is set. - * - * The bit at index 4095 is reserved and should never be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to - * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves a port's VLAN membership table - * - * Retrieves the complete VLAN membership table from a port, containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit will be set if bit 0 is set. - * - * The bit at index 4095 is reserved and will not be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from - * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be - * written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) - * - * @brief Sets a port's acceptable frame type filter - * - * The acceptable frame type is one (or a combination) of the following values: - * - IX_ETH_DB_ACCEPT_ALL_FRAMES - accepts all the frames - * - IX_ETH_DB_UNTAGGED_FRAMES - accepts untagged frames - * - IX_ETH_DB_VLAN_TAGGED_FRAMES - accepts tagged frames - * - IX_ETH_DB_PRIORITY_TAGGED_FRAMES - accepts tagged frames with VLAN ID set to 0 (no VLAN membership) - * - * Except for using the exact values given above only the following combinations are valid: - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES - * - * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent - * to IX_ETH_DB_ACCEPT_ALL_FRAMES. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES - * - * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally - * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the - * VLAN membership list to include only VLAN ID 0; the membership list will need - * to be restored manually to an appropriate value if the acceptable frame type - * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so - * will filter all VLAN traffic bar frames tagged with VLAN ID 0 - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to - * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) - * - * @brief Retrieves a port's acceptable frame type filter - * - * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from - * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frameFilter pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Sets a port's priority mapping table - * - * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal - * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be - * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest). - * If a custom priority mapping table is not specified using this function the following - * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to - * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table - * - * @note The provided table will be copied into internal data structures in EthDB and - * can be deallocated by the called after this function has completed its execution, if - * so desired - * - * @warning The number of available traffic classes differs depending on the NPE images - * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of - * traffic classes. Note that specifiying a traffic class in the priority map which exceeds - * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no - * priority will be remapped. - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds - * the current number of available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Retrieves a port's priority mapping table - * - * The priority mapping table for the given port will be copied in the location - * specified by the caller using "priorityTable" - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from - * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) - * - * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function establishes a mapping between a user (QoS) priority and an internal traffic class. - * The mapping will be saved in the port's priority mapping table. Use this function when not all - * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY userPriority out of range or - * trafficClass is beyond the number of currently available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) - * - * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function retrieves the internal traffic class associated with a QoS (user) priority from a given - * port's priority mapping table. Use this function when not all the QoS priority mappings are - * required (see also @ref ixEthDBPriorityMappingTableGet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_ARG invalid trafficClass pointer argument - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN - * - * This function enables or disables Egress VLAN tagging for the given port and VLAN ID. - * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be - * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format. - * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching - * this VLAN ID will be removed (the frames will be untagged). - * - * VLAN ID 4095 is reserved and should never be used with this function. - * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this - * context to allow the port to send priority-tagged frames or not. - * - * By default, no Egress VLAN tagging is enabled on any port. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and - * false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) - * - * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID - * - * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from - * @param vlanID VLAN [in] - ID whose tagging status is to be extracted - * @param enabled [in] - user-specifed location where the status is copied to; following - * the successfull execution of this function the value will be true if Egress VLAN - * tagging is enabled for the given port and VLAN ID, and false otherwise - * - * - Reentrant - no - * - ISR Callable - no - * - * @see ixEthDBEgressVlanEntryTaggingEnabledGet - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_INVALID_ARG invalid enabled argument pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range - * - * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the - * difference that it can manipulate the Egress tagging status on multiple VLAN IDs, - * defined by a contiguous range. Note that both limits in the range are explicitly - * included in the execution of this function. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range, - * and false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax - * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION. - * However, this can be circumvented, should the user specifically desire this, by either using a - * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets the complete Egress VLAN tagging table for a port - * - * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port - * covering the entire VLAN ID range (0..4094). The vlanSet parameter is a 4096 - * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID. - * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted - * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag. - * - * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged - * frames. - * - * Bit 4095 is reserved and should never be set (it will be ignored if set). - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set - * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @warning This function will automatically add the default port VLAN ID to the Egress tagging table - * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to - * prevent tagging on the default port VLAN ID if the default behavior is not intended. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves the complete Egress VLAN tagging table from a port - * - * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified - * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position - * in the array) is enabled (the bit is set) or not (the bit is unset). - * - * Bit 4095 is reserved and should not be set (it will be ignored if set). - * - * @see ixEthDBEgressVlanTaggingEnabledSet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved - * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have - * room to store 4096 bits (512 bytes) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) - * - * @brief Sets the Ingress VLAN tagging behavior for a port - * - * A port's Ingress tagging behavior is controlled by the taggingAction parameter, - * which can take one of the following values: - * - * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag) - * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID - * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) - * - * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables port ID extraction - * - * This feature can be used in the situation when a multi-port device (e.g. a switch) - * is connected to an IXP4xx port and the device can provide incoming frame port - * identification by tagging the TPID field in the Ethernet frame. Enabling - * port extraction will instruct the NPE to copy the TPID field from the frame and - * place it in the ixp_ne_src_port of the ixp_buf header. In addition, - * the NPE restores the TPID field to 0. - * - * If the frame is not tagged the NPE will fill the ixp_ne_src_port with the - * port ID of the MII interface the frame was received from. - * - * The TPID field is the least significant byte of the type/length field, which is - * normally set to 0x8100 for 802.1Q-tagged frames. - * - * This feature is disabled by default. - * - * @param portID ID of the port to configure port ID extraction on - * @param enable true to enable port ID extraction and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) - * - * @brief Retrieves the feature capability set for a port - * - * This function retrieves the feature capability set for a port or the common capabilities shared between all - * the ports, writing the feature capability set in a user specified location. - * - * The feature capability set will consist of a set formed by OR-ing one or more of the following values: - * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records - * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature - * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes - * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists - * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes - * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data - * - * Note that EthDB provides only the LEARNING feature for non-NPE ports. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for - * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports) - * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid featureSet pointer - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled) - * - * @brief Enables or disables one or more EthDB features - * - * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported - * features) to be enabled or disabled on the selected port (or all the ports). - * - * Note that some features are mutually incompatible: - * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION - * - * Also note that some features require other features to be enabled: - * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING - * - * This function will either enable the entire selected feature set for the selected port (or all the ports), - * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all - * and return an appropriate error message. - * - * The following features are enabled by default (for ports with the respective capability), - * for compatibility reasons with previous versions of CSR: - * - IX_ETH_DB_LEARNING - * - IX_ETH_DB_FILTERING - * - * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable. - * - * Default settings for VLAN, QoS, Firewall and WiFi header conversion features: - * - * VLAN - * - * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior - * of the port is set to be as permissive (it will accept all the frames) and - * non-interferential (it will not change any frames) as possible: - * - the port VLAN ID (VID) is set to 0 - * - the Ingress acceptable frame filter is set to accept all frames - * - the VLAN port membership is set to the complete VLAN range (0 - 4094) - * - the Ingress tagging mode is set to pass-through (will not change frames) - * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094) - * - * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior - * to the settings listed above. Any VLAN settings made by the user are kept. - * - * QoS - * - * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * Firewall - * - * The port firewall is configured by default in black-list mode, and the firewall address table is empty. - * This means the firewall will not filter any frames until the feature is configured and the firewall table is - * downloaded to the NPE. - * - * Spanning Tree - * - * The port is set to STP unblocked mode, therefore it will accept all frames until re-configured. - * - * WiFi header conversion - * - * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this - * feature is configured and the conversion table downloaded to the NPE. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable - * @param enabled BOOL [in] - true to enable the feature and false to disable it - * - * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level; - * when such features are set to disabled using the EthDB API they will be configured in such - * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled - * features cannot be configured or accessed via the EthDB API (except for getting their status). - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features, - * or a feature that depends on another feature which is not present or enabled - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) - * - * @brief Retrieves the availability and status of a feature set - * - * This function returns the availability and status for a feature set. - * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING) - * the "present" and "enabled" return values will be set to true only if all the features in the - * feature set are present and enabled (not only some). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for - * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to - * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG either present or enabled pointer argument is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) - * - * @brief Retrieves the value of a feature property - * - * The EthDB features usually contain feature-specific properties describing or - * controlling how the feature operates. While essential properties (e.g. the - * firewall operating mode) have their own API, secondary properties can be - * retrieved using this function. - * - * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with - * both types of features. - * - * Properties have types associated with them. A descriptor indicating the property - * type is returned in the type argument for convenience. - * - * The currently supported properties and their corresponding features are as follows: - * - * - *
Properties for IX_ETH_DB_VLAN_QOS
Property identifier Property type Property value Read-Only - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY IX_ETH_DB_INTEGER_PROPERTY number of internal traffic classes Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 0 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 1 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 2 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 3 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 4 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 5 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 6 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 7 Yes - *
- * - * @see ixEthDBFeaturePropertySet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved - * @param property @ref IxEthDBProperty [in] - property identifier - * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored - * @param value void [out] - location where the property value will be stored - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, type or value pointer arguments - * @retval IX_ETH_DB_FAIL incorrect property value or unknown error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) - * - * @brief Sets the value of a feature property - * - * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties - * - * The currently supported properties and their corresponding features are as follows: - * - * - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes - * to the number of traffic classes currently in use - * - * Note that this function creates deep copies of the property values; once the function is invoked the client - * can free or reuse the memory area containing the original property value. - * - * Copy behavior for different property types is defined as follows: - * - * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location - * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters - * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location - * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L) - * - * @see ixEthDBFeaturePropertySet - * - * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use; - * do not attempt to set this property directly - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set - * @param property @ref IxEthDBProperty [in] - property identifier - * @param value void [in] - location where the property value is to be copied from - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, value pointer, or invalid property value - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) - * - * @brief Deletes a set of record types from the Ethernet Database - * - * This function deletes all the records of certain types (specified in the recordType filter) - * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID - * to indicate that the specified record types should be deleted for all the ports. - * - * The record type filter can be an ORed combination of the following types: - * - * Record types - * - IX_ETH_DB_FILTERING_RECORD - * - *
Filtering record
MAC address static/dynamic type age
- * - * - IX_ETH_DB_FILTERING_VLAN_RECORD - * - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag
- * - * - IX_ETH_DB_WIFI_RECORD - * - *
WiFi header conversion record
MAC address optional gateway MAC address
- * - * - IX_ETH_DB_FIREWALL_RECORD - * - *
Firewall record
MAC address
- * - IX_ETH_DB_ALL_RECORD_TYPES - * - * Any combination of the above types is valid e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD), - * - * although some might be redundant (it is not an error to do so) e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param recordType @ref IxEthDBRecordType [in] - record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid recordType filter - * - * @note If the record type filter contains any unrecognized value (hence the - * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame - * header conversion - * - * Frame header conversion is controlled by the set of MAC addresses - * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd. - * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet, - * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet. - * - * Note that adding the same MAC address twice will not return an error - * (but will not accomplish anything either), while re-adding a record previously added - * as an "Access Point to Access Point" will migrate the record to the "Access Point - * to Station" type. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) - * - * @brief Adds an "Access Point to Access Point" record to the database - * - * @see ixEthDBWiFiStationEntryAdd - * - * Note that adding the same MAC address twice will simply overwrite the previously - * defined gateway MAC address value in the same record, if the record was previously of the - * "Access Point to Access Point" type. - * - * Re-adding a MAC address as "Access Point to Access Point", which was previously added as - * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and - * record the gateway MAC address. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or gatewayMacAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a WiFi station record - * - * This function removes both types of WiFi records ("Access Point to Station" and - * "Access Point to Access Point"). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC address table for 802.3 => 802.11 frame header - * conversion to the NPE - * - * Note that the frame conversion MAC address table must be individually downloaded - * to each NPE for which the frame header conversion feature is enabled (i.e. it - * is not possible to specify IX_ETH_DB_ALL_PORTS). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) - * - * @brief Sets the GlobalFrameControl field - * - * The GlobalFrameControl field is a 2-byte value inserted in the Frame Control - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param frameControl UINT16 [in] - GlobalFrameControl value - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) - * - * @brief Sets the GlobalDurationID field - * - * The GlobalDurationID field is a 2-byte value inserted in the Duration/ID - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param durationID UINT16 [in] - GlobalDurationID field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) - * - * @brief Sets the BBSID field - * - * The BBSID field is a 6-byte value which - * identifies the infrastructure of the service set managed - * by the Access Point having the IXP400 as its processor. The value - * is written in the BBSID field of the 802.11 frame header. - * The BBSID value is the MAC address of the Access Point. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid bbsid pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) - * - * @brief Sets the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) - * - * @brief Retrieves the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid blocked pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) - * - * @brief Sets the firewall mode to use white or black listing - * - * When enabled, the NPE MAC address based firewall support operates in two modes: - * - * - white-list mode (MAC address based admission) - * - mode set to IX_ETH_DB_FIREWALL_WHITE_LIST - * - only packets originating from MAC addresses contained in the firewall address list - * are allowed on the Rx path - * - black-list mode (MAC address based blocking) - * - mode set to IX_ETH_DB_FIREWALL_BLACK_LIST - * - packets originating from MAC addresses contained in the firewall address list - * are discarded - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * @note by default the firewall operates in black-list mode with an empty address - * list, hence it doesn't filter any packets - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_INVALID_ARGUMENT mode argument is not a valid firewall configuration mode - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables invalid MAC address filtering - * - * According to IEEE802 it is illegal for a source address to be a multicast - * or broadcast address. If this feature is enabled the NPE inspects the source - * MAC addresses of incoming frames and discards them if invalid addresses are - * detected. - * - * By default this service is enabled, if the firewall feature is supported by the - * NPE image. - * - * @param portID ID of the port - * @param enable true to enable invalid MAC address filtering and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds a MAC address to the firewall address list - * - * Note that adding the same MAC address twice will not return an error - * but will not actually accomplish anything. - * - * The firewall MAC address list has a limited number of entries; once - * the maximum number of entries has been reached this function will failed - * to add more addresses, returning IX_ETH_DB_NOMEM. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address from the firewall address list - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR address not found - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC firewall table to a port - * - * @param portID ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) - * - * @brief Adds a user-defined field to a database record - * - * This function associates a user-defined field to a database record. - * The user-defined field is passed as a (void *) parameter, hence it can be used - * for any purpose (such as identifying a structure). Retrieving the user-defined field from - * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined - * field for any internal operation and it is not aware of the significance of its contents. The - * field is only stored as a pointer. - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * The user-defined field can be cleared using a NULL field parameter. - * - * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD, - * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD) - * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field void * [in] - user defined field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) - * - * @brief Retrieves a user-defined field from a database record - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * - * If no user-defined field was registered with the specified record then NULL will be written - * at the location specified by field. - * - * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD - * or IX_ETH_DB_FIREWALL_RECORD) - * @param portID ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr MAC address of the record - * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field location to write the user defined field into - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or field pointer arguments - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field); - -/** - * @} - */ - -#endif /* IxEthDB_H */ diff --git a/drivers/net/npe/include/IxEthDBLocks_p.h b/drivers/net/npe/include/IxEthDBLocks_p.h deleted file mode 100644 index 91ab441b26..0000000000 --- a/drivers/net/npe/include/IxEthDBLocks_p.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file IxEthAccDBLocks_p.h - * - * @brief Definition of transaction lock stacks and lock utility macros - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccDBLocks_p_H -#define IxEthAccDBLocks_p_H - -#include "IxOsPrintf.h" - -/* Lock and lock stacks */ -typedef struct -{ - IxOsalFastMutex* locks[MAX_LOCKS]; - UINT32 stackPointer, basePointer; -} LockStack; - -#define TRY_LOCK(mutex) \ - { \ - if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \ - { \ - return IX_ETH_DB_BUSY; \ - } \ - } - - -#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); } - -#define INIT_STACK(stack) \ - { \ - (stack)->basePointer = 0; \ - (stack)->stackPointer = 0; \ - } - -#define PUSH_LOCK(stack, lock) \ - { \ - if ((stack)->stackPointer == MAX_LOCKS) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_NOMEM; \ - } \ - \ - if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \ - { \ - (stack)->locks[(stack)->stackPointer++] = (lock); \ - } \ - else \ - { \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - } - -#define POP_LOCK(stack) \ - { \ - ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \ - } - -#define UNROLL_STACK(stack) \ - { \ - while ((stack)->stackPointer > (stack)->basePointer) \ - { \ - POP_LOCK(stack); \ - } \ - } - -#define SHIFT_STACK(stack) \ - { \ - if ((stack)->basePointer == MAX_LOCKS - 1) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - \ - ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \ - } - -#endif /* IxEthAccDBLocks_p_H */ diff --git a/drivers/net/npe/include/IxEthDBLog_p.h b/drivers/net/npe/include/IxEthDBLog_p.h deleted file mode 100644 index b3576236ff..0000000000 --- a/drivers/net/npe/include/IxEthDBLog_p.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * @file IxEthDBLog_p.h - * - * @brief definitions of log macros and log configuration - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include - -#ifdef IX_UNIT_TEST -#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */ -#else -#define NULL_PRINT_ROUTINE if(0) printf -#endif - -/*************************************************** - * Globals * - ***************************************************/ -/* safe to permanently leave these on */ -#define HAS_ERROR_LOG -#define HAS_ERROR_IRQ_LOG -#define HAS_WARNING_LOG - -/*************************************************** - * Log Configuration * - ***************************************************/ - -/* debug output can be turned on unless specifically - declared as a non-debug build */ -#ifndef NDEBUG - -#undef HAS_EVENTS_TRACE -#undef HAS_EVENTS_VERBOSE_TRACE - -#undef HAS_SUPPORT_TRACE -#undef HAS_SUPPORT_VERBOSE_TRACE - -#undef HAS_NPE_TRACE -#undef HAS_NPE_VERBOSE_TRACE -#undef HAS_DUMP_NPE_TREE - -#undef HAS_UPDATE_TRACE -#undef HAS_UPDATE_VERBOSE_TRACE - -#endif /* NDEBUG */ - - -/*************************************************** - * Log Macros * - ***************************************************/ - -/************** Globals ******************/ - -#ifdef HAS_ERROR_LOG - - #define ERROR_LOG printf - -#else - - #define ERROR_LOG NULL_PRINT_ROUTINE - -#endif - -#ifdef HAS_ERROR_IRQ_LOG - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - -#else - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif - -#ifdef HAS_WARNING_LOG - - #define WARNING_LOG printf - -#else - - #define WARNING_LOG NULL_PRINT_ROUTINE - -#endif - -/************** Events *******************/ - -#ifdef HAS_EVENTS_TRACE - - #define IX_ETH_DB_EVENTS_TRACE printf - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_EVENTS_VERBOSE_TRACE - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_EVENTS_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_EVENTS_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_EVENTS_TRACE */ - -/************** Support *******************/ - -#ifdef HAS_SUPPORT_TRACE - - #define IX_ETH_DB_SUPPORT_TRACE printf - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_SUPPORT_VERBOSE_TRACE - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_SUPPORT_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_SUPPORT_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_SUPPORT_TRACE */ - -/************** NPE Adaptor *******************/ - -#ifdef HAS_NPE_TRACE - - #define IX_ETH_DB_NPE_TRACE printf - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_NPE_VERBOSE_TRACE - - #define IX_ETH_DB_NPE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_NPE_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_NPE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_NPE_TRACE */ - -#ifdef HAS_DUMP_NPE_TREE - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize) - -#else - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */ - -#endif /* HAS_DUMP_NPE_TREE */ - -/************** Port Update *******************/ - -#ifdef HAS_UPDATE_TRACE - - #define IX_ETH_DB_UPDATE_TRACE printf - - #ifdef HAS_UPDATE_VERBOSE_TRACE - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif - -#else /* HAS_UPDATE_VERBOSE_TRACE */ - - #define IX_ETH_DB_UPDATE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - -#endif /* HAS_UPDATE_TRACE */ diff --git a/drivers/net/npe/include/IxEthDBMessages_p.h b/drivers/net/npe/include/IxEthDBMessages_p.h deleted file mode 100644 index 5907fd59e2..0000000000 --- a/drivers/net/npe/include/IxEthDBMessages_p.h +++ /dev/null @@ -1,234 +0,0 @@ -/** - * @file IxEthDBMessages_p.h - * - * @brief Definitions of NPE messages - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDBMessages_p_H -#define IxEthDBMessages_p_H - -#include -#include -#include "IxEthDB_p.h" - -/* events watched by the Eth event processor */ -#define IX_ETH_DB_MIN_EVENT_ID (IX_ETHNPE_EDB_GETMACADDRESSDATABASE) -#define IX_ETH_DB_MAX_EVENT_ID (IX_ETHNPE_PC_SETAPMACTABLE) - -/* macros to fill and extract data from NPE messages - place any endian conversions here */ -#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); } -#define NPE_MSG_ID(msg) ((msg).data[0] >> 24) - -#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \ - message.data[1] = (vlanMembershipSet << 8) | ttiSet; \ - } while (0); - -#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \ - | (portID << 16); \ - \ - message.data[1] = (tpid << 16) | vlanTag; \ - } while (0); - -#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \ - | portID << 16 \ - | filterMode << 2 \ - | tagMode; \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \ - | portID << 16 \ - | classIndex; \ - \ - message.data[1] = trafficClass << 24 \ - | 0x1 << 23 \ - | aqmQueue << 16 \ - | aqmQueue << 4; \ - } while (0); - -#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \ - | portID << 16 \ - | (enable ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - - -#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \ - do { \ - message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \ - | portID << 16 \ - | (blocked ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETBBSID_MSG(message, portID, bbsid) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \ - | portID << 16 \ - | bbsid->macAddress[0] << 8 \ - | bbsid->macAddress[1]; \ - \ - message.data[1] = bbsid->macAddress[2] << 24 \ - | bbsid->macAddress[3] << 16 \ - | bbsid->macAddress[4] << 8 \ - | bbsid->macAddress[5]; \ - } while (0); - -#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \ - do { \ - message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \ - message.data[1] = frameControlDurationID; \ - } while (0); - -#define FILL_SETAPMACTABLE_MSG(message, zone) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \ - | 0 << 8 /* always use index 0 */ \ - | 64; /* 32 entries, 8 bytes each, 4 bytes in a word */ \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \ - do { \ - message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \ - | portID << 16 \ - | (epDelta & 0xFF) << 8 \ - | mode; \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \ - | (epDelta & 0xFF) << 8 \ - | (blockCount & 0xFF); \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \ - do { \ - message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \ - | portID << 16 \ - | ((maxRxFrameSize + 63) / 64) << 8 /* max Rx 64-byte blocks */ \ - | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \ - \ - message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \ - } while (0); - -#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \ - | portID << 16 \ - | macAddress[0] << 8 \ - | macAddress[1]; \ - \ - message.data[1] = macAddress[2] << 24 \ - | macAddress[3] << 16 \ - | macAddress[4] << 8 \ - | macAddress[5]; \ - } while (0); - -/* access to a MAC node in the NPE tree */ -#define NPE_NODE_BYTE(eltNodeAddr, offset) (((UINT8 *) (eltNodeAddr))[offset]) - -/* browsing of the implicit linear binary tree structure of the NPE tree */ -#define LEFT_CHILD_OFFSET(offset) ((offset) << 1) -#define RIGHT_CHILD_OFFSET(offset) (((offset) << 1) + 1) - -#define IX_EDB_FLAGS_ACTIVE (0x2) -#define IX_EDB_FLAGS_VALID (0x1) -#define IX_EDB_FLAGS_RESERVED (0xfc) -#define IX_EDB_FLAGS_INACTIVE_VALID (0x1) - -#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6) -#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET (6) -#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET (1) -#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6) -#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET (2) - -#define IX_EDB_NPE_NODE_VALID(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0) -#define IX_EDB_NPE_NODE_ACTIVE(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0) -#define IX_EDB_NPE_NODE_PORT_ID(address) (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET)) - -/* macros to send messages to the NPEs */ -#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result == IX_SUCCESS) \ - { \ - result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \ - } \ - } \ - else \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen; -#endif - -#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); } - -#endif /* IxEthDBMessages_p_H */ diff --git a/drivers/net/npe/include/IxEthDBPortDefs.h b/drivers/net/npe/include/IxEthDBPortDefs.h deleted file mode 100644 index 9f5e467832..0000000000 --- a/drivers/net/npe/include/IxEthDBPortDefs.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file IxEthDBPortDefs.h - * - * @brief Public definition of the ports and port capabilities - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs) - * - * @brief IXP400 Public definition of the ports and port capabilities - * - * @{ - */ - -#ifndef IxEthDBPortDefs_H -#define IxEthDBPortDefs_H - -/** - * @brief Port types - currently only Ethernet NPEs are recognized as specific types - * All other (user-defined) ports must be specified as IX_ETH_GENERIC - */ -typedef enum -{ - IX_ETH_GENERIC = 0, /**< generic ethernet port */ - IX_ETH_NPE /**< specific Ethernet NPE */ -} IxEthDBPortType; - -/** - * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it - * should manually age entries or not depending on the port capabilities. - * - * Ethernet NPEs have aging capabilities, meaning that they will age the entries - * automatically (by themselves).*/ -typedef enum -{ - IX_ETH_NO_CAPABILITIES = 0, /**< no aging capabilities */ - IX_ETH_ENTRY_AGING = 0x1 /**< aging capabilities present */ -} IxEthDBPortCapability; - -/** - * @brief Port Definition - a structure contains the Port type and capabilities - */ -typedef struct -{ - IxEthDBPortType type; - IxEthDBPortCapability capabilities; -} IxEthDBPortDefinition; - -/** - * @brief Port definitions structure, indexed on the port ID - * @warning Ports 0 and 1 are used by the Ethernet access component therefore - * it is essential to be left untouched. Port 2 here (WAN) is given as - * an example port. The NPE firmware also assumes the NPE B to be - * the port 0 and NPE C to be the port 1. - * - * @note that only 32 ports (0..31) are supported by EthDB - */ -static const IxEthDBPortDefinition ixEthDBPortDefinitions[] = -{ - /* id type capabilities */ - { /* 0 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE B */ - { /* 1 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE C */ - { /* 2 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE A */ - { /* 3 */ IX_ETH_GENERIC, IX_ETH_NO_CAPABILITIES }, /* WAN port */ -}; - -/** - * @def IX_ETH_DB_NUMBER_OF_PORTS - * @brief number of supported ports - */ -#define IX_ETH_DB_NUMBER_OF_PORTS ARRAY_SIZE(ixEthDBPortDefinitions) - -/** - * @def IX_ETH_DB_UNKNOWN_PORT - * @brief definition of an unknown port - */ -#define IX_ETH_DB_UNKNOWN_PORT (0xff) - -/** - * @def IX_ETH_DB_ALL_PORTS - * @brief Special port ID indicating all the ports - * @note This port ID can be used only by a subset of the EthDB API; each - * function specifically mentions whether this is a valid parameter as the port ID - */ -#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1) - -/** - * @def IX_ETH_DB_PORTS_ASSERTION - * @brief catch invalid port definitions (<2) with a - * compile-time assertion resulting in a duplicate case error. - */ -#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }} - -/** - * @def IX_ETH_DB_CHECK_PORT(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized - */ -#define IX_ETH_DB_CHECK_PORT(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - \ - if (!ixEthDBPortInfo[(portID)].enabled) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ -} - -/** - * @def IX_ETH_DB_CHECK_PORT_ALL(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized; - * tolerates the use of IX_ETH_DB_ALL_PORTS - */ -#define IX_ETH_DB_CHECK_PORT_ALL(portID) \ -{ \ - if ((portID) != IX_ETH_DB_ALL_PORTS) \ - IX_ETH_DB_CHECK_PORT(portID) \ -} - -#endif /* IxEthDBPortDefs_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDBQoS.h b/drivers/net/npe/include/IxEthDBQoS.h deleted file mode 100644 index 6276930dc7..0000000000 --- a/drivers/net/npe/include/IxEthDBQoS.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file IxEthDBQoS.h - * - * @brief Public definitions for QoS traffic classes - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions - * - * @brief IXP00 Public definitions for QoS traffic classes - * - * @{ - */ - -#ifndef IxEthDBQoS_H -#define IxEthDBQoS_H - -/** - * @def IX_ETH_DB_QUEUE_UNAVAILABLE - * @brief alias to indicate a queue (traffic class) is not available - */ -#define IX_ETH_DB_QUEUE_UNAVAILABLE (0) - -#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief number of QoS priorities, according to IEEE 802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) -#endif - -/** - * @brief array containing all the supported traffic class configurations - */ -static const -UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = -{ - { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 4, 5, 6, 7, 8, 9, 10, 11 } - /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */ -}; - -/** - * @brief value used to index the NPE A functionality ID in the traffic class definition table - */ -#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX (0) - -/** - * @brief value used to index the traffic class count in the traffic class definition table - */ -#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX (1) - -/** - * @brief value used to index the queue assignment index in the traffic class definition table - */ -#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX (2) - -/** - * @brief traffic class definitions - * - * This array contains the default traffic class definition configuration, - * as well as any special cases dictated by the functionality ID of NPE A. - * - * The default case should not be removed (otherwise the Ethernet - * components will assert a fatal failure on initialization). - */ -static const -UINT8 ixEthDBTrafficClassDefinitions[][3] = -{ - /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */ - { 0x00, 4, 0 }, /* default case - DO NOT REMOVE */ - { 0x04, 4, 1 }, /* NPE A image ID 0.4.0.0 */ - { 0x09, 3, 2 }, /* NPE A image ID 0.9.0.0 */ - { 0x80, 8, 3 }, /* NPE A image ID 10.80.02.0 */ - { 0x81, 8, 3 }, /* NPE A image ID 10.81.02.0 */ - { 0x82, 8, 3 } /* NPE A image ID 10.82.02.0 */ -}; - -/** - * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps - * - * @verbatim - Number of available traffic classes - 1 2 3 4 5 6 7 8 - QoS Priority - 0 0 0 0 1 1 1 1 2 - 1 0 0 0 0 0 0 0 0 - 2 0 0 0 0 0 0 0 1 - 3 0 0 0 1 1 2 2 3 - 4 0 1 1 2 2 3 3 4 - 5 0 1 1 2 3 4 4 5 - 6 0 1 2 3 4 5 5 6 - 7 0 1 2 3 4 5 6 7 - - @endverbatim - */ -static const -UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = - { - { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */ - { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */ - { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */ - { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */ - { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */ - { 2, 0, 1, 3, 4, 5, 6, 7 } /* 8 traffic classes available */ - }; - -#endif /* IxEthDBQoS_H */ - -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h deleted file mode 100644 index ddc10a5789..0000000000 --- a/drivers/net/npe/include/IxEthDB_p.h +++ /dev/null @@ -1,686 +0,0 @@ -/** - * @file IxEthDB_p.h - * - * @brief Private MAC learning API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDB_p_H -#define IxEthDB_p_H - -#include -#include -#include -#include -#include - -#include "IxEthDBMessages_p.h" -#include "IxEthDBLog_p.h" - -#if (CPU==SIMSPARCSOLARIS) - -/* when running unit tests intLock() won't protect the event queue so we lock it manually */ -#define TEST_FIXTURE_LOCK_EVENT_QUEUE { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); } -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); } - -#else - -#define TEST_FIXTURE_LOCK_EVENT_QUEUE /* nothing */ -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */ - -#endif /* #if(CPU==SIMSPARCSOLARIS) */ - -#ifndef IX_UNIT_TEST - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */ -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT /* nothing */ - -#else - -extern int dbAccessCounter; -extern int overflowEvent; - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; } -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT { overflowEvent = 1; } - -#endif - -/* code readability markers */ -#define __mempool__ /* memory pool marker */ -#define __lock__ /* hash write locking marker */ -#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */ -#define __alignment__ /* marker for data used only as alignment zones */ - -/* constants */ -#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */ - -/** - * number of hash table buckets - * it should be at least 8x the predicted number of entries for performance - * each bucket needs 8 bytes - */ -#define NUM_BUCKETS (8192) - -/** - * number of hash table buckets to preload when incrementing bucket iterator - * = two cache lines - */ -#define IX_ETHDB_CACHE_LINE_AHEAD (2) - -#define IX_ETHDB_BUCKETPTR_AHEAD ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - -#define IX_ETHDB_BUCKET_INDEX_MASK (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1) - -/* locks */ -#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */ - -/* learning tree constants */ -#define INITIAL_ELT_SIZE (8) /**< initial byte size of tree (empty unused root size) */ -#define MAX_ELT_SIZE (512) /**< maximum number of entries (includes unused root) */ -#define MAX_GW_SIZE (32) /**< maximum number of gateway entries (including unused root) */ -#define MAX_FW_SIZE (32) /**< maximum number of firewall entries (including unused root) */ -#define ELT_ENTRY_SIZE (8) /**< entry size, in bytes */ -#define ELT_ROOT_OFFSET (ELT_ENTRY_SIZE) /**< tree root offset, in bytes - node preceeding root is unused */ -#define FULL_ELT_BYTE_SIZE (MAX_ELT_SIZE * ELT_ENTRY_SIZE) /**< full size of tree, in bytes, including unused root */ -#define FULL_GW_BYTE_SIZE (MAX_GW_SIZE * ELT_ENTRY_SIZE) /**< full size of gateway list, in bytes, including unused root */ -#define FULL_FW_BYTE_SIZE (MAX_FW_SIZE * ELT_ENTRY_SIZE) /**< full size of firewall table, in bytes, including unused root */ - -/* maximum size of the VLAN table: - * 4096 bits (one per VLAN) - * 8 bits in one byte - * interleaved VLAN membership and VLAN TTI (*2) */ -#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2) - -/* upper 9 bits used as set index, lower 3 bits as byte index */ -#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3) -#define VLAN_SET_MASK(vlanID) (0x7 - ((vlanID) & 0x7)) - -/* Update zone definitions */ -#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */ - -/* check the above value, we rely on 4k */ -#if NPE_TREE_MEM_SIZE != 4096 - #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes! -#endif - -/* Size Filtering limits (Jumbo frame filtering) */ -#define IX_ETHDB_MAX_FRAME_SIZE 65535 /* other ports than NPE ports */ -#define IX_ETHDB_MIN_FRAME_SIZE 1 /* other ports than NPE ports */ -#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */ -#define IX_ETHDB_MIN_NPE_FRAME_SIZE 1 /* NPE ports firmware limit */ -#define IX_ETHDB_DEFAULT_FRAME_SIZE 1522 - -/* memory management pool sizes */ - -/* - * Note: - * - * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time. - * It should be large enough to cover all the search trees of all the ports simultaneously. - * - * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses - * possible to be held at any time in all the ports. - * - * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE. - * - * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511 - * entries each plus one PCI NIC holding at most 900 entries. - */ - -#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */ -#define MAC_POOL_SIZE (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */ -#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */ - -/* retry policies */ -#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */ -#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */ -#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */ -#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */ - -/* event management */ -#define EVENT_QUEUE_SIZE (500) /**< size of the sink collecting events from the Message Handler FIFO */ -#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */ - -/* MAC descriptors */ -#define STATIC_ENTRY (true) -#define DYNAMIC_ENTRY (false) - -/* age reset on next maintenance - incrementing by 1 will reset to 0 */ -#define AGE_RESET (0xFFFFFFFF) - -/* dependency maps */ -#define EMPTY_DEPENDENCY_MAP (0) - -/* trees */ -#define RIGHT (1) -#define LEFT (-1) - -/* macros */ -#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ -} - -#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - else \ - { \ - if (!ixEthDBPortInfo[portID].initialized) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ - } \ -} - -/* single NPE check */ -#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \ - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \ - { \ - WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \ - \ - return IX_ETH_DB_INVALID_PORT; \ - } - -/* feature check */ -#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \ - if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \ - { \ - return IX_ETH_DB_FEATURE_UNAVAILABLE; \ - } - -/* busy retrying */ -#define BUSY_RETRY(functionCall) \ - { \ - UINT32 retries = 0; \ - IxEthDBStatus br_result; \ - \ - while ((br_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \ - { \ - UINT32 retries = 0; \ - \ - while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -/* iterators */ -#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL) - -/* dependency port maps */ - -/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */ - -/* gives an empty dependency map */ -#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; } - -#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }} - -/** - * gives a map consisting only of 'portID' - */ -#define SET_DEPENDENCY_MAP(map, portID) {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);} - -/** - * gives a map resulting from joining map1 and map2 - */ -#define JOIN_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; } - -/** - * gives the map resulting from joining portID and map - */ -#define JOIN_PORT_TO_MAP(map, portID) { map[portID >> 3] |= 1 << (portID & 0x7); } - -/** - * gives the map resulting from excluding portID from map - */ -#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); } - -/** - * returns true if map1 is a subset of map2 and false otherwise - */ -#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; } - -/** - * returns true is portID is part of map and false otherwise - */ -#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0) - -/** - * returns the difference between map1 and map2 (ports included in map1 and not included in map2) - */ -#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); } - -/** - * returns true if the maps collide (have at least one port in common) and false otherwise - */ -#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; } - -/* size (number of ports) of a dependency map */ -#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }} - -/* copy map2 into map1 */ -#define COPY_DEPENDENCY_MAP(map1, map2) { memcpy (map1, map2, sizeof (map1)); } - -/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */ -#define MAX_PORT_SIZE (0xFF) -#define MAX_PORT_NUMBER (0xFF) - -#define IX_ETH_DB_CHECK_REFERENCE(ptr) { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } } -#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } } - -/* event queue macros */ -#define EVENT_QUEUE_WRAP(offset) ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset)) - -#define CAN_ENQUEUE(eventQueuePtr) ((eventQueuePtr)->length < EVENT_QUEUE_SIZE) - -#define QUEUE_HEAD(eventQueuePtr) (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)]) - -#define QUEUE_TAIL(eventQueuePtr) (&(eventQueuePtr)->queue[(eventQueuePtr)->base]) - -#define PUSH_UPDATE_QUEUE(eventQueuePtr) { (eventQueuePtr)->length++; } - -#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \ - (eventQueuePtr)->length--; \ - } - -#define RESET_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = 0; \ - (eventQueuePtr)->length = 0; \ - } - -/* node stack macros - used to browse a tree without using a recursive function */ -#define NODE_STACK_INIT(stack) { (stack)->nodeCount = 0; } -#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); } -#define NODE_STACK_POP(stack, node, offset) { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; } -#define NODE_STACK_NONEMPTY(stack) ((stack)->nodeCount != 0) - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -#define LOG_NPE_MSG(msg) \ - do { \ - UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \ - npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \ - npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \ - } while (0); -#else -#define LOG_NPE_MSG() /* nothing */ -#endif - -/* ----------- Data -------------- */ - -/* typedefs */ - -typedef UINT32 (*HashFunction)(void *entity); -typedef BOOL (*MatchFunction)(void *reference, void *entry); -typedef void (*FreeFunction)(void *entry); - -/** - * basic component of a hash table - */ -typedef struct HashNode_t -{ - void *data; /**< specific data */ - struct HashNode_t *next; /**< used for bucket chaining */ - - __mempool__ struct HashNode_t *nextFree; /**< memory pool management */ - - __lock__ IxOsalFastMutex lock; /**< node lock */ -} HashNode; - -/** - * @brief hash table iterator definition - * - * an iterator is an object which can be used - * to browse a hash table - */ -typedef struct -{ - UINT32 bucketIndex; /**< index of the currently iterated bucket */ - HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */ - HashNode *node; /**< reference to the currently iterated node */ -} HashIterator; - -/** - * definition of a MAC descriptor (a database record) - */ - -typedef enum -{ - IX_ETH_DB_WIFI_AP_TO_STA = 0x0, - IX_ETH_DB_WIFI_AP_TO_AP = 0x1 -} IxEthDBWiFiRecordType; - -typedef union -{ - struct - { - UINT32 age; - BOOL staticEntry; /**< true if this address is static (doesn't age) */ - } filteringData; - - struct - { - UINT32 age; - BOOL staticEntry; - UINT32 ieee802_1qTag; - } filteringVlanData; - - struct - { - IxEthDBWiFiRecordType type; /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */ - UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */ - UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved2[2]; - } wifiData; -} IxEthDBRecordData; - -typedef struct MacDescriptor_t -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved1[2]; - - UINT32 portID; - IxEthDBRecordType type; - IxEthDBRecordData recordData; - - /* used for internal operations, such as NPE linearization */ - void *internal; - - /* custom user data */ - void *user; - - __mempool__ struct MacDescriptor_t *nextFree; /**< memory pool management */ - __smartpointer__ UINT32 refCount; /**< smart pointer reference counter */ -} MacDescriptor; - -/** - * hash table definition - */ -typedef struct -{ - HashNode *hashBuckets[NUM_BUCKETS]; - UINT32 numBuckets; - - __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS]; - - HashFunction entryHashFunction; - MatchFunction *matchFunctions; - FreeFunction freeFunction; -} HashTable; - -typedef enum -{ - IX_ETH_DB_MAC_KEY = 1, - IX_ETH_DB_MAC_PORT_KEY = 2, - IX_ETH_DB_MAC_VLAN_KEY = 3, - IX_ETH_DB_MAX_KEY_INDEX = 3 -} IxEthDBSearchKeyType; - -typedef struct MacTreeNode_t -{ - __smartpointer__ MacDescriptor *descriptor; - struct MacTreeNode_t *left, *right; - - __mempool__ struct MacTreeNode_t *nextFree; -} MacTreeNode; - -typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type); - -typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node); - -typedef struct -{ - BOOL updateEnabled; /**< true if updates are enabled for port */ - BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */ - BOOL treeInitialized; /**< true if the NPE has received an initial tree */ - IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */ - void *npeUpdateZone; /**< port update memory zone */ - void *npeGwUpdateZone; /**< port update memory zone for gateways */ - void *vlanUpdateZone; /**< port update memory zone for VLAN tables */ - MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */ - BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */ -} PortUpdateMethod; - -typedef struct -{ - IxEthDBPortId portID; /**< port ID */ - BOOL enabled; /**< true if the port is enabled */ - BOOL agingEnabled; /**< true if aging on this port is enabled */ - BOOL initialized; - IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */ - PortUpdateMethod updateMethod; /**< update method structure */ - BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */ - UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */ - UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */ - - UINT8 bbsid[6]; - __alignment__ UINT8 reserved[2]; - UINT32 frameControlDurationID; /**< Frame Control - Duration/ID WiFi control */ - - IxEthDBVlanTag vlanTag; /**< default VLAN tag for port */ - IxEthDBPriorityTable priorityTable; /**< QoS <=> internal priority mapping */ - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - - UINT32 npeFrameFilter; - UINT32 npeTaggingAction; - - IxEthDBFirewallMode firewallMode; - BOOL srcAddressFilterEnabled; - - BOOL stpBlocked; - - IxEthDBFeature featureCapability; - IxEthDBFeature featureStatus; - - UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT]; - - UINT32 ixEthDBTrafficClassCount; - - UINT32 ixEthDBTrafficClassAvailable; - - - - __lock__ IxOsalMutex npeAckLock; -} PortInfo; - -/* list of port information structures indexed on port Ids */ -extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -typedef enum -{ - IX_ETH_DB_ADD_FILTERING_RECORD = 0xFF0001, - IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002 -} PortEventType; - -typedef struct -{ - UINT32 eventType; - IxEthDBPortId portID; - IxEthDBMacAddr macAddr; - BOOL staticEntry; -} PortEvent; - -typedef struct -{ - PortEvent queue[EVENT_QUEUE_SIZE]; - UINT32 base; - UINT32 length; -} PortEventQueue; - -typedef struct -{ - IxEthDBPortId portID; /**< originating port */ - MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */ - UINT32 addressCount; /**< number of addresses */ -} TreeSyncInfo; - -typedef struct -{ - MacTreeNode *nodes[MAX_ELT_SIZE]; - UINT32 offsets[MAX_ELT_SIZE]; - UINT32 nodeCount; -} MacTreeNodeStack; - -/* Prototypes */ - -/* ----------- Memory management -------------- */ - -IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void); - -IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void); -IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *); - -IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree); -IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void); - -/* Hash Table */ -IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator); - -/* API Support */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); -IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* DB Core functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); - -/* Learning support */ -IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2); -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress); - -/* Port updates */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type); -IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts); -IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void); -IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void); -IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta); - -/* Init/unload */ -IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void); -IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions); -IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void); -IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType); - -/* Event processing */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* NPE adaptor */ -IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize); -IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex); -IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node); - -/* Other public API functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate); - -/* Maximum Tx/Rx public functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize); - -/* VLAN-related */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* Record search */ -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter); - -/* Utilities */ -IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac); -IX_ETH_DB_PUBLIC void showHashInfo(void); -IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void); -IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error); -IX_ETH_DB_PUBLIC int numHashElements(void); -IX_ETH_DB_PUBLIC void zapHashtable(void); -IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value); - -/* Single Eth NPE Check */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId); - -#endif /* IxEthDB_p_H */ - diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h deleted file mode 100644 index 8d7de3d4ce..0000000000 --- a/drivers/net/npe/include/IxEthMii.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * @file IxEthMii.h - * - * @brief this file contains the public API of @ref IxEthMii component - * - * Design notes : - * The main intent of this API is to inplement MII high level fonctionalitoes - * to support the codelets provided with the IXP400 software releases. It - * superceedes previous interfaces provided with @ref IxEThAcc component. - * - * This API has been tested with the PHYs provided with the - * IXP400 development platforms. It may not work for specific Ethernet PHYs - * used on specific boards. - * - * This source code detects and interface the LXT972, LXT973 and KS6995 - * Ethernet PHYs. - * - * This source code should be considered as an example which may need - * to be adapted for different hardware implementations. - * - * It is strongly recommended to use public domain and GPL utilities - * like libmii, mii-diag for MII interface support. - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_H -#define IxEthMii_H - -#include - -/** - * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API - * - * @brief ethMii is a library that does provides access to the - * Ethernet PHYs - * - *@{ - */ - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) - * - * @brief Scan the MDIO bus for PHYs - * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to - * true if a phy is discovered at address n. - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries - * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when - * the indicated number of PHYs is found). - * - * @return IX_STATUS - * - IX_ETH_ACC_SUCCESS - * - IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) - * - * - * @brief Configure a PHY - * Configure a PHY's speed, duplex and autonegotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s - * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex - * @param autonegotiate BOOL [in] - set to true to enable autonegotiation - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr) - * - * - * @brief Enable PHY Loopback in a specific Eth MII port - * - * @note When PHY Loopback is enabled, frames sent out to the PHY from the - * IXP400 will be looped back to the IXP400. They will not be transmitted out - * on the wire. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackEnable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr) - * - * - * @brief Disable PHY Loopback in a specific Eth MII port - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackDisable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyReset(UINT32 phyAddr) - * - * @brief Reset a PHY - * Reset a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); - - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) - * - * @brief Retrieve the current status of a PHY - * Retrieve the link, speed, duplex and autonegotiation status of a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * @param linkUp BOOL [out] - set to true if the link is up - * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s - * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex - * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyShow (UINT32 phyAddr) - * - * - * @brief Display information on a specified PHY - * Display link status, speed, duplex and Auto Negotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr); - -#endif /* ndef IxEthMii_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthMii_p.h b/drivers/net/npe/include/IxEthMii_p.h deleted file mode 100644 index 0c48a6971a..0000000000 --- a/drivers/net/npe/include/IxEthMii_p.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * @file IxEthMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_p_H -#define IxEthMii_p_H - - -/* MII definitions - these have been verified against the LXT971 and - LXT972 PHYs*/ - -#define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */ - -#define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -#define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/ - - -/* MII control register bit */ - -#define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */ -#define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */ -#define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */ -#define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */ -#define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */ -#define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */ -#define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */ -#define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ -#define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ -#define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */ -#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */ -#define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */ - -/* MII Status register bit definitions */ - -#define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */ -#define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */ -#define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */ -#define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */ -#define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */ -#define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */ -#define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */ -#define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */ -#define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */ -#define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */ -#define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */ - - -/* LXT971/2 Status 2 register bit definitions */ -#define IX_ETH_MII_SR2_100 0x4000 -#define IX_ETH_MII_SR2_TX 0x2000 -#define IX_ETH_MII_SR2_RX 0x1000 -#define IX_ETH_MII_SR2_COL 0x0800 -#define IX_ETH_MII_SR2_LINK 0x0400 -#define IX_ETH_MII_SR2_FD 0x0200 -#define IX_ETH_MII_SR2_AUTO 0x0100 -#define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080 -#define IX_ETH_MII_SR2_POLARITY 0x0020 -#define IX_ETH_MII_SR2_PAUSE 0x0010 -#define IX_ETH_MII_SR2_ERROR 0x0008 - -/* MII Link Code word bit definitions */ - -#define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */ -#define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */ -#define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */ - -/* MII Next Page bit definitions */ - -#define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */ -#define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */ -#define IX_ETH_MII_NP_MSG 0x2000 /* message page */ -#define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */ -#define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */ - -/* MII Expansion Register bit definitions */ - -#define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */ -#define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */ -#define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */ -#define IX_ETH_MII_EXP_PR 0x0002 /* full page received */ -#define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */ - -/* technology ability field bit definitions */ - -#define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */ -#define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */ -#define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */ -#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */ - -#define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */ -#define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */ -#define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK -#define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */ - -#define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */ -#define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */ -#define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */ - -/* Definitions for MII access routines*/ - -#define IX_ETH_MII_GO BIT(31) -#define IX_ETH_MII_WRITE BIT(26) -#define IX_ETH_MII_TIMEOUT_10TH_SECS (5) -#define IX_ETH_MII_10TH_SEC_IN_MILLIS (100) -#define IX_ETH_MII_READ_FAIL BIT(31) - -/* When we reset the PHY we delay for 2 seconds to allow the reset to - complete*/ -#define IX_ETH_MII_RESET_DELAY_MS (2000) -#define IX_ETH_MII_RESET_POLL_MS (50) - -#define IX_ETH_MII_REG_SHL 16 -#define IX_ETH_MII_ADDR_SHL 21 - -/* supported PHYs */ -#define IX_ETH_MII_LXT971_PHY_ID 0x001378E0 -#define IX_ETH_MII_LXT972_PHY_ID 0x001378E2 -#define IX_ETH_MII_LXT973_PHY_ID 0x00137A10 -#define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11 -#define IX_ETH_MII_KS8995_PHY_ID 0x00221450 -#define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF - - -#define IX_ETH_MII_INVALID_PHY_ID 0x00000000 -#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthNpe.h b/drivers/net/npe/include/IxEthNpe.h deleted file mode 100644 index 20bfa76c36..0000000000 --- a/drivers/net/npe/include/IxEthNpe.h +++ /dev/null @@ -1,671 +0,0 @@ -#ifndef __doxygen_HIDE /* This file is not part of the API */ - -/** - * @file IxEthNpe.h - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API - * - * @brief Contains the API for Ethernet NPE. - * - * All messages given to NPE, get back an acknowledgment. The acknowledgment - * is identical to the message sent to the NPE (except for NPE_GETSTATUS message). - * - * @{ - */ - - -/*-------------------------------------------------------------------------- - * APB Message IDs - XScale->NPE - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS - * - * @brief Request from the XScale client for the NPE to return the firmware - * version of the currently executing image. - * - * Acknowledgment message id is same as the request message id. - * NPE returns the firmware version ID to XScale. - */ -#define IX_ETHNPE_NPE_GETSTATUS 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS - * - * @brief Request from the XScale client for the NPE to set the Ethernet - * port's port ID and MAC address. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE - * - * @brief Request from XScale client to the NPE requesting upload of - * Ethernet Filtering Database or Header Conversion Database from NPE's - * data memory to XScale accessible SDRAM. - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE - * - * @brief Request from XScale client to the NPE requesting download of - * Ethernet Filtering Database or Header Conversion Database from SDRAM - * to the NPE's datamemory. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE 0x03 - -/** - * @def IX_ETHNPE_GETSTATS - * - * @brief Request from the XScale client for the current MAC port statistics - * data to be written to the (empty) statistics structure and the specified - * location in externa memory. - */ -#define IX_ETHNPE_GETSTATS 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS - * - * @brief Request from the XScale client to the NPE to reset all of its internal - * MAC port statistics state variables. - * - * As a side effect, this message entails an implicit request that the NPE - * write the current MAC port statistics into the MAC statistics structure - * at the specified location in external memory. - */ -#define IX_ETHNPE_RESETSTATS 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS - * - * @brief Request from the XScale client to the NPE to configure maximum framelengths - * and block sizes in receive and transmit direction. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE - * - * @brief Request from the XScale client to the NPE to configure VLAN frame type - * filtering and VLAN the tagging mode for the receiver. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID - * - * @brief Request from the XScale client to the NPE to set receiver's default - * VLAN tag (PVID)and internal traffic class. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for 8 consecutive VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for a range of VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY - * - * @brief Request from the XScale client to the NPE to map a user priority - * to QoS class and an AQM queue number. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE - * - * @brief Request from the XScale client to the NPE to enable or disable - * portID extraction from VLAN-tagged frames for the specified port. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE - * - * @brief Request from the XScale client to the NPE to block or unblock - * forwarding for spanning tree BPDUs. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE - * - * @brief Request from the XScale client to the NPE to configure firewall - * services modes of operation and/or download Ethernet Firewall Database from - * SDRAM to NPE. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID - * - * @brief Request from the XScale client to the NPE to set global frame control - * and duration/ID field for the 802.3 to 802.11 protocol header conversion - * service. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID - * - * @brief Request from the XScale client to the NPE to set global BBSID field - * value for the 802.3 to 802.11 protocol header conversion service. - */ -#define IX_ETHNPE_PC_SETBBSID 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE - * - * @brief Request from the XScale client to the NPE to update a block/section/ - * range of the AP MAC Address Table. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE - * - * @brief Turn on or off the NPE frame loopback. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE (0x12) - -/*-------------------------------------------------------------------------- - * APB Message IDs - NPE->XScale - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version - * id is returned in the message. - */ -#define IX_ETHNPE_NPE_GETSTATUS_ACK 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK 0x03 - -/** - * @def IX_ETHNPE_GETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_GETSTATS message. - */ -#define IX_ETHNPE_GETSTATS_ACK 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message. - */ -#define IX_ETHNPE_RESETSTATS_ACK 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID message. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message. - */ -#define IX_ETHNPE_PC_SETBBSID_ACK 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE_ACK 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE_ACK (0x12) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field boundary definitions - *------------------------------------------------------------------------*/ - -/** - * @def MASK(hi,lo) - * - * @brief Macro for mask - */ -#define MASK(hi,lo) (((1 << (1 + ((hi) - (lo)))) - 1) << (lo)) - -/** - * @def BITS(x,hi,lo) - * - * @brief Macro for bits - */ -#define BITS(x,hi,lo) (((x) & MASK(hi,lo)) >> (lo)) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK - * - * @brief QMgr Queue LENGTH field mask - */ -#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK 0x3fff - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R - * - * @brief QMgr Queue FLAG field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_FLAG_R 20 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK - * - * @brief QMgr Queue FLAG field mask - * - * Multicast bit : BIT(4) - * Broadcast bit : BIT(5) - * IP bit : BIT(6) (linux only) - * - */ -#ifdef __vxworks -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x30 -#else -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x70 -#endif - - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L - * - * @brief QMgr Queue NPE ID field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_L 1 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R - * - * @brief QMgr Queue NPE ID field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L - * - * @brief QMgr Queue Priority field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L 2 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R - * - * @brief QMgr Queue Priority field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L - * - * @brief QMgr Queue Address field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_L 31 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R - * - * @brief QMgr Queue Address field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_R 5 - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field masks - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK - * - * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK - * - * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager - * Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field value extraction macros - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of FreeNet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; - * Set to 1 for entries originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) - * - * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry - * - * 0-5: Assignable (by the XScale client) to any of the physical ports. - * 6: It is reserved - * 7: Indication that the NPE did not find the associated frame's destination MAC address within - * its internal filtering database. - */ -#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \ - IX_ETHNPE_QM_Q_Field_PortID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of RxEnet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) - * - * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry - * - * Priority of the packet (as described in IEEE 802.1D). This field is - * cleared upon return from the Ethernet NPE to the TxEnetDone queue. - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of Queue Manager TxEnet Queue - * Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries - * originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK) - - -/*-------------------------------------------------------------------------- - * NPE limits - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN - * - * @brief Macro to check the minimum length of a rx free buffer - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - * - * @brief Mask to apply to the mbuf length before submitting it to the NPE - * (the NPE handles only rx free mbufs which are multiple of 64) - * - * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) - * - * @brief Round up to get the size necessary to receive without chaining - * the frames which are (size) bytes (the NPE operates by multiple of 64) - * e.g. To receive 1514 bytes frames, the size of the buffers in replenish - * has to be at least (1514+63)&(~63) = 1536 bytes. - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) - * - * @brief Round down to apply to the mbuf length before submitting - * it to the NPE. (the NPE operates by multiple of 64) - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX - * - * @brief maximum mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - * - * @brief default mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522) - -/** - * @def IX_ETHNPE_ACC_LENGTH_OFFSET - * - * @brief Offset of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_LENGTH_OFFSET 16 - -/** - * @def IX_ETHNPE_ACC_PKTLENGTH_MASK - * - * @brief Mask of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff - - -/** - *@} - */ - -#endif /* __doxygen_HIDE */ diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h deleted file mode 100644 index 987b00b562..0000000000 --- a/drivers/net/npe/include/IxFeatureCtrl.h +++ /dev/null @@ -1,718 +0,0 @@ -/** - * @file IxFeatureCtrl.h - * - * @date 30-Jan-2003 - - * @brief This file contains the public API of the IXP400 Feature Control - * component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API - * - * @brief The Public API for the IXP400 Feature Control. - * - * @{ - */ - -#ifndef IXFEATURECTRL_H -#define IXFEATURECTRL_H - -/* - * User defined include files - */ -#include "IxOsal.h" - -/* - * #defines and macros - */ - -/************************************************************* - * The following are IxFeatureCtrlComponentCheck return values. - ************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_DISABLED - * - * @brief Hardware Component is disabled/unavailable. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_ENABLED - * - * @brief Hardware Component is available. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_ENABLED 1 - -/*********************************************************************************** - * Product ID in XScale CP15 - Register 0 - * - It contains information on the maximum XScale Core Frequency and - * Silicon Stepping. - * - XScale Core Frequency Id indicates only the maximum XScale frequency - * achievable and not the running XScale frequency (maybe stepped down). - * - The register is read by using ixFeatureCtrlProductIdRead. - * - Usage example: - * productId = ixFeatureCtrlProductIdRead(); - * if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) == - * IX_FEATURE_CTRL_SILICON_TYPE_A0 ) - * if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) == - * IX_FEATURE_CTRL_XSCALE_FREQ_533 ) - * - * 31 28 27 24 23 20 19 16 15 12 11 9 8 4 3 0 - * -------------------------------------------------------------------------------- - * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id | - * -------------------------------------------------------------------------------- - * - * Maximum Achievable XScale Core Frequency Id : 533MHz - 0x1C - * 400MHz - 0x1D - * 266MHz - 0x1F - * - * THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b> - * - * The above is applicable to IXP42X only. CP15 in IXP46X does not contain any - * Frequency ID. - * - * Si Stepping Id : A - 0x0 - * B - 0x1 - * - * XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0 - * IXP46X - 0x1 - *************************************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_A0 - * - * @brief This is the value of A0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_A0 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_B0 - * - * @brief This is the value of B0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_B0 1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK 0xF - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK (0x7) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET 9 - - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_533 - * - * @brief This is the value of 533MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_533 ((0x1C)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_400 - * - * @brief This is the value of 400MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_400 ((0x1D)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_266 - * - * @brief This is the value of 266MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK - * - * @brief This is the mask of XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_32PHY - * - * @brief Maximum UTOPIA PHY available is 32. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_32PHY 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_16PHY - * - * @brief Maximum UTOPIA PHY available is 16. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_16PHY 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_8PHY - * - * @brief Maximum UTOPIA PHY available to is 8. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_8PHY 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_4PHY - * - * @brief Maximum UTOPIA PHY available to is 4. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_4PHY 0x3 - -#ifdef __ixp46X - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_533FREQ - * - * @brief Maximum frequency available to IXP46x is 533 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_533FREQ 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_667FREQ - * - * @brief Maximum frequency available to IXP46x is 667 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_667FREQ 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_400FREQ - * - * @brief Maximum frequency available to IXP46x is 400 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_400FREQ 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_266FREQ - * - * @brief Maximum frequency available to IXP46x is 266 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_266FREQ 0x3 - -#endif /* __ixp46X */ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE 0x0000 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE 0xffff - -/** - * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component - * - * @ingroup IxFeatureCtrlAPI - * - * @brief This section describes software configuration in access component. The - * configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( ) - * will be used across applicable access component to check the configuration. - * ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration. - * - * @note All software configurations are default to be enabled. - * - * @{ - */ -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED - * - * @brief Software configuration is disabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED - * - * @brief Software configuration is enabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1 - -/** - * Section for enums - **/ - -/** - * @ingroup IxFeatureCtrlBuildDevice - * - * @enum IxFeatureCtrlBuildDevice - * - * @brief Indicates software build type. - * - * Default build type is IXP42X - * - */ -typedef enum -{ - IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /** - * - if(IX_FEATURE_CTRL_COMPONENT_DISABLED != - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0))
- * - if(IX_FEATURE_CTRL_COMPONENT_ENABLED == - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI))
- * - * This function is typically called during component initialization time. - * - * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as - * defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0) - - * - * @return - * - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available - * - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable - */ -PUBLIC IX_STATUS -ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void) - * - * @brief This function will return IXP400 product ID i.e. CP15, - * Register 0. - * - * @return - * - IxFeatureCtrlProductId - the value of product ID. - * - */ -PUBLIC IxFeatureCtrlProductId -ixFeatureCtrlProductIdRead (void) ; - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) - * - * @brief This function checks whether the specified software configuration is - * enabled or disabled. - * - * Usage Example:
- * - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED != - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED == - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - * This function is typically called during access component initialization time. - * - * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * - * @return - * - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled. - * - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled. - */ -PUBLIC IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) - * - * @brief This function enable/disable the specified software configuration. - * - * Usage Example:
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used - * to enable Ethernet Learning Feature
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used - * to disable Ethernet Learning Feature
- * - * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software - * configuration. - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlIxp400SwVersionShow (void) - * - * @brief This function shows the current software release information for IXP400 - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlIxp400SwVersionShow (void); - -#endif /* IXFEATURECTRL_H */ - -/** - * @} defgroup IxFeatureCtrlAPI - */ diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h deleted file mode 100644 index da71c42023..0000000000 --- a/drivers/net/npe/include/IxHssAcc.h +++ /dev/null @@ -1,1292 +0,0 @@ -/** - * @file IxHssAcc.h - * - * @date 07-DEC-2001 - * - * @brief This file contains the public API of the IXP400 HSS Access - * component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API - * - * @brief The public API for the IXP400 HssAccess component - * - * IxHssAcc is the access layer to the HSS packetised and channelised - * services - * - * Design Notes
- *
    - *
  • When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of - * the transmitted data is not preserved. All raw data that is transmitted - * will be received in proper order by the receiver, but the first bit of - * the packet may be seen at any offset within a byte; all subsequent bytes - * will have the same offset for the duration of the packet. The same offset - * also applies to all subsequent packets received on the packet-pipe too. - * (Similar results will occur for data received from remote end.) While - * this behavior will also occur for 56Kbps HDLC mode, the HDLC - * encoding/decoding will preserve the original byte alignment at the - * receiver end. - *
- * - * 56Kbps Packetised Service Bandwidth Limitation
- *
    - *
  • IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate - * for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e. - * it supports 56Kbps packetised service on up to 8 T1 trunks. It does - * not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per - * HSS port) unless those trunks are running 'fractional E1' with maximum - * aggregate rate of 12.288 Mbps in each direction.
    - * [1] 12.288Mbps = 1.536Mbp * 8 T1 - *
- * @{ */ - -#ifndef IXHSSACC_H -#define IXHSSACC_H - -#include "IxOsal.h" - -/* - * #defines for function return types, etc. - */ - -/** - * @def IX_HSSACC_TSLOTS_PER_HSS_PORT - * - * @brief The max number of TDM timeslots supported per HSS port - 4E1's = - * 32x4 = 128 - */ -#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128 - -/* ----------------------------------------------------------- - The following are HssAccess return values returned through - service interfaces. The globally defined IX_SUCCESS (0) and - IX_FAIL (1) in IxOsalTypes.h are also used. - ----------------------------------------------------------- */ -/** - * @def IX_HSSACC_PARAM_ERR - * - * @brief HssAccess function return value for a parameter error - */ -#define IX_HSSACC_PARAM_ERR 2 - -/** - * @def IX_HSSACC_RESOURCE_ERR - * - * @brief HssAccess function return value for a resource error - */ -#define IX_HSSACC_RESOURCE_ERR 3 - -/** - * @def IX_HSSACC_PKT_DISCONNECTING - * - * @brief Indicates that a disconnect call is progressing and will - * disconnect soon - */ -#define IX_HSSACC_PKT_DISCONNECTING 4 - -/** - * @def IX_HSSACC_Q_WRITE_OVERFLOW - * - * @brief Indicates that an attempt to Tx or to replenish an - * RxFree Q failed due to Q overflow. - */ -#define IX_HSSACC_Q_WRITE_OVERFLOW 5 - -/* ------------------------------------------------------------------- - The following errors are HSS/NPE errors returned on error retrieval - ------------------------------------------------------------------- */ -/** - * @def IX_HSSACC_NO_ERROR - * - * @brief HSS port no error present - */ -#define IX_HSSACC_NO_ERROR 0 - -/** - * @def IX_HSSACC_TX_FRM_SYNC_ERR - * - * @brief HSS port TX Frame Sync error - */ -#define IX_HSSACC_TX_FRM_SYNC_ERR 1 - -/** - * @def IX_HSSACC_TX_OVER_RUN_ERR - * - * @brief HSS port TX over-run error - */ -#define IX_HSSACC_TX_OVER_RUN_ERR 2 - -/** - * @def IX_HSSACC_CHANNELISED_SW_TX_ERR - * - * @brief NPE software error in channelised TX - */ -#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3 - -/** - * @def IX_HSSACC_PACKETISED_SW_TX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_TX_ERR 4 - -/** - * @def IX_HSSACC_RX_FRM_SYNC_ERR - * - * @brief HSS port RX Frame Sync error - */ -#define IX_HSSACC_RX_FRM_SYNC_ERR 5 - -/** - * @def IX_HSSACC_RX_OVER_RUN_ERR - * - * @brief HSS port RX over-run error - */ -#define IX_HSSACC_RX_OVER_RUN_ERR 6 - -/** - * @def IX_HSSACC_CHANNELISED_SW_RX_ERR - * - * @brief NPE software error in channelised RX - */ -#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7 - -/** - * @def IX_HSSACC_PACKETISED_SW_RX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_RX_ERR 8 - -/* ----------------------------------- - Packetised service specific defines - ----------------------------------- */ - -/** - * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE - * - * @brief Minimum size of the Rx mbuf in bytes which the client must supply - * to the component. - */ -#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64 - -/* -------------------------------------------------------------------- - Enumerated Types - these enumerated values may be used in setting up - the contents of hardware registers - -------------------------------------------------------------------- */ -/** - * @enum IxHssAccHssPort - * @brief The HSS port ID - There are two identical ports (0-1). - * - */ -typedef enum -{ - IX_HSSACC_HSS_PORT_0, /**< HSS Port 0 */ - IX_HSSACC_HSS_PORT_1, /**< HSS Port 1 */ - IX_HSSACC_HSS_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHssPort; - -/** - * @enum IxHssAccHdlcPort - * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per - * HSS port and they correspond to the 4 E1/T1 trunks. - * - */ -typedef enum -{ - IX_HSSACC_HDLC_PORT_0, /**< HDLC Port 0 */ - IX_HSSACC_HDLC_PORT_1, /**< HDLC Port 1 */ - IX_HSSACC_HDLC_PORT_2, /**< HDLC Port 2 */ - IX_HSSACC_HDLC_PORT_3, /**< HDLC Port 3 */ - IX_HSSACC_HDLC_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHdlcPort; - -/** - * @enum IxHssAccTdmSlotUsage - * @brief The HSS TDM stream timeslot assignment types - * - */ -typedef enum -{ - IX_HSSACC_TDMMAP_UNASSIGNED, /**< Unassigned */ - IX_HSSACC_TDMMAP_HDLC, /**< HDLC - packetised */ - IX_HSSACC_TDMMAP_VOICE56K, /**< Voice56K - channelised */ - IX_HSSACC_TDMMAP_VOICE64K, /**< Voice64K - channelised */ - IX_HSSACC_TDMMAP_MAX /**< Delimiter for error checks */ -} IxHssAccTdmSlotUsage; - -/** - * @enum IxHssAccFrmSyncType - * @brief The HSS frame sync pulse type - * - */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_ACTIVE_LOW, /**< Frame sync is sampled low */ - IX_HSSACC_FRM_SYNC_ACTIVE_HIGH, /**< sampled high */ - IX_HSSACC_FRM_SYNC_FALLINGEDGE, /**< sampled on a falling edge */ - IX_HSSACC_FRM_SYNC_RISINGEDGE, /**< sampled on a rising edge */ - IX_HSSACC_FRM_SYNC_TYPE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncType; - -/** - * @enum IxHssAccFrmSyncEnable - * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is - * used - * */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_INPUT, /**< Frame sync is sampled as an input */ - IX_HSSACC_FRM_SYNC_INVALID_VALUE, /**< 1 is not used */ - IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated - off a falling clock edge */ - IX_HSSACC_FRM_SYNC_OUTPUT_RISING, /**< Frame sync is an output generated - off a rising clock edge */ - IX_HSSACC_FRM_SYNC_ENABLE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncEnable; - -/** - * @enum IxHssAccClkEdge - * @brief IxHssAccClkEdge is used to determine the clk edge to use for - * framing and data - * - */ -typedef enum -{ - IX_HSSACC_CLK_EDGE_FALLING, /**< Clock sampled off a falling edge */ - IX_HSSACC_CLK_EDGE_RISING, /**< Clock sampled off a rising edge */ - IX_HSSACC_CLK_EDGE_MAX /**< Delimiter for error checks */ -} IxHssAccClkEdge; - -/** - * @enum IxHssAccClkDir - * @brief The HSS clock direction - * - */ -typedef enum -{ - IX_HSSACC_SYNC_CLK_DIR_INPUT, /**< Clock is an input */ - IX_HSSACC_SYNC_CLK_DIR_OUTPUT, /**< Clock is an output */ - IX_HSSACC_SYNC_CLK_DIR_MAX /**< Delimiter for error checks */ -} IxHssAccClkDir; - -/** - * @enum IxHssAccFrmPulseUsage - * @brief The HSS frame pulse usage - * - */ -typedef enum -{ - IX_HSSACC_FRM_PULSE_ENABLED, /**< Generate/Receive frame pulses */ - IX_HSSACC_FRM_PULSE_DISABLED, /**< Disregard frame pulses */ - IX_HSSACC_FRM_PULSE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmPulseUsage; - -/** - * @enum IxHssAccDataRate - * @brief The HSS Data rate in relation to the clock - * - */ -typedef enum -{ - IX_HSSACC_CLK_RATE, /**< Data rate is at the configured clk speed */ - IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */ - IX_HSSACC_DATA_RATE_MAX /**< Delimiter for error checks */ -} IxHssAccDataRate; - -/** - * @enum IxHssAccDataPolarity - * @brief The HSS data polarity type - * - */ -typedef enum -{ - IX_HSSACC_DATA_POLARITY_SAME, /**< Don't invert data between NPE and - HSS FIFOs */ - IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS - FIFOs */ - IX_HSSACC_DATA_POLARITY_MAX /**< Delimiter for error checks */ -} IxHssAccDataPolarity; - -/** - * @enum IxHssAccBitEndian - * @brief HSS Data endianness - * - */ -typedef enum -{ - IX_HSSACC_LSB_ENDIAN, /**< TX/RX Least Significant Bit first */ - IX_HSSACC_MSB_ENDIAN, /**< TX/RX Most Significant Bit first */ - IX_HSSACC_ENDIAN_MAX /**< Delimiter for the purposes of error checks */ -} IxHssAccBitEndian; - - -/** - * @enum IxHssAccDrainMode - * @brief Tx pin open drain mode - * - */ -typedef enum -{ - IX_HSSACC_TX_PINS_NORMAL, /**< Normal mode */ - IX_HSSACC_TX_PINS_OPEN_DRAIN, /**< Open Drain mode */ - IX_HSSACC_TX_PINS_MAX /**< Delimiter for error checks */ -} IxHssAccDrainMode; - -/** - * @enum IxHssAccSOFType - * @brief HSS start of frame types - * - */ -typedef enum -{ - IX_HSSACC_SOF_FBIT, /**< Framing bit transmitted and expected on rx */ - IX_HSSACC_SOF_DATA, /**< Framing bit not transmitted nor expected on rx */ - IX_HSSACC_SOF_MAX /**< Delimiter for error checks */ -} IxHssAccSOFType; - -/** - * @enum IxHssAccDataEnable - * @brief IxHssAccDataEnable is used to determine whether or not to drive - * the data pins - * - */ -typedef enum -{ - IX_HSSACC_DE_TRI_STATE, /**< TRI-State the data pins */ - IX_HSSACC_DE_DATA, /**< Push data out the data pins */ - IX_HSSACC_DE_MAX /**< Delimiter for error checks */ -} IxHssAccDataEnable; - -/** - * @enum IxHssAccTxSigType - * @brief IxHssAccTxSigType is used to determine how to drive the data pins - * - */ -typedef enum -{ - IX_HSSACC_TXSIG_LOW, /**< Drive the data pins low */ - IX_HSSACC_TXSIG_HIGH, /**< Drive the data pins high */ - IX_HSSACC_TXSIG_HIGH_IMP, /**< Drive the data pins with high impedance */ - IX_HSSACC_TXSIG_MAX /**< Delimiter for error checks */ -} IxHssAccTxSigType; - -/** - * @enum IxHssAccFbType - * @brief IxHssAccFbType determines how to drive the Fbit - * - * @warning This will only be used for T1 @ 1.544MHz - * - */ -typedef enum -{ - IX_HSSACC_FB_FIFO, /**< Fbit is dictated in FIFO */ - IX_HSSACC_FB_HIGH_IMP, /**< Fbit is high impedance */ - IX_HSSACC_FB_MAX /**< Delimiter for error checks */ -} IxHssAccFbType; - -/** - * @enum IxHssAcc56kEndianness - * @brief 56k data endianness when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KE_BIT_7_UNUSED, /**< High bit is unused */ - IX_HSSACC_56KE_BIT_0_UNUSED, /**< Low bit is unused */ - IX_HSSACC_56KE_MAX /**< Delimiter for error checks */ -} IxHssAcc56kEndianness; - -/** - * @enum IxHssAcc56kSel - * @brief 56k data transmission type when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KS_32_8_DATA, /**< 32/8 bit data */ - IX_HSSACC_56KS_56K_DATA, /**< 56K data */ - IX_HSSACC_56KS_MAX /**< Delimiter for error checks */ -} IxHssAcc56kSel; - - -/** - * @enum IxHssAccClkSpeed - * @brief IxHssAccClkSpeed represents the HSS clock speeds available - * - */ -typedef enum -{ - IX_HSSACC_CLK_SPEED_512KHZ, /**< 512KHz */ - IX_HSSACC_CLK_SPEED_1536KHZ, /**< 1.536MHz */ - IX_HSSACC_CLK_SPEED_1544KHZ, /**< 1.544MHz */ - IX_HSSACC_CLK_SPEED_2048KHZ, /**< 2.048MHz */ - IX_HSSACC_CLK_SPEED_4096KHZ, /**< 4.096MHz */ - IX_HSSACC_CLK_SPEED_8192KHZ, /**< 8.192MHz */ - IX_HSSACC_CLK_SPEED_MAX /**< Delimiter for error checking */ -} IxHssAccClkSpeed; - -/** - * @enum IxHssAccPktStatus - * @brief Indicates the status of packets passed to the client - * - */ -typedef enum -{ - IX_HSSACC_PKT_OK, /**< Error free.*/ - IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown - occurrance.*/ - IX_HSSACC_HDLC_ALN_ERROR, /**< HDLC alignment error */ - IX_HSSACC_HDLC_FCS_ERROR, /**< HDLC Frame Check Sum error.*/ - IX_HSSACC_RXFREE_Q_EMPTY_ERROR, /**< RxFree Q became empty - while receiving this packet.*/ - IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED, /**< HDLC frame size - received is greater than - max specified at connect.*/ - IX_HSSACC_HDLC_ABORT_ERROR, /**< HDLC frame received is invalid due to an - abort sequence received.*/ - IX_HSSACC_DISCONNECT_IN_PROGRESS /**< Packet returned - because a disconnect is in progress */ -} IxHssAccPktStatus; - - -/** - * @enum IxHssAccPktCrcType - * @brief HDLC CRC type - * - */ -typedef enum -{ - IX_HSSACC_PKT_16_BIT_CRC = 16, /**< 16 bit CRC is being used */ - IX_HSSACC_PKT_32_BIT_CRC = 32 /**< 32 bit CRC is being used */ -} IxHssAccPktCrcType; - -/** - * @enum IxHssAccPktHdlcIdleType - * @brief HDLC idle transmission type - * - */ -typedef enum -{ - IX_HSSACC_HDLC_IDLE_ONES, /**< idle tx/rx will be a succession of ones */ - IX_HSSACC_HDLC_IDLE_FLAGS /**< idle tx/rx will be repeated flags */ -} IxHssAccPktHdlcIdleType; - -/** - * @brief Structure containing HSS port configuration parameters - * - * Note: All of these are used for TX. Only some are specific to RX. - * - */ -typedef struct -{ - IxHssAccFrmSyncType frmSyncType; /**< frame sync pulse type (tx/rx) */ - IxHssAccFrmSyncEnable frmSyncIO; /**< how the frame sync pulse is - used (tx/rx) */ - IxHssAccClkEdge frmSyncClkEdge; /**< frame sync clock edge type - (tx/rx) */ - IxHssAccClkEdge dataClkEdge; /**< data clock edge type (tx/rx) */ - IxHssAccClkDir clkDirection; /**< clock direction (tx/rx) */ - IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync - pulse or not (tx/rx) */ - IxHssAccDataRate dataRate; /**< data rate in relation to the - clock (tx/rx) */ - IxHssAccDataPolarity dataPolarity; /**< data polarity type (tx/rx) */ - IxHssAccBitEndian dataEndianness; /**< data endianness (tx/rx) */ - IxHssAccDrainMode drainMode; /**< tx pin open drain mode (tx) */ - IxHssAccSOFType fBitUsage; /**< start of frame types (tx/rx) */ - IxHssAccDataEnable dataEnable; /**< whether or not to drive the data - pins (tx) */ - IxHssAccTxSigType voice56kType; /**< how to drive the data pins for - voice56k type (tx) */ - IxHssAccTxSigType unassignedType; /**< how to drive the data pins for - unassigned type (tx) */ - IxHssAccFbType fBitType; /**< how to drive the Fbit (tx) */ - IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using - the 56k type (tx) */ - IxHssAcc56kSel voice56kSel; /**< 56k data transmission type when - using the 56k type (tx) */ - unsigned frmOffset; /**< frame pulse offset in bits wrt - the first timeslot (0-1023) (tx/rx) */ - unsigned maxFrmSize; /**< frame size in bits (1-1024) - (tx/rx) */ -} IxHssAccPortConfig; - -/** - * @brief Structure containing HSS configuration parameters - * - */ -typedef struct -{ - IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */ - IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */ - unsigned numChannelised; /**< The number of channelised - timeslots (0-32) */ - unsigned hssPktChannelCount; /**< The number of packetised - clients (0 - 4) */ - UINT8 channelisedIdlePattern; /**< The byte to be transmitted on - channelised service when there - is no client data to tx */ - BOOL loopback; /**< The HSS loopback state */ - unsigned packetizedIdlePattern; /**< The data to be transmitted on - packetised service when there is - no client data to tx */ - IxHssAccClkSpeed clkSpeed; /**< The HSS clock speed */ -} IxHssAccConfigParams; - -/** - * @brief This structure contains 56Kbps, HDLC-mode configuration parameters - * - */ -typedef struct -{ - BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */ - IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness - - ignored if hdlc56kMode is false*/ - BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused - bit while in 56kbps mode - - ignored if hdlc56kMode is false*/ -} IxHssAccHdlcMode; - -/** - * @brief This structure contains information required by the NPE to - * configure the HDLC co-processor - * - */ -typedef struct -{ - IxHssAccPktHdlcIdleType hdlcIdleType; /**< What to transmit when a HDLC port is idle */ - IxHssAccBitEndian dataEndian; /**< The HDLC data endianness */ - IxHssAccPktCrcType crcType; /**< The CRC type to be used for this HDLC port */ -} IxHssAccPktHdlcFraming; - -/** - * @typedef UINT32 IxHssAccPktUserId - * - * @brief The client supplied value which will be supplied as a parameter - * with a given callback. - * - * This value will be passed into the ixHssAccPktPortConnect function once each - * with given callbacks. This value will then be passed back to the client - * as one of the parameters to each of these callbacks, - * when these callbacks are called. - */ -typedef UINT32 IxHssAccPktUserId; - - -/** - * @typedef IxHssAccLastErrorCallback - * @brief Prototype of the clients function to accept notification of the - * last error - * - * This function is registered through the config. The client will initiate - * the last error retrieval. The HssAccess component will send a message to - * the NPE through the NPE Message Handler. When a response to the read is - * received, the NPE Message Handler will callback the HssAccess component - * which will execute this function in the same IxNpeMh context. The client - * will be passed the last error and the related service port (packetised - * 0-3, channelised 0) - * - * @param lastHssError unsigned [in] - The last Hss error registered that - * has been registered. - * @param servicePort unsigned [in] - This is the service port number. - * (packetised 0-3, channelised 0) - * - * @return void - */ -typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError, - unsigned servicePort); - -/** - * @typedef IxHssAccPktRxCallback - * @brief Prototype of the clients function to accept notification of - * packetised rx - * - * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass - * received data in the form of mbufs to the client. The mbuf passed back - * to the client could contain a chain of buffers, depending on the packet - * size received. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the - * payload received. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been received. - * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId rxUserId); - -/** - * @typedef IxHssAccPktRxFreeLowCallback - * @brief Prototype of the clients function to accept notification of - * requirement of more Rx Free buffers - * - * The client can choose to register a callback of this type when - * calling a connecting. This function is registered through the ixHssAccPktPortConnect. - * If defined, the access layer will provide the trigger for - * this callback. The callback will be responsible for supplying mbufs to - * the access layer for use on the receive path from the HSS using - * ixHssPktAccFreeBufReplenish. - * - * @return void - */ -typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId); - -/** - * @typedef IxHssAccPktTxDoneCallback - * @brief Prototype of the clients function to accept notification of - * completion with Tx buffers - * - * This function is registered through the ixHssAccPktPortConnect. It enables - * the hssPktAcc to pass buffers back to the client - * when transmission is complete. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained - * the payload that was for Tx. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been transmitted. - * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId txDoneUserId); - -/** - * @typedef IxHssAccChanRxCallback - * @brief Prototype of the clients function to accept notification of - * channelised rx - * - * This callback, if defined by the client in the connect, will get called - * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ - * is not empty. The queued entry will be dequeued and this function will - * be executed. - * - * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two - * identical ports (0-1). - * @param txOffset unsigned [in] - an offset indicating from where within - * the txPtrList the NPE is currently transmitting from. - * @param rxOffset unsigned [in] - an offset indicating where within the - * receive buffers the NPE has just written the received data to. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * - * @return void - */ -typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId, - unsigned rxOffset, - unsigned txOffset, - unsigned numHssErrs); - -/* - * Prototypes for interface functions. - */ - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback) - * - * @brief Initialise a HSS port. No channelised or packetised connections - * should exist in the HssAccess layer while this interface is being called. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS - * configuration structure - * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size - * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port - * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client - * callback to report last error - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate ( - IxHssAccHssPort hssPortId) - * - * @brief Initiate the retrieval of the last HSS error. The HSS port - * should be configured before attempting to call this interface. - * - * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccInit () - * - * @brief This function is responsible for initialising resources for use - * by the packetised and channelised clients. It should be called after - * HSS NPE image has been downloaded into NPE-A and before any other - * HssAccess interface is called. - * No other HssAccPacketised interface should be called while this interface - * is being processed. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccInit (void); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId) - * - * @brief This function is responsible for connecting a client to one of - * the 4 available HDLC ports. The HSS port should be configured before - * attempting a connect. No other HssAccPacketised interface should be - * called while this connect is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and - * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param hdlcFraming BOOL [in] - This value determines whether the service - * will use HDLC data or the debug, raw data type i.e. no HDLC processing - * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode - * configuration parameters - * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion - * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for - * transmit and pre-HDLC processing for receive, for the specified HDLC Termination - * Point - * @param blockSizeInWords unsigned [in] - The max tx/rx block size - * @param rawIdleBlockPattern UINT32 [in] - Tx idle pattern in raw mode - * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for TX - * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for RX - * @param frmFlagStart unsigned - Number of flags to precede to - * transmitted flags (0-2). - * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to - * the clients packet receive function. - * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value - * to be passed back as an argument to the supplied rxCallback - * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to - * the clients Rx free buffer request function. If NULL, assume client will - * trigger independently. - * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value - * to be passed back as an argument to the supplied rxFreeLowCallback - * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the - * clients Tx done callback function - * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value - * to be passed back as an argument to the supplied txDoneCallback - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for enabling a packetised service - * for the specified HSS/HDLC port combination. It enables the RX flow. The - * client must have already connected to a packetised service and is responsible - * for ensuring an adequate amount of RX mbufs have been supplied to the access - * component before enabling the packetised service. This function must be called - * on a given port before any call to ixHssAccPktPortTx on the same port. - * No other HssAccPacketised interface should be called while this interface is - * being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service - * on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disabling a packetised service - * for the specified HSS/HDLC port combination. It disables the RX flow. - * The client must have already connected to and enabled a packetised service - * for the specified HDLC port. This disable interface can be called before a - * disconnect, but is not required to. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable - * the service on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disconnecting a client from one - * of the 4 available HDLC ports. It is not required that the Rx Flow - * has been disabled before calling this function. If the RX Flow has not been - * disabled, the disconnect will disable it before proceeding with the - * disconnect. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting - * procedure but it has not completed yet. - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is called to check if a given HSS/HDLC port - * combination is in a connected state or not. This function may be called - * at any time to determine a ports state. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - true The state of this HSS/HDLC port combination is disconnected, - * so if a disconnect was called, it is now completed. - * - false The state of this HSS/HDLC port combination is connected, - * so if a disconnect was called, it is not yet completed. - */ -PUBLIC BOOL -ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls at regular intervals to provide - * mbufs to the access component for RX. A connection should exist for - * the specified hssPortId/hdlcPortId combination before attempting to call this - * interface. Also, the connection should not be in a disconnecting state. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - */ -PUBLIC IX_STATUS -ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls when it wants to transmit - * packetised data. An enabled connection should exist on the specified - * hssPortId/hdlcPortId combination before attempting to call this interface. - * No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the - * client has filled with the payload - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error. See note. - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - * - * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be - * obtained to send the chain of mbufs to the NPE. This is a normal scenario. - * HssAcc has a pool of descriptors and this error means that they are currently - * all in use. - * The recommended approach to this is to retry until a descriptor becomes free - * and the packet is successfully transmitted. - * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback - * callback is triggered, and then retry, as it is this event that causes a - * transmit descriptor to be freed. - */ -PUBLIC IX_STATUS -ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback) - * - * @brief This function allows the client to connect to the Tx/Rx NPE - * Channelised Service. There can only be one client per HSS port. The - * client is responsible for ensuring that the HSS port is configured - * appropriately before its connect request. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access - * component after bytesPerTSTrigger have been received for all trunk - * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for - * 2ms trigger. - * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the - * client to be filled by data received. The buffer at this address is part - * of a pool of buffers to be accessed in a circular fashion. This address - * will be written to by the NPE. Therefore, it needs to be a physical address. - * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per - * timeslot within the receive memory. This figure will depend on the - * latency of the system. It needs to be deep enough for data to be read by - * the client before the NPE re-writes over that memory e.g. if the client - * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to - * be 40bytes * 3. This would give the client 3 * 5ms of time before - * received data is over-written. - * @param *txPtrList UINT32 [in] - The address of an area of contiguous - * memory allocated by the client to be populated with pointers to data for - * transmission. Each pointer list contains a pointer per active channel. - * The txPtrs will point to data to be transmitted by the NPE. Therefore, - * they must point to physical addresses. - * @param numTxPtrLists unsigned [in] - The number of pointer lists in - * txPtrList. This figure is dependent on jitter. - * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in - * bytes, that each pointer within the PtrList points to. - * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function - * pointer to be called back to handle the actual tx/rx of channelised - * data. If this is not NULL, an ISR will call this function. If this - * pointer is NULL, it implies that the client will use a polling mechanism - * to detect when the tx and rx of channelised data is to occur. The client - * will use hssChanAccStatus for this. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ - -PUBLIC IX_STATUS -ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for enabling a channelised service - * for the specified HSS port. It enables the NPE RX flow. The client must - * have already connected to a channelised service before enabling the - * channelised service. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortEnable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for disabling a channelised service - * for the specified HSS port. It disables the NPE RX flow. The client must - * have already connected to and enabled a channelised service for the - * specified HSS port. This disable interface can be called before a - * disconnect, but is not required to. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortDisable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId) - * - * @brief This function allows the client to Disconnect from a channelised - * service. If the NPE RX Flow has not been disabled, the disconnect will - * disable it before proceeding with other disconnect functionality. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanDisconnect (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs) - * - * @brief This function is called by the client to query whether or not - * channelised data has been received. If there is, hssChanAcc will return - * the details in the output parameters. An enabled connection should - * exist on the specified hssPortId before attempting to call this interface. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether - * or not the access component has read any data for the client. If - * false, the other output parameters will not have been written to. - * @param *rxOffset unsigned [out] - An offset to indicate to the client - * where within the receive buffers the NPE has just written the received - * data to. - * @param *txOffset unsigned [out] - An offset to indicate to the client - * from where within the txPtrList the NPE is currently transmitting from - * @param *numHssErrs unsigned [out] - The total number of HSS port errors - * since initial port configuration - * - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccShow (void) - * - * @brief This function will display the current state of the IxHssAcc - * component. The output is sent to stdout. - * - * @return void - */ -PUBLIC void -ixHssAccShow (void); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccStatsInit (void) - * - * @brief This function will reset the IxHssAcc statistics. - * - * @return void - */ -PUBLIC void -ixHssAccStatsInit (void); - -#endif /* IXHSSACC_H */ - -/** - * @} defgroup IxHssAcc - */ diff --git a/drivers/net/npe/include/IxI2cDrv.h b/drivers/net/npe/include/IxI2cDrv.h deleted file mode 100644 index 033154046f..0000000000 --- a/drivers/net/npe/include/IxI2cDrv.h +++ /dev/null @@ -1,843 +0,0 @@ -/** - * @file IxI2cDrv.h - * - * @brief Header file for the IXP400 I2C Driver (IxI2cDrv) - * - * @version $Revision: 0.1 $ - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API - * - * @brief IXP400 I2C Driver Public API - * - * @{ - */ -#ifndef IXI2CDRV_H -#define IXI2CDRV_H - -#ifdef __ixp46X -#include "IxOsal.h" - -/* - * Section for #define - */ - -/** - * @ingroup IxI2cDrv - * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected - * through the API ixI2cDrvDelayTypeSelect. - */ -#define IX_I2C_US_POLL_FOR_XFER_STATUS 20 - -/** - * @ingroup IxI2cDrv - * @brief The number of tries that will be attempted to call a callback - * function if the callback does not or is unable to resolve the - * issue it is called to resolve - */ -#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC 10 - - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Rx full bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100 - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Tx empty bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100 - -/* - * Section for enum - */ - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cMasterStatus - * - * @brief The master status - transfer complete, bus error or arbitration loss - */ -typedef enum -{ - IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS, - IX_I2C_MASTER_XFER_BUS_ERROR, - IX_I2C_MASTER_XFER_ARB_LOSS -} IxI2cMasterStatus; - - -/** - * @ingroup IxI2cDrv - * - * @enum IX_I2C_STATUS - * - * @brief The status that can be returned in a I2C driver initialization - */ -typedef enum -{ - IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */ - IX_I2C_FAIL, /**< Fail status */ - IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */ - IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */ - IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */ - IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */ - IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */ - IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */ - IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */ - IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */ - IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */ - IX_I2C_NOT_INIT, /**< I2C is not initialized yet */ - IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */ - IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */ - IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */ - IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */ - IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */ - IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */ - IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */ - IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */ - IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */ - IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */ - IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */ - IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */ - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */ - IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */ - IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */ - IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */ -} IX_I2C_STATUS; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cSpeedMode - * - * @brief Type of speed modes supported by the I2C hardware. - */ -typedef enum -{ - IX_I2C_NORMAL_MODE = 0x0, - IX_I2C_FAST_MODE -} IxI2cSpeedMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cXferMode - * - * @brief Used for indicating it is a repeated start or normal transfer - */ -typedef enum -{ - IX_I2C_NORMAL = 0x0, - IX_I2C_REPEATED_START -} IxI2cXferMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cFlowMode - * - * @brief Used for indicating it is a poll or interrupt mode - */ -typedef enum -{ - IX_I2C_POLL_MODE = 0x0, - IX_I2C_INTERRUPT_MODE -} IxI2cFlowMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cDelayMode - * - * @brief Used for selecting looping delay or OS scheduler delay - */ -typedef enum -{ - IX_I2C_LOOP_DELAY = 1, /**< delay in microseconds */ - IX_I2C_SCHED_DELAY /**< delay in miliseconds */ -} IxI2cDelayMode; - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its receive. The parameter that is passed will - * provide the status of the read (success, arb loss, or bus - * error), the transfer mode (normal or repeated start, the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its transmit. The parameter that is passed will - * provide the status of the write (success, arb loss, or buss - * error), the transfer mode (normal or repeated start), the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a read. The parameters - * that is passed will provide the read status, buffer pointer, - * buffer size, and the bytes received. When a start of a read - * is initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a write. The parameters - * that is passed will provide the write status, buffer pointer, - * buffer size, and the bytes received. When a start of a write is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer and to fill it with data. - * While transmitting, if the data in the buffer empties, this - * callback will be called to request for more data to be filled in - * the same or new buffer. When the transmit is complete, this - * callback will be called to free the memory or other actions to - * be taken. - */ -typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a general - * call detected in interrupt mode for a read. The parameters that - * is passed will provide the read status, buffer pointer, buffer - * size, and the bytes received. When a start of a read is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/* - * Section for struct - */ - -/** - * @brief contains all the variables required to initialize the I2C unit - * - * Structure to be filled and used for calling initialization - */ -typedef struct -{ - IxI2cSpeedMode I2cSpeedSelect; /** - * NOTE: 1) An individual callback is to be registered for each Slave and Master - * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time - * stamp interrupts either the same callback or two separate callbacks the API has - * to be invoked twice. - * 2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for - * slave mode is tied to GPIO 8 pin. This signal is software routed by default to - * PCI for backwards compatibility with the IXDP425 Development Platform. This - * routing must be disabled for the auxiliary slave time stamp register to work - * properly. The following commands may be used to accomplish this. However, refer - * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for - * more specific information. - * - * For Linux (at the Redboot prompt i.e., before loading zImage): - * mfill -b 0x54100000 -1 -l 1 -p 8 - * mfill -b 0x54100001 -1 -l 1 -p 0x7f - * For vxWorks, at the prompt: - * intDisable(25) - * ixdp400FpgaIODetach(8) - * - * - * @li Re-entrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or - invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode, - IxTimeSyncAccAuxTimeCallback auxTimeCallback); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable( - IxTimeSyncAccAuxMode auxMode) - * - * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp - * in the IEEE 1588 hardware assist block - * - * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which - * the interrupt will be disabled. - * - * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave) - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll( - IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime) - * - * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated - * (Master or Slave) - * - * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked - * @param auxPollFlag [out] - true if the time stamp captured in auxiliary - snapshot register - * false if the time stamp not captured in - auxiliary snapshot register - * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the - * client provided buffer - * - * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based - * on the mode specified. Return true and the contents of the Auxiliary snapshot, - * if it is available else return false. - * - * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable - * for more information for Auxiliary Slave mode. - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag, - callback or invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void) - * - * @brief Resets the IEEE 1588 hardware assist block - * - * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats - *timeSyncStats) - * - * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer - * - * @param timeSyncStats [out] - TimeSync statistics counter values - * - * This API will return the statistics of the received or transmitted messages. - * - * NOTE: 1) These counters are updated only when the client polls for the time - * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module - * does not either transmit or receive messages and does only run the code - * when explicit requests received by client application. - * - * 2) These statistics reflect the number of valid PTP messages exchanged - * in Master and Slave modes but includes all the messages (including valid - * non-PTP messages) while operating in the Any mode. - * - * @li Reentrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn void ixTimeSyncAccStatsReset(void) - * - * @brief Reset Time Sync statistics - * - * This API will reset the statistics counters of the TimeSync access layer. - * - * @li Reentrant : yes - * @li ISR Callable: no - * - * @return @li None - */ -PUBLIC void -ixTimeSyncAccStatsReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void) - * - * @brief Displays the Time Sync current status - * - * This API will display status on the current configuration of the IEEE - * 1588 hardware assist block, contents of the various time stamp registers, - * outstanding interrupts and/or events. - * - * Note that this is intended for debug only, and in contrast to the other - * functions, it does not clear the any of the status bits associated with - * active timestamps and so is passive in its nature. - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccShow(void); - -#endif /* __ixp46X */ -#endif /* IXTIMESYNCACC_H */ - -/** - * @} defgroup IxTimeSyncAcc - */ - diff --git a/drivers/net/npe/include/IxTimerCtrl.h b/drivers/net/npe/include/IxTimerCtrl.h deleted file mode 100644 index a865b933a3..0000000000 --- a/drivers/net/npe/include/IxTimerCtrl.h +++ /dev/null @@ -1,239 +0,0 @@ -/** - * @file IxTimerCtrl.h - * @brief - * This is the header file for the Timer Control component. - * - * The timer callback control component provides a mechanism by which different - * client components can start a timer and have a supplied callback function - * invoked when the timer expires. - * The callbacks are all dispatched from one thread inside this component. - * Any component that needs to be called periodically should use this facility - * rather than create its own task with a sleep loop. - * - * @par - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API - * - * @brief The public API for the IXP400 Timer Control Component. - * - * @{ - */ - -#ifndef IxTimerCtrl_H -#define IxTimerCtrl_H - - -#include "IxTypes.h" -/* #include "Ossl.h" */ - -/* - * #defines and macros used in this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_NO_FREE_TIMERS - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * all available timer resources are used. - */ -#define IX_TIMERCTRL_NO_FREE_TIMERS 2 - - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_PARAM_ERROR - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * the client has supplied invalid parameters. - */ -#define IX_TIMERCTRL_PARAM_ERROR 3 - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @brief A typedef for a pointer to a timer callback function. - * @para void * - This parameter is supplied by the client when the - * timer is started and passed back to the client in the callback. - * @note in general timer callback functions should not block or - * take longer than 100ms. This constraint is required to ensure that - * higher priority callbacks are not held up. - * All callbacks are called from the same thread. - * This thread is a shared resource. - * The parameter passed is provided when the timer is scheduled. - */ -typedef void (*IxTimerCtrlTimerCallback)(void *userParam); - - -/** - * @ingroup IxTimerCtrl - * - * @brief List used to identify the users of timers. - * @note The order in this list indicates priority. Components appearing - * higher in the list will be given priority over components lower in the - * list. When adding components, please insert at an appropriate position - * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) . - */ -typedef enum -{ - IxTimerCtrlAdslPurpose, - /* Insert new purposes above this line only - */ - IxTimerCtrlMaxPurpose -} -IxTimerCtrlPurpose; - - -/* - * Function definition - */ - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * This function - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback - * will be called. The time must be greater than the duration of one OS tick. - * @param *timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param interval UINT32 [in] - the interval in milliseconds between calls to func. - * @param timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlCancel (unsigned id) - * - * @brief Cancels a scheduled callback. - * - * @param id unsigned [in] - the id of the callback to be cancelled. - * @return - * @li IX_SUCCESS - The timer was successfully stopped. - * @li IX_FAIL - The id parameter did not corrrespond to any running timer.. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlCancel (unsigned id); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlInit(void) - * - * @brief Initialise the Timer Control Component. - * @return - * @li IX_SUCCESS - The timer control component initialized successfully. - * @li IX_FAIL - The timer control component initialization failed, - * or the component was already initialized. - * @note This must be done before any other API function is called. - * This function should be called once only and is not re-entrant. - */ -PUBLIC IX_STATUS -ixTimerCtrlInit(void); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlShow( void ) - * - * @brief Display the status of the Timer Control Component. - * @return void - * @note Displays a list of running timers. - * This function is not re-entrant. This function does not suspend the calling thread. - */ -PUBLIC void -ixTimerCtrlShow( void ); - -#endif /* IXTIMERCTRL_H */ - diff --git a/drivers/net/npe/include/IxTypes.h b/drivers/net/npe/include/IxTypes.h deleted file mode 100644 index f936a50bb3..0000000000 --- a/drivers/net/npe/include/IxTypes.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file IxTypes.h (Replaced by OSAL) - * - * @date 28-NOV-2001 - - * @brief This file contains basic types used by the IXP400 software - * - * Design Notes: - * This file shall only include fundamental types and definitions to be - * shared by all the IXP400 components. - * Please DO NOT add component-specific types here. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxTypes IXP400 Types (IxTypes) - * - * @brief Basic data types used by the IXP400 project - * - * @{ - */ - -#ifndef IxTypes_H - -#ifndef __doxygen_HIDE - -#define IxTypes_H - -#endif /* __doxygen_HIDE */ - - -/* WR51880: Undefined data types workaround for backward compatibility */ -#ifdef __linux -#ifndef __INCvxTypesOldh -typedef int (*FUNCPTR)(void); -typedef int STATUS; -#define OK (0) -#define ERROR (-1) -#endif -#endif - -#include "IxOsalBackward.h" - -#endif /* IxTypes_H */ - -/** - * @} addtogroup IxTypes - */ diff --git a/drivers/net/npe/include/IxUART.h b/drivers/net/npe/include/IxUART.h deleted file mode 100644 index ff23b22fe7..0000000000 --- a/drivers/net/npe/include/IxUART.h +++ /dev/null @@ -1,434 +0,0 @@ -/** - * @file IxUART.h - * - * @date 12-OCT-01 - * - * @brief Public header for the Intel IXP400 internal UART, generic driver. - * - * Design Notes: - * This driver allows you to perform the following functions: - * Device Initialization, - * send/receive characters. - * - * Perform Uart IOCTL for the following: - * Set/Get the current baud rate, - * set parity, - * set the number of Stop bits, - * set the character Length (5,6,7,8), - * enable/disable Hardware flow control. - * - * Only Polled mode is supported for now. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API - * - * @brief IXP400 UARTAcc Driver Public API - * - * @{ - */ - - -/* Defaults */ - -/** - * @defgroup DefaultDefines Defines for Default Values - * - * @brief Default values which can be used for UART configuration - * - * @sa ixUARTDev - */ - -/** - * @def IX_UART_DEF_OPTS - * - * @brief The default hardware options to set the UART to - - * no flow control, 8 bit word, 1 stop bit, no parity - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_OPTS (CLOCAL | CS8) - -/** - * @def IX_UART_DEF_XMIT - * - * @brief The default UART FIFO size - must be no bigger than 64 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_XMIT 64 - -/** - * @def IX_UART_DEF_BAUD - * - * @brief The default UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_BAUD 9600 - -/** - * @def IX_UART_MIN_BAUD - * - * @brief The minimum UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MIN_BAUD 9600 - -/** - * @def IX_UART_MAX_BAUD - * - * @brief The maximum UART baud rate - 926100 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MAX_BAUD 926100 - -/** - * @def IX_UART_XTAL - * - * @brief The UART clock speed - * - * @ingroup DefaultDefines - */ -#define IX_UART_XTAL 14745600 - - - -/* IOCTL commands (Request codes) */ - -/** - * @defgroup IoctlCommandDefines Defines for IOCTL Commands - * - * @brief IOCTL Commands (Request codes) which can be used - * with @ref ixUARTIoctl - */ - - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_SET - * - * @brief Set the baud rate - */ -#define IX_BAUD_SET 0 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_GET - * - * @brief Get the baud rate - */ -#define IX_BAUD_GET 1 - -/** - * @ingroup IoctlCommandDefines - * @def IX_MODE_SET - * @brief Set the UART mode of operation - */ -#define IX_MODE_SET 2 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_MODE_GET - * - * @brief Get the current UART mode of operation - */ -#define IX_MODE_GET 3 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_SET - * - * @brief Set the UART device options - */ -#define IX_OPTS_SET 4 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_GET - * - * @brief Get the UART device options - */ -#define IX_OPTS_GET 5 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_STATS_GET - * - * @brief Get the UART statistics - */ -#define IX_STATS_GET 6 - - -/* POSIX style ioctl arguments */ - -/** - * @defgroup IoctlArgDefines Defines for IOCTL Arguments - * - * @brief POSIX style IOCTL arguments which can be used - * with @ref ixUARTIoctl - * - * @sa ixUARTMode - */ - - -/** - * @ingroup IoctlArgDefines - * - * @def CLOCAL - * - * @brief Software flow control - */ -#ifdef CLOCAL -#undef CLOCAL -#endif -#define CLOCAL 0x1 - -/** - * @ingroup IoctlArgDefines - * - * @def CREAD - * - * @brief Enable interrupt receiver - */ -#ifdef CREAD -#undef CREAD -#endif -#define CREAD 0x2 - -/** - * @ingroup IoctlArgDefines - * - * @def CSIZE - * - * @brief Characters size - */ -#ifdef CSIZE -#undef CSIZE -#endif -#define CSIZE 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def CS5 - * - * @brief 5 bits - */ -#ifdef CS5 -#undef CS5 -#endif -#define CS5 0x0 - -/** - * @ingroup IoctlArgDefines - * - * @def CS6 - * - * @brief 6 bits - */ -#ifdef CS6 -#undef CS6 -#endif -#define CS6 0x4 - -/** - * @ingroup IoctlArgDefines - * - * @def CS7 - * - * @brief 7 bits - */ -#ifdef CS7 -#undef CS7 -#endif -#define CS7 0x8 - -/** - * @ingroup IoctlArgDefines - * - * @def CS8 - * - * @brief 8 bits - */ -#ifdef CS8 -#undef CS8 -#endif -#define CS8 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def STOPB - * - * @brief Send two stop bits (else one) - */ -#define STOPB 0x20 - -/** - * @ingroup IoctlArgDefines - * - * @def PARENB - * - * @brief Parity detection enabled (else disabled) - */ -#ifdef PARENB -#undef PARENB -#endif -#define PARENB 0x40 - -/** - * @ingroup IoctlArgDefines - * - * @def PARODD - * - * @brief Odd parity (else even) - */ -#ifdef PARODD -#undef PARODD -#endif -#define PARODD 0x80 - -/** - * @enum ixUARTMode - * @brief The mode to set to UART to. - */ -typedef enum -{ - INTERRUPT=0, /**< Interrupt mode */ - POLLED, /**< Polled mode */ - LOOPBACK /**< Loopback mode */ -} ixUARTMode; - -/** - * @struct ixUARTStats - * @brief Statistics for the UART. - */ -typedef struct -{ - UINT32 rxCount; - UINT32 txCount; - UINT32 overrunErr; - UINT32 parityErr; - UINT32 framingErr; - UINT32 breakErr; -} ixUARTStats; - -/** - * @struct ixUARTDev - * @brief Device descriptor for the UART. - */ -typedef struct -{ - UINT8 *addr; /**< device base address */ - ixUARTMode mode; /**< interrupt, polled or loopback */ - int baudRate; /**< baud rate */ - int freq; /**< UART clock frequency */ - int options; /**< hardware options */ - int fifoSize; /**< FIFO xmit size */ - - ixUARTStats stats; /**< device statistics */ -} ixUARTDev; - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * - * @brief Initialise the UART. This puts the chip in a quiescent state. - * - * @pre The base address for the UART must contain a valid value. - * Also the baud rate and hardware options must contain sensible values - * otherwise the defaults will be used as defined in ixUART.h - * - * @post UART is initialized and ready to send and receive data. - * - * @note This function should only be called once per device. - * - * @retval IX_SUCCESS - UART device successfully initialised. - * @retval IX_FAIL - Critical error, device not initialised. - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar) - * - * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device. - * @param outChar int [out] - character to transmit. - * - * @brief Transmit a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully transmitted. - * @retval IX_FAIL - output buffer is full (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param *inChar char [in] - character read from the device. - * - * @brief Receive a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully read. - * @retval IX_FAIL - input buffer empty (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param cmd int [in] - an ioctl request code. - * @param arg void* [in] - optional argument used to set the device mode, - * baud rate, and hardware options. - * - * @brief Perform I/O control routines on the device. - * - * @retval IX_SUCCESS - requested feature was set/read successfully. - * @retval IX_FAIL - error setting/reading the requested feature. - * - * @sa IoctlCommandDefines - * @sa IoctlArgDefines - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg); - -/** - * @} defgroup IxUARTAcc - */ diff --git a/drivers/net/npe/include/IxVersionId.h b/drivers/net/npe/include/IxVersionId.h deleted file mode 100644 index 1769dcda45..0000000000 --- a/drivers/net/npe/include/IxVersionId.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file IxVersionId.h - * - * @date 22-Aug-2002 - * - * @brief This file contains the IXP400 Software version identifier - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxVersionId IXP400 Version ID (IxVersionId) - * - * @brief Version Identifiers - * - * @{ - */ - -#ifndef IXVERSIONID_H -#define IXVERSIONID_H - -/** - * @brief Version Identifier String - * - * This string will be updated with each customer release of the IXP400 - * Software. - */ -#define IX_VERSION_ID "2_0" - -/** - * This string will be updated with each customer release of the IXP400 - * ADSL driver package. - */ -#define IX_VERSION_ADSL_ID "1_12" - - -/** - * This string will be updated with each customer release of the IXP400 - * USB Client driver package. - */ -#define IX_VERSION_USBRNDIS_ID "1_9" - -/** - * This string will be updated with each customer release of the IXP400 - * I2C Linux driver package. - */ -#define IX_VERSION_I2C_LINUX_ID "1_0" - -/** - * @brief Linux Ethernet Driver Patch Version Identifier String - * - * This string will be updated with each release of Linux Ethernet Patch - */ -#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4" - -/** - * @brief Linux Integration Patch Version Identifier String - * - * This String will be updated with each release of Linux Integration Patch - */ -#define LINUX_INTEGRATION_PATCH_ID "1_3" - -/** - * @brief Linux Ethernet Readme version Identifier String - * - * This string will be updated with each release of Linux Ethernet Readme - */ -#define LINUX_ETHERNET_README_ID "1_3" - -/** - * @brief Linux Integration Readme version Identifier String - * - * This string will be updated with each release of Linux Integration Readme - */ - -#define LINUX_INTEGRATION_README_ID "1_3" - -/** - * @brief Linux I2C driver Readme version Identifier String - * - * This string will be updated with each release of Linux I2C Driver Readme - */ -#define LINUX_I2C_DRIVER_README_ID "1_0" - -/** - * @brief ixp425_eth_update_nf_bridge.patch version Identifier String - * - * This string will be updated with each release of ixp425_eth_update_nf_bridge. -patch - * - */ - -#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3" - -/** - * @brief Internal Release Identifier String - * - * This string will be updated with each internal release (SQA drop) - * of the IXP400 Software. - */ -#define IX_VERSION_INTERNAL_ID "SQA3_5" - -/** - * @brief Compatible Tornado Version Identifier - */ -#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0" - -/** - * @brief Compatible Linux Version Identifier - */ -#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1" - - -#endif /* IXVERSIONID_H */ - -/** - * @} addtogroup IxVersionId - */ diff --git a/drivers/net/npe/include/ix_error.h b/drivers/net/npe/include/ix_error.h deleted file mode 100644 index 4c599996cf..0000000000 --- a/drivers/net/npe/include/ix_error.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_error.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file will describe the basic error type and support functions that - * will be used by the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:19:03 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_ERROR_H__) -#define __IX_ERROR_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_ERROR_H__) */ - diff --git a/drivers/net/npe/include/ix_macros.h b/drivers/net/npe/include/ix_macros.h deleted file mode 100644 index b4cf7602ae..0000000000 --- a/drivers/net/npe/include/ix_macros.h +++ /dev/null @@ -1,242 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_macros.h - * - * = DESCRIPTION - * This file will define the basic preprocessor macros that are going to be used - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:41:05 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_MACROS_H__) -#define __IX_MACROS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK16 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK16( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint16)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD16 - * - * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD16 - * - * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD16( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) - -/** - * MACRO NAME: IX_SET_BIT_FIELD16 - * - * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData16. - */ -#define IX_SET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \ - ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK32 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK32( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint32)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD32 - * - * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD32 - * - * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD32( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) - - -/** - * MACRO NAME: IX_SET_BIT_FIELD32 - * - * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData32. - */ -#define IX_SET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \ - ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_MACROS_H__) */ diff --git a/drivers/net/npe/include/ix_os_type.h b/drivers/net/npe/include/ix_os_type.h deleted file mode 100644 index e14d561c28..0000000000 --- a/drivers/net/npe/include/ix_os_type.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_os_type.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file provides protable symbol definitions for the current OS type. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:43:30 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_OS_TYPE_H__) -#define __IX_OS_TYPE_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_OS_TYPE_H__) */ - diff --git a/drivers/net/npe/include/ix_ossl.h b/drivers/net/npe/include/ix_ossl.h deleted file mode 100644 index eaa2629b8d..0000000000 --- a/drivers/net/npe/include/ix_ossl.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OSSL Abstraction layer header file - * - * = FILENAME - * ix_ossl.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains the prototypes of OS-independent wrapper - * functions which allow the programmer not to be tied to a specific - * operating system. The OSSL functions can be divided into three classes: - * - * 1) synchronization-related wrapper functions around thread system calls - * 2) thread-related wrapper functions around thread calls - * 3) transactor/workbench osapi calls -- defined in osApi.h - * - * Both 1 and 2 classes of functions provide Thread Management, Thread - * Synchronization, Mutual Exclusion and Timer primitives. Namely, - * creation and deletion functions as well as the standard "wait" and - * "exit". Additionally, a couple of utility functions which enable to - * pause the execution of a thread are also provided. - * - * The 3rd class provides a slew of other OSAPI functions to handle - * Transactor/WorkBench OS calls. - * - * - * OSSL Thread APIs: - * The OSSL thread functions that allow for thread creation, - * get thread id, thread deletion and set thread priroity. - * - * ix_ossl_thread_create - * ix_ossl_thread_get_id - * ix_ossl_thread_exit - * ix_ossl_thread_kill - * ix_ossl_thread_set_priority - * ix_ossl_thread__delay - * - * OSSL Semaphore APIs: - * The OSSL semaphore functions that allow for initialization, - * posting, waiting and deletion of semaphores. - * - * ix_ossl_sem_init - * ix_ossl_sem_fini - * ix_ossl_sem_take - * ix_ossl_sem_give - * ix_ossl_sem_flush - * - * OSSL Mutex APIs: - * The OSSL wrapper functions that allow for initialization, - * posting, waiting and deletion of mutexes. - * - * ix_ossl_mutex_init - * ix_ossl_mutex_fini - * ix_ossl_mutex_lock - * ix_ossl_mutex_unlock - * - * OSSL Timer APIs: - * The timer APIs provide sleep and get time functions. - * - * ix_ossl_sleep - * ix_ossl_sleep_tick - * ix_ossl_time_get - * - * OSAPIs for Transactor/WorkBench: - * These OSAPI functions are used for transator OS calls. - * They are defined in osApi.h. - * - * Sem_Init - * Sem_Destroy - * Sem_Wait - * Sem_Wait - * Thread_Create - * Thread_Cancel - * Thread_SetPriority - * delayMs - * delayTick - * - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = ACKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - * 02/22/2002 : Renamed osapi.h os_api.h - * Moved OS header file includes from OSSL.h to os_api.h - * Moved OS specific datatypes to os_api.h - * Modified data types, macros and functions as per - * 'C' coding guidelines. - * - * - * ============================================================================ - */ - -#ifndef _IX_OSSL_H -#ifndef __doxygen_hide -#define _IX_OSSL_H -#endif /* __doxygen_hide */ - -#include "IxOsalBackward.h" - -#endif /* _IX_OSSL_H */ - -/** - * @} defgroup IxOSSL - */ diff --git a/drivers/net/npe/include/ix_symbols.h b/drivers/net/npe/include/ix_symbols.h deleted file mode 100644 index 0006b227c6..0000000000 --- a/drivers/net/npe/include/ix_symbols.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_symbols.h - * - * = DESCRIPTION - * This file declares all the global preprocessor symbols required by - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/23/2002 10:41:13 AM - creation time - * ============================================================================ - */ - -#if !defined(__IX_SYMBOLS_H__) -#define __IX_SYMBOLS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - -/** - * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms. - * We are planning to provide a simulation version of the library that should work - * with the Transactor rather than the hardware. This implementation will be done on - * WIN32 in the form of a DLL that will need to export functions and symbols. - */ -#if (_IX_OS_TYPE_ == _IX_OS_WIN32_) -# if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_) -# define IX_EXPORT_FUNCTION __declspec( dllexport ) -# elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_) -# define IX_EXPORT_FUNCTION __declspec( dllimport ) -# else -# define IX_EXPORT_FUNCTION extern -# endif -#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_) -# define IX_EXPORT_FUNCTION __declspec(dllexport) -#else -# define IX_EXPORT_FUNCTION extern -#endif - - -/** - * This symbols should be defined when we want to build for a multithreaded environment - */ -#define _IX_MULTI_THREADED_ 1 - - -/** - * This symbol should be defined in the case we to buils for a multithreaded environment - * but we want that our modules to work as if they are used in a single threaded environment. - */ -/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_ 1 */ - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_SYMBOLS_H__) */ diff --git a/drivers/net/npe/include/ix_types.h b/drivers/net/npe/include/ix_types.h deleted file mode 100644 index 6945506049..0000000000 --- a/drivers/net/npe/include/ix_types.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_types.h - * - * = DESCRIPTION - * This file will define generic types that will guarantee the protability - * between different architectures and compilers. It should be used the entire - * IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:44:17 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_TYPES_H__) -#define __IX_TYPES_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * Define generic integral data types that will guarantee the size. - */ - -/** - * TYPENAME: ix_int8 - * - * DESCRIPTION: This type defines an 8 bit signed integer value. - * - */ -typedef signed char ix_int8; - - -/** - * TYPENAME: ix_uint8 - * - * DESCRIPTION: This type defines an 8 bit unsigned integer value. - * - */ -typedef unsigned char ix_uint8; - - -/** - * TYPENAME: ix_int16 - * - * DESCRIPTION: This type defines an 16 bit signed integer value. - * - */ -typedef signed short int ix_int16; - - -/** - * TYPENAME: ix_uint16 - * - * DESCRIPTION: This type defines an 16 bit unsigned integer value. - * - */ -typedef unsigned short int ix_uint16; - - -/** - * TYPENAME: ix_int32 - * - * DESCRIPTION: This type defines an 32 bit signed integer value. - * - */ -typedef signed int ix_int32; - - -/** - * TYPENAME: ix_uint32 - * - * DESCRIPTION: This type defines an 32 bit unsigned integer value. - * - */ -#ifndef __wince -typedef unsigned int ix_uint32; -#else -typedef unsigned long ix_uint32; -#endif - -/** - * TYPENAME: ix_int64 - * - * DESCRIPTION: This type defines an 64 bit signed integer value. - * - */ -#ifndef __wince -__extension__ typedef signed long long int ix_int64; -#endif - -/** - * TYPENAME: ix_uint64 - * - * DESCRIPTION: This type defines an 64 bit unsigned integer value. - * - */ -#ifndef __wince -__extension__ typedef unsigned long long int ix_uint64; -#endif - - -/** - * TYPENAME: ix_bit_mask8 - * - * DESCRIPTION: This is a generic type for a 8 bit mask. - */ -typedef ix_uint8 ix_bit_mask8; - - -/** - * TYPENAME: ix_bit_mask16 - * - * DESCRIPTION: This is a generic type for a 16 bit mask. - */ -typedef ix_uint16 ix_bit_mask16; - - -/** - * TYPENAME: ix_bit_mask32 - * - * DESCRIPTION: This is a generic type for a 32 bit mask. - */ -typedef ix_uint32 ix_bit_mask32; - - -/** - * TYPENAME: ix_bit_mask64 - * - * DESCRIPTION: This is a generic type for a 64 bit mask. - */ -#ifndef __wince -typedef ix_uint64 ix_bit_mask64; -#endif - - -/** - * TYPENAME: ix_handle - * - * DESCRIPTION: This type defines a generic handle. - * - */ -typedef ix_uint32 ix_handle; - - - -/** - * DESCRIPTION: This symbol defines a NULL handle - * - */ -#define IX_NULL_HANDLE ((ix_handle)0) - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_TYPES_H__) */ diff --git a/drivers/net/npe/include/npe.h b/drivers/net/npe/include/npe.h deleted file mode 100644 index 1c6ae26ddc..0000000000 --- a/drivers/net/npe/include/npe.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef NPE_H -#define NPE_H - -/* - * defines... - */ -#define CONFIG_SYS_NPE_NUMS 1 -#ifdef CONFIG_HAS_ETH1 -#undef CONFIG_SYS_NPE_NUMS -#define CONFIG_SYS_NPE_NUMS 2 -#endif - -#define NPE_NUM_PORTS 3 -#define ACTIVE_PORTS 1 - -#define NPE_PKT_SIZE 1600 - -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS 64 -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS 2 - -#define NPE_MBUF_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS) - -#define NPE_PKT_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - NPE_PKT_SIZE * ACTIVE_PORTS) - -#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE) - -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ - -/* - * structs... - */ -struct npe { - u8 active; /* NPE active */ - u8 eth_id; /* IX_ETH_PORT_1 or IX_ETH_PORT_2 */ - u8 phy_no; /* which PHY (0 - 31) */ - u8 mac_address[6]; - - IX_OSAL_MBUF *rxQHead; - IX_OSAL_MBUF *txQHead; - - u8 *tx_pkts; - u8 *rx_pkts; - IX_OSAL_MBUF *rx_mbufs; - IX_OSAL_MBUF *tx_mbufs; - - int print_speed; - - int rx_read; - int rx_write; - int rx_len[PKTBUFSRX]; -}; - -/* - * prototypes... - */ -extern int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -#endif /* ifndef NPE_H */ diff --git a/drivers/net/npe/include/os_datatypes.h b/drivers/net/npe/include/os_datatypes.h deleted file mode 100644 index def891b862..0000000000 --- a/drivers/net/npe/include/os_datatypes.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OS Specific Data Types header file - * - * = FILENAME - * OSSL.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains definitions and encapsulations for OS specific data types. These - * encapsulated data types are used by OSSL header files and OS API functions. - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = AKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - - * ============================================================================ - */ - -#ifndef _OS_DATATYPES_H -#define _OS_DATATYPES_H - -#include "IxOsalBackward.h" - -#endif /* _OS_DATATYPES_H */ - diff --git a/drivers/net/npe/miiphy.c b/drivers/net/npe/miiphy.c deleted file mode 100644 index 002fb8113b..0000000000 --- a/drivers/net/npe/miiphy.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*-----------------------------------------------------------------------------+ - | - | File Name: miiphy.c - | - | Function: This module has utilities for accessing the MII PHY through - | the EMAC3 macro. - | - | Author: Mark Wisner - | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | - | - +-----------------------------------------------------------------------------*/ - -#include -#include -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/***********************************************************/ -/* Dump out to the screen PHY regs */ -/***********************************************************/ - -void miiphy_dump (char *devname, unsigned char addr) -{ - unsigned long i; - unsigned short data; - - - for (i = 0; i < 0x1A; i++) { - if (miiphy_read (devname, addr, i, &data)) { - printf ("read error for reg %lx\n", i); - return; - } - printf ("Phy reg %lx ==> %4x\n", i, data); - - /* jump to the next set of regs */ - if (i == 0x07) - i = 0x0f; - - } /* end for loop */ -} /* end dump */ - - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, MII_ADVERTISE, &adv); - adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF); - miiphy_write (devname, addr, MII_ADVERTISE, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, MII_BMCR, &ctl); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - miiphy_write (devname, addr, MII_BMCR, ctl); - - return 0; -} - - -int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - u16 val; - - ixEthAccMiiReadRtn(addr, reg, &val); - *value = val; - - return 0; -} /* phy_read */ - - -int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - ixEthAccMiiWriteRtn(addr, reg, value); - return 0; -} /* phy_write */ diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c deleted file mode 100644 index 00b381ec4a..0000000000 --- a/drivers/net/npe/npe.c +++ /dev/null @@ -1,680 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if 0 -#define DEBUG /* define for debug output */ -#endif - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL; -static int npe_exists[NPE_NUM_PORTS]; -static int npe_used[NPE_NUM_PORTS]; - -/* A little extra so we can align to cacheline. */ -static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1]; -static u8 *npe_alloc_end; -static u8 *npe_alloc_free; - -static void *npe_alloc(int size) -{ - static int count = 0; - void *p = NULL; - - size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1); - count++; - - if ((npe_alloc_free + size) < npe_alloc_end) { - p = npe_alloc_free; - npe_alloc_free += size; - } else { - printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size); - } - return p; -} - -/* Not interrupt safe! */ -static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new) -{ - IX_OSAL_MBUF *m = *q; - - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL; - - if (m) { - while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m)) - m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new; - } else - *q = new; -} - -/* Not interrupt safe! */ -static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q) -{ - IX_OSAL_MBUF *m = *q; - if (m) - *q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - return m; -} - -static void reset_tx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->txQHead = NULL; - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) { - m = &p_npe->tx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - mbuf_enqueue(&p_npe->txQHead, m); - } -} - -static void reset_rx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->rxQHead = NULL; - - HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) { - m = &p_npe->rx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id); - break; - } - } -} - -static void init_rx_mbufs(struct npe* p_npe) -{ - p_npe->rxQHead = NULL; - - p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->rx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_rx_mbufs(p_npe); -} - -static void init_tx_mbufs(struct npe* p_npe) -{ - p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->tx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_tx_mbufs(p_npe); -} - -/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */ -static int __eth_to_npe(int eth_id) -{ - switch(eth_id) { - case IX_ETH_PORT_1: - return IX_NPEMH_NPEID_NPEB; - - case IX_ETH_PORT_2: - return IX_NPEMH_NPEID_NPEC; - - case IX_ETH_PORT_3: - return IX_NPEMH_NPEID_NPEA; - } - return 0; -} - -/* Poll the CSR machinery. */ -static void npe_poll(int eth_id) -{ - if (qDispatcherFunc != NULL) { - ixNpeMhMessagesReceive(__eth_to_npe(eth_id)); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - } -} - -/* ethAcc RX callback */ -static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - struct npe* p_npe = (struct npe *)cbTag; - - if (IX_OSAL_MBUF_MLEN(m) > 0) { - mbuf_enqueue(&p_npe->rxQHead, m); - - if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) { - debug("Rx overflow: rx_write=%d rx_read=%d\n", - p_npe->rx_write, p_npe->rx_read); - } else { - debug("Received message #%d (len=%d)\n", p_npe->rx_write, - IX_OSAL_MBUF_MLEN(m)); - memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m), - IX_OSAL_MBUF_MLEN(m)); - p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m); - p_npe->rx_write++; - if (p_npe->rx_write == PKTBUFSRX) - p_npe->rx_write = 0; - -#ifdef CONFIG_PRINT_RX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; i<60; i++) { - debug("%02x ", *ptr++); - } - debug("\n"); - } -#endif - } - - m = mbuf_dequeue(&p_npe->rxQHead); - } else { - debug("Received frame with length 0!!!\n"); - m = mbuf_dequeue(&p_npe->rxQHead); - } - - /* Now return mbuf to NPE */ - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - debug("npe_rx_callback: Error returning mbuf.\n"); - } -} - -/* ethAcc TX callback */ -static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - struct npe* p_npe = (struct npe *)cbTag; - - debug("%s\n", __FUNCTION__); - - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - mbuf_enqueue(&p_npe->txQHead, m); -} - - -static int npe_set_mac_address(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - IxEthAccMacAddr npeMac; - - debug("%s\n", __FUNCTION__); - - /* Set MAC address */ - memcpy(npeMac.macAddress, dev->enetaddr, 6); - - if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) { - printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n", - npeMac.macAddress[0], npeMac.macAddress[1], - npeMac.macAddress[2], npeMac.macAddress[3], - npeMac.macAddress[4], npeMac.macAddress[5]); - return 0; - } - - return 1; -} - -/* Boot-time CSR library initialization. */ -static int npe_csr_load(void) -{ - int i; - - if (ixQMgrInit() != IX_SUCCESS) { - debug("Error initialising queue manager!\n"); - return 0; - } - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) { - printf("Error initialising NPE Message handler!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-B!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-C!\n"); - return 0; - } - - /* don't need this for U-Boot */ - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false); - - if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet access driver!\n"); - return 0; - } - - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (!npe_used[i] || !npe_exists[i]) - continue; - if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet port%d!\n", i); - } - if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) { - printf("Error setting scheduling discipline for port %d.\n", i); - } - if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error disabling RX FCS for port %d.\n", i); - } - if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error enabling TX FCS for port %d.\n", i); - } - } - - return 1; -} - -static int npe_init(struct eth_device *dev, bd_t * bis) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - u16 reg_short; - int speed; - int duplex; - - debug("%s: 1\n", __FUNCTION__); - -#ifdef CONFIG_MII_NPE0_FIXEDLINK - if (0 == p_npe->eth_id) { - speed = CONFIG_MII_NPE0_SPEED; - duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF; - } else -#endif -#ifdef CONFIG_MII_NPE1_FIXEDLINK - if (1 == p_npe->eth_id) { - speed = CONFIG_MII_NPE1_SPEED; - duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF; - } else -#endif - { - miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and - * autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) && - !(reg_short & BMSR_ANEGCOMPLETE)) { - puts("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts(" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc('.'); - miiphy_read(dev->name, p_npe->phy_no, - MII_BMSR, ®_short); - } - udelay(1000); /* 1 ms */ - } - puts(" done\n"); - /* another 500 ms (results in faster booting) */ - udelay(500000); - } - speed = miiphy_speed(dev->name, p_npe->phy_no); - duplex = miiphy_duplex(dev->name, p_npe->phy_no); - } - - if (p_npe->print_speed) { - p_npe->print_speed = 0; - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - } - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - /* initialize mbuf pool */ - init_rx_mbufs(p_npe); - init_tx_mbufs(p_npe); - - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register RX callback!\n"); - return -1; - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register TX callback!\n"); - return -1; - } - - npe_set_mac_address(dev); - - if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - printf("can't enable port!\n"); - return -1; - } - - p_npe->active = 1; - - return 0; -} - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ -/* Uninitialize CSR library. */ -static void npe_csr_unload(void) -{ - ixEthAccUnload(); - ixEthDBUnload(); - ixNpeMhUnload(); - ixQMgrUnload(); -} - -/* callback which is used by ethAcc to recover RX buffers when stopping */ -static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - debug("%s\n", __FUNCTION__); -} - -/* callback which is used by ethAcc to recover TX buffers when stopping */ -static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - debug("%s\n", __FUNCTION__); -} -#endif - -static void npe_halt(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - - debug("%s\n", __FUNCTION__); - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(100); - } - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering rx callback!\n"); - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering tx callback!\n"); - } - - if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - debug("npe_stop: Error disabling NPEB!\n"); - } - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(10000); - } - - /* - * For U-Boot only, we are probably launching Linux or other OS that - * needs a clean slate for its NPE library. - */ -#if 0 /* test-only */ - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (npe_used[i] && npe_exists[i]) - if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS) - printf("Failed to stop and reset NPE B.\n"); - } -#endif - -#endif - p_npe->active = 0; -} - - -static int npe_send(struct eth_device *dev, void *packet, int len) -{ - struct npe *p_npe = (struct npe *)dev->priv; - u8 *dest; - int err; - IX_OSAL_MBUF *m; - - debug("%s\n", __FUNCTION__); - m = mbuf_dequeue(&p_npe->txQHead); - dest = IX_OSAL_MBUF_MDATA(m); - IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len; - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL; - - memcpy(dest, (char *)packet, len); - - if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY)) - != IX_ETH_ACC_SUCCESS) { - printf("npe_send: Can't submit frame. err[%d]\n", err); - mbuf_enqueue(&p_npe->txQHead, m); - return 0; - } - -#ifdef DEBUG_PRINT_TX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; ieth_id); - - return len; -} - -static int npe_rx(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - - debug("%s\n", __FUNCTION__); - npe_poll(p_npe->eth_id); - - debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read); - while (p_npe->rx_write != p_npe->rx_read) { - debug("Reading message #%d\n", p_npe->rx_read); - NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]); - p_npe->rx_read++; - if (p_npe->rx_read == PKTBUFSRX) - p_npe->rx_read = 0; - } - - return 0; -} - -int npe_initialize(bd_t * bis) -{ - static int virgin = 0; - struct eth_device *dev; - int eth_num = 0; - struct npe *p_npe = NULL; - uchar enetaddr[6]; - - for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) { - - /* See if we can actually bring up the interface, otherwise, skip it */ -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) { - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) - continue; - } else -#endif - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - continue; - - /* Allocate device structure */ - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (dev == NULL) { - printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - /* Allocate our private use data */ - p_npe = (struct npe *)malloc(sizeof(struct npe)); - if (p_npe == NULL) { - printf("%s: Cannot allocate private hw data for eth_device %d", - __FUNCTION__, eth_num); - free(dev); - return -1; - } - memset(p_npe, 0, sizeof(struct npe)); - - p_npe->eth_id = eth_num; - memcpy(dev->enetaddr, enetaddr, 6); -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) - p_npe->phy_no = CONFIG_PHY1_ADDR; - else -#endif - p_npe->phy_no = CONFIG_PHY_ADDR; - - sprintf(dev->name, "NPE%d", eth_num); - dev->priv = (void *)p_npe; - dev->init = npe_init; - dev->halt = npe_halt; - dev->send = npe_send; - dev->recv = npe_rx; - - p_npe->print_speed = 1; - - if (0 == virgin) { - virgin = 1; - - if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) { - switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) { - case IX_FEATURE_CTRL_SILICON_TYPE_B0: - default: /* newer than B0 */ - /* - * If it is B0 or newer Silicon, we - * only enable port when its - * corresponding Eth Coprocessor is - * available. - */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - break; - case IX_FEATURE_CTRL_SILICON_TYPE_A0: - /* - * If it is A0 Silicon, we enable both as both Eth Coprocessors - * are available. - */ - npe_exists[IX_ETH_PORT_1] = true; - npe_exists[IX_ETH_PORT_2] = true; - break; - } - } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - } - - npe_used[IX_ETH_PORT_1] = 1; - npe_used[IX_ETH_PORT_2] = 1; - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) - & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - if (!npe_csr_load()) - return 0; - } - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); -#endif - - } /* end for each supported device */ - - return 1; -} diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 32c2ab9944..b80980d552 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -13,6 +13,7 @@ static int ar8021_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + phydev->supported = phydev->drv->features; return 0; } @@ -40,7 +41,7 @@ static int ar8035_config(struct phy_device *phydev) static struct phy_driver AR8021_driver = { .name = "AR8021", .uid = 0x4dd040, - .mask = 0x4fffff, + .mask = 0x4ffff0, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, @@ -52,7 +53,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8021_config, + .config = genphy_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 9deee9bd2a..d9135cb57d 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -248,17 +248,26 @@ struct smc91111_priv{ #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) +#elif CONFIG_ARM64 +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) #endif #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) #ifdef CONFIG_ADNPESC1 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} +#define SMC_outw(a, d, r) \ + ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ + SSYNC(); \ + }) +#elif CONFIG_ARM64 +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+(r))) = d) #endif #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ word __w = SMC_inw((a),(r)&~1); \ diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index a1766052fd..dbda9e6f24 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -16,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #undef DEBUG #define ENET_ADDR_LENGTH 6 @@ -579,24 +577,27 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, } #ifdef CONFIG_OF_CONTROL -int xilinx_emaclite_init(bd_t *bis) +int xilinx_emaclite_of_init(const void *blob) { int offset = 0; u32 ret = 0; u32 reg; do { - offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + offset = fdt_node_offset_by_compatible(blob, offset, "xlnx,xps-ethernetlite-1.00.a"); if (offset != -1) { - reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg"); + reg = fdtdec_get_addr(blob, offset, "reg"); if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 rxpp = fdtdec_get_int(blob, offset, "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 txpp = fdtdec_get_int(blob, offset, "xlnx,tx-ping-pong", 0); - ret |= xilinx_emaclite_initialize(bis, reg, + ret |= xilinx_emaclite_initialize(NULL, reg, txpp, rxpp); + } else { + debug("EMACLITE: Can't get base address\n"); + return -1; } } } while (offset != -1); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 4ce12f9a73..7eb6f1f9ad 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -597,3 +599,43 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) return 1; } + +#ifdef CONFIG_OF_CONTROL +int zynq_gem_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg, phy_reg; + + debug("ZYNQ GEM: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "xlnx,ps7-ethernet-1.00.a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + offset = fdtdec_lookup_phandle(blob, offset, + "phy-handle"); + if (offset != -1) + phy_reg = fdtdec_get_addr(blob, offset, + "reg"); + else + phy_reg = 0; + + debug("ZYNQ GEM: addr %x, phyaddr %x\n", + reg, phy_reg); + + ret |= zynq_gem_initialize(NULL, reg, + phy_reg, 0); + + } else { + debug("ZYNQ GEM: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 6182a5904d..e73a498619 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o -obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 2085cd6b9b..6317fb1324 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -510,8 +510,8 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); - printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, - pci_info->regs); + printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, + (temp16 & 0xf), pci_info->regs); hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c deleted file mode 100644 index d71fda2846..0000000000 --- a/drivers/pci/pci_ixp.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * IXP PCI Init - * - * (C) Copyright 2011 - * Michael Schwingen, michael@schwingen.org - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void non_prefetch_read(unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write(unsigned int addr, unsigned int cmd, - unsigned int data); - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x00000000 -#define PCI_MEMORY_SIZE 0x04000000 - -#define PCI_MEM_BUS 0x48000000 -#define PCI_MEM_PHY 0x00000000 -#define PCI_MEM_SIZE 0x04000000 - -#define PCI_IO_BUS 0x00000000 -#define PCI_IO_PHY 0x00000000 -#define PCI_IO_SIZE 0x00010000 - -/* build address value for config sycle */ -static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg) -{ - unsigned int bus = PCI_BUS(bdf); - unsigned int dev = PCI_DEV(bdf); - unsigned int func = PCI_FUNC(bdf); - unsigned int addr; - - if (bus) { /* secondary bus, use type 1 config cycle */ - addr = bdf | (reg & ~3) | 1; - } else { - /* - primary bus, type 0 config cycle. address bits 31:28 - specify the device 10:8 specify the function - */ - addr = BIT((31 - dev)) | (func << 8) | (reg & ~3); - } - - return addr; -} - -static int pci_config_status(void) -{ - unsigned int regval; - - regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET); - if ((regval & PCI_ISR_PFE) == 0) - return OK; - - /* no device present, make sure that the master abort bit is reset */ - writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET); - return ERROR; -} - -static int pci_ixp_hose_read_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int *val) -{ - unsigned int retval; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where); - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval); - *val = retval; - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short *val) -{ - unsigned int n; - unsigned int retval; - unsigned int addr; - unsigned int byteEnables; - int stat; - - debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - - /*Pick out the word we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char *val) -{ - unsigned int retval; - unsigned int n; - unsigned int byteEnables; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits, active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - /*Pick out the byte we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_write_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int val) -{ - unsigned int addr; - int stat; - - debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x", - bdf, where, val); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static void non_prefetch_read(unsigned int addr, - unsigned int cmd, unsigned int *data) -{ - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - - /*set up and execute the read */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - - /*The result of the read is now in np_rdata */ - *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET); - - return; -} - -static void non_prefetch_write(unsigned int addr, - unsigned int cmd, unsigned int data) -{ - - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - /*set up the write */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - /*Execute the write by writing to NP_WDATA */ - writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET); - - return; -} - -static void crp_write(unsigned int offset, unsigned int data) -{ - /* - * The CRP address register bit 16 indicates that we want to do a - * write - */ - writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET); - writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET); -} - -void pci_ixp_init(struct pci_controller *hose) -{ - unsigned int csr; - - /* - * Specify that the AHB bus is operating in big endian mode. Set up - * byte lane swapping between little-endian PCI and the big-endian - * AHB bus - */ -#ifdef __ARMEB__ - csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; -#else - csr = PCI_CSR_ABE; -#endif - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET); - - /* - * We configure the PCI inbound memory windows to be - * 1:1 mapped to SDRAM - */ - crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000); - crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000); - crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000); - crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000); - - /* - * Enable CSR window at 64 MiB to allow PCI masters - * to continue prefetching past 64 MiB boundary. - */ - crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000); - /* - * Enable the IO window to be way up high, at 0xfffffc00 - */ - crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01); - - /*Setup PCI-AHB and AHB-PCI address mappings */ - writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET); - - writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET); - - writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET); - - crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay(1000); - - /* clear error bits in status register */ - writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE, - PCI_CSR_BASE + PCI_ISR_OFFSET); - - /* - * Set Initialize Complete in PCI Control Register: allow IXP4XX to - * respond to PCI configuration cycles. - */ - csr |= PCI_CSR_IC; - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - hose->first_busno = 0; - hose->last_busno = 0; - - /* System memory space */ - pci_set_region(hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_set_ops(hose, - pci_ixp_hose_read_config_byte, - pci_ixp_hose_read_config_word, - pci_ixp_hose_read_config_dword, - pci_ixp_hose_write_config_byte, - pci_ixp_hose_write_config_word, - pci_ixp_hose_write_config_dword); - - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 0000000000..c48737e6c9 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,617 @@ +/* + * Freescale i.MX6 PCI Express Root-Complex driver + * + * Copyright (C) 2013 Marek Vasut + * + * Based on upstream Linux kernel driver: + * pci-imx6.c: Sean Cross + * pcie-designware.c: Jingoo Han + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_ADDR 0x01000000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_ADDR 0x01100000 +#define MX6_MEM_SIZE 0xe00000 +#define MX6_ROOT_ADDR 0x01f00000 +#define MX6_ROOT_SIZE 0xfc000 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) + +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19 + +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16 + +/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D + +#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +/* + * PHY access functions + */ +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) +{ + u32 val; + u32 max_iterations = 10; + u32 wait_counter = 0; + + do { + val = readl(dbi_base + PCIE_PHY_STAT); + val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; + wait_counter++; + + if (val == exp_val) + return 0; + + udelay(1); + } while (wait_counter < max_iterations); + + return -ETIMEDOUT; +} + +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) +{ + u32 val; + int ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) +{ + u32 val, phy_ctl; + int ret; + + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + /* assert Read signal */ + phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; + writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = readl(dbi_base + PCIE_PHY_STAT); + *data = val & 0xffff; + + /* deassert Read signal */ + writel(0x00, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) +{ + u32 var; + int ret; + + /* write addr */ + /* cap addr */ + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* capture data */ + var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); + writel(var, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert cap data */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + /* assert wr signal */ + var = 0x1 << PCIE_PHY_CTRL_WR_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack */ + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert wr signal */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + writel(0x0, dbi_base + PCIE_PHY_CTRL); + + return 0; +} + +static int imx6_pcie_link_up(void) +{ + u32 rc, ltssm; + int rx_valid, temp; + + /* link is debug bit 36, debug register 1 starts at bit 32 */ + rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) + return -EAGAIN; + + /* + * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. + * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). + * If (MAC/LTSSM.state == Recovery.RcvrLock) + * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition + * to gen2 is stuck + */ + pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); + ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; + + if (rx_valid & 0x01) + return 0; + + if (ltssm != 0x0d) + return 0; + + printf("transition to gen2 is stuck, reset PHY!\n"); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + udelay(3000); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + return 0; +} + +/* + * iATU region setup + */ +static int imx_pcie_regions_setup(void) +{ + /* + * i.MX6 defines 16MB in the AXI address map for PCIe. + * + * That address space excepted the pcie registers is + * split and defined into different regions by iATU, + * with sizes and offsets as follows: + * + * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO + * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM + * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers + */ + + /* CMD reg:I/O space, MEM space, and Bus Master Enable */ + setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, + PCI_CLASS_BRIDGE_PCI << 16); + + /* Region #0 is used for Outbound CFG space access. */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); + writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); + + writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); + + return 0; +} + +/* + * PCI Express accessors + */ +static uint32_t get_bus_address(pci_dev_t d, int where) +{ + uint32_t va_address; + + /* Reconfigure Region #0 */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + if (PCI_BUS(d) < 2) + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + else + writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); + + if (PCI_BUS(d) == 0) { + va_address = MX6_DBI_ADDR; + } else { + writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; + } + + va_address += (where & ~0x3); + + return va_address; +} + +static int imx_pcie_addr_valid(pci_dev_t d) +{ + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) + return -EINVAL; + if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) + return -EINVAL; + return 0; +} + +/* + * Replace the original ARM DABT handler with a simple jump-back one. + * + * The problem here is that if we have a PCIe bridge attached to this PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly. + * + * To work around the problem, we backup the current DABT handler address + * and replace it with our own DABT handler, which only bounces right back + * into the code. + */ +static void imx_pcie_fix_dabt_handler(bool set) +{ + extern uint32_t *_data_abort; + uint32_t *data_abort_addr = (uint32_t *)&_data_abort; + + static const uint32_t data_abort_bounce_handler = 0xe25ef004; + uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; + + static uint32_t data_abort_backup; + + if (set) { + data_abort_backup = *data_abort_addr; + *data_abort_addr = data_abort_bounce_addr; + } else { + *data_abort_addr = data_abort_backup; + } +} + +static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 *val) +{ + uint32_t va_address; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) { + *val = 0xffffffff; + return ret; + } + + va_address = get_bus_address(d, where); + + /* + * Read the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. Note that writing the + * "val" with valid value is also imperative here as in case we + * did got DABT, the val would contain random value. + */ + imx_pcie_fix_dabt_handler(true); + writel(0xffffffff, val); + *val = readl(va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 val) +{ + uint32_t va_address = 0; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) + return ret; + + va_address = get_bus_address(d, where); + + /* + * Write the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. + */ + imx_pcie_fix_dabt_handler(true); + writel(val, va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +/* + * Initial bus setup + */ +static int imx6_pcie_assert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + return 0; +} + +static int imx6_pcie_init_phy(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_DEVICE_TYPE_MASK, + IOMUXC_GPR12_DEVICE_TYPE_RC); + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_LOS_LEVEL_MASK, + IOMUXC_GPR12_LOS_LEVEL_9); + + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | + (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), + &iomuxc_regs->gpr[8]); + + return 0; +} + +__weak int imx6_pcie_toggle_power(void) +{ +#ifdef CONFIG_PCIE_IMX_POWER_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); + mdelay(20); +#endif + return 0; +} + +__weak int imx6_pcie_toggle_reset(void) +{ + /* + * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' + * for detailed understanding of the PCIe CR reset logic. + * + * The PCIe #PERST reset line _MUST_ be connected, otherwise your + * design does not conform to the specification. You must wait at + * least 20 mS after de-asserting the #PERST so the EP device can + * do self-initialisation. + * + * In case your #PERST pin is connected to a plain GPIO pin of the + * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's + * configuration file and the condition below will handle the rest + * of the reset toggling. + * + * In case your #PERST toggling logic is more complex, for example + * connected via CPLD or somesuch, you can override this function + * in your board file and implement reset logic as needed. You must + * not forget to wait at least 20 mS after de-asserting #PERST in + * this case either though. + * + * In case your #PERST line of the PCIe EP device is not connected + * at all, your design is broken and you should fix your design, + * otherwise you will observe problems like for example the link + * not coming up after rebooting the system back from running Linux + * that uses the PCIe as well OR the PCIe link might not come up in + * Linux at all in the first place since it's in some non-reset + * state due to being previously used in U-Boot. + */ +#ifdef CONFIG_PCIE_IMX_PERST_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); + mdelay(20); +#else + puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); +#endif + return 0; +} + +static int imx6_pcie_deassert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + imx6_pcie_toggle_power(); + + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + enable_pcie_clock(); + + /* + * Wait for the clock to settle a bit, when the clock are sourced + * from the CPU, we need about 30mS to settle. + */ + mdelay(50); + + imx6_pcie_toggle_reset(); + + return 0; +} + +static int imx_pcie_link_up(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t tmp; + int count = 0; + + imx6_pcie_assert_core_reset(); + imx6_pcie_init_phy(); + imx6_pcie_deassert_core_reset(); + + imx_pcie_regions_setup(); + + /* + * FIXME: Force the PCIe RC to Gen1 operation + * The RC must be forced into Gen1 mode before bringing the link + * up, otherwise no downstream devices are detected. After the + * link is up, a managed Gen1->Gen2 transition can be initiated. + */ + tmp = readl(MX6_DBI_ADDR + 0x7c); + tmp &= ~0xf; + tmp |= 0x1; + writel(tmp, MX6_DBI_ADDR + 0x7c); + + /* LTSSM enable, starting link. */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + while (!imx6_pcie_link_up()) { + udelay(10); + count++; + if (count >= 2000) { + debug("phy link never came up\n"); + debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); + return -EINVAL; + } + } + + return 0; +} + +void imx_pcie_init(void) +{ + /* Static instance of the controller. */ + static struct pci_controller pcc; + struct pci_controller *hose = &pcc; + int ret; + + memset(&pcc, 0, sizeof(pcc)); + + /* PCI I/O space */ + pci_set_region(&hose->regions[0], + MX6_IO_ADDR, MX6_IO_ADDR, + MX6_IO_SIZE, PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], + MX6_MEM_ADDR, MX6_MEM_ADDR, + MX6_MEM_SIZE, PCI_REGION_MEM); + + /* System memory space */ + pci_set_region(&hose->regions[2], + MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, + 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + imx_pcie_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + imx_pcie_write_config); + + /* Start the controller. */ + ret = imx_pcie_link_up(); + + if (!ret) { + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); + } +} + +/* Probe function. */ +void pci_init_board(void) +{ + imx_pcie_init(); +} diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c index f2648329d4..94015aa41a 100644 --- a/drivers/power/battery/bat_trats2.c +++ b/drivers/power/battery/bat_trats2.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include static struct battery battery_trats; diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b45ffad67..4129bdabfb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c new file mode 100644 index 0000000000..22c1f15eeb --- /dev/null +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int pmic_init(unsigned char bus) +{ + static const char name[] = "PFUZE100_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 29ccc831af..fe1f316021 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -140,6 +140,9 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_SUCCESS; } + if (argc < 3) + return CMD_RET_USAGE; + name = argv[1]; cmd = argv[2]; diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index d5a2725c97..003d322d23 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6b4cadefdb..571c18fa93 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_IXP_SERIAL) += serial_ixp.o obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o @@ -34,6 +33,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o +obj-$(CONFIG_ARC_SERIAL) += serial_arc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 8de2eca2ac..d4ed60c303 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -17,62 +18,34 @@ DECLARE_GLOBAL_DATA_PTR; static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; +static void oc_serial_setbrg(void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + unsigned baudrate; + #if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF assignment*/ - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - (unsigned)CONFIG_BAUDRATE) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) - break; - } - best_m = - ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(baud, &uart->baud); - - return; -} - + /* Everything's already setup for fixed-baud PTF assignment */ + baudrate = CONFIG_BAUDRATE; #else - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - + baudrate = gd->baudrate; +#endif /* compute best N and M couple */ best_n = YANU_MAX_PRESCALER_N; for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - gd->baudrate) { + baudrate) { best_n = n; break; } } for (k = 0;; k++) { - if (gd->baudrate <= (max_uns >> (15+n-k))) + if (baudrate <= (max_uns >> (15+n-k))) break; } best_m = - (gd->baudrate * (1 << (15 + n - k))) / + (baudrate * (1 << (15 + n - k))) / ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; @@ -81,9 +54,6 @@ static void oc_serial_setbrg(void) return; } - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - static int oc_serial_init(void) { unsigned action,control; @@ -154,7 +124,7 @@ static int oc_serial_tstc(void) ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); } -statoc int oc_serial_getc(void) +static int oc_serial_getc(void) { while (serial_tstc() == 0) WATCHDOG_RESET (); diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index ffff5e1497..51fd871dff 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -11,9 +11,11 @@ */ #include +#include #include #include #include +#include /* * @@ -30,7 +32,10 @@ static unsigned int serial_buf_read; static int sandbox_serial_init(void) { - os_tty_raw(0); + struct sandbox_state *state = state_get_current(); + + if (state->term_raw != STATE_TERM_COOKED) + os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS); return 0; } @@ -60,6 +65,9 @@ static int sandbox_serial_tstc(void) ssize_t count; os_usleep(100); +#ifdef CONFIG_LCD + lcd_sync(); +#endif if (next_index == serial_buf_read) return 1; /* buffer full */ diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df2b84aaaf..df05bde461 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -150,7 +150,6 @@ serial_initfunc(oc_serial_initialize); serial_initfunc(sandbox_serial_initialize); serial_initfunc(clps7111_serial_initialize); serial_initfunc(imx_serial_initialize); -serial_initfunc(ixp_serial_initialize); serial_initfunc(ks8695_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); serial_initfunc(max3100_serial_initialize); @@ -160,6 +159,7 @@ serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); +serial_initfunc(arc_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -243,7 +243,6 @@ void serial_initialize(void) sandbox_serial_initialize(); clps7111_serial_initialize(); imx_serial_initialize(); - ixp_serial_initialize(); ks8695_serial_initialize(); lh7a40x_serial_initialize(); max3100_serial_initialize(); @@ -253,6 +252,7 @@ void serial_initialize(void) sh_serial_initialize(); arm_dcc_initialize(); mxs_auart_initialize(); + arc_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c new file mode 100644 index 0000000000..2ddbf32a50 --- /dev/null +++ b/drivers/serial/serial_arc.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct arc_serial_regs { + unsigned int id0; + unsigned int id1; + unsigned int id2; + unsigned int id3; + unsigned int data; + unsigned int status; + unsigned int baudl; + unsigned int baudh; +}; + +/* Bit definitions of STATUS register */ +#define UART_RXEMPTY (1 << 5) +#define UART_OVERFLOW_ERR (1 << 1) +#define UART_TXEMPTY (1 << 7) + +struct arc_serial_regs *regs; + +static void arc_serial_setbrg(void) +{ + int arc_console_baud; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; + writeb(arc_console_baud & 0xff, ®s->baudl); + +#ifdef CONFIG_ARC + /* + * UART ISS(Instruction Set simulator) emulation has a subtle bug: + * A existing value of Baudh = 0 is used as a indication to startup + * it's internal state machine. + * Thus if baudh is set to 0, 2 times, it chokes. + * This happens with BAUD=115200 and the formaula above + * Until that is fixed, when running on ISS, we will set baudh to !0 + */ + if (gd->arch.running_on_hw) + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); + else + writeb(1, ®s->baudh); +#else + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); +#endif +} + +static int arc_serial_init(void) +{ + regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; + serial_setbrg(); + return 0; +} + +static void arc_serial_putc(const char c) +{ + if (c == '\n') + arc_serial_putc('\r'); + + while (!(readb(®s->status) & UART_TXEMPTY)) + ; + + writeb(c, ®s->data); +} + +static int arc_serial_tstc(void) +{ + return !(readb(®s->status) & UART_RXEMPTY); +} + +static int arc_serial_getc(void) +{ + while (!arc_serial_tstc()) + ; + + /* Check for overflow errors */ + if (readb(®s->status) & UART_OVERFLOW_ERR) + return 0; + + return readb(®s->data) & 0xFF; +} + +static struct serial_device arc_serial_drv = { + .name = "arc_serial", + .start = arc_serial_init, + .stop = NULL, + .setbrg = arc_serial_setbrg, + .putc = arc_serial_putc, + .puts = default_serial_puts, + .getc = arc_serial_getc, + .tstc = arc_serial_tstc, +}; + +void arc_serial_initialize(void) +{ + serial_register(&arc_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &arc_serial_drv; +} diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c deleted file mode 100644 index b9d0f5bfa5..0000000000 --- a/drivers/serial/serial_ixp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * 14.7456 MHz - * Baud Rate = -------------- - * 16 x Divisor - */ -#define SERIAL_CLOCK 921600 - -DECLARE_GLOBAL_DATA_PTR; - -static void ixp_serial_setbrg(void) -{ - unsigned int quot = 0; - int uart = CONFIG_SYS_IXP425_CONSOLE; - - if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) - quot = SERIAL_CLOCK / gd->baudrate; - else - hang (); - - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ - - /* set baud rate */ - LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - DLL(uart) = quot & 0xff; - DLH(uart) = quot >> 8; - LCR(uart) = LCR_WLS0 | LCR_WLS1; -#ifdef CONFIG_SERIAL_RTS_ACTIVE - MCR(uart) = MCR_RTS; /* set RTS active */ -#else - MCR(uart) = 0; /* set RTS inactive */ -#endif - IER(uart) = IER_UUE; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int ixp_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void ixp_serial_putc(const char c) -{ - /* wait for room in the tx FIFO on UART */ - while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - THR(CONFIG_SYS_IXP425_CONSOLE) = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_tstc(void) -{ - return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_getc(void) -{ - while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; -} - -static struct serial_device ixp_serial_drv = { - .name = "ixp_serial", - .start = ixp_serial_init, - .stop = NULL, - .setbrg = ixp_serial_setbrg, - .putc = ixp_serial_putc, - .puts = default_serial_puts, - .getc = ixp_serial_getc, - .tstc = ixp_serial_tstc, -}; - -void ixp_serial_initialize(void) -{ - serial_register(&ixp_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ixp_serial_drv; -} diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 89f5d68dd0..98c62b4c14 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -100,8 +100,8 @@ static int serial_init_dev(const int dev_index) { struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - /* enable FIFOs */ - writel(0x1, &uart->ufcon); + /* enable FIFOs, auto clear Rx FIFO */ + writel(0x3, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 22c6bf099c..53a8af02d6 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -13,6 +14,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -182,6 +185,30 @@ DECLARE_PSSERIAL_FUNCTIONS(1); struct serial_device uart_zynq_serial1_device = INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); +#ifdef CONFIG_OF_CONTROL +__weak struct serial_device *default_serial_console(void) +{ + const void *blob = gd->fdt_blob; + int node; + unsigned int base_addr; + + node = fdt_path_offset(blob, "serial0"); + if (node < 0) + return NULL; + + base_addr = fdtdec_get_addr(blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) + return NULL; + + if (base_addr == ZYNQ_SERIAL_BASEADDR0) + return &uart_zynq_serial0_device; + + if (base_addr == ZYNQ_SERIAL_BASEADDR1) + return &uart_zynq_serial1_device; + + return NULL; +} +#else __weak struct serial_device *default_serial_console(void) { #if defined(CONFIG_ZYNQ_SERIAL_UART0) @@ -194,6 +221,7 @@ __weak struct serial_device *default_serial_console(void) #endif return NULL; } +#endif void zynq_serial_initalize(void) { diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 819dec663f..21a3ef4d97 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -20,8 +20,8 @@ #include #elif defined(CONFIG_DW_UDC) #include -#elif defined(CONFIG_MV_UDC) -#include +#elif defined(CONFIG_CI_UDC) +#include #endif #include diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 6d252926c6..981ed614b1 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -6,6 +6,8 @@ # obj-$(CONFIG_SOUND) += sound.o -obj-$(CONFIG_I2S) += samsung-i2s.o +obj-$(CONFIG_I2S) += sound-i2s.o +obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o +obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98095) += max98095.o diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c new file mode 100644 index 0000000000..fe5c9e9b38 --- /dev/null +++ b/drivers/sound/sandbox.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int sound_play(uint32_t msec, uint32_t frequency) +{ + sandbox_sdl_sound_start(frequency); + mdelay(msec); + sandbox_sdl_sound_stop(); + + return 0; +} + +int sound_init(const void *blob) +{ + return sandbox_sdl_sound_init(); +} diff --git a/drivers/sound/sound-i2s.c b/drivers/sound/sound-i2s.c new file mode 100644 index 0000000000..749bbbd031 --- /dev/null +++ b/drivers/sound/sound-i2s.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wm8994.h" +#include "max98095.h" + +/* defines */ +#define SOUND_400_HZ 400 +#define SOUND_BITS_IN_BYTE 8 + +static struct i2stx_info g_i2stx_pri; + +/* + * get_sound_i2s_values gets values for i2s parameters + * + * @param i2stx_info i2s transmitter transfer param structure + * @param blob FDT blob if enabled else NULL + */ +static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob) +{ + int node; + int error = 0; + int base; + + node = fdt_path_offset(blob, "i2s"); + if (node <= 0) { + debug("EXYNOS_SOUND: No node for sound in device tree\n"); + return -1; + } + + /* + * Get the pre-defined sound specific values from FDT. + * All of these are expected to be correct otherwise + * wrong register values in i2s setup parameters + * may result in no sound play. + */ + base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Missing i2s base\n", __func__); + return -1; + } + i2s->base_address = base; + + i2s->audio_pll_clk = fdtdec_get_int(blob, + node, "samsung,i2s-epll-clock-frequency", -1); + error |= i2s->audio_pll_clk; + debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); + i2s->samplingrate = fdtdec_get_int(blob, + node, "samsung,i2s-sampling-rate", -1); + error |= i2s->samplingrate; + debug("samplingrate = %d\n", i2s->samplingrate); + i2s->bitspersample = fdtdec_get_int(blob, + node, "samsung,i2s-bits-per-sample", -1); + error |= i2s->bitspersample; + debug("bitspersample = %d\n", i2s->bitspersample); + i2s->channels = fdtdec_get_int(blob, + node, "samsung,i2s-channels", -1); + error |= i2s->channels; + debug("channels = %d\n", i2s->channels); + i2s->rfs = fdtdec_get_int(blob, + node, "samsung,i2s-lr-clk-framesize", -1); + error |= i2s->rfs; + debug("rfs = %d\n", i2s->rfs); + i2s->bfs = fdtdec_get_int(blob, + node, "samsung,i2s-bit-clk-framesize", -1); + error |= i2s->bfs; + debug("bfs = %d\n", i2s->bfs); + + i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1); + error |= i2s->id; + debug("id = %d\n", i2s->id); + + if (error == -1) { + debug("fail to get sound i2s node properties\n"); + return -1; + } + + return 0; +} + +/* + * Init codec + * + * @param blob FDT blob + * @param pi2s_tx i2s parameters required by codec + * @return int value, 0 for success + */ +static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) +{ + int ret; + const char *codectype; + int node; + + /* Get the node from FDT for sound */ + node = fdt_path_offset(blob, "i2s"); + if (node <= 0) { + debug("EXYNOS_SOUND: No node for sound in device tree\n"); + debug("node = %d\n", node); + return -1; + } + + /* + * Get the pre-defined sound codec specific values from FDT. + * All of these are expected to be correct otherwise sound + * can not be played + */ + codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL); + debug("device = %s\n", codectype); + if (!strcmp(codectype, "wm8994")) { + /* Check the codec type and initialise the same */ + ret = wm8994_init(blob, pi2s_tx->id + 1, + pi2s_tx->samplingrate, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->bitspersample, pi2s_tx->channels); + } else if (!strcmp(codectype, "max98095")) { + ret = max98095_init(blob, pi2s_tx->id + 1, + pi2s_tx->samplingrate, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->bitspersample); + } else { + debug("%s: Unknown codec type %s\n", __func__, codectype); + return -1; + } + + if (ret) { + debug("%s: Codec init failed\n", __func__); + return -1; + } + + return 0; +} + +int sound_init(const void *blob) +{ + int ret; + struct i2stx_info *pi2s_tx = &g_i2stx_pri; + + /* Get the I2S Values */ + if (get_sound_i2s_values(pi2s_tx, blob) < 0) { + debug(" FDT I2S values failed\n"); + return -1; + } + + if (codec_init(blob, pi2s_tx) < 0) { + debug(" Codec init failed\n"); + return -1; + } + + ret = i2s_tx_init(pi2s_tx); + if (ret) { + debug("%s: Failed to init i2c transmit: ret=%d\n", __func__, + ret); + return ret; + } + + + return ret; +} + +int sound_play(uint32_t msec, uint32_t frequency) +{ + unsigned int *data; + unsigned long data_size; + unsigned int ret = 0; + + /*Buffer length computation */ + data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels; + data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE); + data = malloc(data_size); + + if (data == NULL) { + debug("%s: malloc failed\n", __func__); + return -1; + } + + sound_create_square_wave((unsigned short *)data, + data_size / sizeof(unsigned short), + frequency); + + while (msec >= 1000) { + ret = i2s_transfer_tx_data(&g_i2stx_pri, data, + (data_size / sizeof(int))); + msec -= 1000; + } + if (msec) { + unsigned long size = + (data_size * msec) / (sizeof(int) * 1000); + + ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size); + } + + free(data); + + return ret; +} diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index 9b8ce5a9ef..9dda2dba82 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -5,193 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include -#include -#include -#include -#include -#include #include -#include -#include "wm8994.h" -#include "max98095.h" -/* defines */ -#define SOUND_400_HZ 400 -#define SOUND_BITS_IN_BYTE 8 - -static struct i2stx_info g_i2stx_pri; - -/* - * get_sound_i2s_values gets values for i2s parameters - * - * @param i2stx_info i2s transmitter transfer param structure - * @param blob FDT blob if enabled else NULL - */ -static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob) -{ -#ifdef CONFIG_OF_CONTROL - int node; - int error = 0; - int base; - - node = fdt_path_offset(blob, "i2s"); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - return -1; - } - - /* - * Get the pre-defined sound specific values from FDT. - * All of these are expected to be correct otherwise - * wrong register values in i2s setup parameters - * may result in no sound play. - */ - base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) { - debug("%s: Missing i2s base\n", __func__); - return -1; - } - i2s->base_address = base; - - i2s->audio_pll_clk = fdtdec_get_int(blob, - node, "samsung,i2s-epll-clock-frequency", -1); - error |= i2s->audio_pll_clk; - debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); - i2s->samplingrate = fdtdec_get_int(blob, - node, "samsung,i2s-sampling-rate", -1); - error |= i2s->samplingrate; - debug("samplingrate = %d\n", i2s->samplingrate); - i2s->bitspersample = fdtdec_get_int(blob, - node, "samsung,i2s-bits-per-sample", -1); - error |= i2s->bitspersample; - debug("bitspersample = %d\n", i2s->bitspersample); - i2s->channels = fdtdec_get_int(blob, - node, "samsung,i2s-channels", -1); - error |= i2s->channels; - debug("channels = %d\n", i2s->channels); - i2s->rfs = fdtdec_get_int(blob, - node, "samsung,i2s-lr-clk-framesize", -1); - error |= i2s->rfs; - debug("rfs = %d\n", i2s->rfs); - i2s->bfs = fdtdec_get_int(blob, - node, "samsung,i2s-bit-clk-framesize", -1); - error |= i2s->bfs; - debug("bfs = %d\n", i2s->bfs); - - i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1); - error |= i2s->id; - debug("id = %d\n", i2s->id); - - if (error == -1) { - debug("fail to get sound i2s node properties\n"); - return -1; - } -#else - i2s->base_address = samsung_get_base_i2s(); - i2s->audio_pll_clk = I2S_PLL_CLK; - i2s->samplingrate = I2S_SAMPLING_RATE; - i2s->bitspersample = I2S_BITS_PER_SAMPLE; - i2s->channels = I2S_CHANNELS; - i2s->rfs = I2S_RFS; - i2s->bfs = I2S_BFS; - i2s->id = 0; -#endif - return 0; -} - -/* - * Init codec - * - * @param blob FDT blob - * @param pi2s_tx i2s parameters required by codec - * @return int value, 0 for success - */ -static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) -{ - int ret; - const char *codectype; -#ifdef CONFIG_OF_CONTROL - int node; - - /* Get the node from FDT for sound */ - node = fdt_path_offset(blob, "i2s"); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - debug("node = %d\n", node); - return -1; - } - - /* - * Get the pre-defined sound codec specific values from FDT. - * All of these are expected to be correct otherwise sound - * can not be played - */ - codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL); - debug("device = %s\n", codectype); -#else - codectype = AUDIO_CODEC; -#endif - if (!strcmp(codectype, "wm8994")) { - /* Check the codec type and initialise the same */ - ret = wm8994_init(blob, pi2s_tx->id + 1, - pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample, pi2s_tx->channels); - } else if (!strcmp(codectype, "max98095")) { - ret = max98095_init(blob, pi2s_tx->id + 1, - pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample); - } else { - debug("%s: Unknown codec type %s\n", __func__, codectype); - return -1; - } - - if (ret) { - debug("%s: Codec init failed\n", __func__); - return -1; - } - - return 0; -} - -int sound_init(const void *blob) -{ - int ret; - struct i2stx_info *pi2s_tx = &g_i2stx_pri; - - /* Get the I2S Values */ - if (get_sound_i2s_values(pi2s_tx, blob) < 0) { - debug(" FDT I2S values failed\n"); - return -1; - } - - if (codec_init(blob, pi2s_tx) < 0) { - debug(" Codec init failed\n"); - return -1; - } - - ret = i2s_tx_init(pi2s_tx); - if (ret) { - debug("%s: Failed to init i2c transmit: ret=%d\n", __func__, - ret); - return ret; - } - - - return ret; -} - -/* - * Generates square wave sound data for 1 second - * - * @param data data buffer pointer - * @param size size of the buffer - * @param freq frequency of the wave - */ -static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq) +void sound_create_square_wave(unsigned short *data, int size, uint32_t freq) { const int sample = 48000; const unsigned short amplitude = 16000; /* between 1 and 32767 */ @@ -218,39 +35,3 @@ static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq) } } } - -int sound_play(uint32_t msec, uint32_t frequency) -{ - unsigned int *data; - unsigned long data_size; - unsigned int ret = 0; - - /*Buffer length computation */ - data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels; - data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE); - data = malloc(data_size); - - if (data == NULL) { - debug("%s: malloc failed\n", __func__); - return -1; - } - - sound_prepare_buffer((unsigned short *)data, - data_size / sizeof(unsigned short), frequency); - - while (msec >= 1000) { - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, - (data_size / sizeof(int))); - msec -= 1000; - } - if (msec) { - unsigned long size = - (data_size * msec) / (sizeof(int) * 1000); - - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size); - } - - free(data); - - return ret; -} diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 8a5eddcbfd..a2e9c00ea6 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -102,33 +102,26 @@ void AT91F_SpiEnable(int cs) { unsigned long mode; + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode &= ~AT91_SPI_PCS; + switch (cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 0: + mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16; break; - case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 1: + mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16; break; - case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 2: + mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16; break; case 3: - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16; break; } + writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR); + /* SPI_Enable */ writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); } diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index aa89d89a32..71a31d0127 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -140,12 +141,12 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 baud; - sclk = get_sclk(); + clk = get_spi_clk(); /* baud should be rounded up */ - baud = DIV_ROUND_UP(sclk, 2 * hz); + baud = DIV_ROUND_UP(clk, 2 * hz); if (baud < 2) baud = 2; else if (baud > (u16)-1) diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index 07b833d3a3..eba01d16f5 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -135,11 +136,11 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 clock; - sclk = get_sclk1(); - clock = sclk / hz; + clk = get_spi_clk(); + clock = clk / hz; if (clock) clock--; bss->clock = clock; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 95dd03f7b3..f3f029d634 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -115,7 +115,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, { u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); s32 reg_ctrl, reg_config; - u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; + u32 pre_div = 0, post_div = 0; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; if (max_hz == 0) { @@ -164,8 +165,10 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (mode & SPI_CPOL) + if (mode & SPI_CPOL) { sclkpol = 1; + sclkctl = 1; + } if (mode & SPI_CPHA) sclkpha = 1; @@ -180,6 +183,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, (ss_pol << (cs + MXC_CSPICON_SSPOL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | + (sclkctl << (cs + MXC_CSPICON_CTL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | (sclkpha << (cs + MXC_CSPICON_PHA)); diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index a3ad056473..651e46e4bd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -260,8 +260,9 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, } /* wait to finish of transfer */ - while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & - OMAP3_MCSPI_CHSTAT_EOT)); + while ((readl(&ds->regs->channel[ds->slave.cs].chstat) & + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)); /* Disable the channel otherwise the next immediate RX will get affected */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index 7895305a05..12e9bdad38 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -202,3 +202,16 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, return ret; } + +/** + * Set up a new SPI slave for an fdt node + * + * @param blob Device tree blob + * @param node SPI peripheral node to use + * @return 0 if ok, -1 on error + */ +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, + int spi_node) +{ + return NULL; +} diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5a5b482769..dfa5d0ca21 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 @@ -39,7 +41,8 @@ #define MM_SWITCH 0x01 #define MEM_CS 0x100 #define MEM_CS_UNSELECT 0xfffff0ff -#define MMAP_START_ADDR 0x5c000000 +#define MMAP_START_ADDR_DRA 0x5c000000 +#define MMAP_START_ADDR_AM43x 0x30000000 #define CORE_CTRL_IO 0x4a002558 #define QSPI_CMD_READ (0x3 << 0) @@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) struct spi_slave *slave = &qslave->slave; u32 memval = 0; - slave->memory_map = (void *)MMAP_START_ADDR; +#ifdef CONFIG_DRA7XX + slave->memory_map = (void *)MMAP_START_ADDR_DRA; +#else + slave->memory_map = (void *)MMAP_START_ADDR_AM43x; +#endif memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | @@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct ti_qspi_slave *qslave; +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); if (!qslave) { printf("SPI_error: Fail to allocate ti_qspi_slave\n"); @@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const uchar *txp = dout; uchar *rxp = din; uint status; - int timeout, val; + int timeout; + +#ifdef CONFIG_DRA7XX + int val; +#endif debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", slave->bus, slave->cs, bitlen, words, flags); @@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &qslave->base->memswitch); +#ifdef CONFIG_DRA7XX val = readl(CORE_CTRL_IO); val |= MEM_CS; writel(val, CORE_CTRL_IO); +#endif return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &qslave->base->memswitch); +#ifdef CONFIG_DRA7XX val = readl(CORE_CTRL_IO); val &= MEM_CS_UNSELECT; writel(val, CORE_CTRL_IO); +#endif return 0; } @@ -265,6 +285,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd |= QSPI_3_PIN; qslave->cmd |= 0xfff; +/* FIXME: This delay is required for successfull + * completion of read/write/erase. Once its root + * caused, it will be remove from the driver. + */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 03f54749f7..94551c4c0c 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o ifdef CONFIG_USB_ETHER_ASIX obj-y += asix.o endif +obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 659533a8d4..ce133f0069 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -468,8 +468,6 @@ static int asix_send(struct eth_device *eth, void *packet, int length) memcpy(msg, &packet_len, sizeof(packet_len)); memcpy(msg + sizeof(packet_len), (void *)packet, length); - if (length & 1) - length++; err = usb_bulk_msg(dev->pusb_dev, usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c new file mode 100644 index 0000000000..c353286b60 --- /dev/null +++ b/drivers/usb/eth/mcs7830.c @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2013 Gerhard Sittig + * based on the U-Boot Asix driver as well as information + * from the Linux Moschip driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices + */ + +#include +#include +#include +#include +#include + +#include "usb_ether.h" + +#define MCS7830_BASE_NAME "mcs" + +#define USBCALL_TIMEOUT 1000 +#define LINKSTATUS_TIMEOUT 5000 /* link status, connect timeout */ +#define LINKSTATUS_TIMEOUT_RES 50 /* link status, resolution in msec */ + +#define MCS7830_RX_URB_SIZE 2048 + +/* command opcodes */ +#define MCS7830_WR_BREQ 0x0d +#define MCS7830_RD_BREQ 0x0e + +/* register layout, numerical offset specs for USB API calls */ +struct mcs7830_regs { + uint8_t multicast_hashes[8]; + uint8_t packet_gap[2]; + uint8_t phy_data[2]; + uint8_t phy_command[2]; + uint8_t configuration; + uint8_t ether_address[6]; + uint8_t frame_drop_count; + uint8_t pause_threshold; +}; +#define REG_MULTICAST_HASH offsetof(struct mcs7830_regs, multicast_hashes) +#define REG_PHY_DATA offsetof(struct mcs7830_regs, phy_data) +#define REG_PHY_CMD offsetof(struct mcs7830_regs, phy_command) +#define REG_CONFIG offsetof(struct mcs7830_regs, configuration) +#define REG_ETHER_ADDR offsetof(struct mcs7830_regs, ether_address) +#define REG_FRAME_DROP_COUNTER offsetof(struct mcs7830_regs, frame_drop_count) +#define REG_PAUSE_THRESHOLD offsetof(struct mcs7830_regs, pause_threshold) + +/* bit masks and default values for the above registers */ +#define PHY_CMD1_READ 0x40 +#define PHY_CMD1_WRITE 0x20 +#define PHY_CMD1_PHYADDR 0x01 + +#define PHY_CMD2_PEND 0x80 +#define PHY_CMD2_READY 0x40 + +#define CONF_CFG 0x80 +#define CONF_SPEED100 0x40 +#define CONF_FDX_ENABLE 0x20 +#define CONF_RXENABLE 0x10 +#define CONF_TXENABLE 0x08 +#define CONF_SLEEPMODE 0x04 +#define CONF_ALLMULTICAST 0x02 +#define CONF_PROMISCUOUS 0x01 + +#define PAUSE_THRESHOLD_DEFAULT 0 + +/* bit masks for the status byte which follows received ethernet frames */ +#define STAT_RX_FRAME_CORRECT 0x20 +#define STAT_RX_LARGE_FRAME 0x10 +#define STAT_RX_CRC_ERROR 0x08 +#define STAT_RX_ALIGNMENT_ERROR 0x04 +#define STAT_RX_LENGTH_ERROR 0x02 +#define STAT_RX_SHORT_FRAME 0x01 + +/* + * struct mcs7830_private - private driver data for an individual adapter + * @config: shadow for the network adapter's configuration register + * @mchash: shadow for the network adapter's multicast hash registers + */ +struct mcs7830_private { + uint8_t config; + uint8_t mchash[8]; +}; + +/* + * mcs7830_read_reg() - read a register of the network adapter + * @dev: network device to read from + * @idx: index of the register to start reading from + * @size: number of bytes to read + * @data: buffer to read into + * Return: zero upon success, negative upon error + */ +static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx, + uint16_t size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size); + + debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); + + len = usb_control_msg(dev->pusb_dev, + usb_rcvctrlpipe(dev->pusb_dev, 0), + MCS7830_RD_BREQ, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, idx, buf, size, + USBCALL_TIMEOUT); + if (len != size) { + debug("%s() len=%d != sz=%d\n", __func__, len, size); + return -EIO; + } + memcpy(data, buf, size); + return 0; +} + +/* + * mcs7830_write_reg() - write a register of the network adapter + * @dev: network device to write to + * @idx: index of the register to start writing to + * @size: number of bytes to write + * @data: buffer holding the data to write + * Return: zero upon success, negative upon error + */ +static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx, + uint16_t size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size); + + debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); + + memcpy(buf, data, size); + len = usb_control_msg(dev->pusb_dev, + usb_sndctrlpipe(dev->pusb_dev, 0), + MCS7830_WR_BREQ, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, idx, buf, size, + USBCALL_TIMEOUT); + if (len != size) { + debug("%s() len=%d != sz=%d\n", __func__, len, size); + return -EIO; + } + return 0; +} + +/* + * mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution + * @dev: network device to talk to + * @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode + * @index: number of the PHY register to read or write + * Return: zero upon success, negative upon error + */ +static int mcs7830_phy_emit_wait(struct ueth_data *dev, + uint8_t rwflag, uint8_t index) +{ + int rc; + int retry; + uint8_t cmd[2]; + + /* send the PHY read/write request */ + cmd[0] = rwflag | PHY_CMD1_PHYADDR; + cmd[1] = PHY_CMD2_PEND | (index & 0x1f); + rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + if (rc < 0) + return rc; + + /* wait for the response to become available (usually < 1ms) */ + retry = 10; + do { + rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + if (rc < 0) + return rc; + if (cmd[1] & PHY_CMD2_READY) + return 0; + if (!retry--) + return -ETIMEDOUT; + mdelay(1); + } while (1); + /* UNREACH */ +} + +/* + * mcs7830_read_phy() - read a PHY register of the network adapter + * @dev: network device to read from + * @index: index of the PHY register to read from + * Return: non-negative 16bit register content, negative upon error + */ +static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index) +{ + int rc; + uint16_t val; + + /* issue the PHY read request and wait for its execution */ + rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index); + if (rc < 0) + return rc; + + /* fetch the PHY data which was read */ + rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val); + if (rc < 0) + return rc; + rc = le16_to_cpu(val); + debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc); + return rc; +} + +/* + * mcs7830_write_phy() - write a PHY register of the network adapter + * @dev: network device to write to + * @index: index of the PHY register to write to + * @val: value to write to the PHY register + * Return: zero upon success, negative upon error + */ +static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val) +{ + int rc; + + debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val); + + /* setup the PHY data which is to get written */ + val = cpu_to_le16(val); + rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val); + if (rc < 0) + return rc; + + /* issue the PHY write request and wait for its execution */ + rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index); + if (rc < 0) + return rc; + + return 0; +} + +/* + * mcs7830_write_config() - write to the network adapter's config register + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * the data which gets written is taken from the shadow config register + * within the device driver's private data + */ +static int mcs7830_write_config(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + rc = mcs7830_write_reg(dev, REG_CONFIG, + sizeof(priv->config), &priv->config); + if (rc < 0) { + debug("writing config to adapter failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_write_mchash() - write the network adapter's multicast filter + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * the data which gets written is taken from the shadow multicast hashes + * within the device driver's private data + */ +static int mcs7830_write_mchash(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH, + sizeof(priv->mchash), &priv->mchash); + if (rc < 0) { + debug("writing multicast hash to adapter failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation + * @eth: network device to run link negotiation on + * Return: zero upon success, negative upon error + * + * the routine advertises available media and starts autonegotiation + */ +static int mcs7830_set_autoneg(struct ueth_data *dev) +{ + int adv, flg; + int rc; + + debug("%s()\n", __func__); + + /* + * algorithm taken from the Linux driver, which took it from + * "the original mcs7830 version 1.4 driver": + * + * enable all media, reset BMCR, enable auto neg, restart + * auto neg while keeping the enable auto neg flag set + */ + + adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA; + rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv); + + flg = 0; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + flg |= BMCR_ANENABLE; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + flg |= BMCR_ANRESTART; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + return rc; +} + +/* + * mcs7830_get_rev() - identify a network adapter's chip revision + * @eth: network device to identify + * Return: non-negative number, reflecting the revision number + * + * currently, only "rev C and higher" and "below rev C" are needed, so + * the return value is #1 for "below rev C", and #2 for "rev C and above" + */ +static int mcs7830_get_rev(struct ueth_data *dev) +{ + uint8_t buf[2]; + int rc; + int rev; + + /* register 22 is readable in rev C and higher */ + rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf); + if (rc < 0) + rev = 1; + else + rev = 2; + debug("%s() rc=%d, rev=%d\n", __func__, rc, rev); + return rev; +} + +/* + * mcs7830_apply_fixup() - identify an adapter and potentially apply fixups + * @eth: network device to identify and apply fixups to + * Return: zero upon success (no errors emitted from here) + * + * this routine identifies the network adapter's chip revision, and applies + * fixups for known issues + */ +static int mcs7830_apply_fixup(struct ueth_data *dev) +{ + int rev; + int i; + uint8_t thr; + + rev = mcs7830_get_rev(dev); + debug("%s() rev=%d\n", __func__, rev); + + /* + * rev C requires setting the pause threshold (the Linux driver + * is inconsistent, the implementation does it for "rev C + * exactly", the introductory comment says "rev C and above") + */ + if (rev == 2) { + debug("%s: applying rev C fixup\n", dev->eth_dev.name); + thr = PAUSE_THRESHOLD_DEFAULT; + for (i = 0; i < 2; i++) { + (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD, + sizeof(thr), &thr); + mdelay(1); + } + } + + return 0; +} + +/* + * mcs7830_basic_reset() - bring the network adapter into a known first state + * @eth: network device to act upon + * Return: zero upon success, negative upon error + * + * this routine initializes the network adapter such that subsequent invocations + * of the interface callbacks can exchange ethernet frames; link negotiation is + * triggered from here already and continues in background + */ +static int mcs7830_basic_reset(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + /* + * comment from the respective Linux driver, which + * unconditionally sets the ALLMULTICAST flag as well: + * should not be needed, but does not work otherwise + */ + priv->config = CONF_TXENABLE; + priv->config |= CONF_ALLMULTICAST; + + rc = mcs7830_set_autoneg(dev); + if (rc < 0) { + error("setting autoneg failed\n"); + return rc; + } + + rc = mcs7830_write_mchash(dev); + if (rc < 0) { + error("failed to set multicast hash\n"); + return rc; + } + + rc = mcs7830_write_config(dev); + if (rc < 0) { + error("failed to set configuration\n"); + return rc; + } + + rc = mcs7830_apply_fixup(dev); + if (rc < 0) { + error("fixup application failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_read_mac() - read an ethernet adapter's MAC address + * @eth: network device to read from + * Return: zero upon success, negative upon error + * + * this routine fetches the MAC address stored within the ethernet adapter, + * and stores it in the ethernet interface's data structure + */ +static int mcs7830_read_mac(struct eth_device *eth) +{ + struct ueth_data *dev; + int rc; + uint8_t buf[ETH_ALEN]; + + debug("%s()\n", __func__); + dev = eth->priv; + + rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf); + if (rc < 0) { + debug("reading MAC from adapter failed\n"); + return rc; + } + + memcpy(ð->enetaddr[0], buf, ETH_ALEN); + return 0; +} + +/* + * mcs7830_write_mac() - write an ethernet adapter's MAC address + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * this routine takes the MAC address from the ethernet interface's data + * structure, and writes it into the ethernet adapter such that subsequent + * exchange of ethernet frames uses this address + */ +static int mcs7830_write_mac(struct eth_device *eth) +{ + struct ueth_data *dev; + int rc; + + debug("%s()\n", __func__); + dev = eth->priv; + + if (sizeof(eth->enetaddr) != ETH_ALEN) + return -EINVAL; + rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr); + if (rc < 0) { + debug("writing MAC to adapter failed\n"); + return rc; + } + return 0; +} + +/* + * mcs7830_init() - network interface's init callback + * @eth: network device to initialize + * @bd: board information + * Return: zero upon success, negative upon error + * + * after initial setup during probe() and get_info(), this init() callback + * ensures that the link is up and subsequent send() and recv() calls can + * exchange ethernet frames + */ +static int mcs7830_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev; + int timeout; + int have_link; + + debug("%s()\n", __func__); + dev = eth->priv; + + timeout = 0; + do { + have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS; + if (have_link) + break; + udelay(LINKSTATUS_TIMEOUT_RES * 1000); + timeout += LINKSTATUS_TIMEOUT_RES; + } while (timeout < LINKSTATUS_TIMEOUT); + if (!have_link) { + debug("ethernet link is down\n"); + return -ETIMEDOUT; + } + return 0; +} + +/* + * mcs7830_send() - network interface's send callback + * @eth: network device to send the frame from + * @packet: ethernet frame content + * @length: ethernet frame length + * Return: zero upon success, negative upon error + * + * this routine send an ethernet frame out of the network interface + */ +static int mcs7830_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev; + int rc; + int gotlen; + /* there is a status byte after the ethernet frame */ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t)); + + dev = eth->priv; + + memcpy(buf, packet, length); + rc = usb_bulk_msg(dev->pusb_dev, + usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), + &buf[0], length, &gotlen, + USBCALL_TIMEOUT); + debug("%s() TX want len %d, got len %d, rc %d\n", + __func__, length, gotlen, rc); + return rc; +} + +/* + * mcs7830_recv() - network interface's recv callback + * @eth: network device to receive frames from + * Return: zero upon success, negative upon error + * + * this routine checks for available ethernet frames that the network + * interface might have received, and notifies the network stack + */ +static int mcs7830_recv(struct eth_device *eth) +{ + struct ueth_data *dev; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE); + int rc, wantlen, gotlen; + uint8_t sts; + + debug("%s()\n", __func__); + dev = eth->priv; + + /* fetch input data from the adapter */ + wantlen = MCS7830_RX_URB_SIZE; + rc = usb_bulk_msg(dev->pusb_dev, + usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), + &buf[0], wantlen, &gotlen, + USBCALL_TIMEOUT); + debug("%s() RX want len %d, got len %d, rc %d\n", + __func__, wantlen, gotlen, rc); + if (rc != 0) { + error("RX: failed to receive\n"); + return rc; + } + if (gotlen > wantlen) { + error("RX: got too many bytes (%d)\n", gotlen); + return -EIO; + } + + /* + * the bulk message that we received from USB contains exactly + * one ethernet frame and a trailing status byte + */ + if (gotlen < sizeof(sts)) + return -EIO; + gotlen -= sizeof(sts); + sts = buf[gotlen]; + + if (sts == STAT_RX_FRAME_CORRECT) { + debug("%s() got a frame, len=%d\n", __func__, gotlen); + NetReceive(buf, gotlen); + return 0; + } + + debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n", + sts, + (sts & STAT_RX_LARGE_FRAME) ? "large" : "-", + (sts & STAT_RX_LENGTH_ERROR) ? "length" : "-", + (sts & STAT_RX_SHORT_FRAME) ? "short" : "-", + (sts & STAT_RX_CRC_ERROR) ? "crc" : "-", + (sts & STAT_RX_ALIGNMENT_ERROR) ? "align" : "-"); + return -EIO; +} + +/* + * mcs7830_halt() - network interface's halt callback + * @eth: network device to cease operation of + * Return: none + * + * this routine is supposed to undo the effect of previous initialization and + * ethernet frames exchange; in this implementation it's a NOP + */ +static void mcs7830_halt(struct eth_device *eth) +{ + debug("%s()\n", __func__); +} + +/* + * mcs7830_iface_idx - index of detected network interfaces + * + * this counter keeps track of identified supported interfaces, + * to assign unique names as more interfaces are found + */ +static int mcs7830_iface_idx; + +/* + * mcs7830_eth_before_probe() - network driver's before_probe callback + * Return: none + * + * this routine initializes driver's internal data in preparation of + * subsequent probe callbacks + */ +void mcs7830_eth_before_probe(void) +{ + mcs7830_iface_idx = 0; +} + +/* + * struct mcs7830_dongle - description of a supported Moschip ethernet dongle + * @vendor: 16bit USB vendor identification + * @product: 16bit USB product identification + * + * this structure describes a supported USB ethernet dongle by means of the + * vendor and product codes found during USB enumeration; no flags are held + * here since all supported dongles have identical behaviour, and required + * fixups get determined at runtime, such that no manual configuration is + * needed + */ +struct mcs7830_dongle { + uint16_t vendor; + uint16_t product; +}; + +/* + * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles + */ +static const struct mcs7830_dongle const mcs7830_dongles[] = { + { 0x9710, 0x7832, }, /* Moschip 7832 */ + { 0x9710, 0x7830, }, /* Moschip 7830 */ + { 0x9710, 0x7730, }, /* Moschip 7730 */ + { 0x0df6, 0x0021, }, /* Sitecom LN 30 */ +}; + +/* + * mcs7830_eth_probe() - network driver's probe callback + * @dev: detected USB device to check + * @ifnum: detected USB interface to check + * @ss: USB ethernet data structure to fill in upon match + * Return: #1 upon match, #0 upon mismatch or error + * + * this routine checks whether the found USB device is supported by + * this ethernet driver, and upon match fills in the USB ethernet + * data structure which later is passed to the get_info callback + */ +int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + struct usb_interface *iface; + struct usb_interface_descriptor *iface_desc; + int i; + struct mcs7830_private *priv; + int ep_in_found, ep_out_found, ep_intr_found; + + debug("%s()\n", __func__); + + /* iterate the list of supported dongles */ + iface = &dev->config.if_desc[ifnum]; + iface_desc = &iface->desc; + for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) { + if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor && + dev->descriptor.idProduct == mcs7830_dongles[i].product) + break; + } + if (i == ARRAY_SIZE(mcs7830_dongles)) + return 0; + debug("detected USB ethernet device: %04X:%04X\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); + + /* fill in driver private data */ + priv = calloc(1, sizeof(*priv)); + if (!priv) + return 0; + + /* fill in the ueth_data structure, attach private data */ + memset(ss, 0, sizeof(*ss)); + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->subclass = iface_desc->bInterfaceSubClass; + ss->protocol = iface_desc->bInterfaceProtocol; + ss->dev_priv = priv; + + /* + * a minimum of three endpoints is expected: in (bulk), + * out (bulk), and interrupt; ignore all others + */ + ep_in_found = ep_out_found = ep_intr_found = 0; + for (i = 0; i < iface_desc->bNumEndpoints; i++) { + uint8_t eptype, epaddr; + bool is_input; + + eptype = iface->ep_desc[i].bmAttributes; + eptype &= USB_ENDPOINT_XFERTYPE_MASK; + + epaddr = iface->ep_desc[i].bEndpointAddress; + is_input = epaddr & USB_DIR_IN; + epaddr &= USB_ENDPOINT_NUMBER_MASK; + + if (eptype == USB_ENDPOINT_XFER_BULK) { + if (is_input && !ep_in_found) { + ss->ep_in = epaddr; + ep_in_found++; + } + if (!is_input && !ep_out_found) { + ss->ep_out = epaddr; + ep_out_found++; + } + } + + if (eptype == USB_ENDPOINT_XFER_INT) { + if (is_input && !ep_intr_found) { + ss->ep_int = epaddr; + ss->irqinterval = iface->ep_desc[i].bInterval; + ep_intr_found++; + } + } + } + debug("endpoints: in %d, out %d, intr %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); + + /* apply basic sanity checks */ + if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || !ss->ep_int) { + debug("device probe incomplete\n"); + return 0; + } + + dev->privptr = ss; + return 1; +} + +/* + * mcs7830_eth_get_info() - network driver's get_info callback + * @dev: detected USB device + * @ss: USB ethernet data structure filled in at probe() + * @eth: ethernet interface data structure to fill in + * Return: #1 upon success, #0 upon error + * + * this routine registers the mandatory init(), send(), recv(), and + * halt() callbacks with the ethernet interface, can register the + * optional write_hwaddr() callback with the ethernet interface, + * and initiates configuration of the interface such that subsequent + * calls to those callbacks results in network communication + */ +int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth) +{ + debug("%s()\n", __func__); + if (!eth) { + debug("%s: missing parameter.\n", __func__); + return 0; + } + + snprintf(eth->name, sizeof(eth->name), "%s%d", + MCS7830_BASE_NAME, mcs7830_iface_idx++); + eth->init = mcs7830_init; + eth->send = mcs7830_send; + eth->recv = mcs7830_recv; + eth->halt = mcs7830_halt; + eth->write_hwaddr = mcs7830_write_mac; + eth->priv = ss; + + if (mcs7830_basic_reset(ss)) + return 0; + + if (mcs7830_read_mac(eth)) + return 0; + debug("MAC %pM\n", eth->enetaddr); + + return 1; +} diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 2c4126be36..1dda54c2f1 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -30,6 +30,13 @@ static const struct usb_eth_prob_dev prob_dev[] = { .get_info = asix_eth_get_info, }, #endif +#ifdef CONFIG_USB_ETHER_MCS7830 + { + .before_probe = mcs7830_eth_before_probe, + .probe = mcs7830_eth_probe, + .get_info = mcs7830_eth_get_info, + }, +#endif #ifdef CONFIG_USB_ETHER_SMSC95XX { .before_probe = smsc95xx_eth_before_probe, diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index f13b172a66..804a2bd412 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -21,7 +21,7 @@ endif ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o -obj-$(CONFIG_MV_UDC) += mv_udc.o +obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/ci_udc.c similarity index 79% rename from drivers/usb/gadget/mv_udc.c rename to drivers/usb/gadget/ci_udc.c index da41738653..14b1e9b8bf 100644 --- a/drivers/usb/gadget/mv_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -20,9 +20,9 @@ #include #include #include -#include +#include #include "../host/ehci.h" -#include "mv_udc.h" +#include "ci_udc.h" /* * Check if the system has too long cachelines. If the cachelines are @@ -70,85 +70,85 @@ static struct usb_endpoint_descriptor ep0_in_desc = { .bmAttributes = USB_ENDPOINT_XFER_CONTROL, }; -static int mv_pullup(struct usb_gadget *gadget, int is_on); -static int mv_ep_enable(struct usb_ep *ep, +static int ci_pullup(struct usb_gadget *gadget, int is_on); +static int ci_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc); -static int mv_ep_disable(struct usb_ep *ep); -static int mv_ep_queue(struct usb_ep *ep, +static int ci_ep_disable(struct usb_ep *ep); +static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req); +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); -static struct usb_gadget_ops mv_udc_ops = { - .pullup = mv_pullup, +static struct usb_gadget_ops ci_udc_ops = { + .pullup = ci_pullup, }; -static struct usb_ep_ops mv_ep_ops = { - .enable = mv_ep_enable, - .disable = mv_ep_disable, - .queue = mv_ep_queue, - .alloc_request = mv_ep_alloc_request, - .free_request = mv_ep_free_request, +static struct usb_ep_ops ci_ep_ops = { + .enable = ci_ep_enable, + .disable = ci_ep_disable, + .queue = ci_ep_queue, + .alloc_request = ci_ep_alloc_request, + .free_request = ci_ep_free_request, }; /* Init values for USB endpoints. */ -static const struct usb_ep mv_ep_init[2] = { +static const struct usb_ep ci_ep_init[2] = { [0] = { /* EP 0 */ .maxpacket = 64, .name = "ep0", - .ops = &mv_ep_ops, + .ops = &ci_ep_ops, }, [1] = { /* EP 1..n */ .maxpacket = 512, .name = "ep-", - .ops = &mv_ep_ops, + .ops = &ci_ep_ops, }, }; -static struct mv_drv controller = { +static struct ci_drv controller = { .gadget = { - .name = "mv_udc", - .ops = &mv_udc_ops, + .name = "ci_udc", + .ops = &ci_udc_ops, .is_dualspeed = 1, }, }; /** - * mv_get_qh() - return queue head for endpoint + * ci_get_qh() - return queue head for endpoint * @ep_num: Endpoint number * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) * * This function returns the QH associated with particular endpoint * and it's direction. */ -static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) +static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) { return &controller.epts[(ep_num * 2) + dir_in]; } /** - * mv_get_qtd() - return queue item for endpoint + * ci_get_qtd() - return queue item for endpoint * @ep_num: Endpoint number * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) * * This function returns the QH associated with particular endpoint * and it's direction. */ -static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) +static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) { return controller.items[(ep_num * 2) + dir_in]; } /** - * mv_flush_qh - flush cache over queue head + * ci_flush_qh - flush cache over queue head * @ep_num: Endpoint number * * This function flushes cache over QH for particular endpoint. */ -static void mv_flush_qh(int ep_num) +static void ci_flush_qh(int ep_num) { - struct ept_queue_head *head = mv_get_qh(ep_num, 0); + struct ept_queue_head *head = ci_get_qh(ep_num, 0); const uint32_t start = (uint32_t)head; const uint32_t end = start + 2 * sizeof(*head); @@ -156,14 +156,14 @@ static void mv_flush_qh(int ep_num) } /** - * mv_invalidate_qh - invalidate cache over queue head + * ci_invalidate_qh - invalidate cache over queue head * @ep_num: Endpoint number * * This function invalidates cache over QH for particular endpoint. */ -static void mv_invalidate_qh(int ep_num) +static void ci_invalidate_qh(int ep_num) { - struct ept_queue_head *head = mv_get_qh(ep_num, 0); + struct ept_queue_head *head = ci_get_qh(ep_num, 0); uint32_t start = (uint32_t)head; uint32_t end = start + 2 * sizeof(*head); @@ -171,14 +171,14 @@ static void mv_invalidate_qh(int ep_num) } /** - * mv_flush_qtd - flush cache over queue item + * ci_flush_qtd - flush cache over queue item * @ep_num: Endpoint number * * This function flushes cache over qTD pair for particular endpoint. */ -static void mv_flush_qtd(int ep_num) +static void ci_flush_qtd(int ep_num) { - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; const uint32_t end_raw = start + 2 * sizeof(*item); const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); @@ -187,14 +187,14 @@ static void mv_flush_qtd(int ep_num) } /** - * mv_invalidate_qtd - invalidate cache over queue item + * ci_invalidate_qtd - invalidate cache over queue item * @ep_num: Endpoint number * * This function invalidates cache over qTD pair for particular endpoint. */ -static void mv_invalidate_qtd(int ep_num) +static void ci_invalidate_qtd(int ep_num) { - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; const uint32_t end_raw = start + 2 * sizeof(*item); const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); @@ -203,20 +203,20 @@ static void mv_invalidate_qtd(int ep_num) } static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - return &mv_ep->req; + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + return &ci_ep->req; } -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) { return; } static void ep_enable(int num, int in, int maxpacket) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; unsigned n; n = readl(&udc->epctrl[num]); @@ -226,22 +226,22 @@ static void ep_enable(int num, int in, int maxpacket) n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); if (num != 0) { - struct ept_queue_head *head = mv_get_qh(num, in); + struct ept_queue_head *head = ci_get_qh(num, in); head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; - mv_flush_qh(num); + ci_flush_qh(num); } writel(n, &udc->epctrl[num]); } -static int mv_ep_enable(struct usb_ep *ep, +static int ci_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); int num, in; num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (desc->bEndpointAddress & USB_DIR_IN) != 0; - mv_ep->desc = desc; + ci_ep->desc = desc; if (num) { int max = get_unaligned_le16(&desc->wMaxPacketSize); @@ -259,15 +259,15 @@ static int mv_ep_enable(struct usb_ep *ep, return 0; } -static int mv_ep_disable(struct usb_ep *ep) +static int ci_ep_disable(struct usb_ep *ep) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); - mv_ep->desc = NULL; + ci_ep->desc = NULL; return 0; } -static int mv_bounce(struct mv_ep *ep, int in) +static int ci_bounce(struct ci_ep *ep, int in) { uint32_t addr = (uint32_t)ep->req.buf; uint32_t ba; @@ -306,7 +306,7 @@ flush: return 0; } -static void mv_debounce(struct mv_ep *ep, int in) +static void ci_debounce(struct ci_ep *ep, int in) { uint32_t addr = (uint32_t)ep->req.buf; uint32_t ba = (uint32_t)ep->b_buf; @@ -328,36 +328,36 @@ free: free(ep->b_buf); } -static int mv_ep_queue(struct usb_ep *ep, +static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_item *item; struct ept_queue_head *head; int bit, num, len, in, ret; - num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = mv_get_qtd(num, in); - head = mv_get_qh(num, in); + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + head = ci_get_qh(num, in); len = req->length; - ret = mv_bounce(mv_ep, in); + ret = ci_bounce(ci_ep, in); if (ret) return ret; item->next = TERMINATE; item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)mv_ep->b_buf; - item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; - mv_flush_qtd(num); + item->page0 = (uint32_t)ci_ep->b_buf; + item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; + ci_flush_qtd(num); head->next = (unsigned) item; head->info = 0; DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, mv_ep->b_buf); - mv_flush_qh(num); + num, in ? "in" : "out", len, ci_ep->b_buf); + ci_flush_qh(num); if (in) bit = EPT_TX(num); @@ -369,7 +369,7 @@ static int mv_ep_queue(struct usb_ep *ep, return 0; } -static void handle_ep_complete(struct mv_ep *ep) +static void handle_ep_complete(struct ci_ep *ep) { struct ept_queue_item *item; int num, in, len; @@ -377,8 +377,8 @@ static void handle_ep_complete(struct mv_ep *ep) in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) ep->desc = &ep0_out_desc; - item = mv_get_qtd(num, in); - mv_invalidate_qtd(num); + item = ci_get_qtd(num, in); + ci_invalidate_qtd(num); if (item->info & 0xff) printf("EP%d/%s FAIL info=%x pg0=%x\n", @@ -386,7 +386,7 @@ static void handle_ep_complete(struct mv_ep *ep) len = (item->info >> 16) & 0x7fff; ep->req.length -= len; - mv_debounce(ep, in); + ci_debounce(ep, in); DBG("ept%d %s complete %x\n", num, in ? "in" : "out", len); @@ -403,15 +403,15 @@ static void handle_ep_complete(struct mv_ep *ep) static void handle_setup(void) { struct usb_request *req = &controller.ep[0].req; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_head *head; struct usb_ctrlrequest r; int status = 0; int num, in, _num, _in, i; char *buf; - head = mv_get_qh(0, 0); /* EP0 OUT */ + head = ci_get_qh(0, 0); /* EP0 OUT */ - mv_invalidate_qh(0); + ci_invalidate_qh(0); memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); writel(EPT_RX(0), &udc->epstat); DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), @@ -425,7 +425,7 @@ static void handle_setup(void) if ((r.wValue == 0) && (r.wLength == 0)) { req->length = 0; for (i = 0; i < NUM_ENDPOINTS; i++) { - struct mv_ep *ep = &controller.ep[i]; + struct ci_ep *ep = &controller.ep[i]; if (!ep->desc) continue; @@ -478,7 +478,7 @@ static void stop_activity(void) { int i, num, in; struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; writel(readl(&udc->epcomp), &udc->epcomp); writel(readl(&udc->epstat), &udc->epstat); writel(0xffffffff, &udc->epflush); @@ -492,16 +492,16 @@ static void stop_activity(void) & USB_ENDPOINT_NUMBER_MASK; in = (controller.ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0; - head = mv_get_qh(num, in); + head = ci_get_qh(num, in); head->info = INFO_ACTIVE; - mv_flush_qh(num); + ci_flush_qh(num); } } } void udc_irq(void) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; unsigned n = readl(&udc->usbsts); writel(n, &udc->usbsts); int bit, i, num, in; @@ -563,7 +563,7 @@ void udc_irq(void) int usb_gadget_handle_interrupts(void) { u32 value; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; value = readl(&udc->usbsts); if (value) @@ -572,9 +572,9 @@ int usb_gadget_handle_interrupts(void) return value; } -static int mv_pullup(struct usb_gadget *gadget, int is_on) +static int ci_pullup(struct usb_gadget *gadget, int is_on) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; if (is_on) { /* RESET */ writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); @@ -602,7 +602,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on) void udc_disconnect(void) { - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* disable pullup */ stop_activity(); writel(USBCMD_FS2, &udc->usbcmd); @@ -611,7 +611,7 @@ void udc_disconnect(void) controller.driver->disconnect(&controller.gadget); } -static int mvudc_probe(void) +static int ci_udc_probe(void) { struct ept_queue_head *head; uint8_t *imem; @@ -673,23 +673,23 @@ static int mvudc_probe(void) controller.items[i] = (struct ept_queue_item *)imem; if (i & 1) { - mv_flush_qh(i - 1); - mv_flush_qtd(i - 1); + ci_flush_qh(i - 1); + ci_flush_qtd(i - 1); } } INIT_LIST_HEAD(&controller.gadget.ep_list); /* Init EP 0 */ - memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); + memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); controller.ep[0].desc = &ep0_in_desc; controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); /* Init EP 1..n */ for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &mv_ep_init[1], - sizeof(*mv_ep_init)); + memcpy(&controller.ep[i].ep, &ci_ep_init[1], + sizeof(*ci_ep_init)); list_add_tail(&controller.ep[i].ep.ep_list, &controller.gadget.ep_list); } @@ -699,7 +699,7 @@ static int mvudc_probe(void) int usb_gadget_register_driver(struct usb_gadget_driver *driver) { - struct mv_udc *udc; + struct ci_udc *udc; int ret; if (!driver) @@ -713,9 +713,9 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) if (ret) return ret; - ret = mvudc_probe(); + ret = ci_udc_probe(); if (!ret) { - udc = (struct mv_udc *)controller.ctrl->hcor; + udc = (struct ci_udc *)controller.ctrl->hcor; /* select ULPI phy */ writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); diff --git a/drivers/usb/gadget/mv_udc.h b/drivers/usb/gadget/ci_udc.h similarity index 94% rename from drivers/usb/gadget/mv_udc.h rename to drivers/usb/gadget/ci_udc.h index c7d8b33984..42f6ef4ab3 100644 --- a/drivers/usb/gadget/mv_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -3,12 +3,12 @@ * * Licensed under the GPL-2 or later. */ -#ifndef __GADGET__MV_UDC_H__ -#define __GADGET__MV_UDC_H__ +#ifndef __GADGET__CI_UDC_H__ +#define __GADGET__CI_UDC_H__ #define NUM_ENDPOINTS 6 -struct mv_udc { +struct ci_udc { #define MICRO_8FRAME 0x8 #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) #define USBCMD_FS2 (1 << 15) @@ -48,7 +48,7 @@ struct mv_udc { u32 epctrl[16]; /* 0x1c0 */ }; -struct mv_ep { +struct ci_ep { struct usb_ep ep; struct list_head queue; const struct usb_endpoint_descriptor *desc; @@ -59,14 +59,14 @@ struct mv_ep { uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); }; -struct mv_drv { +struct ci_drv { struct usb_gadget gadget; struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; struct ept_queue_item *items[2 * NUM_ENDPOINTS]; uint8_t *items_mem; - struct mv_ep ep[NUM_ENDPOINTS]; + struct ci_ep ep[NUM_ENDPOINTS]; }; struct ept_queue_head { diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index a045864d73..de75ff1339 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -164,9 +164,14 @@ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req) dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf, req->length, f_dfu->blk_seq_num); +} - if (req->length == 0) - puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); +static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) +{ + struct f_dfu *f_dfu = req->context; + + dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf, + req->length, f_dfu->blk_seq_num); } static void handle_getstatus(struct usb_request *req) @@ -174,19 +179,22 @@ static void handle_getstatus(struct usb_request *req) struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + dfu_set_poll_timeout(dstat, 0); + switch (f_dfu->dfu_state) { case DFU_STATE_dfuDNLOAD_SYNC: case DFU_STATE_dfuDNBUSY: f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE; break; case DFU_STATE_dfuMANIFEST_SYNC: + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; break; + case DFU_STATE_dfuMANIFEST: + dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT); default: break; } - dfu_set_poll_timeout(dstat, 0); - if (f_dfu->poll_timeout) if (!(f_dfu->blk_seq_num % (dfu_get_buf_size() / DFU_USB_BUFSIZ))) @@ -446,10 +454,11 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_GETSTATUS: /* We're MainfestationTolerant */ - f_dfu->dfu_state = DFU_STATE_dfuIDLE; + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; handle_getstatus(req); f_dfu->blk_seq_num = 0; value = RET_STAT_LEN; + req->complete = dnload_request_flush; break; case USB_REQ_DFU_GETSTATE: handle_getstate(req); @@ -463,6 +472,33 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, return value; } +static int state_dfu_manifest(struct f_dfu *f_dfu, + const struct usb_ctrlrequest *ctrl, + struct usb_gadget *gadget, + struct usb_request *req) +{ + int value = 0; + + switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + /* We're MainfestationTolerant */ + f_dfu->dfu_state = DFU_STATE_dfuIDLE; + handle_getstatus(req); + f_dfu->blk_seq_num = 0; + value = RET_STAT_LEN; + puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); + break; + case USB_REQ_DFU_GETSTATE: + handle_getstate(req); + break; + default: + f_dfu->dfu_state = DFU_STATE_dfuERROR; + value = RET_STALL; + break; + } + return value; +} + static int state_dfu_upload_idle(struct f_dfu *f_dfu, const struct usb_ctrlrequest *ctrl, struct usb_gadget *gadget, @@ -539,7 +575,7 @@ static dfu_state_fn dfu_state[] = { state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */ state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */ state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */ - NULL, /* DFU_STATE_dfuMANIFEST */ + state_dfu_manifest, /* DFU_STATE_dfuMANIFEST */ NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */ state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */ state_dfu_error /* DFU_STATE_dfuERROR */ diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index b1fe8bd3a8..f896169743 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2515,7 +2515,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, buffhds_first_it: bh->inreq_busy = 0; bh->outreq_busy = 0; - bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL); + bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN); if (unlikely(!bh->buf)) { rc = -ENOMEM; goto error_release; @@ -2622,7 +2622,7 @@ usb_copy_descriptors(struct usb_descriptor_header **src) bytes += (*tmp)->bLength; bytes += (n_desc + 1) * sizeof(*tmp); - mem = kmalloc(bytes, GFP_KERNEL); + mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes); if (!mem) return NULL; diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c4c9909155..f5c0224f21 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -614,7 +614,7 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) { struct usb_request *req; - req = alloc_ep_req(ep, ep->maxpacket); + req = alloc_ep_req(ep, THOR_PACKET_SIZE); debug("%s: ep:%p req:%p\n", __func__, ep, req); if (!req) @@ -623,8 +623,6 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) memset(req->buf, 0, req->length); req->complete = thor_rx_tx_complete; - memset(req->buf, 0x55, req->length); - return req; } diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h index 04ee9a2438..833a9d24ae 100644 --- a/drivers/usb/gadget/f_thor.h +++ b/drivers/usb/gadget/f_thor.h @@ -11,7 +11,7 @@ #define _USB_THOR_H_ #include -#include +#include /* THOR Composite Gadget */ #define STRING_MANUFACTURER_IDX 0 diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index aa54b8547e..cc94771e32 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,10 +144,10 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_MV_UDC -#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) +#ifdef CONFIG_CI_UDC +#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name)) #else -#define gadget_is_mv(g) 0 +#define gadget_is_ci(g) 0 #endif #ifdef CONFIG_USB_GADGET_FOTG210 @@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x19; else if (gadget_is_m66592(gadget)) return 0x20; - else if (gadget_is_mv(gadget)) + else if (gadget_is_ci(gadget)) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index ba17a04265..63d4487a9b 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -843,7 +843,7 @@ static struct s3c_udc memory = { int s3c_udc_probe(struct s3c_plat_otg_data *pdata) { struct s3c_udc *dev = &memory; - int retval = 0, i; + int retval = 0; debug("%s: %p\n", __func__, pdata); @@ -864,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) the_controller = dev; - for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) { - dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE, - DMA_BUFFER_SIZE); - dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i]; - invalidate_dcache_range((unsigned long) dev->dma_buf[i], - (unsigned long) (dev->dma_buf[i] - + DMA_BUFFER_SIZE)); + usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, + ROUND(sizeof(struct usb_ctrlrequest), + CONFIG_SYS_CACHELINE_SIZE)); + if (!usb_ctrl) { + error("No memory available for UDC!\n"); + return -ENOMEM; } - usb_ctrl = dev->dma_buf[0]; - usb_ctrl_dma_addr = dev->dma_addr[0]; + + usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; udc_reinit(dev); diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 1cbf8f60a7..06dfeed905 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -29,10 +29,6 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) { u32 ep_ctrl; - flush_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); @@ -52,10 +48,6 @@ void s3c_udc_pre_setup(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -82,10 +74,6 @@ static inline void s3c_ep0_complete_out(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Complete Out packet.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -109,27 +97,20 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) u32 ep_num = ep_index(ep); buf = req->req.buf + req->req.actual; - - length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket); + length = min(req->req.length - req->req.actual, + ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); ep->len = length; ep->dma_buf = buf; - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num], - (unsigned long) ep->dev->dma_buf[ep_num] - + ROUND(ep->ep.maxpacket, - CONFIG_SYS_CACHELINE_SIZE)); - - if (length == 0) + if (ep_num == EP0_CON || length == 0) pktcnt = 1; else pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; - pktcnt = 1; ctrl = readl(®->out_endp[ep_num].doepctl); - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->out_endp[ep_num].doepdma); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -152,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) u32 *buf, ctrl = 0; u32 length, pktcnt; u32 ep_num = ep_index(ep); - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; buf = req->req.buf + req->req.actual; length = req->req.length - req->req.actual; @@ -162,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - memcpy(p, ep->dma_buf, length); - flush_dcache_range((unsigned long) p , - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); if (length == 0) pktcnt = 1; @@ -178,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->in_endp[ep_num].diepdma); + writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -212,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) struct s3c_ep *ep = &dev->ep[ep_num]; struct s3c_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; if (list_empty(&ep->queue)) { debug_cond(DEBUG_OUT_EP != 0, @@ -232,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) xfer_size = ep->len - xfer_size; - invalidate_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); - - memcpy(ep->dma_buf, p, ep->len); + /* + * NOTE: + * + * Please be careful with proper buffer allocation for USB request, + * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only + * with starting address, but also its size shall be a cache line + * multiplication. + * + * This will prevent from corruption of data allocated immediatelly + * before or after the buffer. + * + * For armv7, the cache_v7.c provides proper code to emit "ERROR" + * message to warn users. + */ + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); req->req.actual += min(xfer_size, req->req.length - req->req.actual); is_short = (xfer_size < ep->ep.maxpacket); @@ -729,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) { - u32 bytes; - - bytes = sizeof(struct usb_ctrlrequest); - - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)], - (unsigned long) ep->dev->dma_buf[ep_index(ep)] - + DMA_BUFFER_SIZE); + invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); debug_cond(DEBUG_EP0 != 0, - "%s: bytes=%d, ep_index=%d %p\n", __func__, - bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]); + "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, + max, ep_index(ep), cp); - return bytes; + return max; } /** @@ -873,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -u16 g_status; - int s3c_udc_get_status(struct s3c_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; + u16 g_status = 0; u32 ep_ctrl; - u32 *p = the_controller->dma_buf[1]; debug_cond(DEBUG_SETUP != 0, "%s: *** USB_REQ_GET_STATUS\n", __func__); @@ -918,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 1; } - memcpy(p, &g_status, sizeof(g_status)); + memcpy(usb_ctrl, &g_status, sizeof(g_status)); - flush_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) usb_ctrl, + (unsigned long) usb_ctrl + + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma); + writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6629fef66a..bf87204e22 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o -obj-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45e5d6a5bd..1ca7cf5d9b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -86,7 +86,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, #endif } - if (!strcmp(phy_type, "utmi")) { + if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); setbits_be32(&ehci->control, UTMI_PHY_EN); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 17187caed4..6017090ebe 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -395,6 +395,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); qh->qh_endpt2 = cpu_to_hc32(endpt); qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); tdp = &qh->qh_overlay.qt_next; @@ -1161,14 +1162,16 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, debug("ehci intr queue: out of memory\n"); goto fail1; } - result->first = memalign(32, sizeof(struct QH) * queuesize); + result->first = memalign(USB_DMA_MINALIGN, + sizeof(struct QH) * queuesize); if (!result->first) { debug("ehci intr queue: out of memory\n"); goto fail2; } result->current = result->first; result->last = result->first + queuesize - 1; - result->tds = memalign(32, sizeof(struct qTD) * queuesize); + result->tds = memalign(USB_DMA_MINALIGN, + sizeof(struct qTD) * queuesize); if (!result->tds) { debug("ehci intr queue: out of memory\n"); goto fail3; @@ -1186,6 +1189,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, qh->qh_link = QH_LINK_TERMINATE; qh->qh_overlay.qt_next = (uint32_t)td; + qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE; qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ (1 << 14) | diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c deleted file mode 100644 index 646e815e71..0000000000 --- a/drivers/usb/host/ehci-ixp4xx.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008, Michael Trimarchi - * - * Author: Michael Trimarchi - * This code is based on ehci freescale driver - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - -#include "ehci.h" -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - *hccr = (struct ehci_hccr *)(0xcd000100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - printf("IXP4XX init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index 5aa190b52d..46e4cee1d0 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -254,105 +254,7 @@ static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type) /* --- Virtual Root Hub ---------------------------------------------------- */ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x02, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 0x22, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'S', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'P', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '1', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '1', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'x', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* * Hub class-specific descriptor is constructed dynamically diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 219d18232a..dc0a4e3179 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1094,103 +1094,7 @@ static int dl_done_list(ohci_t *ohci) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c index 42e564ef5e..3c659c60c9 100644 --- a/drivers/usb/host/ohci-s3c24xx.c +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -873,100 +873,7 @@ static int dl_done_list(struct ohci *ohci, struct td *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, - 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index fd30d6726c..dfe5423b8a 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -557,109 +557,7 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; */ - - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 34, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '8', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'A', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '5', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '9', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '7', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *cmd) diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile index ba72348b76..3facf0fc10 100644 --- a/drivers/usb/musb-new/Makefile +++ b/drivers/usb/musb-new/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o -CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \ - $(call cc-option,-Wno-unused-but-set-variable) \ - $(call cc-option,-Wno-unused-label) -CFLAGS += $(CFLAGS_NO_WARN) +ccflags-y := $(call cc-option,-Wno-unused-variable) \ + $(call cc-option,-Wno-unused-but-set-variable) \ + $(call cc-option,-Wno-unused-label) diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c index 35268ba58e..65fff887d3 100644 --- a/drivers/usb/musb/blackfin_usb.c +++ b/drivers/usb/musb/blackfin_usb.c @@ -11,6 +11,7 @@ #include #include +#include #include #include "musb_core.h" diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 799bd30e22..f0ba8aaaa3 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -28,99 +28,8 @@ static const struct musb_epinfo epinfo[3] = { static int rh_devnum; static u32 port_status; -/* Device descriptor */ -static const u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.1 */ - 0x02, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; +#include -/* Configuration descriptor */ -static const u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x02, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static const unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static const unsigned char root_hub_str_index1[] = { - 0x1c, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'M', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'S', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'B', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; #endif /* diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a7f54698ac..c527029241 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 6db4073596..b52e9edd25 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1473,7 +1473,11 @@ int video_display_bitmap(ulong bmp_image, int x, int y) printf("Error: malloc in gunzip failed!\n"); return 1; } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, + /* + * NB: we need to force offset of +2 + * See doc/README.displaying-bmps + */ + if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2, (uchar *) bmp_image, &len) != 0) { printf("Error: no valid bmp or bmp.gz image at %lx\n", @@ -1489,7 +1493,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) /* * Set addr to decompressed image */ - bmp = (bmp_image_t *) dst; + bmp = (bmp_image_t *)(dst+2); if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 7d4c6e092d..e1e0d802f6 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid) lcd_set_flush_dcache(1); } -#ifdef CONFIG_CMD_BMP -static void draw_logo(void) -{ - int x, y; - ulong addr; - - if (panel_width >= panel_info.logo_width) { - x = ((panel_width - panel_info.logo_width) >> 1); - } else { - x = 0; - printf("Warning: image width is bigger than display width\n"); - } - - if (panel_height >= panel_info.logo_height) { - y = ((panel_height - panel_info.logo_height) >> 1) - 4; - } else { - y = 0; - printf("Warning: image height is bigger than display height\n"); - } - - addr = panel_info.logo_addr; - bmp_display(addr, x, y); -} -#endif - void __exynos_cfg_lcd_gpio(void) { } @@ -129,6 +104,13 @@ void __exynos_backlight_reset(void) void exynos_backlight_reset(void) __attribute__((weak, alias("__exynos_backlight_reset"))); +int __exynos_lcd_misc_init(vidinfo_t *vid) +{ + return 0; +} +int exynos_lcd_misc_init(vidinfo_t *vid) + __attribute__((weak, alias("__exynos_lcd_misc_init"))); + static void lcd_panel_on(vidinfo_t *vid) { udelay(vid->init_delay); @@ -306,10 +288,15 @@ void lcd_ctrl_init(void *lcdbase) #ifdef CONFIG_OF_CONTROL if (exynos_fimd_parse_dt(gd->fdt_blob)) debug("Can't get proper panel info\n"); +#ifdef CONFIG_EXYNOS_MIPI_DSIM + exynos_init_dsim_platform_data(&panel_info); +#endif + exynos_lcd_misc_init(&panel_info); #else /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); #endif + panel_width = panel_info.vl_width; panel_height = panel_info.vl_height; @@ -323,9 +310,6 @@ void lcd_enable(void) if (panel_info.logo_on) { memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); -#ifdef CONFIG_CMD_BMP - draw_logo(); -#endif } lcd_panel_on(&panel_info); diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index f962c4f0a6..cebbba7581 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id) /* DATAPATH is DMA */ cfg |= EXYNOS_WINCON_DATAPATH_DMA; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_WSWP_ENABLE; - else /* To get output console on LCD */ - cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; + cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; /* dma burst is 16 */ cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; - else /* To get output console on LCD */ + switch (pvid->vl_bpix) { + case 4: cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; + break; + default: + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; + break; + } writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id)); diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c index 8bb8feaa9c..7dd4652931 100644 --- a/drivers/video/exynos_mipi_dsi.c +++ b/drivers/video/exynos_mipi_dsi.c @@ -9,6 +9,8 @@ #include #include +#include +#include #include #include #include @@ -22,7 +24,14 @@ #define master_to_driver(a) (a->dsim_lcd_drv) #define master_to_device(a) (a->dsim_lcd_dev) +DECLARE_GLOBAL_DATA_PTR; + static struct exynos_platform_mipi_dsim *dsim_pd; +#ifdef CONFIG_OF_CONTROL +static struct mipi_dsim_config dsim_config_dt; +static struct exynos_platform_mipi_dsim dsim_platform_data_dt; +static struct mipi_dsim_lcd_device mipi_lcd_device_dt; +#endif struct mipi_dsim_ddi { int bus_id; @@ -238,3 +247,90 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) dsim_pd = pd; } + +#ifdef CONFIG_OF_CONTROL +int exynos_dsim_config_parse_dt(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI); + if (node <= 0) { + printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n"); + return -ENODEV; + } + + dsim_config_dt.e_interface = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-interface", 0); + + dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-virtual-ch", 0); + + dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-pixel-format", 0); + + dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-burst-mode", 0); + + dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-no-data-lane", 0); + + dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-byte-clk", 0); + + dsim_config_dt.hfp = fdtdec_get_int(blob, node, + "samsung,dsim-config-hfp", 0); + + dsim_config_dt.p = fdtdec_get_int(blob, node, + "samsung,dsim-config-p", 0); + dsim_config_dt.m = fdtdec_get_int(blob, node, + "samsung,dsim-config-m", 0); + dsim_config_dt.s = fdtdec_get_int(blob, node, + "samsung,dsim-config-s", 0); + + dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node, + "samsung,dsim-config-pll-stable-time", 0); + + dsim_config_dt.esc_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-esc-clk", 0); + + dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node, + "samsung,dsim-config-stop-holding-cnt", 0); + + dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-bta-timeout", 0); + + dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-rx-timeout", 0); + + mipi_lcd_device_dt.name = fdtdec_get_config_string(blob, + "samsung,dsim-device-name"); + + mipi_lcd_device_dt.id = fdtdec_get_int(blob, node, + "samsung,dsim-device-id", 0); + + mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node, + "samsung,dsim-device-bus_id", 0); + + mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node, + "samsung,dsim-device-reverse-panel", 0); + + return 0; +} + +void exynos_init_dsim_platform_data(vidinfo_t *vid) +{ + if (exynos_dsim_config_parse_dt(gd->fdt_blob)) + debug("Can't get proper dsim config.\n"); + + strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name); + dsim_platform_data_dt.dsim_config = &dsim_config_dt; + dsim_platform_data_dt.mipi_power = mipi_power; + dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl; + dsim_platform_data_dt.lcd_panel_info = (void *)vid; + + mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt); + + dsim_pd = &dsim_platform_data_dt; +} +#endif diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c new file mode 100644 index 0000000000..ba4578e9d1 --- /dev/null +++ b/drivers/video/sandbox_sdl.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1366, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +vidinfo_t panel_info; + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_ctrl_init(void *lcdbase) +{ + /* + * Allocate memory to keep BMP color conversion map. This is required + * for 8 bit BMPs only (hence 256 colors). If malloc fails - keep + * going, it is not even clear if displyaing the bitmap will be + * required on the way up. + */ + panel_info.cmap = malloc(256 * NBITS(panel_info.vl_bpix) / 8); +} + +void lcd_enable(void) +{ + if (sandbox_sdl_init_display(panel_info.vl_col, panel_info.vl_row, + panel_info.vl_bpix)) + puts("LCD init failed\n"); +} + +int sandbox_lcd_sdl_early_init(void) +{ + const void *blob = gd->fdt_blob; + int xres = LCD_MAX_WIDTH, yres = LCD_MAX_HEIGHT; + int node; + int ret = 0; + + /* + * The code in common/lcd.c does not cope with not being able to + * set up a frame buffer. It will just happily keep writing to + * invalid memory. So here we make sure that at least some buffer + * is available even if it actually won't be displayed. + */ + node = fdtdec_next_compatible(blob, 0, COMPAT_SANDBOX_LCD_SDL); + if (node >= 0) { + xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH); + yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT); + if (xres < 0 || xres > LCD_MAX_WIDTH) { + xres = LCD_MAX_WIDTH; + ret = -EINVAL; + } + if (yres < 0 || yres > LCD_MAX_HEIGHT) { + yres = LCD_MAX_HEIGHT; + ret = -EINVAL; + } + } + + panel_info.vl_col = xres; + panel_info.vl_row = yres; + panel_info.vl_bpix = LCD_COLOR16; + + return ret; +} diff --git a/dts/.gitignore b/dts/.gitignore new file mode 100644 index 0000000000..1b3718065c --- /dev/null +++ b/dts/.gitignore @@ -0,0 +1,2 @@ +*.dtb +*.dtb.S diff --git a/dts/Makefile b/dts/Makefile index 6c7198f65f..e59550c9d2 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -7,64 +7,41 @@ # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is # enabled. See doc/README.fdt-control for more details. +DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) ifeq ($(DEVICE_TREE),) -$(if $(CONFIG_DEFAULT_DEVICE_TREE),,\ -$(error Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file)) -DEVICE_TREE = $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) +DEVICE_TREE := unset endif -DTS_INCDIRS = $(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts -DTS_INCDIRS += $(SRCTREE)/board/$(VENDOR)/dts -DTS_INCDIRS += $(SRCTREE)/arch/$(ARCH)/dts +DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb -DTS_CPPFLAGS := -x assembler-with-cpp -undef -D__DTS__ \ - -nostdinc $(addprefix -I,$(DTS_INCDIRS)) +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ -DTC_FLAGS := -R 4 -p 0x1000 \ - $(addprefix -i ,$(DTS_INCDIRS)) +$(obj)/dt.dtb: $(DTB) FORCE + $(call if_changed,copy) -# Use a constant name for this so we can access it from C code. -# objcopy doesn't seem to allow us to set the symbol name independently of -# the filename. -DT_BIN := $(obj)dt.dtb +targets += dt.dtb -$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts - $(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp - $(DTC) $(DTC_FLAGS) -O dtb -o ${DT_BIN} $(DT_BIN).dts.tmp +$(DTB): arch-dtbs + $(Q)test -e $@ || ( \ + echo >&2; \ + echo >&2 "Device Tree Source is not correctly specified."; \ + echo >&2 "Please define 'CONFIG_DEFAULT_DEVICE_TREE'"; \ + echo >&2 "or build with 'DEVICE_TREE=' argument"; \ + echo >&2; \ + /bin/false) -process_lds = \ - $(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p' +arch-dtbs: + $(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbs -# Run the compiler and get the link script from the linker -GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1 +.SECONDARY: $(obj)/dt.dtb.S -$(obj)dt.o: $(DT_BIN) - # We want the output format and arch. - # We also hope to win a prize for ugliest Makefile / shell interaction - # We look in the LDSCRIPT first. - # Then try the linker which should give us the answer. - # Then check it worked. - [ -n "$(LDSCRIPT)" ] && \ - oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \ - oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\ - \ - [ -z $${oformat} ] && \ - oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\ - [ -z $${oarch} ] && \ - oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\ - \ - [ -z $${oformat} ] && \ - echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - [ -z $${oarch} ] && \ - echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - \ - cd $(dir ${DT_BIN}) && \ - $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \ - $(notdir ${DT_BIN}) $@ - rm $(DT_BIN) +obj-$(CONFIG_OF_EMBED) := dt.dtb.o -obj-$(CONFIG_OF_EMBED) := dt.o +dtbs: $(obj)/dt.dtb + @: -binary: $(DT_BIN) +clean-files := dt.dtb.S + +# Let clean descend into dts directories +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/examples/Makefile b/examples/Makefile new file mode 100644 index 0000000000..18d008e7b5 --- /dev/null +++ b/examples/Makefile @@ -0,0 +1,9 @@ +ifndef CONFIG_SANDBOX + +ifdef FTRACE +subdir-ccflags-y += -finstrument-functions -DFTRACE +endif + +subdir-y += standalone +subdir-$(CONFIG_API) += api +endif diff --git a/examples/api/Makefile b/examples/api/Makefile index cad10a3ecb..6cf23d10ac 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -11,59 +11,47 @@ ifeq ($(ARCH),arm) LOAD_ADDR = 0x1000000 endif -include $(TOPDIR)/config.mk - # Resulting ELF and binary exectuables will be named demo and demo.bin -OUTPUT = $(obj)demo +extra-y = demo # Source files located in the examples/api directory -SOBJ_FILES-y += crt0.o -COBJ_FILES-y += demo.o -COBJ_FILES-y += glue.o -COBJ_FILES-y += libgenwrap.o +OBJ-y += crt0.o +OBJ-y += demo.o +OBJ-y += glue.o +OBJ-y += libgenwrap.o # Source files which exist outside the examples/api directory -EXT_COBJ_FILES-y += lib/crc32.o -EXT_COBJ_FILES-y += lib/ctype.o -EXT_COBJ_FILES-y += lib/div64.o -EXT_COBJ_FILES-y += lib/string.o -EXT_COBJ_FILES-y += lib/time.o -EXT_COBJ_FILES-y += lib/vsprintf.o -EXT_SOBJ_FILES-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o - -# Create a list of source files so their dependencies can be auto-generated -SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S)) +EXT_COBJ-y += lib/crc32.o +EXT_COBJ-y += lib/ctype.o +EXT_COBJ-y += lib/div64.o +EXT_COBJ-y += lib/string.o +EXT_COBJ-y += lib/time.o +EXT_COBJ-y += lib/vsprintf.o +EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o # Create a list of object files to be compiled -OBJS += $(addprefix $(obj),$(SOBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(COBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y))) -OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y))) - -all: $(obj).depend $(OUTPUT) +OBJS := $(OBJ-y) $(notdir $(EXT_COBJ-y) $(EXT_SOBJ-y)) +targets += $(OBJS) +OBJS := $(addprefix $(obj)/,$(OBJS)) ######################################################################### -$(OUTPUT): $(OBJS) - $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS) - $(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null +quiet_cmd_link_demo = LD $@ +cmd_link_demo = $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $(filter-out $(PHONY), $^) $(PLATFORM_LIBS) + +$(obj)/demo: $(OBJS) FORCE + $(call if_changed,link_demo) + +# demo.bin is never genrated. Is this necessary? +OBJCOPYFLAGS_demo.bin := -O binary +$(obj)/demo.bin: $(obj)/demo FORCE + $(call if_changed,objcopy) # Rule to build generic library C files -$(obj)%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(CFLAGS) -c -o $@ $< +$(addprefix $(obj)/,$(notdir $(EXT_COBJ-y))): $(obj)/%.o: lib/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) # Rule to build architecture-specific library assembly files -$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S - $(CC) -g $(CFLAGS) -c -o $@ $< - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +$(addprefix $(obj)/,$(notdir $(EXT_SOBJ-y))): $(obj)/%.o: arch/powerpc/lib/%.S FORCE + $(call if_changed_dep,as_o_S) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 0841c758ff..9ab5446c68 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -5,45 +5,38 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ELF-y := hello_world - -ELF-$(CONFIG_SMC91111) += smc91111_eeprom -ELF-$(CONFIG_SMC911X) += smc911x_eeprom -ELF-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 -ELF-$(CONFIG_MPC5xxx) += interrupt -ELF-$(CONFIG_8xx) += test_burst timer -ELF-$(CONFIG_8260) += mem_to_mem_idma2intr -ELF-$(CONFIG_PPC) += sched +extra-y := hello_world +extra-$(CONFIG_SMC91111) += smc91111_eeprom +extra-$(CONFIG_SMC911X) += smc911x_eeprom +extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 +extra-$(CONFIG_MPC5xxx) += interrupt +extra-$(CONFIG_8xx) += test_burst timer +extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr +extra-$(CONFIG_PPC) += sched # # Some versions of make do not handle trailing white spaces properly; # leading to build failures. The problem was found with GNU Make 3.80. # Using 'strip' as a workaround for the problem. # -ELF := $(strip $(ELF-y)) +ELF := $(strip $(extra-y)) -SREC := $(addsuffix .srec,$(ELF)) -BIN := $(addsuffix .bin,$(ELF)) +extra-y += $(addsuffix .srec,$(extra-y)) $(addsuffix .bin,$(extra-y)) +clean-files := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra-)) COBJS := $(ELF:=.o) -LIB = $(obj)libstubs.o +LIB = $(obj)/libstubs.o -LIBAOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o -LIBAOBJS-$(CONFIG_8xx) += test_burst_lib.o -LIBAOBJS := $(LIBAOBJS-y) +LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o +LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o +LIBOBJS-y += stubs.o -LIBCOBJS = stubs.o +.SECONDARY: $(call objectify,$(COBJS)) +targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y) -LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) - -SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) -OBJS := $(addprefix $(obj),$(COBJS)) -ELF := $(addprefix $(obj),$(ELF)) -BIN := $(addprefix $(obj),$(BIN)) -SREC := $(addprefix $(obj),$(SREC)) +LIBOBJS := $(addprefix $(obj)/,$(LIBOBJS-y)) +ELF := $(addprefix $(obj)/,$(ELF)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) @@ -51,43 +44,34 @@ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) # relocatable executable. The relocation data is not needed, and # also causes the entry point of the standalone application to be # inconsistent. -ifeq ($(ARCH),powerpc) -AFLAGS := $(filter-out $(RELFLAGS),$(AFLAGS)) -CFLAGS := $(filter-out $(RELFLAGS),$(CFLAGS)) -CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS)) +ifeq ($(CONFIG_PPC),y) +PLATFORM_CPPFLAGS := $(filter-out $(RELFLAGS),$(PLATFORM_CPPFLAGS)) endif # We don't want gcc reordering functions if possible. This ensures that an # application's entry point will be the first function in the application's # source file. -CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder) -CFLAGS += $(CFLAGS_NTR) - -all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF) - -######################################################################### -$(LIB): $(obj).depend $(LIBOBJS) - $(call cmd_link_o_target, $(LIBOBJS)) - -$(ELF): -$(obj)%: $(obj)%.o $(LIB) - $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ - -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ - -L$(gcclibdir) -lgcc - -$(SREC): -$(obj)%.srec: $(obj)% - $(OBJCOPY) -O srec $< $@ 2>/dev/null - -$(BIN): -$(obj)%.bin: $(obj)% - $(OBJCOPY) -O binary $< $@ 2>/dev/null +ccflags-y += $(call cc-option,-fno-toplevel-reorder) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +quiet_cmd_link_lib = LD $@ + cmd_link_lib = $(LD) $(ld_flags) -r -o $@ $(filter $(LIBOBJS), $^) -sinclude $(obj).depend +$(LIB): $(LIBOBJS) FORCE + $(call if_changed,link_lib) -######################################################################### +quiet_cmd_link_elf = LD $@ + cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ + -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) -L$(gcclibdir) -lgcc + +$(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE + $(call if_changed,link_elf) + +$(obj)/%.srec: OBJCOPYFLAGS := -O srec +$(obj)/%.srec: $(obj)/% FORCE + $(call if_changed,objcopy) + +$(obj)/%.bin: OBJCOPYFLAGS := -O binary +$(obj)/%.bin: $(obj)/% FORCE + $(call if_changed,objcopy) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 32a19ce354..c5c025dab3 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -210,6 +210,19 @@ gd_t *global_data; " l.jr r13\n" \ " l.nop\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13"); +#elif defined(CONFIG_ARC) +/* + * r25 holds the pointer to the global_data. r10 is call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile( \ +" .align 4\n" \ +" .globl " #x "\n" \ +#x ":\n" \ +" ld r10, [r25, %0]\n" \ +" ld r10, [r10, %1]\n" \ +" j [r10]\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10"); #else /*" addi $sp, $sp, -24\n" \ " br $r16\n" \*/ diff --git a/fs/Makefile b/fs/Makefile index 34dc0351ed..18221658fc 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_CMD_CBFS) += cbfs/ obj-$(CONFIG_CMD_CRAMFS) += cramfs/ obj-$(CONFIG_FS_EXT4) += ext4/ obj-y += fat/ -obj-$(CONFIG_CMD_FDOS) += fdos/ obj-$(CONFIG_CMD_JFFS2) += jffs2/ obj-$(CONFIG_CMD_REISER) += reiserfs/ obj-$(CONFIG_SANDBOX) += sandbox/ diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 735b256417..417ce7b63b 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -174,6 +174,14 @@ int ext4fs_ls(const char *dirname) return 0; } +int ext4fs_exists(const char *filename) +{ + int file_len; + + file_len = ext4fs_open(filename); + return file_len >= 0; +} + int ext4fs_read(char *buf, unsigned len) { if (ext4fs_root == NULL || ext4fs_file == NULL) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 6ed4dfef79..0206b14d5f 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -829,7 +829,7 @@ __u8 do_fat_read_at_block[MAX_CLUSTSIZE] long do_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize, int dols) + unsigned long maxsize, int dols, int dogetsize) { char fnamecopy[2048]; boot_sector bs; @@ -1177,7 +1177,10 @@ rootdir_done: subname = nextname; } - ret = get_contents(mydata, dentptr, pos, buffer, maxsize); + if (dogetsize) + ret = FAT2CPU32(dentptr->size); + else + ret = get_contents(mydata, dentptr, pos, buffer, maxsize); debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret); exit: @@ -1188,7 +1191,7 @@ exit: long do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols) { - return do_fat_read_at(filename, 0, buffer, maxsize, dols); + return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0); } int file_fat_detectfs(void) @@ -1258,11 +1261,18 @@ int file_fat_ls(const char *dir) return do_fat_read(dir, NULL, 0, LS_YES); } +int fat_exists(const char *filename) +{ + int sz; + sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1); + return sz >= 0; +} + long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize) { printf("reading %s\n", filename); - return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO); + return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0); } long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile deleted file mode 100644 index 2f8b5addd6..0000000000 --- a/fs/fdos/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Stäubli Faverges - -# Pierre AUBERT p.aubert@staubli.com -# -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := fat.o vfat.o dev.o fdos.o fs.o subdir.o diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c deleted file mode 100644 index 4c48663e09..0000000000 --- a/fs/fdos/dev.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include "dos.h" -#include "fdos.h" - -#define NB_HEADS 2 -#define NB_TRACKS 80 -#define NB_SECTORS 18 - - -static int lastwhere; - -/*----------------------------------------------------------------------------- - * dev_open -- - *----------------------------------------------------------------------------- - */ -int dev_open (void) -{ - lastwhere = 0; - return (0); -} - -/*----------------------------------------------------------------------------- - * dev_read -- len and where are sectors number - *----------------------------------------------------------------------------- - */ -int dev_read (void *buffer, int where, int len) -{ - PRINTF ("dev_read (len = %d, where = %d)\n", len, where); - - /* Si on ne desire pas lire a la position courante, il faut un seek */ - if (where != lastwhere) { - if (!fdc_fdos_seek (where)) { - PRINTF ("seek error in dev_read"); - lastwhere = -1; - return (-1); - } - } - - if (!fdc_fdos_read (buffer, len)) { - PRINTF ("read error\n"); - lastwhere = -1; - return (-1); - } - lastwhere = where + len; - return (0); -} -/*----------------------------------------------------------------------------- - * check_dev -- verify the diskette format - *----------------------------------------------------------------------------- - */ -int check_dev (BootSector_t *boot, Fs_t *fs) -{ - unsigned int heads, sectors, tracks; - int BootP, Infp0, InfpX, InfTm; - int sect_per_track; - - /* Display Boot header */ - PRINTF ("Jump to boot code 0x%02x 0x%02x 0x%02x\n", - boot -> jump [0], boot -> jump [1], boot -> jump[2]); - PRINTF ("OEM name & version '%*.*s'\n", - BANNER_LG, BANNER_LG, boot -> banner ); - PRINTF ("Bytes per sector hopefully 512 %d\n", - __le16_to_cpu (boot -> secsiz)); - PRINTF ("Cluster size in sectors %d\n", - boot -> clsiz); - PRINTF ("Number of reserved (boot) sectors %d\n", - __le16_to_cpu (boot -> nrsvsect)); - PRINTF ("Number of FAT tables hopefully 2 %d\n", - boot -> nfat); - PRINTF ("Number of directory slots %d\n", - __le16_to_cpu (boot -> dirents)); - PRINTF ("Total sectors on disk %d\n", - __le16_to_cpu (boot -> psect)); - PRINTF ("Media descriptor=first byte of FAT %d\n", - boot -> descr); - PRINTF ("Sectors in FAT %d\n", - __le16_to_cpu (boot -> fatlen)); - PRINTF ("Sectors/track %d\n", - __le16_to_cpu (boot -> nsect)); - PRINTF ("Heads %d\n", - __le16_to_cpu (boot -> nheads)); - PRINTF ("number of hidden sectors %d\n", - __le32_to_cpu (boot -> nhs)); - PRINTF ("big total sectors %d\n", - __le32_to_cpu (boot -> bigsect)); - PRINTF ("physical drive ? %d\n", - boot -> physdrive); - PRINTF ("reserved %d\n", - boot -> reserved); - PRINTF ("dos > 4.0 diskette %d\n", - boot -> dos4); - PRINTF ("serial number %d\n", - __le32_to_cpu (boot -> serial)); - PRINTF ("disk label %*.*s\n", - LABEL_LG, LABEL_LG, boot -> label); - PRINTF ("FAT type %8.8s\n", - boot -> fat_type); - PRINTF ("reserved by 2M %d\n", - boot -> res_2m); - PRINTF ("2M checksum (not used) %d\n", - boot -> CheckSum); - PRINTF ("2MF format version %d\n", - boot -> fmt_2mf); - PRINTF ("1 if write track after format %d\n", - boot -> wt); - PRINTF ("data transfer rate on track 0 %d\n", - boot -> rate_0); - PRINTF ("data transfer rate on track<>0 %d\n", - boot -> rate_any); - PRINTF ("offset to boot program %d\n", - __le16_to_cpu (boot -> BootP)); - PRINTF ("T1: information for track 0 %d\n", - __le16_to_cpu (boot -> Infp0)); - PRINTF ("T2: information for track<>0 %d\n", - __le16_to_cpu (boot -> InfpX)); - PRINTF ("T3: track sectors size table %d\n", - __le16_to_cpu (boot -> InfTm)); - PRINTF ("Format date 0x%04x\n", - __le16_to_cpu (boot -> DateF)); - PRINTF ("Format time 0x%04x\n", - __le16_to_cpu (boot -> TimeF)); - - - /* information is extracted from boot sector */ - heads = __le16_to_cpu (boot -> nheads); - sectors = __le16_to_cpu (boot -> nsect); - fs -> tot_sectors = __le32_to_cpu (boot -> bigsect); - if (__le16_to_cpu (boot -> psect) != 0) { - fs -> tot_sectors = __le16_to_cpu (boot -> psect); - } - - sect_per_track = heads * sectors; - tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track; - - BootP = __le16_to_cpu (boot -> BootP); - Infp0 = __le16_to_cpu (boot -> Infp0); - InfpX = __le16_to_cpu (boot -> InfpX); - InfTm = __le16_to_cpu (boot -> InfTm); - - if (boot -> dos4 == EXTENDED_BOOT && - strncmp( boot->banner,"2M", 2 ) == 0 && - BootP < SZ_STD_SECTOR && - Infp0 < SZ_STD_SECTOR && - InfpX < SZ_STD_SECTOR && - InfTm < SZ_STD_SECTOR && - BootP >= InfTm + 2 && - InfTm >= InfpX && - InfpX >= Infp0 && - Infp0 >= 76 ) { - - return (-1); - } - - if (heads != NB_HEADS || - tracks != NB_TRACKS || - sectors != NB_SECTORS || - __le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR || - fs -> tot_sectors == 0 || - (fs -> tot_sectors % sectors) != 0) { - return (-1); - } - - return (0); -} diff --git a/fs/fdos/dos.h b/fs/fdos/dos.h deleted file mode 100644 index b0b7d2aa06..0000000000 --- a/fs/fdos/dos.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DOS_H_ -#define _DOS_H_ - -/* Definitions for Dos diskettes */ - -/* General definitions */ -#define SZ_STD_SECTOR 512 /* Standard sector size */ -#define MDIR_SIZE 32 /* Direntry size */ -#define FAT_BITS 12 /* Diskette use 12 bits fat */ - -#define MAX_PATH 128 /* Max size of the MSDOS PATH */ -#define MAX_DIR_SECS 64 /* Taille max d'un repertoire (en */ - /* secteurs) */ -/* Misc. definitions */ -#define DELMARK '\xe5' -#define EXTENDED_BOOT (0x29) -#define MEDIA_STD (0xf0) -#define JUMP_0_1 (0xe9) -#define JUMP_0_2 (0xeb) - -/* Boot size is 256 bytes, but we need to read almost a sector, then - assume bootsize is 512 */ -#define BOOTSIZE 512 - -/* Fat definitions for 12 bits fat */ -#define FAT12_MAX_NB 4086 -#define FAT12_LAST 0x0ff6 -#define FAT12_END 0x0fff - -/* file attributes */ -#define ATTR_READONLY 0x01 -#define ATTR_HIDDEN 0x02 -#define ATTR_SYSTEM 0x04 -#define ATTR_VOLUME 0x08 -#define ATTR_DIRECTORY 0x10 -#define ATTR_ARCHIVE 0x20 -#define ATTR_VSE 0x0f - -/* Name format */ -#define EXTCASE 0x10 -#define BASECASE 0x8 - -/* Definition of the boot sector */ -#define BANNER_LG 8 -#define LABEL_LG 11 - -typedef struct bootsector -{ - unsigned char jump [3]; /* 0 Jump to boot code */ - char banner [BANNER_LG]; /* 3 OEM name & version */ - unsigned short secsiz; /* 11 Bytes per sector hopefully 512 */ - unsigned char clsiz; /* 13 Cluster size in sectors */ - unsigned short nrsvsect; /* 14 Number of reserved (boot) sectors */ - unsigned char nfat; /* 16 Number of FAT tables hopefully 2 */ - unsigned short dirents; /* 17 Number of directory slots */ - unsigned short psect; /* 19 Total sectors on disk */ - unsigned char descr; /* 21 Media descriptor=first byte of FAT */ - unsigned short fatlen; /* 22 Sectors in FAT */ - unsigned short nsect; /* 24 Sectors/track */ - unsigned short nheads; /* 26 Heads */ - unsigned int nhs; /* 28 number of hidden sectors */ - unsigned int bigsect; /* 32 big total sectors */ - unsigned char physdrive; /* 36 physical drive ? */ - unsigned char reserved; /* 37 reserved */ - unsigned char dos4; /* 38 dos > 4.0 diskette */ - unsigned int serial; /* 39 serial number */ - char label [LABEL_LG]; /* 43 disk label */ - char fat_type [8]; /* 54 FAT type */ - unsigned char res_2m; /* 62 reserved by 2M */ - unsigned char CheckSum; /* 63 2M checksum (not used) */ - unsigned char fmt_2mf; /* 64 2MF format version */ - unsigned char wt; /* 65 1 if write track after format */ - unsigned char rate_0; /* 66 data transfer rate on track 0 */ - unsigned char rate_any; /* 67 data transfer rate on track<>0 */ - unsigned short BootP; /* 68 offset to boot program */ - unsigned short Infp0; /* 70 T1: information for track 0 */ - unsigned short InfpX; /* 72 T2: information for track<>0 */ - unsigned short InfTm; /* 74 T3: track sectors size table */ - unsigned short DateF; /* 76 Format date */ - unsigned short TimeF; /* 78 Format time */ - unsigned char junk [BOOTSIZE - 80]; /* 80 remaining data */ -} __attribute__ ((packed)) BootSector_t; - -/* Structure d'une entree de repertoire */ -typedef struct directory { - char name [8]; /* file name */ - char ext [3]; /* file extension */ - unsigned char attr; /* attribute byte */ - unsigned char Case; /* case of short filename */ - unsigned char reserved [9]; /* ?? */ - unsigned char time [2]; /* time stamp */ - unsigned char date [2]; /* date stamp */ - unsigned short start; /* starting cluster number */ - unsigned int size; /* size of the file */ -} __attribute__ ((packed)) Directory_t; - - -#define MAX_VFAT_SUBENTRIES 20 -#define VSE_NAMELEN 13 - -#define VSE1SIZE 5 -#define VSE2SIZE 6 -#define VSE3SIZE 2 - -#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1) - -#define MAX_VNAMELEN (255) - -#define VSE_PRESENT 0x01 -#define VSE_LAST 0x40 -#define VSE_MASK 0x1f - -/* Flag used by vfat_lookup */ -#define DO_OPEN 1 -#define ACCEPT_PLAIN 0x20 -#define ACCEPT_DIR 0x10 -#define ACCEPT_LABEL 0x08 -#define SINGLE 2 -#define MATCH_ANY 0x40 - -struct vfat_subentry { - unsigned char id; /* VSE_LAST pour la fin, VSE_MASK */ - /* pour un VSE */ - char text1 [VSE1SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char attribute; /* 0x0f pour les VFAT */ - unsigned char hash1; /* toujours 0 */ - unsigned char sum; /* Checksum du nom court */ - char text2 [VSE2SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char sector_l; /* 0 pour les VFAT */ - unsigned char sector_u; /* 0 pour les VFAT */ - char text3 [VSE3SIZE * 2]; /* Caracteres encodes sur 16 bits */ -} __attribute__ ((packed)) ; - -struct vfat_state { - char name [VBUFSIZE]; - int status; /* is now a bit map of 32 bits */ - int subentries; - unsigned char sum; /* no need to remember the sum for each */ - /* entry, it is the same anyways */ -} __attribute__ ((packed)) ; - -/* Conversion macros */ -#define DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980) -#define DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5))) -#define DOS_DAY(dir) ((dir)->date[0] & 0x1f) -#define DOS_HOUR(dir) ((dir)->time[1] >> 3) -#define DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5))) -#define DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2) - - -#endif diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c deleted file mode 100644 index 408fec7600..0000000000 --- a/fs/fdos/fat.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fat_decode -- - *----------------------------------------------------------------------------- - */ -unsigned int fat_decode (Fs_t *fs, unsigned int num) -{ - unsigned int start = num * 3 / 2; - unsigned char *address = fs -> fat_buf + start; - - if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR)) - return 1; - - if (num & 1) - return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4); - else - return ((address [1] & 0xf) << 8) | (address [0] & 0xff ); -} -/*----------------------------------------------------------------------------- - * check_fat -- - *----------------------------------------------------------------------------- - */ -static int check_fat (Fs_t *fs) -{ - int i, f; - - /* Cluster verification */ - for (i = 3 ; i < fs -> num_clus; i++){ - f = fat_decode (fs, i); - if (f < FAT12_LAST && f > fs -> num_clus){ - /* Wrong cluster number detected */ - return (-1); - } - } - return (0); -} -/*----------------------------------------------------------------------------- - * read_one_fat -- - *----------------------------------------------------------------------------- - */ -static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat) -{ - if (dev_read (fs -> fat_buf, - (fs -> fat_start + nfat * fs -> fat_len), - fs -> fat_len) < 0) { - return (-1); - } - - if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) { - if ((fs -> fat_buf [0] != boot -> descr && - (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) || - fs -> fat_buf [0] < MEDIA_STD){ - /* Unknown Media */ - return (-1); - } - if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){ - /* FAT doesn't start with good values */ - return (-1); - } - } - - if (fs -> num_clus >= FAT12_MAX_NB) { - /* Too much clusters */ - return (-1); - } - - return check_fat (fs); -} -/*----------------------------------------------------------------------------- - * read_fat -- - *----------------------------------------------------------------------------- - */ -int read_fat (BootSector_t *boot, Fs_t *fs) -{ - unsigned int buflen; - int i; - - /* Allocate Fat Buffer */ - buflen = fs -> fat_len * SZ_STD_SECTOR; - if (fs -> fat_buf) { - free (fs -> fat_buf); - } - - if ((fs -> fat_buf = malloc (buflen)) == NULL) { - return (-1); - } - - /* Try to read each Fat */ - for (i = 0; i< fs -> nb_fat; i++){ - if (read_one_fat (boot, fs, i) == 0) { - /* Fat is OK */ - fs -> num_fat = i; - break; - } - } - - if (i == fs -> nb_fat){ - return (-1); - } - - if (fs -> fat_len > (((fs -> num_clus + 2) * - (FAT_BITS / 4) -1 ) / 2 / - SZ_STD_SECTOR + 1)) { - return (-1); - } - return (0); -} diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c deleted file mode 100644 index 4e2f479191..0000000000 --- a/fs/fdos/fdos.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; - -Fs_t fs; -File_t file; - -/*----------------------------------------------------------------------------- - * dos_open -- - *----------------------------------------------------------------------------- - */ -int dos_open(char *name) -{ - int lg; - int entry; - char *fname; - - /* We need to suppress the " char around the name */ - if (name [0] == '"') { - name ++; - } - lg = strlen (name); - if (name [lg - 1] == '"') { - name [lg - 1] = '\0'; - } - - /* Open file system */ - if (fs_init (&fs) < 0) { - return -1; - } - - /* Init the file descriptor */ - file.name = name; - file.fs = &fs; - - /* find the subdirectory containing the file */ - if (open_subdir (&file) < 0) { - return (-1); - } - - fname = basename (name); - - /* if we try to open root directory */ - if (*fname == '\0') { - file.file = file.subdir; - return (0); - } - - /* find the file in the subdir */ - entry = 0; - if (vfat_lookup (&file.subdir, - file.fs, - &file.file.dir, - &entry, - 0, - fname, - ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN, - 0, - &file.file) != 0) { - /* File not found */ - printf ("File not found\n"); - return (-1); - } - - return 0; -} - -/*----------------------------------------------------------------------------- - * dos_read -- - *----------------------------------------------------------------------------- - */ -int dos_read (ulong addr) -{ - int read = 0, nb; - - /* Try to boot a directory ? */ - if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) { - printf ("Unable to boot %s !!\n", file.name); - return (-1); - } - while (read < file.file.FileSize) { - PRINTF ("read_file (%ld)\n", (file.file.FileSize - read)); - nb = read_file (&fs, - &file.file, - (char *)addr + read, - read, - (file.file.FileSize - read)); - PRINTF ("read_file -> %d\n", nb); - if (nb < 0) { - printf ("read error\n"); - return (-1); - } - read += nb; - } - return (read); -} -/*----------------------------------------------------------------------------- - * dos_dir -- - *----------------------------------------------------------------------------- - */ -int dos_dir (void) -{ - int entry; - Directory_t dir; - char *name; - - - if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) { - printf ("%s: not a directory !!\n", file.name); - return (1); - } - entry = 0; - if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) { - PRINTF ("Allcation error\n"); - return (1); - } - - while (vfat_lookup (&file.file, - file.fs, - &dir, - &entry, - 0, - NULL, - ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY, - name, - NULL) == 0) { - /* Display file info */ - printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n", - (dir.attr & ATTR_DIRECTORY) ? "dir" : " ", - __le32_to_cpu (dir.size), - month [DOS_MONTH (&dir) - 1], - DOS_DAY (&dir), - DOS_YEAR (&dir), - DOS_HOUR (&dir), - DOS_MINUTE (&dir), - DOS_SEC (&dir), - name); - - } - free (name); - return (0); -} diff --git a/fs/fdos/fdos.h b/fs/fdos/fdos.h deleted file mode 100644 index 2d8fe9d13d..0000000000 --- a/fs/fdos/fdos.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FDOS_H_ -#define _FDOS_H_ - - -#undef FDOS_DEBUG - -#ifdef FDOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* Data structure describing media */ -typedef struct fs -{ - unsigned long tot_sectors; - - int cluster_size; - int num_clus; - - int fat_start; - int fat_len; - int nb_fat; - int num_fat; - - int dir_start; - int dir_len; - - unsigned char *fat_buf; - -} Fs_t; - -/* Data structure describing one file system slot */ -typedef struct slot { - int (*map) (struct fs *fs, - struct slot *file, - int where, - int *len); - unsigned long FileSize; - - unsigned short int FirstAbsCluNr; - unsigned short int PreviousAbsCluNr; - unsigned short int PreviousRelCluNr; - - Directory_t dir; -} Slot_t; - -typedef struct file { - char *name; - int Case; - Fs_t *fs; - Slot_t subdir; - Slot_t file; -} File_t; - - -/* dev.c */ -int dev_read (void *buffer, int where, int len); -int dev_open (void); -int check_dev (BootSector_t *boot, Fs_t *fs); - -/* fat.c */ -unsigned int fat_decode (Fs_t *fs, unsigned int num); -int read_fat (BootSector_t *boot, Fs_t *fs); - -/* vfat.c */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file); - -/* subdir.c */ -char *basename (char *name); -int open_subdir (File_t *desc); -int open_file (Slot_t *file, Directory_t *dir); -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len); -void init_subdir (void); - -/* fs.c */ -int fs_init (Fs_t *fs); - - -#endif diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c deleted file mode 100644 index 39d3eae20d..0000000000 --- a/fs/fdos/fs.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fill_fs -- Read info on file system - *----------------------------------------------------------------------------- - */ -static int fill_fs (BootSector_t *boot, Fs_t *fs) -{ - - fs -> fat_start = __le16_to_cpu (boot -> nrsvsect); - fs -> fat_len = __le16_to_cpu (boot -> fatlen); - fs -> nb_fat = boot -> nfat; - - fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len; - fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR; - fs -> cluster_size = boot -> clsiz; - fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size; - - return (0); -} - -/*----------------------------------------------------------------------------- - * fs_init -- - *----------------------------------------------------------------------------- - */ -int fs_init (Fs_t *fs) -{ - BootSector_t *boot; - - /* Initialize physical device */ - if (dev_open () < 0) { - PRINTF ("Unable to initialize the fdc\n"); - return (-1); - } - init_subdir (); - - /* Allocate space for read the boot sector */ - if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) { - PRINTF ("Unable to allocate space for boot sector\n"); - return (-1); - } - - /* read boot sector */ - if (dev_read (boot, 0, 1)){ - PRINTF ("Error during boot sector read\n"); - free (boot); - return (-1); - } - - /* we verify it'a a DOS diskette */ - if (boot -> jump [0] != JUMP_0_1 && boot -> jump [0] != JUMP_0_2) { - PRINTF ("Not a DOS diskette\n"); - free (boot); - return (-1); - } - - if (boot -> descr < MEDIA_STD) { - /* We handle only recent medias (type F0) */ - PRINTF ("unrecognized diskette type\n"); - free (boot); - return (-1); - } - - if (check_dev (boot, fs) < 0) { - PRINTF ("Bad diskette\n"); - free (boot); - return (-1); - } - - if (fill_fs (boot, fs) < 0) { - free (boot); - - return (-1); - } - - /* Read FAT */ - if (read_fat (boot, fs) < 0) { - free (boot); - return (-1); - } - - free (boot); - return (0); -} diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c deleted file mode 100644 index 97f6fb7102..0000000000 --- a/fs/fdos/subdir.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int cache_sect; -static unsigned char cache [SZ_STD_SECTOR]; - - -#define min(x,y) ((x)<(y)?(x):(y)) - -static int descend (Slot_t *parent, - Fs_t *fs, - char *path); - -/*----------------------------------------------------------------------------- - * init_subdir -- - *----------------------------------------------------------------------------- - */ -void init_subdir (void) -{ - cache_sect = -1; -} -/*----------------------------------------------------------------------------- - * basename -- - *----------------------------------------------------------------------------- - */ -char *basename (char *name) -{ - register char *cptr; - - if (!name || !*name) { - return (""); - } - - for (cptr= name; *cptr++; ); - while (--cptr >= name) { - if (*cptr == '/') { - return (cptr + 1); - } - } - return(name); -} -/*----------------------------------------------------------------------------- - * root_map -- - *----------------------------------------------------------------------------- - */ -static int root_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where); - if (*len < 0 ) { - *len = 0; - return (-1); - } - return fs -> dir_start * SZ_STD_SECTOR + where; -} -/*----------------------------------------------------------------------------- - * normal_map -- - *----------------------------------------------------------------------------- - */ -static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - int offset; - int NrClu; - unsigned short RelCluNr; - unsigned short CurCluNr; - unsigned short NewCluNr; - unsigned short AbsCluNr; - int clus_size; - - clus_size = fs -> cluster_size * SZ_STD_SECTOR; - offset = where % clus_size; - - *len = min (*len, file -> FileSize - where); - - if (*len < 0 ) { - *len = 0; - return (0); - } - - if (file -> FirstAbsCluNr < 2){ - *len = 0; - return (0); - } - - RelCluNr = where / clus_size; - - if (RelCluNr >= file -> PreviousRelCluNr){ - CurCluNr = file -> PreviousRelCluNr; - AbsCluNr = file -> PreviousAbsCluNr; - } else { - CurCluNr = 0; - AbsCluNr = file -> FirstAbsCluNr; - } - - - NrClu = (offset + *len - 1) / clus_size; - while (CurCluNr <= RelCluNr + NrClu) { - if (CurCluNr == RelCluNr){ - /* we have reached the beginning of our zone. Save - * coordinates */ - file -> PreviousRelCluNr = RelCluNr; - file -> PreviousAbsCluNr = AbsCluNr; - } - NewCluNr = fat_decode (fs, AbsCluNr); - if (NewCluNr == 1 || NewCluNr == 0) { - PRINTF("Fat problem while decoding %d %x\n", - AbsCluNr, NewCluNr); - return (-1); - } - if (CurCluNr == RelCluNr + NrClu) { - break; - } - - if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) { - *len = 0; - return 0; - } - - if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1) - break; - CurCluNr++; - AbsCluNr = NewCluNr; - } - - *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset); - - return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size + - fs -> dir_start + fs -> dir_len) * - SZ_STD_SECTOR + offset); -} -/*----------------------------------------------------------------------------- - * open_subdir -- open the subdir containing the file - *----------------------------------------------------------------------------- - */ -int open_subdir (File_t *desc) -{ - char *pathname; - char *tmp, *s, *path; - char terminator; - - if ((pathname = (char *)malloc (MAX_PATH)) == NULL) { - return (-1); - } - - strcpy (pathname, desc -> name); - - /* Suppress file name */ - tmp = basename (pathname); - *tmp = '\0'; - - /* root directory init */ - desc -> subdir.FirstAbsCluNr = 0; - desc -> subdir.FileSize = -1; - desc -> subdir.map = root_map; - desc -> subdir.dir.attr = ATTR_DIRECTORY; - - tmp = pathname; - for (s = tmp; ; ++s) { - if (*s == '/' || *s == '\0') { - path = tmp; - terminator = *s; - *s = '\0'; - if (s != tmp && strcmp (path,".")) { - if (descend (&desc -> subdir, desc -> fs, path) < 0) { - free (pathname); - return (-1); - } - } - if (terminator == 0) { - break; - } - tmp = s + 1; - } - } - free (pathname); - return (0); -} -/*----------------------------------------------------------------------------- - * descend -- - *----------------------------------------------------------------------------- - */ -static int descend (Slot_t *parent, - Fs_t *fs, - char *path) -{ - int entry; - Slot_t SubDir; - - if(path[0] == '\0' || strcmp (path, ".") == 0) { - return (0); - } - - - entry = 0; - if (vfat_lookup (parent, - fs, - &(SubDir.dir), - &entry, - 0, - path, - ACCEPT_DIR | SINGLE | DO_OPEN, - 0, - &SubDir) == 0) { - *parent = SubDir; - return (0); - } - - if (strcmp(path, "..") == 0) { - parent -> FileSize = -1; - parent -> FirstAbsCluNr = 0; - parent -> map = root_map; - return (0); - } - return (-1); -} -/*----------------------------------------------------------------------------- - * open_file -- - *----------------------------------------------------------------------------- - */ -int open_file (Slot_t *file, Directory_t *dir) -{ - int first; - unsigned long size; - - first = __le16_to_cpu (dir -> start); - - if(first == 0 && - (dir -> attr & ATTR_DIRECTORY) != 0) { - file -> FirstAbsCluNr = 0; - file -> FileSize = -1; - file -> map = root_map; - return (0); - } - - if ((dir -> attr & ATTR_DIRECTORY) != 0) { - size = (1UL << 31) - 1; - } - else { - size = __le32_to_cpu (dir -> size); - } - - file -> map = normal_map; - file -> FirstAbsCluNr = first; - file -> PreviousRelCluNr = 0xffff; - file -> FileSize = size; - return (0); -} -/*----------------------------------------------------------------------------- - * read_file -- - *----------------------------------------------------------------------------- - */ -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len) -{ - int pos; - int read, nb, sect, offset; - - pos = file -> map (fs, file, where, &len); - if (pos < 0) { - return -1; - } - if (len == 0) { - return (0); - } - - /* Compute sector number */ - sect = pos / SZ_STD_SECTOR; - offset = pos % SZ_STD_SECTOR; - read = 0; - - if (offset) { - /* Read doesn't start at the sector beginning. We need to use our */ - /* cache */ - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return (-1); - } - cache_sect = sect; - } - nb = min (len, SZ_STD_SECTOR - offset); - - memcpy (buf, cache + offset, nb); - read += nb; - len -= nb; - sect += 1; - } - - if (len > SZ_STD_SECTOR) { - nb = (len - 1) / SZ_STD_SECTOR; - if (dev_read (buf + read, sect, nb) < 0) { - return ((read) ? read : -1); - } - /* update sector position */ - sect += nb; - - /* Update byte position */ - nb *= SZ_STD_SECTOR; - read += nb; - len -= nb; - } - - if (len) { - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return ((read) ? read : -1); - cache_sect = -1; - } - cache_sect = sect; - } - - memcpy (buf + read, cache, len); - read += len; - } - return (read); -} diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c deleted file mode 100644 index 2b87d0f5a7..0000000000 --- a/fs/fdos/vfat.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v); - -static int unicode_read (char *in, char *out, int num); -static int match (const char *s, const char *p); -static unsigned char sum_shortname (char *name); -static int check_vfat (struct vfat_state *v, Directory_t *dir); -static char *conv_name (char *name, char *ext, char Case, char *ans); - - -/*----------------------------------------------------------------------------- - * clear_vfat -- - *----------------------------------------------------------------------------- - */ -static void clear_vfat (struct vfat_state *v) -{ - v -> subentries = 0; - v -> status = 0; -} - -/*----------------------------------------------------------------------------- - * vfat_lookup -- - *----------------------------------------------------------------------------- - */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file) -{ - int found; - struct vfat_state vfat; - char newfile [VSE_NAMELEN]; - int vfat_present = 0; - - if (*entry == -1) { - return -1; - } - - found = 0; - clear_vfat (&vfat); - while (1) { - if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) { - if (vfat_start) { - *vfat_start = *entry; - } - break; - } - (*entry)++; - - /* Empty slot */ - if (dirent -> name[0] == '\0'){ - if (vfat_start == 0) { - break; - } - continue; - } - - if (dirent -> attr == ATTR_VSE) { - /* VSE entry, continue */ - continue; - } - if ( (dirent -> name [0] == DELMARK) || - ((dirent -> attr & ATTR_DIRECTORY) != 0 && - (flags & ACCEPT_DIR) == 0) || - ((dirent -> attr & ATTR_VOLUME) != 0 && - (flags & ACCEPT_LABEL) == 0) || - (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) && - (flags & ACCEPT_PLAIN) == 0)) { - clear_vfat (&vfat); - continue; - } - - vfat_present = check_vfat (&vfat, dirent); - if (vfat_start) { - *vfat_start = *entry - 1; - if (vfat_present) { - *vfat_start -= vfat.subentries; - } - } - - if (dirent -> attr & ATTR_VOLUME) { - strncpy (newfile, dirent -> name, 8); - newfile [8] = '\0'; - strncat (newfile, dirent -> ext, 3); - newfile [11] = '\0'; - } - else { - conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile); - } - - if (flags & MATCH_ANY) { - found = 1; - break; - } - - if ((vfat_present && match (vfat.name, filename)) || - (match (newfile, filename))) { - found = 1; - break; - } - clear_vfat (&vfat); - } - - if (found) { - if ((flags & DO_OPEN) && file) { - if (open_file (file, dirent) < 0) { - return (-1); - } - } - if (outname) { - if (vfat_present) { - strcpy (outname, vfat.name); - } - else { - strcpy (outname, newfile); - } - } - return (0); /* File found */ - } else { - *entry = -1; - return -1; /* File not found */ - } -} - -/*----------------------------------------------------------------------------- - * dir_read -- Read one directory entry - *----------------------------------------------------------------------------- - */ -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v) -{ - - /* read the directory entry */ - if (read_file (fs, - dir, - (char *)dirent, - num * MDIR_SIZE, - MDIR_SIZE) != MDIR_SIZE) { - return (-1); - } - - if (v && (dirent -> attr == ATTR_VSE)) { - struct vfat_subentry *vse; - unsigned char id, last_flag; - char *c; - - vse = (struct vfat_subentry *) dirent; - id = vse -> id & VSE_MASK; - last_flag = (vse -> id & VSE_LAST); - if (id > MAX_VFAT_SUBENTRIES) { - /* Invalid VSE entry */ - return (-1); - } - - - /* Decode VSE */ - if(v -> sum != vse -> sum) { - clear_vfat (v); - v -> sum = vse -> sum; - } - - - v -> status |= 1 << (id - 1); - if (last_flag) { - v -> subentries = id; - } - - c = &(v -> name [VSE_NAMELEN * (id - 1)]); - c += unicode_read (vse->text1, c, VSE1SIZE); - c += unicode_read (vse->text2, c, VSE2SIZE); - c += unicode_read (vse->text3, c, VSE3SIZE); - - if (last_flag) { - *c = '\0'; /* Null terminate long name */ - } - - } - return (0); -} - -/*----------------------------------------------------------------------------- - * unicode_read -- - *----------------------------------------------------------------------------- - */ -static int unicode_read (char *in, char *out, int num) -{ - int j; - - for (j = 0; j < num; ++j) { - if (in [1]) - *out = '_'; - else - *out = in [0]; - out ++; - in += 2; - } - return num; -} - -/*----------------------------------------------------------------------------- - * match -- - *----------------------------------------------------------------------------- - */ -static int match (const char *s, const char *p) -{ - - for (; *p != '\0'; ) { - if (toupper (*s) != toupper (*p)) { - return (0); - } - p++; - s++; - } - - if (*s != '\0') { - return (0); - } - else { - return (1); - } -} -/*----------------------------------------------------------------------------- - * sum_shortname -- - *----------------------------------------------------------------------------- - */ -static unsigned char sum_shortname (char *name) -{ - unsigned char sum; - int j; - - for (j = sum = 0; j < 11; ++j) { - sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) + - (name [j] ? name [j] : ' '); - } - return (sum); -} -/*----------------------------------------------------------------------------- - * check_vfat -- - * Return 1 if long name is valid, 0 else - *----------------------------------------------------------------------------- - */ -static int check_vfat (struct vfat_state *v, Directory_t *dir) -{ - char name[12]; - - if (v -> subentries == 0) { - return 0; - } - - strncpy (name, dir -> name, 8); - strncpy (name + 8, dir -> ext, 3); - name [11] = '\0'; - - if (v -> sum != sum_shortname (name)) { - return 0; - } - - if( (v -> status & ((1 << v -> subentries) - 1)) != - (1 << v -> subentries) - 1) { - return 0; - } - v->name [VSE_NAMELEN * v -> subentries] = 0; - - return 1; -} -/*----------------------------------------------------------------------------- - * conv_name -- - *----------------------------------------------------------------------------- - */ -static char *conv_name (char *name, char *ext, char Case, char *ans) -{ - char tname [9], text [4]; - int i; - - i = 0; - while (i < 8 && name [i] != ' ' && name [i] != '\0') { - tname [i] = name [i]; - i++; - } - tname [i] = '\0'; - - if (Case & BASECASE) { - for (i = 0; i < 8 && tname [i]; i++) { - tname [i] = tolower (tname [i]); - } - } - - i = 0; - while (i < 3 && ext [i] != ' ' && ext [i] != '\0') { - text [i] = ext [i]; - i++; - } - text [i] = '\0'; - - if (Case & EXTCASE){ - for (i = 0; i < 3 && text [i]; i++) { - text [i] = tolower (text [i]); - } - } - - if (*text) { - strcpy (ans, tname); - strcat (ans, "."); - strcat (ans, text); - } - else { - strcpy(ans, tname); - } - return (ans); -} diff --git a/fs/fs.c b/fs/fs.c index be1855d129..79d432d58f 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -41,6 +41,11 @@ static inline int fs_ls_unsupported(const char *dirname) return -1; } +static inline int fs_exists_unsupported(const char *filename) +{ + return 0; +} + static inline int fs_read_unsupported(const char *filename, void *buf, int offset, int len) { @@ -59,9 +64,19 @@ static inline void fs_close_unsupported(void) struct fstype_info { int fstype; + /* + * Is it legal to pass NULL as .probe()'s fs_dev_desc parameter? This + * should be false in most cases. For "virtual" filesystems which + * aren't based on a U-Boot block device (e.g. sandbox), this can be + * set to true. This should also be true for the dumm entry at the end + * of fstypes[], since that is essentially a "virtual" (non-existent) + * filesystem. + */ + bool null_dev_desc_ok; int (*probe)(block_dev_desc_t *fs_dev_desc, disk_partition_t *fs_partition); int (*ls)(const char *dirname); + int (*exists)(const char *filename); int (*read)(const char *filename, void *buf, int offset, int len); int (*write)(const char *filename, void *buf, int offset, int len); void (*close)(void); @@ -71,36 +86,46 @@ static struct fstype_info fstypes[] = { #ifdef CONFIG_FS_FAT { .fstype = FS_TYPE_FAT, + .null_dev_desc_ok = false, .probe = fat_set_blk_dev, .close = fat_close, .ls = file_fat_ls, + .exists = fat_exists, .read = fat_read_file, + .write = fs_write_unsupported, }, #endif #ifdef CONFIG_FS_EXT4 { .fstype = FS_TYPE_EXT, + .null_dev_desc_ok = false, .probe = ext4fs_probe, .close = ext4fs_close, .ls = ext4fs_ls, + .exists = ext4fs_exists, .read = ext4_read_file, + .write = fs_write_unsupported, }, #endif #ifdef CONFIG_SANDBOX { .fstype = FS_TYPE_SANDBOX, + .null_dev_desc_ok = true, .probe = sandbox_fs_set_blk_dev, .close = sandbox_fs_close, .ls = sandbox_fs_ls, + .exists = sandbox_fs_exists, .read = fs_read_sandbox, .write = fs_write_sandbox, }, #endif { .fstype = FS_TYPE_ANY, + .null_dev_desc_ok = true, .probe = fs_probe_unsupported, .close = fs_close_unsupported, .ls = fs_ls_unsupported, + .exists = fs_exists_unsupported, .read = fs_read_unsupported, .write = fs_write_unsupported, }, @@ -150,6 +175,9 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) fstype != info->fstype) continue; + if (!fs_dev_desc && !info->null_dev_desc_ok) + continue; + if (!info->probe(fs_dev_desc, &fs_partition)) { fs_type = info->fstype; return 0; @@ -182,6 +210,19 @@ int fs_ls(const char *dirname) return ret; } +int fs_exists(const char *filename) +{ + int ret; + + struct fstype_info *info = fs_get_info(fs_type); + + ret = info->exists(filename); + + fs_close(); + + return ret; +} + int fs_read(const char *filename, ulong addr, int offset, int len) { struct fstype_info *info = fs_get_info(fs_type); @@ -212,16 +253,11 @@ int fs_write(const char *filename, ulong addr, int offset, int len) void *buf; int ret; - /* - * We don't actually know how many bytes are being read, since len==0 - * means read the whole file. - */ buf = map_sysmem(addr, len); ret = info->write(filename, buf, offset, len); unmap_sysmem(buf); - /* If we requested a specific number of bytes, check we got it */ - if (ret >= 0 && len && ret != len) { + if (ret >= 0 && ret != len) { printf("** Unable to write file %s **\n", filename); ret = -1; } @@ -312,6 +348,15 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], return 0; } +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype) +{ + if (fs_set_blk_dev(dev_type, dev_part, fstype)) + return 0; + + return fs_exists(file); +} + int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype) { diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index dd028da8e3..85079788c9 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -72,6 +72,14 @@ int sandbox_fs_ls(const char *dirname) return 0; } +int sandbox_fs_exists(const char *filename) +{ + ssize_t sz; + + sz = os_get_filesize(filename); + return sz >= 0; +} + void sandbox_fs_close(void) { } diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 389b0e37e7..8c8c6ac683 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -13,6 +13,3 @@ obj-y := ubifs.o io.o super.o sb.o master.o lpt.o obj-y += lpt_commit.o scan.o lprops.o obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o obj-y += log.o orphan.o recovery.o replay.o - -# SEE README.arm-unaligned-accesses -$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 633631e4d4..2213201572 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -2137,6 +2137,13 @@ void ubifs_compress(const void *in_buf, int in_len, void *out_buf, int *out_len, int ubifs_decompress(const void *buf, int len, void *out, int *out_len, int compr_type); +/* these are used in cmd_ubifs.c */ +int ubifs_init(void); +int ubifs_mount(char *vol_name); +void ubifs_umount(struct ubifs_info *c); +int ubifs_ls(char *dir_name); +int ubifs_load(char *filename, u32 addr, u32 size); + #include "debug.h" #include "misc.h" #include "key.h" diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile index d811287ddb..45ff7458c6 100644 --- a/fs/yaffs2/Makefile +++ b/fs/yaffs2/Makefile @@ -24,9 +24,6 @@ obj-y := \ yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \ yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o -YCFLAGS = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM -YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE -YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES - -CFLAGS += $(YCFLAGS) -CPPFLAGS += $(YCFLAGS) +ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \ + -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \ + -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES diff --git a/fs/yaffs2/yaffs_list.h b/fs/yaffs2/yaffs_list.h deleted file mode 100644 index a7afaea27b..0000000000 --- a/fs/yaffs2/yaffs_list.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * YAFFS: Yet another Flash File System . A NAND-flash specific file system. - * - * Copyright (C) 2002-2011 Aleph One Ltd. - * for Toby Churchill Ltd and Brightstar Engineering - * - * Created by Charles Manning - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License version 2.1 as - * published by the Free Software Foundation. - * - * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. - */ - -/* - * This file is just holds extra declarations of macros that would normally - * be providesd in the Linux kernel. These macros have been written from - * scratch but are functionally equivalent to the Linux ones. - * - */ - -#ifndef __YAFFS_LIST_H__ -#define __YAFFS_LIST_H__ - - -/* - * This is a simple doubly linked list implementation that matches the - * way the Linux kernel doubly linked list implementation works. - */ - -struct list_head { - struct list_head *next; /* next in chain */ - struct list_head *prev; /* previous in chain */ -}; - - -/* Initialise a static list */ -#define LIST_HEAD(name) \ -struct list_head name = { &(name), &(name)} - - - -/* Initialise a list head to an empty list */ -#define INIT_LIST_HEAD(p) \ -do { \ - (p)->next = (p);\ - (p)->prev = (p); \ -} while (0) - - -/* Add an element to a list */ -static inline void list_add(struct list_head *new_entry, - struct list_head *list) -{ - struct list_head *list_next = list->next; - - list->next = new_entry; - new_entry->prev = list; - new_entry->next = list_next; - list_next->prev = new_entry; - -} - -static inline void list_add_tail(struct list_head *new_entry, - struct list_head *list) -{ - struct list_head *list_prev = list->prev; - - list->prev = new_entry; - new_entry->next = list; - new_entry->prev = list_prev; - list_prev->next = new_entry; - -} - - -/* Take an element out of its current list, with or without - * reinitialising the links.of the entry*/ -static inline void list_del(struct list_head *entry) -{ - struct list_head *list_next = entry->next; - struct list_head *list_prev = entry->prev; - - list_next->prev = list_prev; - list_prev->next = list_next; - -} - -static inline void list_del_init(struct list_head *entry) -{ - list_del(entry); - entry->next = entry->prev = entry; -} - - -/* Test if the list is empty */ -static inline int list_empty(struct list_head *entry) -{ - return (entry->next == entry); -} - - -/* list_entry takes a pointer to a list entry and offsets it to that - * we can find a pointer to the object it is embedded in. - */ - - -#define list_entry(entry, type, member) \ - ((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member))) - - -/* list_for_each and list_for_each_safe iterate over lists. - * list_for_each_safe uses temporary storage to make the list delete safe - */ - -#define list_for_each(itervar, list) \ - for (itervar = (list)->next; itervar != (list); itervar = itervar->next) - -#define list_for_each_safe(itervar, save_var, list) \ - for (itervar = (list)->next, save_var = (list)->next->next; \ - itervar != (list); \ - itervar = save_var, save_var = save_var->next) - - -#endif diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h index c2ffbfd56d..c6614f13b0 100644 --- a/fs/yaffs2/ydirectenv.h +++ b/fs/yaffs2/ydirectenv.h @@ -77,7 +77,7 @@ void yaffs_qsort(void *aa, size_t n, size_t es, #define YAFFS_ROOT_MODE 0666 #define YAFFS_LOSTNFOUND_MODE 0666 -#include "yaffs_list.h" +#include "linux/list.h" #include "yaffsfs.h" diff --git a/include/.gitignore b/include/.gitignore index 7cd3e90700..bf142fc2f9 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,5 +1,4 @@ /autoconf.mk* -/asm /bmp_logo.h /bmp_logo_data.h /config.h diff --git a/include/amba_clcd.h b/include/amba_clcd.h deleted file mode 100644 index db80517e53..0000000000 --- a/include/amba_clcd.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Register definitions for the AMBA CLCD logic cell. - * - * derived from David A Rusling, although rearranged as a C structure - * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. - * - * Copyright (C) 2001 ARM Limited - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * CLCD Controller Internal Register addresses - */ -struct clcd_registers { - u32 tim0; /* 0x00 */ - u32 tim1; - u32 tim2; - u32 tim3; - u32 ubas; /* 0x10 */ - u32 lbas; -#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) - u32 ienb; - u32 cntl; -#else /* Someone rearranged these two registers on the Versatile */ - u32 cntl; - u32 ienb; -#endif - u32 stat; /* 0x20 */ - u32 intr; - u32 ucur; - u32 lcur; - u32 unused[0x74]; /* 0x030..0x1ff */ - u32 palette[0x80]; /* 0x200..0x3ff */ -}; - -/* Bit definition for TIM2 */ -#define TIM2_CLKSEL (1 << 5) -#define TIM2_IVS (1 << 11) -#define TIM2_IHS (1 << 12) -#define TIM2_IPC (1 << 13) -#define TIM2_IOE (1 << 14) -#define TIM2_BCD (1 << 26) - -/* Bit definitions for control register */ -#define CNTL_LCDEN (1 << 0) -#define CNTL_LCDBPP1 (0 << 1) -#define CNTL_LCDBPP2 (1 << 1) -#define CNTL_LCDBPP4 (2 << 1) -#define CNTL_LCDBPP8 (3 << 1) -#define CNTL_LCDBPP16 (4 << 1) -#define CNTL_LCDBPP16_565 (6 << 1) -#define CNTL_LCDBPP24 (5 << 1) -#define CNTL_LCDBW (1 << 4) -#define CNTL_LCDTFT (1 << 5) -#define CNTL_LCDMONO8 (1 << 6) -#define CNTL_LCDDUAL (1 << 7) -#define CNTL_BGR (1 << 8) -#define CNTL_BEBO (1 << 9) -#define CNTL_BEPO (1 << 10) -#define CNTL_LCDPWR (1 << 11) -#define CNTL_LCDVCOMP(x) ((x) << 12) -#define CNTL_LDMAFIFOTIME (1 << 15) -#define CNTL_WATERMARK (1 << 16) - -/* u-boot specific: information passed by the board file */ -struct clcd_config { - struct clcd_registers *address; - u32 tim0; - u32 tim1; - u32 tim2; - u32 tim3; - u32 cntl; - unsigned long pixclock; -}; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 0de0beaa8b..707400e847 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -21,6 +21,8 @@ */ #ifndef __ASSEMBLY__ +#include + typedef struct global_data { bd_t *bd; unsigned long flags; @@ -61,6 +63,12 @@ typedef struct global_data { unsigned long start_addr_sp; /* start_addr_stackpointer */ unsigned long reloc_off; struct global_data *new_gd; /* relocated global data */ + +#ifdef CONFIG_DM + struct device *dm_root; /* Root instance for Driver Model */ + struct list_head uclass_root; /* Head of core tree */ +#endif + const void *fdt_blob; /* Our device tree, NULL if none */ void *new_fdt; /* Relocated FDT */ unsigned long fdt_size; /* Space reserved for relocated FDT */ diff --git a/include/asm-generic/global_data_flags.h b/include/asm-generic/global_data_flags.h deleted file mode 100644 index bb57fb6c4a..0000000000 --- a/include/asm-generic/global_data_flags.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * transitional header until we merge global_data.h - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_GENERIC_GLOBAL_DATA_FLAGS_H -#define __ASM_GENERIC_GLOBAL_DATA_FLAGS_H - -/* - * Global Data Flags - * - * Note: The low 16 bits are expected for common code. If your arch - * really needs to add your own, use the high 16bits. - */ -#define GD_FLG_RELOC 0x0001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x0002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x0004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x0008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x0010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x0020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x0040 /* Disable console (in & out) */ -#define GD_FLG_ENV_READY 0x0080 /* Environment imported into hash table */ - -#endif diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index f54103980c..e325df40d9 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -78,4 +78,108 @@ int gpio_get_value(unsigned gpio); * @return 0 if ok, -1 on error */ int gpio_set_value(unsigned gpio, int value); + +/* State of a GPIO, as reported by get_state() */ +enum { + GPIOF_INPUT = 0, + GPIOF_OUTPUT, + GPIOF_UNKNOWN, +}; + +struct device; + +/** + * struct struct dm_gpio_ops - Driver model GPIO operations + * + * Refer to functions above for description. These function largely copy + * the old API. + * + * This is trying to be close to Linux GPIO API. Once the U-Boot uses the + * new DM GPIO API, this should be really easy to flip over to the Linux + * GPIO API-alike interface. + * + * Akso it would be useful to standardise additional functions like + * pullup, slew rate and drive strength. + * + * gpio_request)( and gpio_free() are optional - if NULL then they will + * not be called. + * + * Note that @offset is the offset from the base GPIO of the device. So + * offset 0 is the device's first GPIO and offset o-1 is the last GPIO, + * where o is the number of GPIO lines controlled by the device. A device + * is typically used to control a single bank of GPIOs. Within complex + * SoCs there may be many banks and therefore many devices all referring + * to the different IO addresses within the SoC. + * + * The uclass combines all GPIO devices togther to provide a consistent + * numbering from 0 to n-1, where n is the number of GPIOs in total across + * all devices. Be careful not to confuse offset with gpio in the parameters. + */ +struct dm_gpio_ops { + int (*request)(struct device *dev, unsigned offset, const char *label); + int (*free)(struct device *dev, unsigned offset); + int (*direction_input)(struct device *dev, unsigned offset); + int (*direction_output)(struct device *dev, unsigned offset, + int value); + int (*get_value)(struct device *dev, unsigned offset); + int (*set_value)(struct device *dev, unsigned offset, int value); + int (*get_function)(struct device *dev, unsigned offset); + int (*get_state)(struct device *dev, unsigned offset, char *state, + int maxlen); +}; + +/** + * struct gpio_dev_priv - information about a device used by the uclass + * + * The uclass combines all active GPIO devices into a unified numbering + * scheme. To do this it maintains some private information aobut each + * device. + * + * To implement driver model support in your GPIO driver, add a probe + * handler, and set @gpio_count and @bank_name correctly in that handler. + * This tells the uclass the name of the GPIO bank and the number of GPIOs + * it contains. + * + * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called + * 'A0', 'A1', etc. + * @gpio_count: Number of GPIOs in this device + * @gpio_base: Base GPIO number for this device. For the first active device + * this will be 0; the numbering for others will follow sequentially so that + * @gpio_base for device 1 will equal the number of GPIOs in device 0. + */ +struct gpio_dev_priv { + const char *bank_name; + unsigned gpio_count; + unsigned gpio_base; +}; + +/* Access the GPIO operations for a device */ +#define gpio_get_ops(dev) ((struct dm_gpio_ops *)(dev)->driver->ops) + +/** + * gpio_get_bank_info - Return information about a GPIO bank/device + * + * This looks up a device and returns both its GPIO base name and the number + * of GPIOs it controls. + * + * @dev: Device to look up + * @offset_count: Returns number of GPIOs within this bank + * @return bank name of this device + */ +const char *gpio_get_bank_info(struct device *dev, int *offset_count); + +/** + * gpio_lookup_name - Look up a GPIO name and return its details + * + * This is used to convert a named GPIO into a device, offset and GPIO + * number. + * + * @name: GPIO name to look up + * @devp: Returns pointer to device which contains this GPIO + * @offsetp: Returns the offset number within this device + * @gpiop: Returns the absolute GPIO number, numbered from 0 + */ +int gpio_lookup_name(const char *name, struct device **devp, + unsigned int *offsetp, unsigned int *gpiop); + #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 7e1eb4bf5e..458952fb58 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -63,28 +63,16 @@ extern char __image_copy_end[]; extern void _start(void); /* - * ARM needs to use offsets for symbols, since the values of some symbols - * are not resolved prior to relocation (and are just 0). Maybe this can be - * resolved, or maybe other architectures are similar, iwc this should be - * promoted to an architecture option. + * ARM defines its symbols as char[]. Other arches define them as ulongs. */ #ifdef CONFIG_ARM -#define CONFIG_SYS_SYM_OFFSETS -#endif -#ifdef CONFIG_SYS_SYM_OFFSETS -/* Start/end of the relocation entries, as an offset from _start */ -extern ulong _rel_dyn_start_ofs; -extern ulong _rel_dyn_end_ofs; - -/* End of the region to be relocated, as an offset form _start */ -extern ulong _image_copy_end_ofs; - -extern ulong _bss_start_ofs; /* BSS start relative to _start */ -extern ulong _bss_end_ofs; /* BSS end relative to _start */ -extern ulong _end_ofs; /* end of image relative to _start */ - -extern ulong _TEXT_BASE; /* code start */ +extern char __bss_start[]; +extern char __bss_end[]; +extern char __image_copy_start[]; +extern char __image_copy_end[]; +extern char __rel_dyn_start[]; +extern char __rel_dyn_end[]; #else /* don't use offsets: */ diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 43872010c7..e78196797b 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -37,7 +37,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif diff --git a/include/at45.h b/include/at45.h deleted file mode 100644 index df649ba971..0000000000 --- a/include/at45.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef _AT45_H_ -#define _AT45_H_ -#ifdef CONFIG_DATAFLASH_MMC_SELECT -extern void AT91F_SelectMMC(void); -extern void AT91F_SelectSPI(void); -extern int AT91F_GetMuxStatus(void); -#endif -extern void AT91F_SpiInit(void); -extern void AT91F_SpiEnable(int cs); -extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ); -extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress); -extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( - AT91PS_DataflashDesc pDesc); -extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( - AT91PS_DataflashDesc pDataFlashDesc, - unsigned int timeout); -extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ); -extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite); -extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page); -extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ); -extern AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page); -extern AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block); -extern AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ); -extern AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size); -extern AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ); -extern int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer); -extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc); - -#endif diff --git a/include/at91rm9200_i2c.h b/include/at91rm9200_i2c.h deleted file mode 100644 index 486660638c..0000000000 --- a/include/at91rm9200_i2c.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* ATMEL Microcontroller Software Support - ROUSSET - */ -/* ---------------------------------------------------------------------------- */ -/* The software is delivered "AS IS" without warranty or condition of any */ -/* kind, either express, implied or statutory. This includes without */ -/* limitation any warranty or condition with respect to merchantability or */ -/* fitness for any particular purpose, or against the infringements of */ -/* intellectual property rights of others. */ -/* ---------------------------------------------------------------------------- */ -/* File Name : at91rm9200_i2c.h */ -/* Object : AT91RM9200 / TWI definitions */ -/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */ -/* */ -/* ---------------------------------------------------------------------------- */ - -#ifndef AT91RM9200_TWI_H -#define AT91RM9200_TWI_H - -/* ******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ******************************************************************************/ -#ifndef __ASSEMBLY__ - -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; /* Control Register */ - AT91_REG TWI_MMR; /* Master Mode Register */ - AT91_REG TWI_SMR; /* Slave Mode Register */ - AT91_REG TWI_IADR; /* Internal Address Register */ - AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ - AT91_REG Reserved0[3]; - AT91_REG TWI_SR; /* Status Register */ - AT91_REG TWI_IER; /* Interrupt Enable Register */ - AT91_REG TWI_IDR; /* Interrupt Disable Register */ - AT91_REG TWI_IMR; /* Interrupt Mask Register */ - AT91_REG TWI_RHR; /* Receive Holding Register */ - AT91_REG TWI_THR; /* Transmit Holding Register */ - AT91_REG Reserved1[50]; - AT91_REG TWI_RPR; /* Receive Pointer Register */ - AT91_REG TWI_RCR; /* Receive Counter Register */ - AT91_REG TWI_TPR; /* Transmit Pointer Register */ - AT91_REG TWI_TCR; /* Transmit Counter Register */ - AT91_REG TWI_RNPR; /* Receive Next Pointer Register */ - AT91_REG TWI_RNCR; /* Receive Next Counter Register */ - AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG TWI_TNCR; /* Transmit Next Counter Register */ - AT91_REG TWI_PTCR; /* PDC Transfer Control Register */ - AT91_REG TWI_PTSR; /* PDC Transfer Status Register */ -} AT91S_TWI, *AT91PS_TWI; - -#endif - -/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ -#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */ -#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */ -#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */ -#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */ -#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */ -#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */ -#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ -#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */ -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */ -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */ -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */ -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */ -#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */ -#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ -#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ -#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */ -#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */ -#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ -#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */ -#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */ -#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/ -#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */ -#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */ -#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */ -#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */ -#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */ -#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */ -#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */ -/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ -/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */ -/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ - -/* - i2c Support for Atmel's AT91RM9200 Two-Wire Interface - - (c) Rick Bronson - - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef AT91_I2C_H -#define AT91_I2C_H - -#define AT91C_TWI_CLOCK 100000 -#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK) -#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */ - -#if (AT91C_TWI_SCLOCK % 10) >= 5 -#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5) -#else -#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6) -#endif -#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2) - -#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16) - -#endif /* __ASSEMBLY__ */ -#endif /* AT91RM9200_TWI_H */ diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h deleted file mode 100644 index 831cb1e260..0000000000 --- a/include/at91rm9200_net.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Ethernet: An implementation of the Ethernet Device Driver suite for the - * uClinux 2.0.38 operating system. This Driver has been developed - * for AT75C220 board. - * - * NOTE: The driver is implemented for one MAC - * - * Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001 - * - * Authors: Lineo Inc - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91RM9200_ETHERNET -#define AT91RM9200_ETHERNET - -#include -#include -#include - -#define ETHERNET_ADDRESS_SIZE 6 - -typedef unsigned char UCHAR; - -/* Interface to drive the physical layer */ -typedef struct _AT91S_PhyOps -{ - unsigned char (*Init)(AT91S_EMAC *pmac); - unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac); - unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac); - unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *); - -} AT91S_PhyOps,*AT91PS_PhyOps; - - -#define EMAC_DESC_DONE 0x00000001 /* ownership bit */ -#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ - -/****************** function prototypes **********************/ - -/* MII functions */ -void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac); -void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac); -UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput); -UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput); -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops); - -#endif /* AT91RM9200_ETHERNET */ diff --git a/include/bcm5221.h b/include/bcm5221.h deleted file mode 100644 index 4719389cfd..0000000000 --- a/include/bcm5221.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Broadcom BCM5221 Ethernet PHY - * - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define BCM5221_BMCR 0 /* Basic Mode Control Register */ -#define BCM5221_BMSR 1 /* Basic Mode Status Register */ -#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */ -#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */ -#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */ -#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */ -#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */ -#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */ -#define BCM5221_INTR 26 /* Interrupt Register */ - -/* --Bit definitions: BCM5221_BMCR */ -#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ -#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ -#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ -#define BCM5221_AUTONEG (1 << 12) -#define BCM5221_POWER_DOWN (1 << 11) -#define BCM5221_ISOLATE (1 << 10) -#define BCM5221_RESTART_AUTONEG (1 << 9) -#define BCM5221_DUPLEX_MODE (1 << 8) -#define BCM5221_COLLISION_TEST (1 << 7) - -/*--Bit definitions: BCM5221_BMSR */ -#define BCM5221_100BASE_T4 (1 << 15) -#define BCM5221_100BASE_TX_FD (1 << 14) -#define BCM5221_100BASE_TX_HD (1 << 13) -#define BCM5221_10BASE_T_FD (1 << 12) -#define BCM5221_10BASE_T_HD (1 << 11) -#define BCM5221_MF_PREAMB_SUPPR (1 << 6) -#define BCM5221_AUTONEG_COMP (1 << 5) -#define BCM5221_REMOTE_FAULT (1 << 4) -#define BCM5221_AUTONEG_ABILITY (1 << 3) -#define BCM5221_LINK_STATUS (1 << 2) -#define BCM5221_JABBER_DETECT (1 << 1) -#define BCM5221_EXTEND_CAPAB (1 << 0) - -/*--definitions: BCM5221_PHYID1 */ -#define BCM5221_PHYID1_OUI 0x1018 -#define BCM5221_LSB_MASK 0x3F - -/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */ -#define BCM5221_NP (1 << 15) -#define BCM5221_ACK (1 << 14) -#define BCM5221_RF (1 << 13) -#define BCM5221_FCS (1 << 10) -#define BCM5221_T4 (1 << 9) -#define BCM5221_TX_FDX (1 << 8) -#define BCM5221_TX_HDX (1 << 7) -#define BCM5221_10_FDX (1 << 6) -#define BCM5221_10_HDX (1 << 5) -#define BCM5221_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: BCM5221_ANER */ -#define BCM5221_PDF (1 << 4) -#define BCM5221_LP_NP_ABLE (1 << 3) -#define BCM5221_NP_ABLE (1 << 2) -#define BCM5221_PAGE_RX (1 << 1) -#define BCM5221_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: BCM5221_ACSR */ -#define BCM5221_100 (1 << 1) -#define BCM5221_FDX (1 << 0) - -/*--Bit definitions: BCM5221_INTR */ -#define BCM5221_FDX_LED (1 << 15) -#define BCM5221_INTR_ENABLE (1 << 14) -#define BCM5221_FDX_MASK (1 << 11) -#define BCM5221_SPD_MASK (1 << 10) -#define BCM5221_LINK_MASK (1 << 9) -#define BCM5221_INTR_MASK (1 << 8) -#define BCM5221_FDX_CHG (1 << 3) -#define BCM5221_SPD_CHG (1 << 2) -#define BCM5221_LINK_CHG (1 << 1) -#define BCM5221_INTR_STATUS (1 << 0) - -/****************** function prototypes **********************/ -unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac); -unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac); -unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/bitfield.h b/include/bitfield.h new file mode 100644 index 0000000000..ec4815c8e0 --- /dev/null +++ b/include/bitfield.h @@ -0,0 +1,58 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Bitfield operations + * + * These are generic bitfield operations which allow manipulation of variable + * width bitfields within a word. One use of this would be to use data tables + * to determine how to reprogram fields within R/W hardware registers. + * + * Example: + * + * old_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | old | | + * +--------+----+---+--+-----+----------+ + * + * new_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | new | | + * +--------+----+---+--+-----+----------+ + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract(old_reg_val, 10, 5); + * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); + * + * The numbers 10 and 5 could for example come from data + * tables which describe all bitfields in all registers. + */ + +#include + +/* Produces a mask of set bits covering a range of a uint value */ +static inline uint bitfield_mask(uint shift, uint width) +{ + return ((1 << width) - 1) << shift; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract(uint reg_val, uint shift, uint width) +{ + return (reg_val & bitfield_mask(shift, width)) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace(uint reg_val, uint shift, uint width, + uint bitfield_val) +{ + uint mask = bitfield_mask(shift, width); + + return (reg_val & ~mask) | (bitfield_val << shift); +} diff --git a/include/command.h b/include/command.h index f782779d8b..d3f700fc3c 100644 --- a/include/command.h +++ b/include/command.h @@ -64,6 +64,15 @@ extern int var_complete(int argc, char * const argv[], char last_char, int maxv, extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); #endif +/** + * cmd_process_error() - report and process a possible error + * + * @cmdtp: Command which caused the error + * @err: Error code (0 if none, -ve for error, like -EIO) + * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found + */ +int cmd_process_error(cmd_tbl_t *cmdtp, int err); + /* * Monitor Command * diff --git a/include/common.h b/include/common.h index ae45836b94..cbd3c9e043 100644 --- a/include/common.h +++ b/include/common.h @@ -8,9 +8,6 @@ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLY__ /* put C only stuff in this section */ typedef unsigned char uchar; @@ -55,16 +52,13 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC512X) #include -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ || defined(CONFIG_MPC8271) \ || defined(CONFIG_MPC8272) #define CONFIG_MPC8272_FAMILY 1 #endif -#if defined(CONFIG_MPC8272_FAMILY) -#define CONFIG_MPC8260 1 -#endif #include #endif #ifdef CONFIG_MPC86xx @@ -99,6 +93,10 @@ typedef volatile unsigned char vu_char; #include #include +#ifdef __LP64__ +#define CONFIG_SYS_SUPPORT_64BIT_DATA +#endif + #ifdef DEBUG #define _DEBUG 1 #else @@ -305,10 +303,18 @@ int checkdram (void); int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); -extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ +extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void); +#else +static inline int print_cpuinfo(void) +{ + return 0; +} +#endif int update_flash_size(int flash_size); +int arch_early_init_r(void); /** * Show the DRAM size in a board-specific way @@ -355,6 +361,11 @@ int do_ext2load(cmd_tbl_t *, int, int, char * const []); int env_init (void); void env_relocate (void); int envmatch (uchar *, int); + +/* Avoid unfortunate conflict with libc's getenv() */ +#ifdef CONFIG_SANDBOX +#define getenv uboot_getenv +#endif char *getenv (const char *); int getenv_f (const char *name, char *buf, unsigned len); ulong getenv_ulong(const char *name, int base, ulong default_val); @@ -411,6 +422,9 @@ static inline int setenv_addr(const char *varname, const void *addr) #ifdef CONFIG_MIPS # include #endif /* CONFIG_MIPS */ +#ifdef CONFIG_ARC +# include +#endif /* CONFIG_ARC */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); @@ -454,6 +468,7 @@ void api_init (void); /* common/memsize.c */ long get_ram_size (long *, long); +phys_size_t get_effective_memsize(void); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); @@ -657,7 +672,7 @@ int get_clocks (void); int get_clocks_866 (void); int sdram_adjust_866 (void); int adjust_sdram_tbs_8xx (void); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) int prt_8260_clks (void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); @@ -725,7 +740,7 @@ void get_sys_info ( sys_info_t * ); #endif /* $(CPU)/cpu_init.c */ -#if defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) void cpu_init_f (volatile immap_t *immr); #endif #if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) @@ -733,7 +748,7 @@ void cpu_init_f (void); #endif int cpu_init_r (void); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) int prt_8260_rsr (void); #elif defined(CONFIG_MPC83xx) int prt_83xx_rsr (void); @@ -807,8 +822,7 @@ void udelay (unsigned long); void mdelay(unsigned long); /* lib/uuid.c */ -void uuid_str_to_bin(const char *uuid, unsigned char *out); -int uuid_str_valid(const char *uuid); +#include /* lib/vsprintf.c */ #include @@ -820,9 +834,7 @@ char * strmhz(char *buf, unsigned long hz); #include /* lib/rand.c */ -#if defined(CONFIG_RANDOM_MACADDR) || \ - defined(CONFIG_BOOTP_RANDOM_DELAY) || \ - defined(CONFIG_CMD_LINK_LOCAL) +#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index a32b67286e..9e62af27e1 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -38,7 +38,6 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ -#define CONFIG_CMD_FDOS /* Floppy DOS support */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_FUSE /* Device fuse support */ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h new file mode 100644 index 0000000000..5d18a4b903 --- /dev/null +++ b/include/config_distro_defaults.h @@ -0,0 +1,56 @@ +/* + * Copyright 2013-2014 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H +#define _CONFIG_CMD_DISTRO_DEFAULTS_H + +/* + * List of all commands and options that when defined enables support for + * features required by distros to support boards in a standardised and + * consitant manner. + */ + +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK + +#if defined(__arm__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#else +#define CONFIG_BOOTP_VCI_STRING "U-boot.arm" +#endif +#endif + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_PXE + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 2 +#define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SYS_HUSH_PARSER + +#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index d8339b26cc..e6fb47be0b 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -55,6 +55,22 @@ #define HAVE_BLOCK_DEVICE #endif +#if (defined(CONFIG_PARTITION_UUIDS) || \ + defined(CONFIG_EFI_PARTITION) || \ + defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID) || \ + defined(CONFIG_BOOTP_PXE)) && \ + !defined(CONFIG_LIB_UUID) +#define CONFIG_LIB_UUID +#endif + +#if (defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID)) && \ + (!defined(CONFIG_LIB_RAND) && \ + !defined(CONFIG_LIB_HW_RAND)) +#define CONFIG_LIB_RAND +#endif + #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "=> " #endif diff --git a/include/configs/A3000.h b/include/configs/A3000.h index 8f3a672cd5..35e3e6fa8b 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -25,7 +25,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_A3000 1 diff --git a/include/configs/APC405.h b/include/configs/APC405.h index afc9ae885f..2678f50bbb 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -19,7 +19,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/AR405.h b/include/configs/AR405.h index a4bd4b1d6a..45dd46a41e 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_AR405 1 /* ...on a AR405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 2f5340723d..2ff9b598c5 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_ASH405 1 /* ...on a ASH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h deleted file mode 100644 index ef76ce4cfc..0000000000 --- a/include/configs/AdderUSB.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2006 CodeHermit. - * Bryan O'Donoghue - * - * Provides support for USB console on the Analogue & Micro Adder87x - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ADDERUSB__ -#define __ADDERUSB__ - -/* Include the board port */ -#include "Adder.h" - -#define CONFIG_USB_DEVICE /* Include UDC driver */ -#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */ -#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */ -#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */ - -/* If you have a USB-IF assigned VendorID then you may wish to define - * your own vendor specific values either in BoardName.h or directly in - * usbd_vendor_info.h - */ - -/* -#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie" -#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot" -#define CONFIG_USBD_VENDORID 0xFFFF -#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF -#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE -*/ - -#endif /* __ADDERUSB_H__ */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c182158be4..b248302687 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -16,8 +16,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -34,11 +34,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -115,7 +114,7 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -608,7 +607,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -621,7 +620,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 377db7be9a..802e9cce1f 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -22,8 +22,7 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 584aba8d0e..a163e3d8f1 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -38,7 +38,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -55,7 +55,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -326,7 +325,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_IS_IN_NAND #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 6170cbc81f..052a0f1103 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -22,7 +22,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 #ifdef CONFIG_SPIFLASH @@ -30,7 +30,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -47,7 +47,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -55,7 +55,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x8ff80000 +#define CONFIG_SYS_TEXT_BASE 0x8ff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -71,7 +71,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ @@ -540,6 +539,7 @@ combinations. this should be removed later */ #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_RAMBOOT_SPIFLASH) @@ -554,7 +554,7 @@ combinations. this should be removed later #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ @@ -562,13 +562,9 @@ combinations. this should be removed later #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#define CONFIG_ENV_SECT_SIZE 0x20000 #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 1cfb2c2279..92913c8e79 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -20,25 +20,73 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ @@ -130,6 +178,10 @@ (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NO_FLASH +#endif + /* * IFC Definitions */ @@ -183,7 +235,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) /* 8Bit NAND Flash - K9F1G08U0B */ #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -215,6 +267,23 @@ #define CONFIG_SYS_NAND_DDR_LAW 11 /* Set up IFC registers for boot location NOR/NAND */ +#ifdef CONFIG_NAND +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR @@ -230,6 +299,7 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif /* CPLD on IFC, selected by CS2 */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 @@ -269,7 +339,44 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) + +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -278,6 +385,10 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -364,13 +475,19 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 #endif +#elif defined(CONFIG_NAND) +#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE +#endif +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 #endif diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index ba5dba55aa..27539d27d7 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -59,7 +59,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 0bb22be9f3..5b872f61a0 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 764ca2215f..a75c52f2c7 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -25,7 +25,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_CPC45 1 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 85720a503c..05106cde90 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 793ee752d6..34252d4d3b 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 53cf498dbe..bf85439802 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index ce310323f6..7d58e9d13f 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #define CONFIG_CPCI405AB 1 /* ...and special AB version */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index f09fcb0d4b..c2598a3026 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index ae36411dd2..25365f747c 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index a033a3a1e5..7be83b0787 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_CPU86 1 /* ...on a CPU86 board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 06876746a7..d3a59e8ba7 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_CPU87 1 /* ...on a CPU87 board */ #define CONFIG_PCI #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index a4ce6c389f..788fa0f91c 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -19,7 +19,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ /* * Note: I make an "image" from U-Boot itself, which prefixes 0x40 diff --git a/include/configs/CU824.h b/include/configs/CU824.h index 686402762f..dc98a560c8 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -25,7 +25,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8240 1 #define CONFIG_CU824 1 diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 74e79e23e6..68e4a7f405 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DP405 1 /* ...on a DP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 433077d5af..9be2310dbd 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -17,7 +17,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DU405 1 /* ...on a DU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 71be1224f1..be5494b2ec 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -21,7 +21,6 @@ */ #define CONFIG_DU440 1 /* Board is esd DU440 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h deleted file mode 100644 index 208b599f6d..0000000000 --- a/include/configs/EXBITGEN.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -/* I2C configuration */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ - -/* environment is in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NVRAM - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */ -#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */ -#endif - -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ -/* Explanation: - autbooting is altogether disabled and cannot be - enabled if CONFIG_BOOTDELAY is negative. - If you want shorter bootdelay, then - - "setenv bootdelay " to the proper value -*/ - -#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000" - -#define CONFIG_BOOTARGS "root=/dev/ram " \ - "ramdisk_size=32768 " \ - "console=ttyS0,115200 " \ - "ram=128M debug" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_PPC4xx_EMAC -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* UART configuration */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* Default baud rate */ -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_PCI /* no pci support */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 -#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH0_BASE 0xFFF80000 -#define CONFIG_SYS_FLASH0_SIZE 0x00080000 -#define CONFIG_SYS_FLASH1_BASE 0x20000000 -#define CONFIG_SYS_FLASH1_SIZE 0x02000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_RAMSTART -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */ -#endif - -/* On Chip Memory location/size */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* Global info and initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 5c537ced94..0c66092e0b 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_G2000 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 26b3bdf4d0..033dcbfe26 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -24,7 +24,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 62a7f93fc7..e0a233b28a 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -22,7 +22,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_HIDDEN_DRAGON 1 diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 5e1665374c..1783b9ff15 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_HUB405 1 /* ...on a HUB405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h index bbfee7d308..6a3a11cb7f 100644 --- a/include/configs/HWW1U1A.h +++ b/include/configs/HWW1U1A.h @@ -13,7 +13,6 @@ /* High-level system configuration options */ #define CONFIG_BOOKE /* Power/PowerPC Book-E */ #define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */ #define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */ #define CONFIG_FSL_LAW /* FreeScale Local Access Window */ #define CONFIG_P2020 /* FreeScale P2020 */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 7aaa7768fd..8ccb0ff9d8 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ #define CONFIG_MPC8272_FAMILY 1 #define CONFIG_IDS8247 1 #define CPU_ID_STR "MPC8247" diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index a543855a56..e402075d37 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ #define CONFIG_SYS_TEXT_BASE 0xffb00000 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index a5cea8bc3c..a2fdfd3274 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -13,7 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ #define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 52368f8ea0..1861aa86d9 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -13,8 +13,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ /* diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 5738ea97ad..5cc25576ae 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -20,8 +20,6 @@ #define CONFIG_JSE 1 /* JSE has a PPC405GPr */ #define CONFIG_405GP 1 - /* ... which is a 4xxx series */ -#define CONFIG_4x 1 /* ... with a 33MHz OSC. connected to the SysCLK input */ #define CONFIG_SYS_CLK_FREQ 33333333 /* ... with on-chip memory here (4KBytes) */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 39eb2ef133..546b725317 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -23,7 +23,6 @@ #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h deleted file mode 100644 index a9531b0bf3..0000000000 --- a/include/configs/M5271EVB.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Configuation settings for the Freescale M5271EVB - * - * Based on MC5272C3 and r5200 board configs - * (C) Copyright 2006 Lab X Technologies - * (C) Copyright 2003 Josef Baumgartner - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5271EVB_H -#define _M5271EVB_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_M5271EVB /* define board type */ - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#endif -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC - -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ -#define CONFIG_BOOTFILE "u-boot.bin" -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_RETRY_COUNT 5 -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME M5271EVB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp $loadaddr $uboot\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b $loadaddr ffe00000 $filesize;" \ - "save\0" \ - "" - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ 1000000 - -/* Clock configuration - * The external oscillator is a 25.000 MHz - * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk) - * bus_clk = (cpu_clk/2) (fixed ratio) - * - * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to - * match the new clock speed. Max cpu_clk is 150 MHz. - */ -#define CONFIG_SYS_CLK 100000000 -#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_SIZE 0x200000 - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Chip Select 0 : Boot Flash */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001980 - -/* Chip Select 1 : External SRAM */ -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001900 - -#endif /* _M5271EVB_H */ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index de063b70d6..3d7dc1fb2d 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -77,7 +77,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Network configuration */ @@ -268,10 +267,8 @@ /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_GBL_DATA_SIZE) - 32) + GENERATED_GBL_DATA_SIZE) - 32) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index 8a40029809..19ea3167af 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC837x 1 #define CONFIG_MPC8377 1 @@ -122,9 +121,8 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup @@ -314,6 +312,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* * Command line configuration. diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 67154353d3..69ab5bb517 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -89,7 +89,6 @@ #define CONFIG_METROBOX 1 /* Board is Metrobox */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 6042a1e3c4..68824fd2d4 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -17,7 +17,6 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_MIP405 1 /* ...on a MIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 1bf1bf8c41..e84d12f3f8 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -29,7 +29,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8240 1 #define CONFIG_MOUSSE 1 diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 3def26929b..39f7564b74 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -64,8 +64,6 @@ * details. :-( */ #define CONFIG_MPC8272 1 -#else -#define CONFIG_MPC8260 1 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 39c90aa2b0..8d9c8fb45c 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -33,7 +33,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 0131b9c6d4..bf974fd461 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 07719e9265..69b2cb1970 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -14,7 +14,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index aedb529f86..3dd52ce30f 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC831x 1 /* MPC831x CPU family */ #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c4c771b502..65a63e2b7f 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f5b62025d6..1735b3c521 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,7 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 7640d06ee7..6b7d648944 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index ffb9a158ae..398918a940 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -47,7 +47,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index d4c82cd669..aefde74fc5 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 01e7ac7681..1b8bad179b 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -19,7 +19,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index f52e77a3a7..695e47bf07 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 938f7ab3c4..1d1f4c0e22 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9b7cc6474c..faa5495cb4 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -24,7 +24,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif @@ -42,7 +42,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -56,7 +56,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8536 1 #define CONFIG_MPC8536DS 1 @@ -327,7 +326,7 @@ /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) #define CONFIG_SYS_NAND_U_BOOT_START \ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) @@ -627,7 +626,7 @@ #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -650,11 +649,7 @@ #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 - #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 2d42b25121..37c2b9415a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -21,7 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8540 1 /* MPC8540 specific */ #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index b9ad034225..5d229a0d20 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -16,7 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8541 1 /* MPC8541 specific */ #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 90fc2da34b..dade6d3b89 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -14,7 +14,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 5fff1e2cac..190c668303 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -20,7 +20,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 23c6b07c35..5263ffcc8d 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -16,7 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8555 1 /* MPC8555 specific */ #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 44b767919e..ac78d481d6 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -21,7 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ #define CONFIG_MPC8560 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 4f438a8075..02a5acf38e 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -13,7 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index d877e8bbd1..58b9c26e93 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -13,7 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8569 1 /* MPC8569 specific */ #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ @@ -57,7 +56,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 44d83a236e..7b63945888 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -24,7 +24,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif @@ -44,7 +44,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8572 1 #define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f930fcde34..e6d570a6af 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -14,7 +14,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 65d61c28d1..7443acec80 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -17,7 +17,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index b24f6eea2f..c5c929002d 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -25,7 +25,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_MUSENKI 1 diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 9d49de7c61..036396c781 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -13,7 +13,6 @@ #include -#define CONFIG_MPC5xxx 1 #define CONFIG_MPC5200 1 #ifndef CONFIG_SYS_TEXT_BASE @@ -105,6 +104,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* * Autoboot diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index efdf1aa670..27c2fa011d 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x 1 #define CONFIG_MPC8343 1 @@ -228,6 +227,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* USB */ #define CONFIG_SYS_USB_HOST diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 4100b85497..aa2d9c02de 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -40,7 +40,6 @@ #define ERR_LED(code) #endif -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_MVBLUE 1 diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h deleted file mode 100644 index 73cd2a9a37..0000000000 --- a/include/configs/MVS1.h +++ /dev/null @@ -1,384 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MVS 1 /* ...on a MVsensor module */ -#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ -#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo To mount root over NFS use \"run bootnet\";" \ - "echo To mount root from FLASH use \"run bootflash\";" \ - "echo" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG /* watchdog disabled/enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_RUN - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 - -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ -#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */ -#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ - - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#undef FLASH_BASE1_PRELIM - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - - -/* - * FLASH timing: - */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -/* -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) -*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#ifdef CONFIG_MVS_16BIT_FLASH -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) -#endif - -#undef CONFIG_SYS_OR1_REMAP -#undef CONFIG_SYS_OR1_PRELIM -#undef CONFIG_SYS_BR1_PRELIM -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#undef SDRAM_BASE3_PRELIM -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#undef CONFIG_SYS_OR3_PRELIM -#undef CONFIG_SYS_BR3_PRELIM - - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CONFIG_SYS_MAMR_PTA 98 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index f69b9a856c..ad15506fad 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -13,7 +13,6 @@ #include -#define CONFIG_MPC5xxx 1 #define CONFIG_MPC5200 1 #ifndef CONFIG_SYS_TEXT_BASE @@ -93,6 +92,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_VENDOREX +#define CONFIG_LIB_RAND /* * Autoboot diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 7baba93c82..4680afee07 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_OCRTC 1 /* ...on a OCRTC board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h deleted file mode 100644 index 5a9bee3496..0000000000 --- a/include/configs/ORSG.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ORSG 1 /* ...on a ORSG board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ea5cb6501b..eabfc85f0f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -21,19 +21,75 @@ #define CONFIG_NAND_FSL_IFC #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH +#ifdef CONFIG_SECURE_BOOT #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#else +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif #endif #ifdef CONFIG_NAND #define CONFIG_SPL +#ifdef CONFIG_SECURE_BOOT #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT @@ -46,22 +102,62 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#else +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif #endif - #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ #define CONFIG_RAMBOOT_NAND #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -77,7 +173,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ @@ -474,6 +569,43 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -481,7 +613,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -638,12 +770,12 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_RAMBOOT_SDCARD) +#if defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#elif defined(CONFIG_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 @@ -654,6 +786,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #if defined(CONFIG_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ @@ -661,18 +797,15 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_OFFSET (1024 * 1024) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 934a6cb7a6..139d4fed25 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -30,12 +30,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_MMC_BOOT @@ -60,12 +60,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_SPI_BOOT @@ -96,7 +96,7 @@ #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) @@ -122,13 +122,12 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ #define CONFIG_P1022 #define CONFIG_P1022DS #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -366,10 +365,10 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) #elif defined(CONFIG_NAND) #ifdef CONFIG_TPL_BUILD @@ -653,11 +652,7 @@ #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 7de6814a03..b41cb4a13e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -11,7 +11,7 @@ #define __CONFIG_H #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_SYS_MONITOR_BASE @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_P1023 #define CONFIG_MP /* support multiple processors */ @@ -260,11 +259,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -365,7 +360,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 11c74ff5f5..2ffa3546de 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -26,13 +26,13 @@ #ifdef CONFIG_NAND_SPL #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif /* CONFIG_NAND_SPL */ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_SYS_MONITOR_BASE @@ -46,7 +46,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_P1023 #define CONFIG_P1023RDS #define CONFIG_MP /* support multiple processors */ @@ -195,9 +194,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ @@ -220,7 +218,7 @@ extern unsigned long get_clock_freq(void); /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) @@ -386,7 +384,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000) @@ -394,11 +392,7 @@ extern unsigned long get_clock_freq(void); #endif #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -506,7 +500,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 85cb0767ef..2ffaf5c0d9 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif @@ -46,17 +46,17 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -70,7 +70,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ @@ -267,7 +266,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) @@ -495,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) + #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION @@ -513,11 +512,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 - #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index ce3c762559..d414b84dd2 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -29,7 +29,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_P2020 1 #define CONFIG_P2020COME 1 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index ada6c7b871..3d0b5c2fbe 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -20,27 +20,26 @@ #ifdef CONFIG_SDCARD #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_P2020 1 #define CONFIG_P2020DS 1 #define CONFIG_MP 1 /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -578,11 +577,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index ee71252b00..b3880f190f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,8 +18,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -36,11 +36,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -93,12 +92,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_OFFSET (512 * 1097) + #define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -511,14 +510,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -531,7 +530,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 3b5c73e9f7..0989407fc7 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -20,7 +20,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PCI405 1 /* ...on a PCI405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 29888b4e1c..a6f505aaa9 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -17,7 +17,6 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PIP405 1 /* ...on a PIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 947b3d857a..8705161158 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PLU405 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 557a8bad7e..de46216422 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -14,8 +14,7 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_PM520 1 /* ... on PM520 board */ +#define CONFIG_PM520 1 /* PM520 board */ #define CONFIG_SYS_TEXT_BASE 0xfff00000 diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 5aeba4dc4e..6416ad5227 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ #define CONFIG_PM826 1 /* ...on a PM8260 module */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 49b4571e1a..e17fbfbbf8 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ #define CONFIG_PM828 1 /* ...on a PM828 module */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 9fab4b2c7d..c68d9a6ec6 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -13,7 +13,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PMC405 1 /* ...on a PMC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 0984095332..94b95475a8 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index efe69601f3..c5e2f164ce 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -24,7 +24,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF90000 @@ -96,12 +95,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * RTC @@ -143,69 +137,10 @@ #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ #endif -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#if defined (CONFIG_NAND_U_BOOT) -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} -#endif - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#endif #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ @@ -449,7 +384,6 @@ /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -459,16 +393,6 @@ /* Memory Bank 2 (NAND-FLASH) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x018003c0 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 2 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03017200 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000) - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#endif /* Memory Bank 1 (RESET) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 1b17afa61a..e277d0d933 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -59,7 +59,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 28884295e7..f5e0968011 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -184,7 +184,6 @@ * *****************************************************************************/ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 1cdd18c0ba..a1e2ae9753 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -13,7 +13,6 @@ #ifdef CONFIG_MPC8248 #define CPU_ID_STR "MPC8248" #else -#define CONFIG_MPC8260 #define CPU_ID_STR "MPC8250" #endif /* CONFIG_MPC8248 */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 40fb63d14f..46157ccc40 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -16,7 +16,6 @@ #define CONFIG_NAND_U_BOOT #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index 8a689b3573..2c0cb89afa 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8240 1 #define CONFIG_SANDPOINT 1 diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index a17f5ad860..2664d5b169 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_SANDPOINT 1 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d0bc043f9..993f9ae533 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -32,8 +32,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg #endif /* High Level Configuration Options */ @@ -41,11 +41,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -93,12 +92,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -167,7 +166,7 @@ unsigned long get_board_ddr_clk(void); /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 @@ -376,7 +375,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -402,6 +401,25 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +/* Video */ +#define CONFIG_FSL_DIU_FB +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif + /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP @@ -414,9 +432,9 @@ unsigned long get_board_ddr_clk(void); /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 @@ -427,6 +445,11 @@ unsigned long get_board_ddr_clk(void); /* I2C bus multiplexer */ #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_DIU 0xC + +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 /* * RTC configuration @@ -583,17 +606,17 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -612,9 +635,8 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d @@ -671,7 +693,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -706,6 +727,7 @@ unsigned long get_board_ddr_clk(void); "bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ + "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index d721139a1f..395845bd68 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -40,11 +40,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -80,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -92,12 +87,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -152,7 +147,7 @@ /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING @@ -203,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -387,6 +383,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -521,17 +521,17 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -544,13 +544,12 @@ #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -597,7 +596,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -628,9 +626,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 2c02d9da58..68656e6ef1 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -40,11 +40,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -80,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -92,12 +87,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -152,7 +147,7 @@ /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING @@ -203,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -395,6 +391,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -529,17 +529,17 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -552,8 +552,11 @@ #endif #ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 + #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -601,7 +604,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -632,9 +634,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/T2080QDS.h b/include/configs/T208xQDS.h similarity index 95% rename from include/configs/T2080QDS.h rename to include/configs/T208xQDS.h index bff001f433..399ddbb791 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T208xQDS.h @@ -5,21 +5,25 @@ */ /* - * T2080 QDS board configuration file + * T2080/T2081 QDS board configuration file */ -#ifndef __T2080QDS_H -#define __T2080QDS_H +#ifndef __T208xQDS_H +#define __T208xQDS_H -#define CONFIG_T2080QDS #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_SPI_FLASH #define CONFIG_USB_EHCI +#if defined(CONFIG_PPC_T2080) +#define CONFIG_T2080QDS #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_T2081QDS +#endif /* High Level Configuration Options */ #define CONFIG_PHYS_64BIT @@ -27,7 +31,6 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_ENABLE_36BIT_PHYS @@ -45,8 +48,12 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg +#endif #endif #define CONFIG_SRIO_PCIE_BOOT_MASTER @@ -60,7 +67,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -103,12 +110,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -235,7 +242,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 @@ -448,7 +455,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO +#if defined(CONFIG_T2080QDS) #define CONFIG_SPI_FLASH_SPANSION +#elif defined(CONFIG_T2081QDS) +#define CONFIG_SPI_FLASH_EON +#endif + #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 @@ -506,7 +518,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_NET_MULTI #define CONFIG_E1000 #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -544,14 +556,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -564,7 +576,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -681,7 +693,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -802,4 +813,4 @@ unsigned long get_board_ddr_clk(void); #undef CONFIG_CMD_USB #endif -#endif /* __T2080QDS_H */ +#endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h new file mode 100644 index 0000000000..743eee3161 --- /dev/null +++ b/include/configs/T208xRDB.h @@ -0,0 +1,779 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T2080 RDB/PCIe board configuration file + */ + +#ifndef __T2080RDB_H +#define __T2080RDB_H + +#define CONFIG_T2080RDB +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_MMC +#define CONFIG_SPI_FLASH +#define CONFIG_USB_EHCI +#define CONFIG_FSL_SATA_V2 + +/* High Level Configuration Options */ +#define CONFIG_PHYS_64BIT +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg +#endif + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifdef CONFIG_SYS_NO_FLASH +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 133330000 + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ +#define CONFIG_NET_MULTI +#define CONFIG_E1000 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_CORTINA_FW_ADDR 0x120000 + +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_CORTINA_FW_ADDR (512 * 1808) + +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_CORTINA +#define CONFIG_PHY_AQ1202 +#define CONFIG_PHY_REALTEK +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ +#define RGMII_PHY2_ADDR 0x02 +#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ +#define CORTINA_PHY_ADDR2 0x0d +#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ +#define FM1_10GEC4_PHY_ADDR 0x01 +#endif + + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Environment + */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t2080rdb/t2080rdb.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#undef CONFIG_CMD_USB +#endif + +#endif /* __T2080RDB_H */ diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index 5e228f3556..c81c4577e3 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_INTERLAKEN #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -122,7 +122,7 @@ "bank_intlv=auto;" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240emu/ramdisk.uboot\0" \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54d99..56e1293720 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -21,8 +21,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -64,12 +64,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -165,6 +165,9 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 +#define QIXIS_MUX_SDHC_WIDTH8 1 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) @@ -376,14 +379,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -396,7 +399,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -466,6 +469,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_ESDHC_DETECT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ + IS_SVR_REV(get_svr(), 1, 0)) +#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) #endif #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 90f7fc4d79..b4daedceea 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #define CONFIG_TB5200 1 /* ... on a TB5200 base board */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 7aba00914d..92128b9588 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -25,8 +25,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 13500ee139..69c0336cae 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index b34b0a865b..7fd12d3fbc 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ #if 0 #define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 78e8b03cd1..9c7e16305d 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ #define CONFIG_MPC8272_FAMILY 1 #define CONFIG_TQM8272 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 15cf2bd793..6762e3a57e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x specific */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index acc4fdc668..a58eecab84 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -24,8 +24,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ /* diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3d46afe4e8..d4a4b68c80 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOH405 1 /* ...on a VOH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 319a9a227d..c06897b893 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -16,7 +16,6 @@ * (easy to change) */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 00a24ab846..895ad4611b 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMC 1 /* ...specifically an LMC */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 8ed2fa2d87..2a38116dd1 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index d2038e56d0..e4f0d19a41 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -19,7 +19,6 @@ #define CONFIG_IDENT_STRING " $Name: $" #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WUH405 1 /* ...on a WUH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 01cb2c85c0..d76a140728 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index d151869d7b..205adfd8ce 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -13,8 +13,7 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_A3M071 /* ... on A3M071 board */ +#define CONFIG_A3M071 /* A3M071 board */ #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ @@ -59,6 +58,7 @@ #define CONFIG_BOOTP_SERVERIP #define CONFIG_NET_RETRY_COUNT 3 #define CONFIG_CMD_LINK_LOCAL +#define CONFIG_LIB_RAND #define CONFIG_NETCONSOLE #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CMD_PING diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 64737020f5..cc88ac1618 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index d6cef888c6..f57820d8f5 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -27,7 +27,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 @@ -290,9 +289,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/acadia.h b/include/configs/acadia.h index f23d549497..4dd5720d2f 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -16,7 +16,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #ifndef CONFIG_SYS_TEXT_BASE @@ -83,17 +82,11 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -107,16 +100,6 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#else -/* - * No NOR-flash on Acadia when NAND-booting. We need to undef the - * NOR device-tree fixup code as well, since flash_info is not defined - * in this case. - */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE -#endif - #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) @@ -127,61 +110,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * RAM (CRAM) *----------------------------------------------------------------------*/ @@ -220,7 +148,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ "kozio=bootm ffc60000\0" \ @@ -243,14 +170,6 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_USB -/* - * No NOR on Acadia when NAND-booting - */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -261,7 +180,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 3 /* Memory Bank 0 (Flash) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x03337200 @@ -279,24 +197,6 @@ /* Memory Bank 2 (CRAM) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x030400c0 #define CONFIG_SYS_EBC_PB2CR 0x020bc000 -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) - -/* - * When NAND-booting the CRAM EBC setup must be done in sync mode, since the - * NAND-SPL already initialized the CRAM and EBC to sync mode. - */ -/* Memory Bank 1 (CRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0 -#define CONFIG_SYS_EBC_PB1CR 0x000bc000 - -/* Memory Bank 2 (CRAM) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0 -#define CONFIG_SYS_EBC_PB2CR 0x020bc000 -#endif /* Memory Bank 4 (CPLD) initialization */ #define CONFIG_SYS_EBC_PB4AP 0x04006000 diff --git a/include/configs/actux1.h b/include/configs/actux1.h deleted file mode 100644 index 9b8bd78943..0000000000 --- a/include/configs/actux1.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX1 1 - -#define CONFIG_MACH_TYPE 1479 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113842 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef CONFIG_RAM_32MB -# define CONFIG_SYS_SDR_CONFIG 0x18 -# define PHYS_SDRAM_1_SIZE 0x02000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x02000000 -#else /* 16MB SDRAM */ -# define CONFIG_SYS_SDR_CONFIG 0x3A -# define PHYS_SDRAM_1_SIZE 0x01000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x01000000 -#endif - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#ifdef CONFIG_FLASH2X2 -# define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 40 -# define PHYS_FLASH_1 0x50000000 -# define PHYS_FLASH_2 0x50200000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#endif -#ifdef CONFIG_FLASH1X8 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 140 -# define PHYS_FLASH_1 0x50000000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0 -/* NPE1 PHY address (HW Release E only) */ -#define CONFIG_PHY1_ADDR 1 -/* MII PHY management */ -#define CONFIG_MII 1 -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux1/uImage\0" \ - "rootfile=actux1/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux1/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux2.h b/include/configs/actux2.h deleted file mode 100644 index f0cbff79ca..0000000000 --- a/include/configs/actux2.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX2 1 - -#define CONFIG_MACH_TYPE 1480 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#undef CONFIG_CMD_PCI -#undef CONFIG_PCI - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113042 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x00 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux2/uImage\0" \ - "rootfile=actux2/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux2/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux3.h b/include/configs/actux3.h deleted file mode 100644 index 763910745c..0000000000 --- a/include/configs/actux3.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX3 1 - -#define CONFIG_MACH_TYPE 1481 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x10 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux3/uImage\0" \ - "rootfile=actux3/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux3/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux4.h b/include/configs/actux4.h deleted file mode 100644 index 12bd98a7e1..0000000000 --- a/include/configs/actux4.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX4 1 - -#define CONFIG_MACH_TYPE 1532 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66000000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113003 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x02000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max # of sectors per chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 70 -#define PHYS_FLASH_1 0x50000000 -#define PHYS_FLASH_2 0x51000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (252 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 258048 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* SST 39VF020 etc. support */ -#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x1C -/* MII PHY management */ -#define CONFIG_MII 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* environment organization: one complete 4k flash sector */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=51000000\0" \ - "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ - "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ - "kerneladdr=51020000\0" \ - "kernelfile=actux4/uImage\0" \ - "rootfile=actux4/rootfs\0" \ - "rootaddr=51160000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux4/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 5003efff;" \ - " erase 50000000 +${filesize}\0" \ - "writeboot=cp.b 10000 50000000 ${filesize}\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index e31131f6e2..e318c7543f 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -138,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index ded3f331e8..24904b0b7c 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -138,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h index 1e4ce2e7d9..39f7a3cd46 100644 --- a/include/configs/adp-ag102.h +++ b/include/configs/adp-ag102.h @@ -203,11 +203,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/* - * size in bytes reserved for initial data -*/ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/aev.h b/include/configs/aev.h index 0eafb3ca74..2dffcfbed3 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 08bba36095..7849b222b0 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -14,7 +14,6 @@ #define CONFIG_ALPR 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 73a9adb293..ea9e758a69 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -20,6 +20,7 @@ #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ @@ -31,6 +32,12 @@ /* Always 128 KiB env size */ #define CONFIG_ENV_SIZE (128 << 10) +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #ifdef CONFIG_NAND #define NANDARGS \ "mtdids=" MTDIDS_DEFAULT "\0" \ @@ -64,6 +71,9 @@ "bootfile=zImage\0" \ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ @@ -198,9 +208,6 @@ #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX -/* CPSW support */ -#define CONFIG_SPL_ETH_SUPPORT - /* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT @@ -295,6 +302,9 @@ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) /* disable host part of MUSB in SPL */ #undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION /* * Disable CPSW SPL support so we fit within the 101KiB limit. */ @@ -385,13 +395,11 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ @@ -431,6 +439,8 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#undef CONFIG_SPL_SPI_SUPPORT #ifdef CONFIG_NOR_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 115d1b37c9..c17327fef4 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -181,14 +181,12 @@ #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_MULTI #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 468fb43ea8..4407b454dd 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -268,7 +268,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b8b99c806f..0102ff5b7f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -277,7 +277,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4de495a15a..614857dd25 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -34,7 +34,7 @@ /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ #define CONFIG_SPL_YMODEM_SUPPORT /* Enabling L2 Cache */ @@ -69,6 +69,11 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +/* SPL USB Support */ +#define CONFIG_SPL_USB_SUPPORT +#define CONFIG_SPL_USB_HOST_SUPPORT +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + #define CONFIG_CMD_USB #define CONFIG_USB_HOST #define CONFIG_USB_XHCI @@ -79,6 +84,32 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_QSPI_SEL_GPIO 48 +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ @@ -90,30 +121,41 @@ "bootdir=/boot\0" \ "bootfile=zImage\0" \ "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "usbroot=/dev/sda2 rw\0" \ + "usbrootfstype=ext4 rootwait\0" \ + "usbdev=0\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=mmc dev ${mmcdev}; " \ + "setenv devnum ${mmcdev}; " \ "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ + "echo SD/MMC found on device ${devnum};" \ "if run loadbootenv; then " \ "echo Loaded environment from ${bootenv};" \ "run importbootenv;" \ @@ -129,6 +171,26 @@ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ + "usbboot=" \ + "setenv devnum ${usbdev}; " \ + "setenv devtype usb; " \ + "usb start ${usbdev}; " \ + "if usb dev ${usbdev}; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from usb ${usbdev}...; " \ + "run usbargs;" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi\0" \ "findfdt="\ "if test $board_name = AM43EPOS; then " \ "setenv fdtfile am43x-epos-evm.dtb; fi; " \ @@ -139,7 +201,34 @@ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ - "run mmcboot;" + "run mmcboot;" \ + "run usbboot;" #endif + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB + +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" + +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SYS_RX_ETH_BUFFER 64 + #endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 0f38c92fa0..2aea89937a 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -253,10 +253,4 @@ "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ -#define CONFIG_AMCC_DEF_ENV_NAND_UPD \ - "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\ - "nload=tftp 200000 ${u-boot-nand}\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \ - "nupd=run nload nupdate\0" - #endif /* __AMCC_COMMON_H */ diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index bb39491f8b..4282d70266 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -134,8 +134,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 1193013ea0..b10c48c20e 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -355,11 +355,6 @@ #define CONFIG_SYS_RTC_BUS_NUM 0 #endif /* CONFIG_CMD_DATE */ -/* - * Clocks - */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - /* * PLL * diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h new file mode 100644 index 0000000000..88d27db08b --- /dev/null +++ b/include/configs/arcangel4-be.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_SYS_BIG_ENDIAN +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h new file mode 100644 index 0000000000..4579eb97c2 --- /dev/null +++ b/include/configs/arcangel4.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/aria.h b/include/configs/aria.h index b8d955abd0..c36cf33f07 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -31,7 +31,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index e5569c7296..17a2da034d 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -94,7 +94,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0xE80C0000 diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 9584d82af7..515facfd67 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -22,8 +22,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Enable fdt support for Exynos5250 */ -#define CONFIG_ARCH_DEVICE_TREE exynos5250 #define CONFIG_OF_CONTROL #define CONFIG_OF_SEPARATE diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 5d96c31f99..a30c016b41 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -14,7 +14,7 @@ #ifndef __AT91RM9200EK_CONFIG_H__ #define __AT91RM9200EK_CONFIG_H__ -#include +#include /* * set some initial configurations depending on configure target diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b9aa036039..48c12ea880 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -103,6 +103,7 @@ #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_MMC #define CONFIG_CMD_USB 1 /* SDRAM */ @@ -123,6 +124,18 @@ #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define CONFIG_SYS_FLASH_CFI 1 diff --git a/include/configs/atc.h b/include/configs/atc.h index fa391b6280..77fa79a185 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_ATC 1 /* ...on a ATC board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 597bede85e..9c81e3199f 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100 diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index bd4dca5217..066d09ab0a 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -12,7 +12,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100MKII diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index fd76572a47..8f3fd0bb00 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATSTK1002 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 2562460b98..63704b1987 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7001 #define CONFIG_ATSTK1003 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 8e32a10b19..331a60d76a 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7002 #define CONFIG_ATSTK1004 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 9ce22649e7..bbe0aea861 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATSTK1006 diff --git a/include/configs/axs101.h b/include/configs/axs101.h new file mode 100644 index 0000000000..f6b569abfd --- /dev/null +++ b/include/configs/axs101.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_AXS101_H_ +#define _CONFIG_AXS101_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CLK_FREQ 750000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* dwgmac doesn't work with D$ enabled now */ +#define CONFIG_SYS_DCACHE_OFF + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * UART configuration + * + * CONFIG_CONS_INDEX = 1 - Debug UART + * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB + */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#if (CONFIG_CONS_INDEX == 1) + /* Debug UART */ +# define CONFIG_SYS_NS16550_CLK 33333000 +#else + /* FPGA UARTs use different clock */ +# define CONFIG_SYS_NS16550_CLK 33333333 +#endif +#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) +#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) +#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) +#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_ENV_EEPROM_BUS 2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_BASE 0xE001D000 +#define CONFIG_SYS_I2C_BASE1 0xE001E000 +#define CONFIG_SYS_I2C_BASE2 0xE001F000 +#define CONFIG_SYS_I2C_BUS_MAX 3 +#define IC_CLK 50 + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 + +/* + * SD/MMC configuration + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_DOS_PARTITION + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_MII +#define CONFIG_PHY_GIGE + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "AXS# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_AXS101_H_ */ diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index b41a823600..5228ba6ef7 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -84,7 +84,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 326e3d6692..6ba4aaf8cb 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -17,7 +17,6 @@ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #ifndef CONFIG_SYS_TEXT_BASE @@ -87,12 +86,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -121,61 +115,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -183,15 +122,7 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ - -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 1 -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#endif /*----------------------------------------------------------------------- * DDR SDRAM @@ -227,7 +158,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ "" diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h new file mode 100644 index 0000000000..e93b855f8f --- /dev/null +++ b/include/configs/bcm28155_ap.h @@ -0,0 +1,140 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCM28155_AP_H +#define __BCM28155_AP_H + +#include +#include + +/* Architecture, CPU, chip, mach, etc */ +#define CONFIG_ARMV7 +#define CONFIG_KONA +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0xae000000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ +#define CONFIG_STACKSIZE SZ_256K + +/* GPIO Driver */ +#define CONFIG_KONA_GPIO + +/* MMC/SD Driver */ +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_KONA_SDHCI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR +#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO0 "sdio1" +#define CONFIG_SYS_SDIO1 "sdio2" +#define CONFIG_SYS_SDIO2 "sdio3" +#define CONFIG_SYS_SDIO3 "sdio4" + +/* I2C Driver */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_KONA +#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR +#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR +#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR +#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR + +/* Timer Driver */ +#define CONFIG_SYS_TIMER_RATE 32000 +#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ + +/* Init functions */ +#define CONFIG_MISC_INIT_R /* board's misc_init_r function */ + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* No mtest functions as recommended */ +#undef CONFIG_CMD_MEMORY + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Serial Info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* Post pad 3 bytes after each reg addr */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 13000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0x3e000000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */ + +/* console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * One partition type must be defined for part.c + * This is necessary for the fatls command to work on an SD card + * for example. + */ +#define CONFIG_DOS_PARTITION + +/* version string, parser, etc */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* Initial upstream - boot to cmd prompt only */ +#define CONFIG_BOOTCOMMAND "" + +/* Commands */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_BOOTZ +#define CONFIG_FAT_WRITE + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#endif /* __BCM28155_AP_H */ diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index 5b09b45b56..06f095cc41 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -136,7 +136,7 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #define CONFIG_SYS_HUSH_PARSER - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 801caca24f..df9a98bca6 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -17,7 +17,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra30-common.h" diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index a97972b81c..9eb85ebf3d 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -155,7 +155,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 003109329a..3065d22f0b 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -153,6 +153,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* define to enable run status via led */ /* #define CONFIG_STATUS_LED */ diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index fa05103e5a..c0dfe2685b 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -136,7 +136,7 @@ */ #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index db1b6136f3..748ddb3b15 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -179,7 +179,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h index c0e8b5adc8..458868af72 100644 --- a/include/configs/bf527-sdp.h +++ b/include/configs/bf527-sdp.h @@ -112,7 +112,7 @@ */ #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index beab1271a4..b50352823e 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -110,7 +110,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index f5b9658294..d82c5b203d 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -185,6 +185,7 @@ */ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* FLASH/ETHERNET uses the same async bank */ #define SHARED_RESOURCES 1 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 02945bee79..e1705cadae 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -254,6 +254,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* Define if want to do post memory test */ #undef CONFIG_POST diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index ffb0caf947..742c299d23 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -134,7 +134,7 @@ */ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index da5f029435..1a245a2b81 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -181,6 +181,7 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED #define CONFIG_ADI_GPIO2 diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 15ca1af230..3db917e37b 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -160,7 +160,7 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BAUDRATE 57600 #define CONFIG_SYS_PROMPT "Acvilon> " - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index fb6f94873a..0a309d9269 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -102,6 +102,7 @@ * Misc Settings */ #define CONFIG_UART_CONSOLE 0 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Run core 1 from L1 SRAM start address when init uboot on core 0 diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b433..12192ffb5d 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,12 +72,13 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 08ccce0b9a..ea9acf69d1 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -17,6 +17,7 @@ # define CONFIG_BOOTP_DNS # define CONFIG_BOOTP_NTPSERVER # define CONFIG_BOOTP_RANDOM_DELAY +# define CONFIG_LIB_RAND # define CONFIG_KEEP_SERVERADDR # define CONFIG_CMD_DNS # define CONFIG_CMD_PING diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h index 33e04963e6..8bd71c6a15 100644 --- a/include/configs/bluestone.h +++ b/include/configs/bluestone.h @@ -16,7 +16,6 @@ #define CONFIG_APM821XX 1 /* APM821XX series */ #define CONFIG_HOSTNAME bluestone -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/br4.h b/include/configs/br4.h index ef3752dcd5..f8d3158d47 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -135,7 +135,7 @@ #define CONFIG_BOOTCOMMAND "run nandboot" #define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 2b9c1c96e4..ea7b104729 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h new file mode 100644 index 0000000000..7adc8c0fd7 --- /dev/null +++ b/include/configs/bur_am335x_common.h @@ -0,0 +1,196 @@ +/* + * bur_am335x_common.h + * + * common parts used by B&R AM335x based boards + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BUR_AM335X_COMMON_H__ +#define __BUR_AM335X_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* Timer information */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_POWER_TPS65217 + +#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_BAUDRATE 115200 + +/* Network defines */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 4 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_PHYLIB +#define CONFIG_PHY_NATSEMI +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* !CONFIG_SPL_BUILD, ... */ +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* + * ---------------------------------------------------------------------------- + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX + +/* GPIO */ +#define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO +/* + * ---------------------------------------------------------------------------- + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* + * For commands to use, we take the default list and add a few other + * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH + * prior to this include, in order to skip a few commands. When we do + * have flash, if we expect these commands they must be enabled in that + * config. If desired, a specific list of desired commands can be used + * instead. + */ +#include +/* undefine commands, which we do not need */ +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CRC32 +/* define command we need always */ +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + * + * ---------------------------------------------------------------------------- + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +/* General parts of the framework, required. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index d929bde8f2..c90179380f 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -13,8 +13,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index f6faeec06c..8eeb15c0e1 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -33,7 +33,6 @@ #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -126,78 +125,9 @@ /* * Define here the location of the environment variables (FLASH). */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */ -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif - -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - * - * This is the first official implementation of booting from 2k page sized - * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8) - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ - /* this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) - /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif /*----------------------------------------------------------------------- * FLASH related @@ -236,7 +166,6 @@ /*------------------------------------------------------------------------------ * DDR SDRAM *----------------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) #if !defined(CONFIG_ARCHES) /* * NAND booting U-Boot version uses a fixed initialization, since the whole @@ -309,7 +238,6 @@ #define CONFIG_SYS_SDRAM0_MMODE 0x00000432 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000004 #endif /* !defined(CONFIG_ARCHES) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) */ #define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */ @@ -422,7 +350,6 @@ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ @@ -557,15 +484,6 @@ * 0xfe00.0000 -> 4.ce00.0000 */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -/* Memory Bank 3 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x10055e00 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ -#else /* Memory Bank 0 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x10055e00 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) @@ -575,7 +493,6 @@ #define CONFIG_SYS_EBC_PB3AP 0x018003c0 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ #endif -#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ #if !defined(CONFIG_ARCHES) /* Memory Bank 2 (CPLD) initialization */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 4abb03ea56..e15b52737b 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -17,7 +17,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra30-common.h" @@ -30,6 +30,10 @@ #define V_PROMPT "Tegra30 (Cardhu) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define BOARD_EXTRA_ENV_SETTINGS \ + "board_name=cardhu-a04\0" \ + "fdtfile=tegra30-cardhu-a04.dtb\0" + /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 29a023c499..b189bf116f 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -75,7 +75,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "boot_dir=/boot\0" \ "console=ttymxc1\0" \ @@ -92,24 +92,24 @@ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${boot_dir}/${uimage}\0" \ + "loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${boot_dir}/${image}\0" \ "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ "${boot_dir}/${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -118,7 +118,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else "\ "echo ERR: Fail to boot from mmc; " \ diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index b15a1eb7a2..384d8715ad 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -128,7 +128,7 @@ #define FLASHBOOT_ENV_SETTINGS \ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index e2b954c063..8bd499a7d2 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -97,7 +97,7 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 2838012e20..67cf801a3f 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -146,6 +146,7 @@ "flashboot=flread 20040000 1000000 3c0000;" \ "bootm 0x1000000\0" #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index da4cc6718d..34ce75baeb 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -143,7 +143,7 @@ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 7f27eda416..346e27f3eb 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -117,6 +117,7 @@ #define CONFIG_UART_CONSOLE 1 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED #define CONFIG_ADI_GPIO2 diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 93e3c8677e..5265e5f6ef 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -99,7 +99,7 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index ac3d6bd343..7c693d62d1 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -11,8 +11,7 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ #define CONFIG_SYS_TEXT_BASE 0xfc000000 diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 56e9a8e0e8..26b615b8c5 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -114,7 +114,6 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS /* NAND support */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 7729a02ab6..aae05e0333 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -45,13 +45,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 -/* - * The early kernel mapping on ARM currently only maps from the base of DRAM - * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. - * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, - * so that leaves DRAM base to DRAM base + 0x4000 available. - */ -#define CONFIG_SYS_BOOTMAPSZ 0x4000 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -163,10 +156,10 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define GPMC_NAND_ECC_LP_x8_LAYOUT + /* Environment information */ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 46d4f9865f..868813f29b 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -41,7 +41,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ #define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 969b9903fb..1e4bfc49fc 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,15 +15,15 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg #if defined(CONFIG_P3041DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg #elif defined(CONFIG_P4080DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg #elif defined(CONFIG_P5020DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg #elif defined(CONFIG_P5040DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif @@ -41,11 +41,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -91,12 +90,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -514,14 +513,14 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -534,7 +533,7 @@ #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 11ba4cffc4..959e188d9a 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -33,7 +33,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91FAMILY diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index db5ceadba6..ec926fd22d 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -23,8 +23,7 @@ * (easy to change) */ -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 49cfabdc6b..ce521012f2 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -10,7 +10,7 @@ #ifndef _CONFIG_CPUAT91_H #define _CONFIG_CPUAT91_H -#include +#include #ifdef CONFIG_RAMBOOT #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 8a848bea8b..a5c6f8474b 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 5c034175ce..6aa98efd4e 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index bdf012b2b8..fd774a3314 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -17,7 +17,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra114-common.h" diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index da4ff8e61d..e0bf3dc61e 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ diff --git a/include/configs/debris.h b/include/configs/debris.h index 621f895011..4631b8621a 100644 --- a/include/configs/debris.h +++ b/include/configs/debris.h @@ -94,7 +94,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_DEBRIS 1 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index bcb21fefe3..bd96a7d3f4 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -10,7 +10,7 @@ #define __CONFIG_DEVKIT3250_H__ /* SoC and board defines */ -#include +#include #include /* @@ -29,7 +29,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M #define CONFIG_SYS_TEXT_BASE 0x83FA0000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 4f43ba9882..16a00ebe86 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 5049afca7a..af6f56bb34 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -143,8 +143,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index bc5853eb5c..2a8cb3940b 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -20,8 +20,7 @@ * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ /* diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index c527be4909..78778970f4 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -218,9 +217,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index c97963a3f8..1e86c556ab 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f210ed8b92..291c538a34 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -4,7 +4,7 @@ * Lokesh Vutla * * Configuration settings for the TI DRA7XX board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -34,7 +34,18 @@ #define CONFIG_SYS_OMAP_ABE_SYSCK -#include +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART /* CPSW Ethernet */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ @@ -51,7 +62,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 2 /* SPI */ #undef CONFIG_OMAP3_SPI @@ -73,6 +83,8 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SUPPORT_EMMC_BOOT + /* USB xHCI HOST */ #define CONFIG_CMD_USB #define CONFIG_USB_HOST diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h deleted file mode 100644 index 1af7f16989..0000000000 --- a/include/configs/dvlhost.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_DVLHOST 1 - -#define CONFIG_MACH_TYPE 1343 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x01D80000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM: 2* 8Mx16, CL3 */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800 -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE - -/* FLASH organization: one Spansion S29AL032D-04 Flash */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */ -#define CONFIG_PHY_ADDR 0x18 -/* NPE1 PHY: MII IP175 switch, port 5 is host port */ -#define CONFIG_PHY1_ADDR 0x05 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed powerline modem without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE1_FIXEDLINK 1 -#define CONFIG_MII_NPE1_SPEED 100 -#define CONFIG_MII_NPE1_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "ethprime=NPE1\0" \ - "ethrotate=no\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=dvlhost/uImage\0" \ - "rootfile=dvlhost/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} dvlhost/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h index 1e42f5c23c..75f7812e7d 100644 --- a/include/configs/dxr2.h +++ b/include/configs/dxr2.h @@ -26,6 +26,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define BOARD_DFU_BUTTON_LED 64 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ #undef CONFIG_DOS_PARTITION #undef CONFIG_CMD_FAT @@ -49,7 +50,6 @@ #undef CONFIG_MII #undef CONFIG_PHY_GIGE -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #define CONFIG_FACTORYSET diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index ca9792c451..940be1f5d0 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 /* #define CONFIG_MPC8240 1 */ #define CONFIG_MPC8245 1 #define CONFIG_EXALION 1 diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 8dc654ea50..3f0ad69738 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -17,7 +17,6 @@ #define CONFIG_EBONY 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 3a5cc74829..e26591c14f 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -158,8 +158,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 56b4ecf272..9cd3054a15 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -325,7 +325,6 @@ * *****************************************************************************/ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 18e4dafc5c..cf31f0f141 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -9,7 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MPC8260 #define CPU_ID_STR "MPC8270" #define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h new file mode 100644 index 0000000000..2040bf7784 --- /dev/null +++ b/include/configs/exynos4-dt.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON + +/* Enable fdt support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#include + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_MMC_DEFAULT_DEV 0 + +/* PWM */ +#define CONFIG_PWM + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* FAT */ +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +/* EXT4 */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USB_CABLE_CHECK + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 615df64dc1..b7ff47236b 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -51,6 +51,7 @@ #define CONFIG_CMD_SOUND #ifdef CONFIG_CMD_SOUND #define CONFIG_SOUND +#define CONFIG_I2S_SAMSUNG #define CONFIG_I2S #define CONFIG_SOUND_MAX98095 #define CONFIG_SOUND_WM8994 diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index fc015e6939..338d3dc782 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_FAVR32_EZKIT diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 560363d237..b555d82ddc 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -23,8 +23,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ /* diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index a6f1afff97..6810b3befc 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -21,7 +21,6 @@ #define CONFIG_440GR 1 /* Specific PPC440GR support */ #define CONFIG_HOSTNAME gdppc440etx #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 938ee86281..73534addfc 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -11,7 +11,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 3416fe3cec..262c9e9e9a 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -325,7 +325,6 @@ * *****************************************************************************/ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_GW8260 1 /* on an GW8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h new file mode 100644 index 0000000000..33983907f2 --- /dev/null +++ b/include/configs/gw_ventana.h @@ -0,0 +1,425 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO /* display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */ + +#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ + +#include +#include + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Init Functions */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#ifdef CONFIG_SPI_FLASH + +/* SPI */ +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF + #define CONFIG_MXC_SPI + #define CONFIG_SPI_FLASH_MTD + #define CONFIG_SPI_FLASH_BAR + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SF_DEFAULT_BUS 0 + #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) + /* GPIO 3-19 (21248) */ + #define CONFIG_SF_DEFAULT_SPEED 30000000 + #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#else +/* Enable NAND support */ +#define CONFIG_CMD_TIME +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_MXS + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_NAND_5_ADDR_CYCLE + #define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_BURST + #define CONFIG_APBH_DMA_BURST8 +#endif + +#endif /* CONFIG_SPI_FLASH */ + +/* Flattened Image Tree Suport */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Filesystem support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBIFS +#define CONFIG_DOS_PARTITION + +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + +/* + * SATA Configs + */ +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/* + * PCI express + */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + +/* + * PMIC + */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Various command support */ +#include +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ +#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GSC +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_FUSE /* eFUSE read/write support */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + + +/* Ethernet support */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_ARP_TIMEOUT 200UL + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 + +/* serial console (ttymxc1,115200) */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Ventana > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_HWCONFIG + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Memory configuration */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#ifdef CONFIG_SPI_FLASH +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT \ + "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" +#else +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#endif + +/* Persistent Environment Config */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_ENV_OFFSET (6 * 64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) + #define CONFIG_ENV_OFFSET (16 << 20) + #define CONFIG_ENV_SECT_SIZE (128 << 10) + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE (64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* Environment */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.146 +#define HWCONFIG_DEFAULT \ + "hwconfig=rs232;" \ + "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "console=ttymxc1\0" \ + "bootdevs=usb mmc sata flash\0" \ + HWCONFIG_DEFAULT \ + "video=\0" \ + \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x18000000\0" \ + "loadfdt=" \ + "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ + "echo Loaded DTB from boot/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ + "echo Loaded DTB from boot/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ + "echo Loaded DTB from boot/${fdt_file2}; " \ + "fi\0" \ + \ + "script=boot/6x_bootscript-ventana\0" \ + "loadscript=" \ + "if ${fsload} ${loadaddr} ${script}; then " \ + "source; " \ + "fi\0" \ + \ + "uimage=boot/uImage\0" \ + "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ + "mmc_boot=" \ + "setenv fsload 'ext2load mmc 0:1'; " \ + "mmc dev 0 && mmc rescan && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk0p1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + \ + "sata_boot=" \ + "setenv fsload 'ext2load sata 0:1'; sata init && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + "usb_boot=" \ + "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" + +#ifdef CONFIG_SPI_FLASH + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ + "image_uboot=ventana/u-boot_spi.imx\0" \ + \ + "spi_koffset=0x90000\0" \ + "spi_klen=0x200000\0" \ + \ + "spi_updateuboot=echo Updating uboot from " \ + "${serverip}:${image_uboot}...; " \ + "tftpboot ${loadaddr} ${image_uboot} && " \ + "sf probe && sf erase 0 80000 && " \ + "sf write ${loadaddr} 400 ${filesize}\0" \ + "spi_update=echo Updating OS from ${serverip}:${image_os} " \ + "to ${spi_koffset} ...; " \ + "tftp ${loadaddr} ${image_os} && " \ + "sf probe && " \ + "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ + \ + "flash_boot=" \ + "if sf probe && " \ + "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mtdblock3 " \ + "rootfstype=squashfs,jffs2 " \ + "${video} ${extra}; " \ + "bootm; " \ + "fi\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ + \ + "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ + "tftp ${loadaddr} ${image_rootfs} && " \ + "nand erase.part rootfs && " \ + "nand write ${loadaddr} rootfs ${filesize}\0" \ + \ + "flash_boot=" \ + "setenv fsload 'ubifsload'; " \ + "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "ubifsumount; " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "ubifsumount; bootm; " \ + "fi; " \ + "fi\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "for btype in ${bootdevs}; do " \ + "echo; echo Attempting ${btype} boot...; " \ + "if run ${btype}_boot; then; fi; " \ + "done" + +/* Device Tree Support */ +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_LIBFDT +#define CONFIG_FDT_FIXUP_PARTITIONS + +#ifndef CONFIG_SYS_DCACHE_OFF + #define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 3f2fadbb58..4f0603abc1 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_HAMMERHEAD diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d733be9cd5..3ec0e418c1 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" /* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */ @@ -61,8 +61,9 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX /* General networking support */ #define CONFIG_CMD_NET diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 1c74a2e96e..a1a88b5e33 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -13,9 +13,8 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_HMI1001 1 /* HMI1001 board */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_HMI1001 1 /* HMI1001 board */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF00000 diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h index 4055af55bf..2895523344 100644 --- a/include/configs/hummingboard.h +++ b/include/configs/hummingboard.h @@ -14,7 +14,7 @@ #include "mx6_common.h" #include #include -#include +#include #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO @@ -92,7 +92,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -124,22 +124,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -151,19 +151,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -171,7 +171,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -190,7 +190,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/hymod.h b/include/configs/hymod.h index cc250649ea..c973365e12 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -17,7 +17,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_HYMOD 1 /* ...on a Hymod board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/icon.h b/include/configs/icon.h index eafcf5aeaf..bbe9b59b53 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_ICON 1 /* Board is icon */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h deleted file mode 100644 index b882cf0699..0000000000 --- a/include/configs/idmr.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Configuration settings for the iDMR board - * - * Based on MC5272C3, r5200 and M5271EVB board configs - * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2006 Lab X Technologies - * (C) Copyright 2003 Josef Baumgartner - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IDMR_H -#define _IDMR_H - - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_IDMR /* define board type */ - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* - * Default environment settings - */ -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETHPRIME -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ROOTPATH "" -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_HOSTNAME idmr -#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage" -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \ - "filesystem over NFS; echo" - -#define CONFIG_MCFTMR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ethact=FEC\0 " \ - "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \ - "cp.b 200000 ff800000 $(filesize);" \ - "prot on ff800000 ff81ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=/tftpboot/idmr/u-boot.bin\0" \ - "" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Configuration for environment, which occupies third sector in flash. - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_ADDR 0xff820000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#else /* CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#endif /* !CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ (50000000 / 64) -#define CONFIG_SYS_CLK 100000000 - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Ethernet - */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else /* !CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif /* CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_SIZE 0x800000 -/* - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - */ - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 - - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=idmr-0" - -#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ - "64k(env)," \ - "640k(kernel)," \ - "2m(rootfs)," \ - "-(user)"; - -#if defined(CONFIG_CMD_MII) -#error "MII commands don't work on iDMR board and should not be enabled." -#endif - -#endif /* _IDMR_H */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 7d2715d094..e11d1843b9 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ #define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ #define CONFIG_XWAY_SWAP_BYTES diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 608d7592f1..f321975c47 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -16,9 +16,8 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_INKA4X0 1 /* INKA4x0 board */ /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/intip.h b/include/configs/intip.h index d3d7a441b6..b56b3aa340 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -30,7 +30,6 @@ #define CONFIG_IDENT_STRING " intip 0.06" #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/io.h b/include/configs/io.h index 2d67cfc66a..9da6cc6855 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IO 1 /* on a Io board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -199,9 +198,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/io64.h b/include/configs/io64.h index 39ed2850d2..6915b2071c 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -20,7 +20,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_IO64 1 /* Board is Io64 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 788c715a2f..f36c2a3504 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IOCON 1 /* on a IoCon board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -239,9 +238,8 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/ip04.h b/include/configs/ip04.h index d36ae43664..0efa2b7b9f 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -132,6 +132,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R /* needed for MAC address */ #define CONFIG_UART_CONSOLE 0 +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED #undef CONFIG_SHOW_BOOT_PROGRESS /* Enable this if bootretry required; currently it's disabled */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 408168b9bc..41ced15c48 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -16,9 +16,8 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPX5200 1 /* ... on MPX5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_MPX5200 1 /* MPX5200 board */ +#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ #define CONFIG_IPEK01 /* Motherboard is ipek01 */ #define CONFIG_SYS_TEXT_BASE 0xfc000000 diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 71e8ececfc..7dfaa221ee 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -13,8 +13,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* especially an MPC5200 */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_JUPITER 1 /* ... on Jupiter board */ /* diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ca0df2d0ce..fa72eb02f3 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -18,7 +18,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KATMAI 1 /* Board is Katmai */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index d2acc281cd..1990b2df15 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KILAUEA 1 /* Board is Kilauea */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ @@ -119,12 +118,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -152,61 +146,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 405EX the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from location 0xfffff000...0xffffffff the - * NAND controller cannot be accessed since it is attached to CS0 too. - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -231,11 +170,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) @@ -417,7 +354,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "logversion=2\0" \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ @@ -435,16 +371,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP -/* - * Don't run the memory POST on the NAND-booting version. It will - * overwrite part of the U-Boot image which is already loaded from NAND - * to SDRAM. - */ -#if defined(CONFIG_NAND_U_BOOT) -#define CONFIG_SYS_POST_MEMORY_ON 0 -#else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY -#endif /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ @@ -495,18 +422,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -/* booting from NAND, so NAND chips select has to be on CS 0 */ -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ - -/* Memory Bank 1 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x05806500 -#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#else #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -516,7 +431,6 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x018003c0 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#endif /* Memory Bank 2 (FPGA) initialization */ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 2a15ad469b..517f46a3a3 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -99,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -111,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ @@ -135,8 +141,8 @@ * - 'release': for a standalone system kernel/rootfs from flash */ #define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \ - "flashargs add_default addpanic boot\0" \ + "subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \ + "cramfsloadkernel flashargs add_default addpanic boot\0"\ "develop=" \ "tftp 200000 scripts/develop-${arch}.txt && " \ "env import -t 200000 ${filesize} && " \ @@ -220,6 +226,7 @@ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ "bootcmd=km_checkbidhwk && " \ "setenv bootcmd \'if km_checktestboot; then; " \ "setenv boot_bank ${test_bank}; else; " \ @@ -229,6 +236,10 @@ "run ${subbootcmds}; reset\' && " \ "saveenv && saveenv && boot\0" \ "bootlimit=3\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \ "init=/sbin/init-overlay.sh\0" \ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 2cebb2bb0c..763c5bad82 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -70,11 +70,6 @@ #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "update=" \ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ @@ -82,6 +77,7 @@ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ " ${filesize} && " \ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ + "set_fdthigh=true\0" \ "" #endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 47355abed9..29c6f60971 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -15,7 +15,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 5e075c8dd2..ae6b6dcf24 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -84,7 +84,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index e74f85f604..6d77680c82 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -70,7 +70,8 @@ #define CONFIG_KM_PHRAM 0x17F000 #define CONFIG_KM_CRAMFS_ADDR 0x2400000 -#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */ +#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */ /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ @@ -78,15 +79,17 @@ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - -\0" \ - "cramfsloadfdt=true\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_UPDATE_UBOOT \ + "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_MISC_INIT_R +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT + /* * NS16550 Configuration */ @@ -289,10 +292,15 @@ int get_scl(void); " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif +#ifndef CONFIG_KM_BOARD_EXTRA_ENV +#define CONFIG_KM_BOARD_EXTRA_ENV "" +#endif + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_BOARD_EXTRA_ENV \ CONFIG_KM_DEF_ENV \ CONFIG_KM_NEW_ENV \ "arch=arm\0" \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 50330ccf6e..582978afe2 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -15,6 +15,10 @@ #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + #define CONFIG_NAND_ECC_BCH /* common KM defines */ @@ -24,15 +28,14 @@ #define CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ @@ -149,8 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ -#define CONFIG_BOOTCOUNT_LIMIT - /* * Local Bus Definitions */ @@ -207,8 +208,13 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ +/* bootcounter in QRIO */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT @@ -264,7 +270,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ /* I2C */ + #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ @@ -277,6 +286,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ @@ -287,6 +302,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 @@ -421,6 +437,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "update=" \ "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0" \ + "set_fdthigh=true\0" \ "" #define CONFIG_HW_ENV_SETTINGS \ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 74c72325f6..9eb1ad3397 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -40,19 +40,25 @@ #define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16" #define CONFIG_HOSTNAME km_kirkwood_128m16 #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA) +/* KM_NUSA / KM_SUGP1 */ +#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ + +# if defined(CONFIG_KM_NUSA) #define CONFIG_IDENT_STRING "\nKeymile NUSA" #define CONFIG_HOSTNAME kmnusa +# elif defined(CONFIG_KM_SUGP1) +#define CONFIG_IDENT_STRING "\nKeymile SUGP1" +#define CONFIG_HOSTNAME kmsugp1 +#define KM_PCIE_RESET_MPP7 +#endif + #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352 @@ -65,8 +71,7 @@ #define CONFIG_HOSTNAME mgcoge3un #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 #define CONFIG_KM_DISABLE_PCIE @@ -77,8 +82,7 @@ #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 #define CONFIG_HOSTNAME kmcoge5un @@ -97,6 +101,8 @@ #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile SUV31" #define CONFIG_HOSTNAME kmsuv31 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 4158c8dd0f..8bb3571691 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -13,6 +13,11 @@ #define CONFIG_HOSTNAME kmlion1 #define CONFIG_KM_BOARD_NAME "kmlion1" +/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + #else #error ("Board not supported") #endif @@ -42,6 +47,7 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM /* Local bus app1 Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif /* App2 Local bus */ #define CONFIG_SYS_LBAPP2_BASE 0xE0000000 @@ -63,6 +69,5 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM /* Local bus app2 Options */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index cc3c7a8e6a..90e2d7a030 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -106,7 +106,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ @@ -171,7 +170,6 @@ #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 /* i2c */ #define CONFIG_CMD_I2C diff --git a/include/configs/korat.h b/include/configs/korat.h index 811ff995e2..5494a6007d 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -22,7 +22,6 @@ * High Level Configuration Options */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 #ifdef CONFIG_KORAT_PERMANENT diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h index 251327a227..c352a1c804 100644 --- a/include/configs/kvme080.h +++ b/include/configs/kvme080.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_KVME080 1 diff --git a/include/configs/kwb.h b/include/configs/kwb.h new file mode 100644 index 0000000000..0f631c0f60 --- /dev/null +++ b/include/configs/kwb.h @@ -0,0 +1,128 @@ +/* + * kwb.h + * + * specific parts for B&R KWB Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KWB_H__ +#define __CONFIG_KWB_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +#define CONFIG_MACH_TYPE 3589 +/* I2C IP block */ +#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 + +/* GPIO */ +#define CONFIG_SPL_GPIO_SUPPORT + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SPL_MMC_SUPPORT + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +#endif /* CONFIG_SPL_OS_BOOT */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80100000\0" \ + "bootfile=arimg\0" \ + "usbboot=echo Booting from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 ${loadaddr} ${bootfile}; " \ + "usb stop; " \ + "go ${loadaddr};\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload 0; " \ + "dhcp; " \ + "tftp ${loadaddr} arimg; " \ + "go ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run usbupdate;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +/* undefine command which we not need here */ +#undef CONFIG_BOOTM_LINUX +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_GZIP +#undef CONFIG_ZLIB +#undef CONFIG_CMD_CRC32 + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index f183279ba8..5a13ad1139 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -15,6 +15,7 @@ #define CONFIG_KZM_A9_GT #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G +#define CONFIG_SYS_GENERIC_BOARD #include @@ -88,7 +89,6 @@ #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0x00000000 diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index f6e79ba350..2d2e23a2a9 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -80,9 +80,9 @@ * from the Network Space v2 */ #if defined(CONFIG_INETSPACE_V2) -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg #elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg #endif /* diff --git a/include/configs/lager.h b/include/configs/lager.h index b6c1954a94..b420e45e63 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #if defined(CONFIG_SYS_USE_BOOT_NORFLASH) @@ -196,6 +195,5 @@ #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __LAGER_H */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 92865df12a..96a889fe87 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -13,12 +13,12 @@ */ #if defined(CONFIG_LSCHLV2) #define CONFIG_IDENT_STRING " LS-CHLv2" -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg #define CONFIG_MACH_TYPE 3006 #define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ #elif defined(CONFIG_LSXHL) #define CONFIG_IDENT_STRING " LS-XHL" -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg #define CONFIG_MACH_TYPE 2663 /* CONFIG_SYS_TCLK is 200000000 by default */ #else @@ -37,6 +37,7 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_RANDOM_MACADDR +#define CONFIG_LIB_RAND #define CONFIG_KIRKWOOD_GPIO #define CONFIG_OF_LIBFDT diff --git a/include/configs/luan.h b/include/configs/luan.h index 67f75c79a1..15e4a7e5c8 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -17,7 +17,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_LUAN 1 /* Board is Luan */ #define CONFIG_440SP 1 /* Specific PPC440SP support */ -#define CONFIG_4xx 1 /* PPC4xx family */ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index e9c8d8fd55..07ddfc4014 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -22,7 +22,6 @@ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifdef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index a344af4573..f401470251 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -39,18 +39,20 @@ #define CONFIG_CMD_USB #define CONFIG_VIDEO +#define CONFIG_REGEX /* Enable regular expression support */ + /* * Memory configurations */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0xaff00000 +#define CONFIG_SYS_MEMTEST_END 0x8ff00000 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) @@ -128,9 +130,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=mxc-nand" +#define MTDIDS_DEFAULT "nand0=mxc_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=mxc-nand:" \ + "mtdparts=mxc_nand:" \ "1m(bootloader)ro," \ "512k(environment)," \ "512k(redundant-environment)," \ @@ -183,6 +185,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/makalu.h b/include/configs/makalu.h index d6207eb11f..fd4c26eb94 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_MAKALU 1 /* Board is Makalu */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 21b17f6e2c..60e8716a79 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -12,8 +12,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* MPC5200 CPU */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 1b9e2d0f90..a317782dbe 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -14,8 +14,7 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MCC200 1 /* ... on MCC200 board */ +#define CONFIG_MCC200 1 /* MCC200 board */ /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/mcx.h b/include/configs/mcx.h index dcd29ce7cb..47244c0034 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -98,6 +98,7 @@ /* EHCI */ #define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_2 #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP @@ -263,10 +264,9 @@ "${mtdparts} " \ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ "omapdss.def_disp=lcd;" \ - "bootm 0x82000000 0x84000000\0" - -#define CONFIG_BOOTCOMMAND \ - "run nandboot" + "bootm 0x82000000 0x84000000\0" \ + "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ + "then source 82000000;else run nandboot;fi\0" #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING @@ -321,7 +321,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -395,6 +394,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW +#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index d415ecdb5a..6c19817f86 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -29,7 +29,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 047e171100..b270429dd8 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -23,8 +23,7 @@ * (easy to change) */ -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_MECP5200 1 /* ... on MECP5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 3d792398c5..fc7ecfaee4 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -10,7 +10,6 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_MIMC200 diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h deleted file mode 100644 index 5e9e98d2fc..0000000000 --- a/include/configs/mini2440.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * (C) Copyright 2009-2010 - * Michel Pollet - * - * (C) Copyright 2012 - * Gabriel Huau - * - * Configuation settings for the MINI2440 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_S3C2440_GPIO - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ -#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ -#define CONFIG_MINI2440 /* on a MIN2440 Board */ - -#define MACH_TYPE_MINI2440 1999 -#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 - -/* - * We don't use lowlevel_init - */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F - -/* - * input clock of PLL - */ -/* MINI2440 has 12.0000MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_DM9000 -#define CONFIG_DRIVER_DM9000_NO_EEPROM -#define CONFIG_DM9000_BASE 0x20000300 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 - -/* - * allow to overwrite serial and ethaddr - */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES - -/* - * Miscellaneous configurable options - */ -#define CONFIG_LONGHELP -#define CONFIG_SYS_PROMPT "MINI2440 => " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x30000000 -#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x32000000 - -/* boot parameters address */ -#define CONFIG_BOOT_PARAM_ADDR 0x30000100 - -/* - * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need - * it to wrap 100 times (total 1562500) to get 1 sec. - */ -#define CONFIG_SYS_HZ 1562500 - -/* - * valid baudrates - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 - -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 -#define CONFIG_SYS_FLASH_BASE 0x0 - -/* - * Stack should be on the SRAM because - * DRAM is not init - */ -#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) - -/* - * NOR FLASH organization - * Now uses the standard CFI interface - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MONITOR_BASE 0x0 -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* 512 * 4096 sectors, or 32 * 64k blocks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_FLASH_SHOW_PROGRESS 1 - -/* - * Config for NOR flash - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_MY_ENV_OFFSET 0x40000 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) -/* 16k Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 - -/* ATAG configuration */ -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE - -#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 8071ac3808..e8b05932a1 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -15,8 +15,7 @@ */ /* CPU and board */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 38337b4564..7de245b33c 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -29,7 +29,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index de7a53a8c2..4ae9afd4e5 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h deleted file mode 100644 index 4cac8ee46a..0000000000 --- a/include/configs/mpq101.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright 2011 Alex Dubov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Merury Computers MPQ101 board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_36BIT -# define CONFIG_PHYS_64BIT -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ -#define CONFIG_MPC8548 /* MPC8548 specific */ -#define CONFIG_MPQ101 /* MPQ101 board specific */ - -#define CONFIG_SYS_SRIO /* enable serial RapidIO */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_PANIC_HANG - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_ADDR_MAP -# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - - -#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* Fixed 512MB DDR2 parameters */ -#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322 -#define CONFIG_SYS_DDR_TIMING_2 0x03984cce -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca -#define CONFIG_SYS_DDR_MODE_1 0x00400442 -#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x08200100 -#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100 -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400000 - -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0ffffffc - -/* - * RAM definitions - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ - - -/* - * FLASH on the Local Bus - * One bank, 128M, using the CFI driver. - */ -#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull -#else -# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -/* 0xf8001801 */ -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_32 | BR_V) - -/* 0xf8006ff7 */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX \ - | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash. - */ -#define CONFIG_ASSUME_AMD_FLASH - -/* - * Environment parameters - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_USE_PPCENV -#define ENV_IS_EMBEDDED -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ -#define CONFIG_ENV_SIZE 0x800 - -/* Environment at the start of flash sector, before text. */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_TEXT_BASE 0xfffc0800 -#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds" - -/* - * Cypress CY7C67200 USB controller on the Local Bus. - * Not supported by u-boot at present. - */ -#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull -#else -# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE -#endif - -/* 0xf0001001 */ -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -/* fffff002 */ -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ - | OR_GPCM_BCTLD | OR_GPCM_EHTR) - -/* - * Serial Ports - */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ - 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C buses and peripherals - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* I2C RTC - M41T81 */ -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/* I2C EEPROM - 24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* - * RapidIO MMU - */ -#ifdef CONFIG_SYS_SRIO -# define CONFIG_SRIO1 -# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 -# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -# ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull -# else -# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT -# endif -#endif - -/* - * Ethernet - */ -#ifdef CONFIG_TSEC_ENET - -# define CONFIG_MII /* MII PHY management */ -# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ - -# define CONFIG_TSEC1 -# define CONFIG_TSEC1_NAME "eTSEC0" -# define TSEC1_PHY_ADDR 0x10 -# define TSEC1_PHYIDX 0 -# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC2 -# define CONFIG_TSEC2_NAME "eTSEC1" -# define TSEC2_PHY_ADDR 0x11 -# define TSEC2_PHYIDX 0 -# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC3 -# define CONFIG_TSEC3_NAME "eTSEC2" -# define TSEC3_PHY_ADDR 0x12 -# define TSEC3_PHYIDX 0 -# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC4 -# define CONFIG_TSEC4_NAME "eTSEC3" -# define TSEC4_PHY_ADDR 0x13 -# define TSEC4_PHYIDX 0 -# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: eTSEC[0-3] */ -# define CONFIG_ETHPRIME "eTSEC0" -# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -#endif - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_JFFS2 - -/* - * Miscellaneous configurable options - */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -#define CONFIG_FIT /* new uImage format support */ -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */ - -/* Console I/O Buffer Size */ -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 -#else -# define CONFIG_SYS_CBSIZE 256 -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Basic Environment Configuration - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -/*default location for tftp and bootm*/ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#endif /* __CONFIG_H */ diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index 87c06389b4..7343c947ca 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -13,8 +13,6 @@ * (easy to change) */ -#define CONFIG_8260 1 -#define CONFIG_MPC8260 1 #define CONFIG_MUAS3001 1 #define CONFIG_SYS_TEXT_BASE 0xFF000000 diff --git a/include/configs/munices.h b/include/configs/munices.h index 3bda8ebea4..e65a14af23 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -11,8 +11,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_MUNICES 1 /* ... on MUNICes board */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 1b40a36fcf..b496892f06 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -84,7 +84,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyAMA0\0" \ "fdt_file=imx23-evk.dtb\0" \ "fdt_addr=0x41000000\0" \ @@ -98,22 +98,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -121,7 +121,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else " \ "echo ERR: Fail to boot from MMC; " \ diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index af6aafaf1c..aff2419f85 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -62,6 +62,7 @@ /* No NOR flash present */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_MMC @@ -69,7 +70,7 @@ /* U-Boot general configuration */ #define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print buffer sz */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -132,12 +133,104 @@ #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_DEFAULT_FDT_FILE "imx25-pdk.dtb" + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x82000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run netargs; dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __CONFIG_H */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4fd67eb4a0..9b9124ac14 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -198,7 +198,7 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "nand write ${loadaddr} kernel ${filesize}\0" \ "update_nand_fdt=" /* Update fdt */ \ "mtdparts default; " \ @@ -230,10 +230,10 @@ "nand read ${loadaddr} kernel 0x00400000; " \ "if test ${boot_fdt} = yes; then " \ "nand read ${fdt_addr} fdt 0x00080000; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = no; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ "fi; " \ @@ -248,7 +248,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console_fsl=ttyAM0\0" \ "console_mainline=ttyAMA0\0" \ "fdt_file=imx28-evk.dtb\0" \ @@ -264,22 +264,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ @@ -291,19 +291,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi;" \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -311,7 +311,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 1cff171951..b389475ebe 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -143,7 +143,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=imx51-babbage.dtb\0" \ "fdt_addr=0x91000000\0" \ "boot_fdt=try\0" \ @@ -157,22 +157,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -184,20 +184,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -205,7 +205,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ae43ea3c1f..5859f360e0 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -65,6 +65,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -103,7 +104,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=imx53-qsb.dtb\0" \ "fdt_addr=0x71000000\0" \ "boot_fdt=try\0" \ @@ -116,22 +117,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -143,20 +144,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -164,7 +165,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -193,11 +194,11 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 514d634c0c..8a8920f6cc 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -20,6 +20,13 @@ #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_ARM_ERRATA_794072 +#define CONFIG_ARM_ERRATA_761320 #define CONFIG_BOARD_POSTCLK_INIT +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif + #endif diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index f0a82d194c..fd651cfa50 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -72,7 +72,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -85,16 +85,16 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm\0" \ + "bootz\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "dhcp ${image}; bootz\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ @@ -102,7 +102,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index dbbb6f0311..bd0144f5cb 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -41,4 +41,7 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_OF_SEPARATE +#define CONFIG_DEFAULT_DEVICE_TREE imx6q-sabreauto + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 5ee7fa5448..7a2c172d4a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,7 +12,7 @@ #define CONFIG_MX6 #include "mx6_common.h" -#include +#include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -119,7 +119,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ @@ -150,22 +150,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -177,19 +177,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -198,7 +198,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 4919f53328..5d02d23ec7 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -48,4 +48,14 @@ #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index b29f78cc2c..1876dbf35a 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,7 +10,7 @@ #define __CONFIG_H #include -#include +#include #include "mx6_common.h" #define CONFIG_MX6 @@ -76,12 +76,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x81000000\0" \ + "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=0\0" \ @@ -93,22 +93,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -120,19 +120,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -141,7 +141,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 363b277635..ba55177e72 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -59,7 +59,6 @@ /* Memory sizes */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ @@ -81,8 +80,16 @@ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot * binary. In case there was more of this mess, 0x100 bytes are skipped. + * + * In case of a HAB boot, we cannot for some weird reason use the first 4KiB + * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST + * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. + * + * As for the SPL, we must avoid the first 4 KiB as well, but we load the + * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +#define CONFIG_SYS_TEXT_BASE 0x40002000 +#define CONFIG_SPL_TEXT_BASE 0x00001000 /* U-Boot general configuration */ #define CONFIG_SYS_LONGHELP @@ -175,6 +182,11 @@ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #endif +/* OCOTP */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXS_OCOTP +#endif + /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI diff --git a/include/configs/neo.h b/include/configs/neo.h index 62ea8eca86..d549985886 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -10,7 +10,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_NEO 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd1b5..f7e7315a9b 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -#define CONFIG_MV_UDC +#define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER @@ -115,6 +115,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ @@ -352,4 +353,14 @@ #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_CMD_FS_GENERIC +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index ce08454994..133dc6f8cd 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -16,7 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ @@ -276,10 +275,8 @@ #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE #endif -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index f3fb5852f9..4ff2f05c88 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -26,7 +26,6 @@ #define CONFIG_OCOTEA 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h index a578edd0d8..41f7973f2b 100644 --- a/include/configs/omap1510.h +++ b/include/configs/omap1510.h @@ -10,7 +10,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include /* There are 2 sets of general I/O --> diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c58bc91a50..0b57421537 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -120,8 +120,9 @@ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX /* GPIO banks */ #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ @@ -183,8 +184,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 43616e2b02..7f3424b4f0 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -208,7 +208,6 @@ #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 71062a601f..d56d5b00cc 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -10,20 +10,13 @@ #ifndef __IGEP00X0_H #define __IGEP00X0_H -#include +#ifdef CONFIG_BOOT_NAND +#define CONFIG_NAND +#endif -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON +#define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include -#include +#include #include /* @@ -32,53 +25,23 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ #define CONFIG_SUPPORT_RAW_INITRD -/* - * NS16550 Configuration - */ - -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* define to enable boot progress via leds */ #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) #define CONFIG_SHOW_BOOT_PROGRESS #endif +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -95,21 +58,10 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "IGEP" -/* commands to include */ -#include - #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ #ifdef CONFIG_BOOT_ONENAND #define CONFIG_CMD_ONENAND /* ONENAND support */ #endif -#ifdef CONFIG_BOOT_NAND -#define CONFIG_CMD_NAND -#endif #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ @@ -117,24 +69,8 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_OMAP34XX -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -#define CONFIG_BOOTDELAY 3 +/*#undef CONFIG_ENV_IS_NOWHERE*/ #define CONFIG_EXTRA_ENV_SETTINGS \ "usbtty=cdc_acm\0" \ @@ -205,48 +141,6 @@ "fi;" \ "run nandboot;" \ -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - * - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /* * FLASH and environment organization */ @@ -263,23 +157,14 @@ #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET #endif -#ifdef CONFIG_BOOT_NAND +#ifdef CONFIG_NAND #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ #define CONFIG_ENV_ADDR NAND_ENV_OFFSET -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* * SMSC911x Ethernet */ @@ -289,54 +174,9 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -/* MMC boot config */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - +/* OneNAND boot config */ #ifdef CONFIG_BOOT_ONENAND #define CONFIG_SPL_ONENAND_SUPPORT - -/* OneNAND boot config */ #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 @@ -345,13 +185,8 @@ #endif -#ifdef CONFIG_BOOT_NAND -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - /* NAND boot config */ +#ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -363,8 +198,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index bedd6f9cb3..0d03c75ce3 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -295,7 +295,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index e0f026269f..007e27f9f1 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -119,8 +119,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index eacdfaaa53..da67787e69 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -131,8 +131,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 6f1304dc94..a3e8a59972 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -16,7 +16,7 @@ /* TODO: REMOVE THE FOLLOWING * Retained the following till size.h is removed in u-boot */ -#include +#include /* * High Level Configuration Options */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 1dd53fa133..f0fa96efcb 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,8 +138,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 73dc088595..7378acdb21 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -4,7 +4,7 @@ * Steve Sakoman * * Configuration settings for the TI OMAP4 Panda board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * * SPDX-License-Identifier: GPL-2.0+ */ @@ -36,7 +36,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -#include +#include #define CONFIG_CMD_NET /* GPIO */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index b35251120d..a83797454c 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -5,7 +5,7 @@ * Steve Sakoman * * Configuration settings for the TI SDP4430 board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,7 +19,7 @@ #define CONFIG_4430SDP 1 /* working with SDP */ #define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP -#include +#include /* Battery Charger */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 76c5106b45..783b7c3e32 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -4,7 +4,7 @@ * Sricharan R * * Configuration settings for the TI EVM5430 board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,7 +17,7 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#include +#include #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE @@ -37,6 +37,7 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART #define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X diff --git a/include/configs/origen.h b/include/configs/origen.h index f46b833b53..82583382f7 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -6,115 +6,71 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_ORIGEN_H +#define __CONFIG_ORIGEN_H + +#include + +#define CONFIG_SYS_PROMPT "ORIGEN # " + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - #define CONFIG_SYS_DCACHE_OFF 1 +/* ORIGEN has 4 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: ORIGEN has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) + +/* select serial console configuration */ +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - -/* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #undef CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 - #define CONFIG_SPL_TEXT_BASE 0x02021410 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "ORIGEN # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -/* ORIGEN has 4 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ORIGEN" #define CONFIG_CLK_1000_400_200 @@ -122,13 +78,12 @@ /* MIU (Memory Interleaving Unit) */ #define CONFIG_MIU_2BIT_21_7_INTERLEAVED -#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -140,7 +95,4 @@ #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c6df11b8f1..07b61795bb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -159,12 +159,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_MMC_BOOT @@ -189,12 +189,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_SPI_BOOT @@ -221,7 +221,7 @@ #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) @@ -247,7 +247,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -265,7 +265,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 -#define CONFIG_MPC85xx #define CONFIG_MP @@ -580,11 +579,15 @@ #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) +#if defined(CONFIG_P2020RDB) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) +#else +#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) +#endif #elif defined(CONFIG_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 @@ -842,11 +845,7 @@ #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 9837100e31..c296a07599 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -24,11 +24,11 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -42,7 +42,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 -#define CONFIG_MPC85xx #define CONFIG_MP @@ -239,9 +238,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_64BIT_STRTOUL - /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ @@ -407,11 +403,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 1fdd602f5b..225567bd90 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -20,7 +20,6 @@ #define CONFIG_P3P440 1 /* Board is P3P440 */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 2a9fd22dd6..9480d8daf2 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -115,7 +115,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index de254076f2..8abce1b425 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -117,7 +117,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 9e2686ac44..dd0abf8de6 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,7 +17,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" /* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index e929b23f28..f92496571b 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 5c6188955d..31a93c87de 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -20,8 +20,7 @@ High Level Configuration Options (easy to change) -----------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ /* FEC configuration and IDE */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 6f41ee7718..9af3efd4b1 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -297,7 +297,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 5a5fe7ff00..e6e06f2d2e 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -23,7 +23,6 @@ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 2a54e5cea0..553eb8f967 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -30,7 +30,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xF0000000 diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h new file mode 100644 index 0000000000..fc25966e0f --- /dev/null +++ b/include/configs/pengwyn.h @@ -0,0 +1,207 @@ +/* + * pengwyn.h + * + * Copyright (C) 2013 Lothar Felten + * + * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PENGWYN_H +#define __CONFIG_PENGWYN_H + +#define CONFIG_NAND +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 + +#include + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK V_OSCK + +/* set env size */ +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=am335x-pengwyn.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration: primary UART via FDTI */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#if defined(CONFIG_MUSB_HOST) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_SPL_BUILD) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* Disable CPSW SPL support so we fit within the 101KiB limit. */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_NATSEMI + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 327be3fde9..be76478c30 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -22,8 +22,7 @@ * (easy to change) */ -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_PF5200 1 /* ... on PF5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 760dcaca4b..5dcd9cc0d0 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -293,7 +293,6 @@ * *****************************************************************************/ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 03d4269584..e96ed4b4f2 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -135,7 +135,7 @@ #define CONFIG_BOOTCOMMAND "run nandboot" #define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7722f7be2e..6276d43395 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -44,7 +44,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS #define CONFIG_FACTORYSET diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index dd3babb505..98ed8bc97f 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 /* MIPS32 CPU core */ #define CONFIG_QEMU_MIPS #define CONFIG_MISC_INIT_R diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index a1422fca11..e8f5a4c9e8 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS64 /* MIPS64 CPU core */ #define CONFIG_QEMU_MIPS #define CONFIG_MISC_INIT_R diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 20d6178dc1..e91e805bb9 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -15,7 +15,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EP 1 /* Specifc 405EP support*/ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 53128ecc12..a71709bc7c 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -140,8 +140,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/redwood.h b/include/configs/redwood.h index c8bd02e710..622b7c79e6 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -12,7 +12,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC460 family */ #define CONFIG_460SX 1 /* ... PPC460 family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ @@ -121,7 +120,6 @@ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 0b7add7bea..ed8b4dfb51 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -17,7 +17,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include /* Architecture, CPU, etc.*/ #define CONFIG_ARM1176 @@ -95,12 +95,25 @@ #define CONFIG_SYS_LOAD_ADDR 0x1000000 #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_PREBOOT \ + "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \ + "env import -t ${loadaddr} ${filesize}; " \ + "fi" + +#define ENV_DEVICE_SETTINGS \ + "stdin=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + /* * Memory layout for where various images get loaded by boot scripts: * * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it low in memory to avoid conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it low in memory to avoid conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -116,67 +129,112 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stderr=serial,lcd\0" \ - "stdout=serial,lcd\0" \ +#define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ + "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ - "boot_targets=mmc0\0" \ - \ - "script_boot=" \ - "if fatload ${devtype} ${devnum}:1 " \ - "${scriptaddr} boot.scr.uimg; then " \ - "source ${scriptaddr}; " \ - "fi;\0" \ - \ + +#define BOOTCMDS_MMC \ "mmc_boot=" \ "setenv devtype mmc; " \ "if mmc dev ${devnum}; then " \ - "run script_boot; " \ + "run scan_boot; " \ "fi\0" \ + "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" +#define BOOT_TARGETS_MMC "mmc0" + +#define BOOTCMDS_COMMON \ + "rootpart=1\0" \ \ - "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \ + "do_script_boot=" \ + "load ${devtype} ${devnum}:${rootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "source ${scriptaddr}\0" \ + \ + "script_boot=" \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}${script}; then " \ + "echo Found ${prefix}${script}; " \ + "run do_script_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" \ + \ + "do_sysboot_boot=" \ + "sysboot ${devtype} ${devnum}:${rootpart} any " \ + "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \ + \ + "sysboot_boot=" \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}extlinux/extlinux.conf; then " \ + "echo Found ${prefix}extlinux/extlinux.conf; " \ + "run do_sysboot_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi\0" \ + \ + "scan_boot=" \ + "echo Scanning ${devtype} ${devnum}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run sysboot_boot; " \ + "run script_boot; " \ + "done\0" \ + \ + "boot_targets=" \ + BOOT_TARGETS_MMC " " \ + "\0" \ + \ + "boot_prefixes=/\0" \ + \ + "boot_scripts=boot.scr.uimg\0" \ + \ + BOOTCMDS_MMC #define CONFIG_BOOTCOMMAND \ "for target in ${boot_targets}; do run bootcmd_${target}; done" -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTCOMMAND \ + "for target in ${boot_targets}; do run bootcmd_${target}; done" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTCMDS_COMMON + +#define CONFIG_BOOTDELAY 2 /* Shell */ -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE /* Commands */ #include -#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_GPIO #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT -/* Some things don't make sense on this HW or yet */ -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SAVEENV -/* Device tree support for bootm/bootz */ -#define CONFIG_OF_LIBFDT +/* Device tree support */ #define CONFIG_OF_BOARD_SETUP /* ATAGs support for bootm/bootz */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG +#include + +/* Some things don't make sense on this HW or yet */ +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SAVEENV +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING + #endif diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 92318c3394..06211380d4 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -19,7 +19,6 @@ * (easy to change) */ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/rut.h b/include/configs/rut.h index d4519f946c..6bddededae 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -41,7 +41,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_NATSEMI #define CONFIG_FACTORYSET diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 0590d201ce..991c43e1cc 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -34,6 +34,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING @@ -113,8 +114,13 @@ #define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" +#define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R + #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_UPDATEB \ "updatek=" \ @@ -208,8 +214,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) +#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index d9e4c5683f..2da887109d 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -7,78 +7,56 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_UNIVERSAL_H +#define __CONFIG_UNIVERSAL_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */ -#define CONFIG_UNIVERSAL 1 /* working with Universal */ -#define CONFIG_TIZEN 1 /* TIZEN lib */ +#include -#include /* get chip and board defs */ +#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-universal_c210 + +#define CONFIG_TIZEN /* TIZEN lib */ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_L2CACHE_OFF 1 +/* Universal has 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x44800000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* PWM */ -#define CONFIG_PWM 1 +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) -/* Command definition */ -#include +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_ONENAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT +#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_SYS_TEXT_BASE 0x44800000 #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS @@ -106,23 +84,23 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - #define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" #define CONFIG_BOOTBLOCK "10" #define CONFIG_UBIBLOCK "9" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + #define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " #define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ "${mtdparts}" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ @@ -184,53 +162,18 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "Universal # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* Universal has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_ENV_IS_IN_MMC 1 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION 1 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) + +#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ @@ -253,10 +196,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) +#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) +#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) +#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) #define SPI_DELAY udelay(1) #undef SPI_INIT @@ -269,16 +212,45 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" +#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 +#define KEY_PWR_INTERRUPT_MASK (1 << 7) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* * LCD Settings */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_LD9040 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) + +#define LCD_XRES 480 +#define LCD_YRES 800 #endif /* __CONFIG_H */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 3750ad2c3d..b5064ab37c 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -457,6 +457,7 @@ #endif /* CONFIG_BOOT_ROOT_NFS */ #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ +#define CONFIG_LIB_RAND /* * BOOTP options @@ -524,7 +525,6 @@ * *****************************************************************************/ -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_SACSng 1 /* munged for the SACSng */ #define CONFIG_CPM2 1 /* Has a CPM2 */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h new file mode 100644 index 0000000000..91cc7d8e58 --- /dev/null +++ b/include/configs/sama5d3_xplained.h @@ -0,0 +1,203 @@ +/* + * Configuration settings for the SAMA5D3 Xplained board. + * + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_AT91FAMILY +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_DBGU + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP ATMEL_ID_UHPHS + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 4 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_ATMEL_MCI_8BIT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_DOS_PARTITION +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#if CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index c34feb5081..516be85fe0 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -258,6 +258,8 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds #define CONFIG_SPL_MMC_SUPPORT @@ -267,6 +269,27 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#elif CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 + #endif #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index a6d55822b8..fa62cb6cd5 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -20,6 +20,14 @@ #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT +#define CONFIG_DM +#define CONFIG_CMD_DEMO +#define CONFIG_CMD_DM +#define CONFIG_DM_DEMO +#define CONFIG_DM_DEMO_SIMPLE +#define CONFIG_DM_DEMO_SHAPE +#define CONFIG_DM_GPIO +#define CONFIG_DM_TEST /* Number of bits in a C 'long' on this architecture */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 @@ -32,6 +40,7 @@ #define CONFIG_FIT_SIGNATURE #define CONFIG_RSA #define CONFIG_CMD_FDT +#define CONFIG_DEFAULT_DEVICE_TREE sandbox #define CONFIG_FS_FAT #define CONFIG_FS_EXT4 @@ -42,12 +51,13 @@ #define CONFIG_CMD_PART #define CONFIG_DOS_PARTITION #define CONFIG_HOST_MAX_DEVICES 4 +#define CONFIG_CMD_FS_GENERIC #define CONFIG_SYS_VSNPRINTF #define CONFIG_CMD_GPIO #define CONFIG_SANDBOX_GPIO -#define CONFIG_SANDBOX_GPIO_COUNT 20 +#define CONFIG_SANDBOX_GPIO_COUNT 128 #define CONFIG_CMD_GPT #define CONFIG_PARTITION_UUIDS @@ -56,7 +66,7 @@ /* * Size of malloc() pool, although we don't actually use this yet. */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_LONGHELP /* #undef to save memory */ @@ -70,6 +80,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY #define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 3 #define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_IS_NOWHERE @@ -80,6 +91,8 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI_FLASH +#define CONFIG_OF_SPI +#define CONFIG_OF_SPI_FLASH #define CONFIG_SPI_FLASH_SANDBOX #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND @@ -88,7 +101,9 @@ #define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) -#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000 +#define CONFIG_SYS_FDT_LOAD_ADDR 0x100 + +#define CONFIG_PHYSMEM /* Size of our emulated memory */ #define CONFIG_SYS_SDRAM_BASE 0 @@ -116,13 +131,36 @@ #define CONFIG_SHA1 #define CONFIG_SHA256 +#define CONFIG_TPM_TIS_SANDBOX + #define CONFIG_CMD_SANDBOX #define CONFIG_BOOTARGS "" -#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define CONFIG_CROS_EC +#define CONFIG_CMD_CROS_EC +#define CONFIG_CROS_EC_SANDBOX +#define CONFIG_KEYBOARD +#define CONFIG_CROS_EC_KEYB +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SOUND +#define CONFIG_SOUND_SANDBOX +#define CONFIG_CMD_SOUND + +#define CONFIG_SANDBOX_SDL +#define CONFIG_LCD +#define CONFIG_VIDEO_SANDBOX_SDL +#define CONFIG_CMD_BMP +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" #define CONFIG_GZIP_COMPRESSED #define CONFIG_BZIP2 @@ -131,4 +169,6 @@ #define CONFIG_TPM_TIS_SANDBOX +#define CONFIG_CMD_LZMADEC + #endif diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index a85eb1c3fc..8cce34af76 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -56,7 +56,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 7e16c451c3..a1b5751d09 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -12,7 +12,7 @@ /* SoC type is defined in boards.cfg */ #include -#include +#include #if defined(CONFIG_SYS_USE_NANDFLASH) #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 2fd1dc48e4..69dc210917 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -17,7 +17,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b7f83e0105..2516a3e97e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -19,7 +19,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 4912d69dcf..f28f350fcc 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -38,7 +38,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 78f8219c5f..8eb7276618 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -21,7 +21,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 9a11150592..14e033dd80 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -43,7 +43,6 @@ */ #define CONFIG_SC3 1 -#define CONFIG_4xx 1 #define CONFIG_405GP 1 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index c0048aca78..e6d272dd1f 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -69,7 +69,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 2a24ef3c64..fc4f976d8d 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include /* LP0 suspend / resume */ #define CONFIG_TEGRA_LP0 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index d2dedac4ed..b6a5e6a59c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -27,7 +27,6 @@ #define CONFIG_HOSTNAME rainier #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -98,10 +97,7 @@ /* * Environment */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ -#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ -#elif defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ #define CONFIG_ENV_SIZE (8 << 10) /* @@ -149,68 +145,11 @@ #endif #endif /* CONFIG_CMD_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ - /* this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /* * DDR SDRAM */ #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SYS_RAMBOOT) +#if !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ @@ -248,7 +187,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ "" @@ -322,7 +260,7 @@ * overwrite part of the U-Boot image which is already loaded from NAND * to SDRAM. */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_POST_MEMORY_ON 0 #else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY @@ -371,8 +309,7 @@ /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SYS_RAMBOOT) +#if !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x03017200 diff --git a/include/configs/shmin.h b/include/configs/shmin.h index f8155efbc9..4d38f6c554 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -62,7 +62,6 @@ #define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE) #define CONFIG_SYS_MONITOR_LEN (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 286304295d..721c4e6bad 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -265,6 +265,7 @@ #define CONFIG_DFU_NAND #define CONFIG_CMD_DFU #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif /* CONFIG_SPL_BUILD */ @@ -457,7 +458,6 @@ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 447f8e5810..b96eea8890 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -17,8 +17,6 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420 -#define CONFIG_ARCH_DEVICE_TREE exynos5420 - #define CONFIG_VAR_SIZE_SPL #define CONFIG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 94a65c4d01..1ebee714ba 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -13,7 +13,7 @@ /* SoC type is defined in boards.cfg */ #include -#include +#include #define CONFIG_SYS_TEXT_BASE 0x20000000 diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 9a069f3cdb..dacb5604cd 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -41,8 +41,6 @@ #define CONFIG_ENV_SIZE (8*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ - #define CONFIG_ENV_IS_IN_MMC #define CONFIG_CMD_ENV #define CONFIG_CMD_SAVEENV diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 608578ad2c..0254249751 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/pll_config.h" /* * High level configuration diff --git a/include/configs/socrates.h b/include/configs/socrates.h index fd590e4e12..c654a0e4eb 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_MPC8544 1 #define CONFIG_SOCRATES 1 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 23f7ad77b6..c0eba3721d 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ @@ -41,6 +39,15 @@ /* I2C driver configuration */ #define CONFIG_HARD_I2C #define CONFIG_DW_I2C +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#endif #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc5801c..28dddcc5b9 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index 51339b1496..01085dc5c1 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -140,7 +140,10 @@ * can enable it here if your baseboard features ethernet. */ -/* #define CONFIG_MACB */ +#define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #ifdef CONFIG_MACB # define CONFIG_RMII /* use reduced MII inteface */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 2a9c9a349c..5fb40ebf8b 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ #define CONFIG_MPC8560 1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index d0cb68a0ed..914d821905 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ #define CONFIG_MPC8560 1 diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 9ab99244cf..502e795976 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -16,7 +16,6 @@ */ #define CONFIG_460GT 1 /* Specific PPC460GT */ #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 54a5e3e260..bd324ba2fa 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -17,11 +17,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 4ebaf2e2a5..5c0ce7a2e4 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -13,7 +13,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 3dbfc6ad1d..3d5c351b1a 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -18,7 +18,6 @@ #define CONFIG_TAISHAN 1 /* Board is taishan */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index d44b5c036d..3522c1a07a 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -186,7 +186,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9abfe82902..9c04c23ab7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -83,6 +83,13 @@ #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ + /* commands to include */ #include diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c98002317f..20d4cee011 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -37,7 +37,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 /* Misc CPU related */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h deleted file mode 100644 index 2901ed1eeb..0000000000 --- a/include/configs/tb0229.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2003 - * Masami Komiya - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for TANBAC TB0229 board using an VR4131 CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_TB0229 1 /* on a TB0229 Board */ - -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ -#endif -#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \ - "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=dhcp;tftp;run netargs; bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ - "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "read-only=readonly\0" \ - "netargs=run nfsargs addmisc\0" \ - "flash_nfs=run nfsargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_local=run localargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ - "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ - "run addmisc;" \ - "bootm 80400000 80600000\0" \ - "rootpath=/export/miniroot-mipsel\0" \ - "autoload=no\0" \ - "kernel_addr=BFC60000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=u-boot.bin\0" \ - "bootfile=uImage\0" \ - "load=dhcp;tftp 80400000 ${u-boot}\0" \ - "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ - "update_uboot=run load;" \ - "protect off BFC00000 BFC3FFFF;" \ - "erase BFC00000 BFC3FFFF;" \ - "cp.b 80400000 BFC00000 ${filesize}\0" \ - "update_kernel=run load_kernel;" \ - "erase BFC60000 BFD5FFFF;" \ - "cp.b 80400000 BFC60000 ${filesize}\0" \ - "initenv=erase bfc40000 bfc5ffff\0" \ - "" -/*#define CONFIG_BOOTCOMMAND "run flash_local" */ -#define CONFIG_BOOTCOMMAND "run netboot" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xBFC40000 -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#define CONFIG_NR_DRAM_BANKS 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 18432000 -#define CONFIG_SYS_NS16550_COM1 0xaf000800 - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define CONFIG_RTL8139 - -#endif /* __CONFIG_H */ diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 241f21051e..1ff34d517d 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -116,7 +116,7 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 58bcdc8f47..370d97ffe0 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -145,7 +145,7 @@ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - +#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index a3242fe612..76dad4e88c 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -66,27 +66,63 @@ #define BOOT_TARGETS_DHCP "" #endif +#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE) +#define BOOTCMDS_PXE \ + "bootcmd_pxe=" \ + BOOTCMD_INIT_USB \ + "dhcp; " \ + "if pxe get; then " \ + "pxe boot; " \ + "fi\0" +#define BOOT_TARGETS_PXE "pxe" +#else +#define BOOTCMDS_PXE "" +#define BOOT_TARGETS_PXE "" +#endif + #define BOOTCMDS_COMMON \ "rootpart=1\0" \ \ + "do_script_boot=" \ + "load ${devtype} ${devnum}:${rootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "source ${scriptaddr}\0" \ + \ "script_boot=" \ - "if load ${devtype} ${devnum}:${rootpart} " \ - "${scriptaddr} ${prefix}${script}; then " \ - "echo ${script} found! Executing ...;" \ - "source ${scriptaddr};" \ - "fi;\0" \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}${script}; then " \ + "echo Found U-Boot script " \ + "${prefix}${script}; " \ + "run do_script_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" \ + \ + "do_sysboot_boot=" \ + "sysboot ${devtype} ${devnum}:${rootpart} any " \ + "${scriptaddr} ${prefix}extlinux.conf\0" \ + \ + "sysboot_boot=" \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}extlinux.conf; then " \ + "echo Found extlinux config " \ + "${prefix}extlinux.conf; " \ + "run do_sysboot_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi\0" \ \ "scan_boot=" \ "echo Scanning ${devtype} ${devnum}...; " \ "for prefix in ${boot_prefixes}; do " \ - "for script in ${boot_scripts}; do " \ - "run script_boot; " \ - "done; " \ - "done;\0" \ + "run sysboot_boot; " \ + "run script_boot; " \ + "done\0" \ \ "boot_targets=" \ BOOT_TARGETS_MMC " " \ BOOT_TARGETS_USB " " \ + BOOT_TARGETS_PXE " " \ BOOT_TARGETS_DHCP " " \ "\0" \ \ @@ -96,9 +132,11 @@ \ BOOTCMDS_MMC \ BOOTCMDS_USB \ - BOOTCMDS_DHCP + BOOTCMDS_DHCP \ + BOOTCMDS_PXE #define CONFIG_BOOTCOMMAND \ + "set usb_need_init; " \ "for target in ${boot_targets}; do run bootcmd_${target}; done" #endif @@ -129,10 +167,15 @@ "stderr=serial" STDOUT_LCD "\0" \ "" +#ifndef BOARD_EXTRA_ENV_SETTINGS +#define BOARD_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - BOOTCMDS_COMMON + BOOTCMDS_COMMON \ + BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_FDT_SPI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 522cd4133d..ae786cfd7a 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -7,7 +7,7 @@ #ifndef _TEGRA_COMMON_H_ #define _TEGRA_COMMON_H_ -#include +#include #include /* @@ -29,7 +29,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ /* Environment */ #define CONFIG_ENV_VARS_UBOOT_CONFIG @@ -69,33 +68,20 @@ #undef CONFIG_CMD_NET /* network support */ /* turn on command-line edit/hist/auto */ -#define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE /* turn on commonly used storage-related commands */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_PART #define CONFIG_SYS_NO_FLASH #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT V_PROMPT /* * Increasing the size of the IO buffer as default nfsargs size is more @@ -133,8 +119,6 @@ #define CONFIG_TEGRA_GPIO #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM -#define CONFIG_CMD_BOOTZ -#define CONFIG_SUPPORT_RAW_INITRD /* Defines for SPL */ #define CONFIG_SPL @@ -151,10 +135,18 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +#ifdef CONFIG_SPL_BUILD +# define CONFIG_USE_PRIVATE_LIBGCC +#endif + #define CONFIG_SYS_GENERIC_BOARD /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY +#ifndef CONFIG_SPL_BUILD +#include +#endif + #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index a4e8a5f5eb..555c237cbf 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -26,11 +26,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ @@ -51,6 +46,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -68,6 +66,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -83,5 +82,6 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h new file mode 100644 index 0000000000..61e5026574 --- /dev/null +++ b/include/configs/tegra124-common.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_COMMON_H_ +#define _TEGRA124_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* Total I2C ports on Tegra124 */ +#define TEGRA_I2C_NUM_CONTROLLERS 5 + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 + +#endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index b009a316b1..21bf977174 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -24,11 +24,6 @@ */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ @@ -49,6 +44,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -66,6 +64,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" @@ -96,6 +95,7 @@ */ #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 #define CONFIG_EHCI_IS_TDI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 /* Total I2C ports on Tegra20 */ #define TEGRA_I2C_NUM_CONTROLLERS 4 diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index b5550d7d09..443c842240 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -23,11 +23,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ @@ -48,6 +43,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -65,6 +63,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -80,5 +79,6 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index ba16b1c14b..b51400c464 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -233,7 +233,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_ET1011C #define CONFIG_PHY_ET1011C_TX_CLK_FIX diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 4364eef7ba..50c32037ff 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -13,7 +13,6 @@ #define __CONFIG_TI_AM335X_COMMON_H__ #define CONFIG_AM33XX -#define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ @@ -31,6 +30,7 @@ /* Network defines. */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -73,6 +73,10 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + /* Now bring in the rest of the common code. */ #include diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 99b60fcf61..69d69a5421 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -45,11 +45,15 @@ #define CONFIG_BOOTDELAY 1 /* - * DDR information. We say (for simplicity) that we have 1 bank, - * always, even when we have more. We always start at 0x80000000, - * and we place the initial stack pointer in our SRAM. + * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, + * we say (for simplicity) that we have 1 bank, always, even when + * we have more. We always start at 0x80000000, and we place the + * initial stack pointer in our SRAM. Otherwise, we can define + * CONFIG_NR_DRAM_BANKS before including this file. */ +#ifndef CONFIG_NR_DRAM_BANKS #define CONFIG_NR_DRAM_BANKS 1 +#endif #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) @@ -237,7 +241,6 @@ #define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h new file mode 100644 index 0000000000..854cb78882 --- /dev/null +++ b/include/configs/ti_omap3_common.h @@ -0,0 +1,73 @@ +/* + * ti_omap3_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap3530 + * http://www.ti.com/product/omap3630 + * http://www.ti.com/product/dm3730 + */ + +#ifndef __CONFIG_TI_OMAP3_COMMON_H__ +#define __CONFIG_TI_OMAP3_COMMON_H__ + +#define CONFIG_OMAP34XX + +#include +#include + +/* The chip has SDRC controller */ +#define CONFIG_SDRC + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* NS16550 Configuration */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} + +/* Select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER 1 + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_POWER_SUPPORT + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ diff --git a/include/configs/omap4_common.h b/include/configs/ti_omap4_common.h similarity index 92% rename from include/configs/omap4_common.h rename to include/configs/ti_omap4_common.h index d099bfd48a..bcb5eabd75 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -9,8 +9,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_OMAP4_COMMON_H -#define __CONFIG_OMAP4_COMMON_H +#ifndef __CONFIG_TI_OMAP4_COMMON_H +#define __CONFIG_TI_OMAP4_COMMON_H /* * High Level Configuration Options @@ -159,4 +159,14 @@ #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#endif /* __CONFIG_OMAP4_COMMON_H */ +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + +#ifdef CONFIG_SPL_BUILD +/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_I2C_OMAP24XX +#endif + +#endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/omap5_common.h b/include/configs/ti_omap5_common.h similarity index 95% rename from include/configs/omap5_common.h rename to include/configs/ti_omap5_common.h index c7fa37e823..7b10fbd28a 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -14,8 +14,8 @@ * http://www.ti.com/product/omap5432 */ -#ifndef __CONFIG_OMAP5_COMMON_H -#define __CONFIG_OMAP5_COMMON_H +#ifndef __CONFIG_TI_OMAP5_COMMON_H +#define __CONFIG_TI_OMAP5_COMMON_H #define CONFIG_OMAP54XX #define CONFIG_DISPLAY_CPUINFO @@ -146,4 +146,8 @@ #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#endif /* __CONFIG_OMAP5_COMMON_H */ +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + +#endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 48fcb24c4f..162826f7d3 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include #include diff --git a/include/configs/trats.h b/include/configs/trats.h index fdd8b460b0..5d8bd60583 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -7,25 +7,19 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_TRATS_H +#define __CONFIG_TRATS_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* which is in a S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ -#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */ -#define CONFIG_TRATS /* working with TRATS */ -#define CONFIG_TIZEN /* TIZEN lib */ +#include -#include /* get chip and board defs */ +#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TRATS + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats + +#define CONFIG_TIZEN /* TIZEN lib */ #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF @@ -33,129 +27,100 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_TEXT_BASE 0x63300000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + #define CONFIG_SYS_TEXT_BASE 0x63300000 -/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 +#include +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +/* select serial console configuration */ +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* MACH_TYPE_TRATS macro will be removed once added to mach-types */ #define MACH_TYPE_TRATS 3928 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - -/* select serial console configuration */ -#define CONFIG_SERIAL2 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA - -/* PWM */ -#define CONFIG_PWM - -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH - -/* Command definition */ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_SETEXPR - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_BOOTBLOCK "10" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" -#define PARTS_BOOTLOADER "u-boot" #define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" #define PARTS_ROOT "platform" #define PARTS_DATA "data" -#define PARTS_CSC "csc" #define PARTS_UMS "ums" #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOTLOADER",size=60MiB," \ - "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ - "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ "u-boot mmc 80 400;" \ "uImage ext4 0 2;" \ + "modem.bin ext4 0 2;" \ "exynos4210-trats.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -178,7 +143,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ @@ -217,61 +182,18 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4210-trats.dtb\0" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "TRATS # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* TRATS has 4 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE /* Falcon mode definitions */ #define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100 +#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 /* GPT */ -#define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS +#define CONFIG_RANDOM_UUID -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CACHELINE_SIZE 32 +/* I2C */ +#include + +#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 @@ -284,12 +206,11 @@ #define CONFIG_SOFT_I2C_READ_REPEATED_START #define CONFIG_SYS_I2C_INIT_BOARD -#include - /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) +/* POWER */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8997 @@ -300,27 +221,50 @@ #define CONFIG_POWER_MUIC_MAX8997 #define CONFIG_POWER_BATTERY #define CONFIG_POWER_BATTERY_TRATS -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_USB_CABLE_CHECK + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" +#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 0) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 +#define LCD_XRES 720 +#define LCD_YRES 1280 #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 83633b074d..53d449c291 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -8,27 +8,17 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_TRATS2_H +#define __CONFIG_TRATS2_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* which is in a S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ -#define CONFIG_TIZEN /* TIZEN lib */ +#include -#include /* get chip and board defs */ +#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_TIZEN /* TIZEN lib */ #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF @@ -36,126 +26,55 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_END 0x80000000 +/* TRATS2 has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ +#define CONFIG_SYS_TEXT_BASE 0x43e00000 -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_TEXT_BASE 0x78100000 - -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG - -/* MACH_TYPE_TRATS2 */ -#define MACH_TYPE_TRATS2 3765 -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2 - -#define CONFIG_DISPLAY_CPUINFO - -#include +#include /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ #define CONFIG_SERIAL2 - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_CMDLINE_EDITING - #define CONFIG_BAUDRATE 115200 -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH - -/*********************************************************** - * Command definition - ***********************************************************/ -#include - -#undef CONFIG_CMD_ECHO -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NAND -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */ -#undef CONFIG_CMD_NET - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA -#define CONFIG_MMC_DEFAULT_DEV 0 - -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -#define CONFIG_ENV_OVERWRITE +/* Console configuration */ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ -#define PARTS_CSA "csa" +#define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" -#define PARTS_MODEM "modem" +#define PARTS_QBOOT "qboot" #define PARTS_CSC "csc" #define PARTS_ROOT "platform" #define PARTS_DATA "data" @@ -164,25 +83,34 @@ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ "u-boot mmc 80 800;" \ "uImage ext4 0 2;" \ + "modem.bin ext4 0 2;" \ "exynos4412-trats2.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -196,7 +124,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "verify=n\0" \ @@ -237,52 +165,15 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4412-trats2.dtb\0" -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ -#define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS - -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F +/* GPT */ +#define CONFIG_RANDOM_UUID /* I2C */ #include +#define CONFIG_CMD_I2C + #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 @@ -312,27 +203,50 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_POWER_MUIC_MAX77693 #define CONFIG_POWER_FG_MAX77693 #define CONFIG_POWER_BATTERY_TRATS2 -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_USB_CABLE_CHECK + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 1) + +#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) +#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 +#define LCD_XRES 720 +#define LCD_YRES 1280 #endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index cc4001fcd1..80985a2655 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -63,6 +63,9 @@ /* GPIO support */ #define CONFIG_OMAP_GPIO +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ + /* LED support */ #define CONFIG_STATUS_LED #define CONFIG_BOARD_SPECIFIC_LED @@ -134,8 +137,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_BCH @@ -367,11 +368,12 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ - 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\ - 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\ - 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 8e03f6f4c4..f81cfa2e35 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" /* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h new file mode 100644 index 0000000000..8fb87ac441 --- /dev/null +++ b/include/configs/tseries.h @@ -0,0 +1,265 @@ +/* + * tseries.h + * + * specific parts for B&R T-Series Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TSERIES_H__ +#define __CONFIG_TSERIES_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMD_BOOTZ +/*#define CONFIG_MACH_TYPE 3589*/ +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ + +/* MMC/SD IP block */ +#if defined(CONFIG_EMMC_BOOT) + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_OMAP_HSMMC + #define CONFIG_CMD_MMC + #define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + #define CONFIG_SPL_MMC_SUPPORT +#endif /* CONFIG_EMMC_BOOT */ + +/* + * When we have SPI or NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to + * the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif /* CONFIG_SPI_BOOT, ... */ + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* CONFIG_NAND */ +#endif /* CONFIG_SPL_OS_BOOT */ + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif /* CONFIG_NAND */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandimgsize=0x500000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel ${nandimgsize}; " \ + "bootz ${loadaddr}\0" +#else +#define NANDARGS "" +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_MMC +#define MMCARGS \ + "silent=1\0" +#else +#define MMCARGS "" +#endif /* CONFIG_MMC */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80200000\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "rootpath=/tftpboot/tseries/rootfs-small\0" \ + "nfsopts=nolock\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" \ + NANDARGS \ + MMCARGS +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot1;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +#ifdef CONFIG_NAND +/* + * GPMC block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_CMD_NAND +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3)," \ + "512k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env)," \ + "5m(kernel),"\ + "-(rootfs)" +#endif /* CONFIG_NAND */ + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#if defined(CONFIG_SPI_BOOT) +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ + +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#elif defined(CONFIG_NAND) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */ +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE +#else +#error "no storage for Environment defined!" +#endif +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 629299d107..8d7970a376 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -29,7 +29,6 @@ #define CONFIG_ENV_SIZE (128*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) #endif -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ /* * PL011 Configuration diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 614e1fe3b5..a0306de6a3 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -12,7 +12,7 @@ #include "mx6_common.h" #include #include -#include +#include #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO @@ -100,7 +100,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc1\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -132,22 +132,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -159,19 +159,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -179,7 +179,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -199,7 +199,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index c4d04dec38..3c54870783 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -20,7 +20,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_HZ 1000 #define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 8e6e246460..5be62ecb2d 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -30,7 +30,6 @@ * (easy to change) */ -#define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_UTX8245 1 diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 0c544350eb..7f6b0c7cb2 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -12,7 +12,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_V38B 1 /* ...on V38B board */ diff --git a/include/configs/vct.h b/include/configs/vct.h index 99831169a3..5ab4de3274 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,7 +25,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */ #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 5cf4ae5be8..00787bbb28 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_VE8313 1 diff --git a/include/configs/venice2.h b/include/configs/venice2.h new file mode 100644 index 0000000000..2d75f5013f --- /dev/null +++ b/include/configs/venice2.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Venice2) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 5c02c968f9..edf3720b61 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 10738ac24b..29c32fee51 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -101,7 +101,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0" + "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ + "console=ttyAMA0,38400n1" /* * Static configuration when assigning fixed address diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index e8517027e7..dff6adcc7c 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -12,6 +12,8 @@ #define CONFIG_REMAKE_ELF +#define CONFIG_GICV3 + /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ /*#define CONFIG_SYS_GENERIC_BOARD*/ @@ -93,8 +95,13 @@ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ /* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV3 +#define GICD_BASE (0x2f000000) +#define GICR_BASE (0x2f100000) +#else #define GICD_BASE (0x2C001000) #define GICC_BASE (0x2C002000) +#endif #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 8d0a00dcd9..500fd2fd61 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -81,7 +81,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyLP1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -112,22 +112,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -139,19 +139,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -159,7 +159,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 88aaa95fb1..14c6e675c1 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -322,7 +322,6 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ @@ -363,7 +362,6 @@ */ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ #ifndef CONFIG_RAMLOAD #define CONFIG_BOOTCOMMAND "run nfsboot" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 7ecbafe2e5..175311cad9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -29,7 +29,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index a5691825ee..8b803a2ee0 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...or on a SYCAMORE board */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 348847238e..6c74c72952 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -12,7 +12,7 @@ #include "mx6_common.h" #include #include -#include +#include #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/whistler.h b/include/configs/whistler.h index d5c7e3bbd6..9e09f03d52 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" /* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */ diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index 10e1d170ba..437472f3ed 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -17,8 +17,6 @@ /* Set TEXT in RAM */ #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_BOOT_INTERNAL - /* * SPL */ diff --git a/include/configs/x600.h b/include/configs/x600.h index 39540e3806..7405419f0e 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -74,10 +74,9 @@ /* Ethernet config options */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ @@ -86,6 +85,7 @@ /* I2C config options */ #define CONFIG_HARD_I2C #define CONFIG_DW_I2C +#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 @@ -171,7 +171,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_64BIT_VSPRINTF /* Use last 2 lwords in internal SRAM for bootcounter */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 022bc95927..8e6b365364 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -55,7 +55,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h index 2ec3dd18dd..f45700878e 100644 --- a/include/configs/xilinx-ppc440.h +++ b/include/configs/xilinx-ppc440.h @@ -9,7 +9,6 @@ #define __CONFIG_GEN_H /*CPU*/ -#define CONFIG_4xx 1 #define CONFIG_440 1 #define CONFIG_XILINX_440 1 diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index eb193f8673..ca322b2e82 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -18,7 +18,6 @@ #define CONFIG_XPEDITE1000 1 #define CONFIG_SYS_BOARD_NAME "XPedite1000" #define CONFIG_SYS_FORM_PMC 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 88d7f88cc0..cbf4b8e0f7 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index f39d6f9105..baa30395aa 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index e1bdf90de4..bdf55763d5 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8572 1 #define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 2328c7a62e..0b24f3e8d7 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_P2020 1 #define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 2dd742e327..8508a8029e 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -23,7 +23,6 @@ #define CONFIG_HOSTNAME yellowstone #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 5d584fbad4..76717e4579 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -18,7 +18,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index d8aeb3794e..4d7a7fc755 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -15,7 +15,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ZEUS 1 /* Board is Zeus */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EP 1 /* Specifc 405EP support*/ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index e38fa89fda..41a7c99edc 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -138,7 +138,6 @@ unsigned char zipitz2_spi_read(void); * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index c028509a59..00f08aee0c 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -30,14 +30,14 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -#define CONFIG_ZYNQ_SERIAL -#endif - /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) # define CONFIG_ARM_DCC # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#else +# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +# endif #endif /* Ethernet driver */ @@ -295,6 +295,8 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP +#define CONFIG_CLOCKS +#define CONFIG_CMD_CLK #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -349,6 +351,7 @@ # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif +/* Commands */ #include #ifdef CONFIG_SYS_ENET @@ -361,9 +364,6 @@ # undef CONFIG_CMD_NFS #endif -#define CONFIG_CLOCKS -#define CONFIG_CMD_CLK - #if defined(CONFIG_CMD_ZYNQ_RSA) #define CONFIG_RSA #define CONFIG_SHA256 @@ -457,6 +457,7 @@ /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ #define CONFIG_SPL_MAX_FOOTPRINT 0x30000 +#define CONFIG_SPL_MAX_SIZE 0x30000 /* The highest 64k OCM address */ #define OCM_HIGH_ADDR 0xffff0000 @@ -472,7 +473,10 @@ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000 -/* These two can't be more than 0xffffff2c */ -/* CONFIG_SYS_SPL_MALLOC_START + CONFIG_SYS_SPL_MALLOC_SIZE */ +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/cpsw.h b/include/cpsw.h index 743cb96e7e..a73843d2f7 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -19,7 +19,7 @@ struct cpsw_slave_data { u32 slave_reg_ofs; u32 sliver_reg_ofs; - int phy_id; + int phy_addr; int phy_if; }; diff --git a/include/cramfs/cramfs_fs_sb.h b/include/cramfs/cramfs_fs_sb.h deleted file mode 100644 index bc23f94b94..0000000000 --- a/include/cramfs/cramfs_fs_sb.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _CRAMFS_FS_SB -#define _CRAMFS_FS_SB - -/* - * cramfs super-block data in memory - */ -struct cramfs_sb_info { - unsigned long magic; - unsigned long size; - unsigned long blocks; - unsigned long files; - unsigned long flags; -#ifdef CONFIG_CRAMFS_LINEAR - unsigned long linear_phys_addr; - char * linear_virt_addr; -#endif -}; - -#endif diff --git a/include/cros_ec.h b/include/cros_ec.h index 1e89f29eea..1e4d8db96b 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -20,6 +20,7 @@ enum cros_ec_interface_t { CROS_EC_IF_SPI, CROS_EC_IF_I2C, CROS_EC_IF_LPC, /* Intel Low Pin Count interface */ + CROS_EC_IF_SANDBOX, }; /* Our configuration information */ @@ -33,7 +34,7 @@ struct cros_ec_dev { unsigned int bus_num; /* Bus number (for I2C) */ unsigned int max_frequency; /* Maximum interface frequency */ struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */ - int cmd_version_is_supported; /* Device supports command versions */ + int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ /* @@ -63,6 +64,17 @@ struct mbkp_keyscan { uint8_t data[CROS_EC_KEYSCAN_COLS]; }; +/* Holds information about the Chrome EC */ +struct fdt_cros_ec { + struct fmap_entry flash; /* Address and size of EC flash */ + /* + * Byte value of erased flash, or -1 if not known. It is normally + * 0xff but some flash devices use 0 (e.g. STM32Lxxx) + */ + int flash_erase_value; + struct fmap_entry region[EC_FLASH_REGION_COUNT]; +}; + /** * Read the ID of the CROS-EC device * @@ -140,7 +152,7 @@ enum { }; /** - * Set up the Chromium OS matrix keyboard protocol + * Initialise the Chromium OS EC driver * * @param blob Device tree blob containing setup information * @param cros_ecp Returns pointer to the cros_ec device, or NULL if none @@ -157,7 +169,7 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp); * @param info Place to put the info structure */ int cros_ec_info(struct cros_ec_dev *dev, - struct ec_response_cros_ec_info *info); + struct ec_response_mkbp_info *info); /** * Read the host event flags @@ -226,6 +238,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void); int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob); int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob); int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob); +int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob); /** * Read information from the fdt for the i2c cros_ec interface @@ -245,12 +258,20 @@ int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob); */ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob); +/** + * Read information from the fdt for the sandbox cros_ec interface + * + * @param dev CROS-EC device + * @param blob Device tree blob + * @return 0 if ok, -1 if we failed to read all required information + */ +int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob); + /** * Check whether the LPC interface supports new-style commands. * * LPC has its own way of doing this, which involves checking LPC values - * visible to the host. Do this, and update dev->cmd_version_is_supported - * accordingly. + * visible to the host. Do this, and update dev->protocol_version accordingly. * * @param dev CROS-EC device to check */ @@ -301,6 +322,21 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len); +/** + * Send a packet to a CROS-EC device and return the response packet. + * + * Expects the request packet to be stored in dev->dout. Stores the response + * packet in dev->din. + * + * @param dev CROS-EC device + * @param out_bytes Size of request packet to output + * @param in_bytes Maximum size of response packet to receive + * @return number of bytes in response packet, or <0 on error + */ +int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); +int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, + int in_bytes); + /** * Dump a block of data for a command. * @@ -431,4 +467,52 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state); * @return 0 if ok, -1 on error */ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state); + +/** + * Initialize the Chrome OS EC at board initialization time. + * + * @return 0 if ok, -ve on error + */ +int cros_ec_board_init(void); + +/** + * Get access to the error reported when cros_ec_board_init() was called + * + * This permits delayed reporting of the EC error if it failed during + * early init. + * + * @return error (0 if there was no error, -ve if there was an error) + */ +int cros_ec_get_error(void); + +/** + * Returns information from the FDT about the Chrome EC flash + * + * @param blob FDT blob to use + * @param config Structure to use to return information + */ +int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config); + +/** + * Check the current keyboard state, in case recovery mode is requested. + * This function is for sandbox only. + * + * @param ec CROS-EC device + */ +void cros_ec_check_keyboard(struct cros_ec_dev *dev); + +/* + * Tunnel an I2C transfer to the EC + * + * @param dev CROS-EC device + * @param chip Chip address (7-bit I2C address) + * @param addr Register address to read/write + * @param alen Length of register address in bytes + * @param buffer Buffer containing data to read/write + * @param len Length of buffer + * @param is_read 1 if this is a read, 0 if this is a write + */ +int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read); + #endif diff --git a/include/cros_ec_message.h b/include/cros_ec_message.h index b1da53db1b..36e2d83ce1 100644 --- a/include/cros_ec_message.h +++ b/include/cros_ec_message.h @@ -23,7 +23,7 @@ enum { MSG_PROTO_BYTES = MSG_HEADER_BYTES + MSG_TRAILER_BYTES, /* Max length of messages */ - MSG_BYTES = EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES, + MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES, }; #endif diff --git a/include/da9030.h b/include/da9030.h deleted file mode 100644 index 275d6813b0..0000000000 --- a/include/da9030.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2006 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* DA9030 register definitions */ -#define CID 0x00 -#define EVENT_A 0x01 -#define EVENT_B 0x02 -#define EVENT_C 0x03 -#define STATUS 0x04 -#define IRQ_MASK_A 0x05 -#define IRQ_MASK_B 0x06 -#define IRQ_MASK_C 0x07 -#define SYS_CONTROL_A 0x08 -#define SYS_CONTROL_B 0x09 -#define FAULT_LOG 0x0A -#define LDO_10_11 0x10 -#define LDO_15 0x11 -#define LDO_14_16 0x12 -#define LDO_18_19 0x13 -#define LDO_17_SIMCP0 0x14 -#define BUCK2_DVC1 0x15 -#define BUCK2_DVC2 0x16 -#define REG_CONTROL_1_17 0x17 -#define REG_CONTROL_2_18 0x18 -#define USBPUMP 0x19 -#define SLEEP_CONTROL 0x1A -#define STARTUP_CONTROL 0x1B -#define LED1_CONTROL 0x20 -#define LED2_CONTROL 0x21 -#define LED3_CONTROL 0x22 -#define LED4_CONTROL 0x23 -#define LEDPC_CONTROL 0x24 -#define WLED_CONTROL 0x25 -#define MISC_CONTROLA 0x26 -#define MISC_CONTROLB 0x27 -#define CHARGE_CONTROL 0x28 -#define CCTR_CONTROL 0x29 -#define TCTR_CONTROL 0x2A -#define CHARGE_PULSE 0x2B - -/* ... some missing ...*/ - -#define LDO1 0x90 -#define LDO2_3 0x91 -#define LDO4_5 0x92 -#define LDO6_SIMCP 0x93 -#define LDO7_8 0x94 -#define LDO9_12 0x95 -#define BUCK 0x96 -#define REG_CONTROL_1_97 0x97 -#define REG_CONTROL_2_98 0x98 -#define REG_SLEEP_CONTROL1 0x99 -#define REG_SLEEP_CONTROL2 0x9A -#define REG_SLEEP_CONTROL3 0x9B -#define ADC_MAN_CONTROL 0xA0 -#define ADC_AUTO_CONTROL 0xA1 -#define VBATMON 0xA2 -#define VBATMONTXMON 0xA3 -#define TBATHIGHP 0xA4 -#define TBATHIGHN 0xA5 -#define TBATLOW 0xA6 -#define MAN_RES 0xB0 -#define VBAT_RES 0xB1 -#define VBATMIN_RES 0xB2 -#define VBATMINTXON_RES 0xB3 -#define ICHMAX_RES 0xB4 -#define ICHMIN_RES 0xB5 -#define ICHAVERAGE_RES 0xB6 -#define VCHMAX_RES 0xB7 -#define VCHMIN_RES 0xB8 -#define TBAT_RES 0xB9 -#define ADC_IN4_RES 0xBA - -#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */ -#define STATUS_PWREN1 (1<<1) /* PWREN1 value */ -#define STATUS_EXTON (1<<2) /* EXTON value */ -#define STATUS_CHDET (1<<3) /* Charger detection status */ -#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */ -#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */ -#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */ -#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */ - -#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1 -#define SYS_CONTROL_A_SHUT_DOWN (1<<1) -#define SYS_CONTROL_A_HWRES_ENABLE (1<<2) -#define SYS_CONTROL_A_WDOG_ACTION (1<<3) -#define SYS_CONTROL_A_WATCHDOG (1<<7) - -#define MISC_CONTROLB_USB_INT_RISING (1<<2) -#define MISC_CONTROLB_SESSION_VALID_EN (1<<3) - -#define USB_PUMP_USBVE (1<<0) -#define USB_PUMP_USBVEP (1<<1) -#define USB_PUMP_SRP_DETECT (1<<2) -#define USB_PUMP_SESSION_VALID (1<<3) -#define USB_PUMP_VBUS_VALID_4_0 (1<<4) -#define USB_PUMP_VBUS_VALID_4_4 (1<<5) -#define USB_PUMP_EN_USBVE (1<<6) -#define USB_PUMP_EN_USBVEP (1<<7) diff --git a/include/dfu.h b/include/dfu.h index f973426aa9..6c71ecbe35 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -80,6 +80,9 @@ static inline unsigned int get_mmc_blk_size(int dev) #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif +#ifndef DFU_MANIFEST_POLL_TIMEOUT +#define DFU_MANIFEST_POLL_TIMEOUT DFU_DEFAULT_POLL_TIMEOUT +#endif struct dfu_entity { char name[DFU_NAME_SIZE]; @@ -138,6 +141,7 @@ unsigned long dfu_get_buf_size(void); int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num); int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num); +int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num); /* Device specific */ #ifdef CONFIG_DFU_MMC extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s); diff --git a/include/dm-demo.h b/include/dm-demo.h new file mode 100644 index 0000000000..6e38d3c5b3 --- /dev/null +++ b/include/dm-demo.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_DEMO_H +#define __DM_DEMO_H + +#include + +/** + * struct dm_demo_pdata - configuration data for demo instance + * + * @colour: Color of the demo + * @sides: Numbers of sides + * @default_char: Default ASCII character to output (65 = 'A') + */ +struct dm_demo_pdata { + const char *colour; + int sides; + int default_char; +}; + +struct demo_ops { + int (*hello)(struct device *dev, int ch); + int (*status)(struct device *dev, int *status); +}; + +int demo_hello(struct device *dev, int ch); +int demo_status(struct device *dev, int *status); +int demo_list(void); + +int demo_parse_dt(struct device *dev); + +#endif diff --git a/include/dm.h b/include/dm.h new file mode 100644 index 0000000000..8bbb21b575 --- /dev/null +++ b/include/dm.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_H_ +#define _DM_H + +#include +#include +#include + +#endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h new file mode 100644 index 0000000000..c026e8e49c --- /dev/null +++ b/include/dm/device-internal.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_DEVICE_INTERNAL_H +#define _DM_DEVICE_INTERNAL_H + +struct device; + +/** + * device_bind() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver. The device will either + * have platdata, or a device tree node which can be used to create the + * platdata. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @platdata: Pointer to data for this device - the structure is device- + * specific but may include the device's I/O address, etc.. This is NULL for + * devices which use device tree. + * @of_offset: Offset of device tree node for this device. This is -1 for + * devices which don't use device tree. + * @devp: Returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind(struct device *parent, struct driver *drv, + const char *name, void *platdata, int of_offset, + struct device **devp); + +/** + * device_bind_by_name: Create a device and bind it to a driver + * + * This is a helper function used to bind devices which do not use device + * tree. + * + * @parent: Pointer to device's parent + * @info: Name and platdata for this device + * @devp: Returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_by_name(struct device *parent, const struct driver_info *info, + struct device **devp); + +/** + * device_probe() - Probe a device, activating it + * + * Activate a device so that it is ready for use. All its parents are probed + * first. + * + * @dev: Pointer to device to probe + * @return 0 if OK, -ve on error + */ +int device_probe(struct device *dev); + +/** + * device_remove() - Remove a device, de-activating it + * + * De-activate a device so that it is no longer ready for use. All its + * children are deactivated first. + * + * @dev: Pointer to device to remove + * @return 0 if OK, -ve on error (an error here is normally a very bad thing) + */ +int device_remove(struct device *dev); + +/** + * device_unbind() - Unbind a device, destroying it + * + * Unbind a device and remove all memory used by it + * + * @dev: Pointer to device to unbind + * @return 0 if OK, -ve on error + */ +int device_unbind(struct device *dev); + +#endif diff --git a/include/dm/device.h b/include/dm/device.h new file mode 100644 index 0000000000..4cd38ed2d0 --- /dev/null +++ b/include/dm/device.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_DEVICE_H +#define _DM_DEVICE_H + +#include +#include +#include + +struct driver_info; + +/* Driver is active (probed). Cleared when it is removed */ +#define DM_FLAG_ACTIVATED (1 << 0) + +/* DM is responsible for allocating and freeing platdata */ +#define DM_FLAG_ALLOC_PDATA (2 << 0) + +/** + * struct device - An instance of a driver + * + * This holds information about a device, which is a driver bound to a + * particular port or peripheral (essentially a driver instance). + * + * A device will come into existence through a 'bind' call, either due to + * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node + * in the device tree (in which case of_offset is >= 0). In the latter case + * we translate the device tree information into platdata in a function + * implemented by the driver ofdata_to_platdata method (called just before the + * probe method if the device has a device tree node. + * + * All three of platdata, priv and uclass_priv can be allocated by the + * driver, or you can use the auto_alloc_size members of struct driver and + * struct uclass_driver to have driver model do this automatically. + * + * @driver: The driver used by this device + * @name: Name of device, typically the FDT node name + * @platdata: Configuration data for this device + * @of_offset: Device tree node offset for this device (- for none) + * @parent: Parent of this device, or NULL for the top level device + * @priv: Private data for this device + * @uclass: Pointer to uclass for this device + * @uclass_priv: The uclass's private data for this device + * @uclass_node: Used by uclass to link its devices + * @child_head: List of children of this device + * @sibling_node: Next device in list of all devices + * @flags: Flags for this device DM_FLAG_... + */ +struct device { + struct driver *driver; + const char *name; + void *platdata; + int of_offset; + struct device *parent; + void *priv; + struct uclass *uclass; + void *uclass_priv; + struct list_head uclass_node; + struct list_head child_head; + struct list_head sibling_node; + uint32_t flags; +}; + +/* Returns the operations for a device */ +#define device_get_ops(dev) (dev->driver->ops) + +/* Returns non-zero if the device is active (probed and not removed) */ +#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED) + +/** + * struct device_id - Lists the compatible strings supported by a driver + * @compatible: Compatible string + * @data: Data for this compatible string + */ +struct device_id { + const char *compatible; + ulong data; +}; + +/** + * struct driver - A driver for a feature or peripheral + * + * This holds methods for setting up a new device, and also removing it. + * The device needs information to set itself up - this is provided either + * by platdata or a device tree node (which we find by looking up + * matching compatible strings with of_match). + * + * Drivers all belong to a uclass, representing a class of devices of the + * same type. Common elements of the drivers can be implemented in the uclass, + * or the uclass can provide a consistent interface to the drivers within + * it. + * + * @name: Device name + * @id: Identiies the uclass we belong to + * @of_match: List of compatible strings to match, and any identifying data + * for each. + * @bind: Called to bind a device to its driver + * @probe: Called to probe a device, i.e. activate it + * @remove: Called to remove a device, i.e. de-activate it + * @unbind: Called to unbind a device from its driver + * @ofdata_to_platdata: Called before probe to decode device tree data + * @priv_auto_alloc_size: If non-zero this is the size of the private data + * to be allocated in the device's ->priv pointer. If zero, then the driver + * is responsible for allocating any data required. + * @platdata_auto_alloc_size: If non-zero this is the size of the + * platform data to be allocated in the device's ->platdata pointer. + * This is typically only useful for device-tree-aware drivers (those with + * an of_match), since drivers which use platdata will have the data + * provided in the U_BOOT_DEVICE() instantiation. + * ops: Driver-specific operations. This is typically a list of function + * pointers defined by the driver, to implement driver functions required by + * the uclass. + */ +struct driver { + char *name; + enum uclass_id id; + const struct device_id *of_match; + int (*bind)(struct device *dev); + int (*probe)(struct device *dev); + int (*remove)(struct device *dev); + int (*unbind)(struct device *dev); + int (*ofdata_to_platdata)(struct device *dev); + int priv_auto_alloc_size; + int platdata_auto_alloc_size; + const void *ops; /* driver-specific operations */ +}; + +/* Declare a new U-Boot driver */ +#define U_BOOT_DRIVER(__name) \ + ll_entry_declare(struct driver, __name, driver) + +/** + * dev_get_platdata() - Get the platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return platform data, or NULL if none + */ +void *dev_get_platdata(struct device *dev); + +/** + * dev_get_priv() - Get the private data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return private data, or NULL if none + */ +void *dev_get_priv(struct device *dev); + +#endif diff --git a/include/dm/lists.h b/include/dm/lists.h new file mode 100644 index 0000000000..0d09f9a14f --- /dev/null +++ b/include/dm/lists.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_LISTS_H_ +#define _DM_LISTS_H_ + +#include + +/** + * lists_driver_lookup_name() - Return u_boot_driver corresponding to name + * + * This function returns a pointer to a driver given its name. This is used + * for binding a driver given its name and platdata. + * + * @name: Name of driver to look up + * @return pointer to driver, or NULL if not found + */ +struct driver *lists_driver_lookup_name(const char *name); + +/** + * lists_uclass_lookup() - Return uclass_driver based on ID of the class + * id: ID of the class + * + * This function returns the pointer to uclass_driver, which is the class's + * base structure based on the ID of the class. Returns NULL on error. + */ +struct uclass_driver *lists_uclass_lookup(enum uclass_id id); + +int lists_bind_drivers(struct device *parent); + +int lists_bind_fdt(struct device *parent, const void *blob, int offset); + +#endif diff --git a/include/dm/platdata.h b/include/dm/platdata.h new file mode 100644 index 0000000000..0ef3353e74 --- /dev/null +++ b/include/dm/platdata.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_PLATDATA_H +#define _DM_PLATDATA_H + +struct driver_info { + const char *name; + const void *platdata; +}; + +#define U_BOOT_DEVICE(__name) \ + ll_entry_declare(struct driver_info, __name, driver_info) + +#endif diff --git a/include/dm/root.h b/include/dm/root.h new file mode 100644 index 0000000000..0ebccda355 --- /dev/null +++ b/include/dm/root.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_ROOT_H_ +#define _DM_ROOT_H_ + +struct device; + +/** + * dm_root() - Return pointer to the top of the driver tree + * + * This function returns pointer to the root node of the driver tree, + * + * @return pointer to root device, or NULL if not inited yet + */ +struct device *dm_root(void); + +/** + * dm_scan_platdata() - Scan all platform data and bind drivers + * + * This scans all available platdata and creates drivers for each + * + * @return 0 if OK, -ve on error + */ +int dm_scan_platdata(void); + +/** + * dm_scan_fdt() - Scan the device tree and bind drivers + * + * This scans the device tree and creates a driver for each node + * + * @blob: Pointer to device tree blob + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt(const void *blob); + +/** + * dm_init() - Initialize Driver Model structures + * + * This function will initialize roots of driver tree and class tree. + * This needs to be called before anything uses the DM + * + * @return 0 if OK, -ve on error + */ +int dm_init(void); + +#endif diff --git a/include/dm/test.h b/include/dm/test.h new file mode 100644 index 0000000000..eeaa2eb2f4 --- /dev/null +++ b/include/dm/test.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2013 Google, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_TEST_H +#define __DM_TEST_H + +#include + +/** + * struct dm_test_cdata - configuration data for test instance + * + * @ping_add: Amonut to add each time we get a ping + * @base: Base address of this device + */ +struct dm_test_pdata { + int ping_add; + uint32_t base; +}; + +/** + * struct test_ops - Operations supported by the test device + * + * @ping: Ping operation + * @dev: Device to operate on + * @pingval: Value to ping the device with + * @pingret: Returns resulting value from driver + * @return 0 if OK, -ve on error + */ +struct test_ops { + int (*ping)(struct device *dev, int pingval, int *pingret); +}; + +/* Operations that our test driver supports */ +enum { + DM_TEST_OP_BIND = 0, + DM_TEST_OP_UNBIND, + DM_TEST_OP_PROBE, + DM_TEST_OP_REMOVE, + + /* For uclass */ + DM_TEST_OP_POST_BIND, + DM_TEST_OP_PRE_UNBIND, + DM_TEST_OP_POST_PROBE, + DM_TEST_OP_PRE_REMOVE, + DM_TEST_OP_INIT, + DM_TEST_OP_DESTROY, + + DM_TEST_OP_COUNT, +}; + +/* Test driver types */ +enum { + DM_TEST_TYPE_FIRST = 0, + DM_TEST_TYPE_SECOND, +}; + +/* The number added to the ping total on each probe */ +#define DM_TEST_START_TOTAL 5 + +/** + * struct dm_test_priv - private data for the test devices + */ +struct dm_test_priv { + int ping_total; + int op_count[DM_TEST_OP_COUNT]; +}; + +/** + * struct dm_test_perdev_class_priv - private per-device data for test uclass + */ +struct dm_test_uclass_perdev_priv { + int base_add; +}; + +/** + * struct dm_test_uclass_priv - private data for test uclass + */ +struct dm_test_uclass_priv { + int total_add; +}; + +/* + * Operation counts for the test driver, used to check that each method is + * called correctly + */ +extern int dm_testdrv_op_count[DM_TEST_OP_COUNT]; + +extern struct dm_test_state global_test_state; + +/* + * struct dm_test_state - Entire state of dm test system + * + * This is often abreviated to dms. + * + * @root: Root device + * @testdev: Test device + * @fail_count: Number of tests that failed + * @force_fail_alloc: Force all memory allocs to fail + * @skip_post_probe: Skip uclass post-probe processing + */ +struct dm_test_state { + struct device *root; + struct device *testdev; + int fail_count; + int force_fail_alloc; + int skip_post_probe; +}; + +/* Test flags for each test */ +enum { + DM_TESTF_SCAN_PDATA = 1 << 0, /* test needs platform data */ + DM_TESTF_PROBE_TEST = 1 << 1, /* probe test uclass */ + DM_TESTF_SCAN_FDT = 1 << 2, /* scan device tree */ +}; + +/** + * struct dm_test - Information about a driver model test + * + * @name: Name of test + * @func: Function to call to perform test + * @flags: Flags indicated pre-conditions for test + */ +struct dm_test { + const char *name; + int (*func)(struct dm_test_state *dms); + int flags; +}; + +/* Declare a new driver model test */ +#define DM_TEST(_name, _flags) \ + ll_entry_declare(struct dm_test, _name, dm_test) = { \ + .name = #_name, \ + .flags = _flags, \ + .func = _name, \ + } + +/* Declare ping methods for the drivers */ +int test_ping(struct device *dev, int pingval, int *pingret); +int testfdt_ping(struct device *dev, int pingval, int *pingret); + +/** + * dm_check_operations() - Check that we can perform ping operations + * + * This checks that the ping operations work as expected for a device + * + * @dms: Overall test state + * @dev: Device to test + * @base: Base address, used to check ping return value + * @priv: Pointer to private test information + * @return 0 if OK, -ve on error + */ +int dm_check_operations(struct dm_test_state *dms, struct device *dev, + uint32_t base, struct dm_test_priv *priv); + +/** + * dm_test_main() - Run all the tests + * + * This runs all available driver model tests + * + * @return 0 if OK, -ve on error + */ +int dm_test_main(void); + +#endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h new file mode 100644 index 0000000000..f0e691c18c --- /dev/null +++ b/include/dm/uclass-id.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_ID_H +#define _DM_UCLASS_ID_H + +/* TODO(sjg@chromium.org): this could be compile-time generated */ +enum uclass_id { + /* These are used internally by driver model */ + UCLASS_ROOT = 0, + UCLASS_DEMO, + UCLASS_TEST, + UCLASS_TEST_FDT, + + /* U-Boot uclasses start here */ + UCLASS_GPIO, + + UCLASS_COUNT, + UCLASS_INVALID = -1, +}; + +#endif diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h new file mode 100644 index 0000000000..cc65d5259f --- /dev/null +++ b/include/dm/uclass-internal.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_INTERNAL_H +#define _DM_UCLASS_INTERNAL_H + +/** + * uclass_find_device() - Return n-th child of uclass + * @id: Id number of the uclass + * @index: Position of the child in uclass's list + * #devp: Returns pointer to device, or NULL on error + * + * The device is not prepared for use - this is an internal function + * + * @return the uclass pointer of a child at the given index or + * return NULL on error. + */ +int uclass_find_device(enum uclass_id id, int index, struct device **devp); + +/** + * uclass_bind_device() - Associate device with a uclass + * + * Connect the device into uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_bind_device(struct device *dev); + +/** + * uclass_unbind_device() - Deassociate device with a uclass + * + * Disconnect the device from uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_unbind_device(struct device *dev); + +/** + * uclass_post_probe_device() - Deal with a device that has just been probed + * + * Perform any post-processing of a probed device that is needed by the + * uclass. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_post_probe_device(struct device *dev); + +/** + * uclass_pre_remove_device() - Handle a device which is about to be removed + * + * Perform any pre-processing of a device that is about to be removed. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_pre_remove_device(struct device *dev); + +/** + * uclass_find() - Find uclass by its id + * + * @id: Id to serach for + * @return pointer to uclass, or NULL if not found + */ +struct uclass *uclass_find(enum uclass_id key); + +/** + * uclass_destroy() - Destroy a uclass + * + * Destroy a uclass and all its devices + * + * @uc: uclass to destroy + * @return 0 on success, -ve on error + */ +int uclass_destroy(struct uclass *uc); + +#endif diff --git a/include/dm/uclass.h b/include/dm/uclass.h new file mode 100644 index 0000000000..cd23cfed16 --- /dev/null +++ b/include/dm/uclass.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_H +#define _DM_UCLASS_H + +#include +#include + +/** + * struct uclass - a U-Boot drive class, collecting together similar drivers + * + * A uclass provides an interface to a particular function, which is + * implemented by one or more drivers. Every driver belongs to a uclass even + * if it is the only driver in that uclass. An example uclass is GPIO, which + * provides the ability to change read inputs, set and clear outputs, etc. + * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and + * PMIC IO lines, all made available in a unified way through the uclass. + * + * @priv: Private data for this uclass + * @uc_drv: The driver for the uclass itself, not to be confused with a + * 'struct driver' + * dev_head: List of devices in this uclass (devices are attached to their + * uclass when their bind method is called) + * @sibling_node: Next uclass in the linked list of uclasses + */ +struct uclass { + void *priv; + struct uclass_driver *uc_drv; + struct list_head dev_head; + struct list_head sibling_node; +}; + +struct device; + +/** + * struct uclass_driver - Driver for the uclass + * + * A uclass_driver provides a consistent interface to a set of related + * drivers. + * + * @name: Name of uclass driver + * @id: ID number of this uclass + * @post_bind: Called after a new device is bound to this uclass + * @pre_unbind: Called before a device is unbound from this uclass + * @post_probe: Called after a new device is probed + * @pre_remove: Called before a device is removed + * @init: Called to set up the uclass + * @destroy: Called to destroy the uclass + * @priv_auto_alloc_size: If non-zero this is the size of the private data + * to be allocated in the uclass's ->priv pointer. If zero, then the uclass + * driver is responsible for allocating any data required. + * @per_device_auto_alloc_size: Each device can hold private data owned + * by the uclass. If required this will be automatically allocated if this + * value is non-zero. + * @ops: Uclass operations, providing the consistent interface to devices + * within the uclass. + */ +struct uclass_driver { + const char *name; + enum uclass_id id; + int (*post_bind)(struct device *dev); + int (*pre_unbind)(struct device *dev); + int (*post_probe)(struct device *dev); + int (*pre_remove)(struct device *dev); + int (*init)(struct uclass *class); + int (*destroy)(struct uclass *class); + int priv_auto_alloc_size; + int per_device_auto_alloc_size; + const void *ops; +}; + +/* Declare a new uclass_driver */ +#define UCLASS_DRIVER(__name) \ + ll_entry_declare(struct uclass_driver, __name, uclass) + +/** + * uclass_get() - Get a uclass based on an ID, creating it if needed + * + * Every uclass is identified by an ID, a number from 0 to n-1 where n is + * the number of uclasses. This function allows looking up a uclass by its + * ID. + * + * @key: ID to look up + * @ucp: Returns pointer to uclass (there is only one per ID) + * @return 0 if OK, -ve on error + */ +int uclass_get(enum uclass_id key, struct uclass **ucp); + +/** + * uclass_get_device() - Get a uclass device based on an ID and index + * + * id: ID to look up + * @index: Device number within that uclass (0=first) + * @ucp: Returns pointer to uclass (there is only one per for each ID) + * @return 0 if OK, -ve on error + */ +int uclass_get_device(enum uclass_id id, int index, struct device **ucp); + +/** + * uclass_first_device() - Get the first device in a uclass + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass, or NULL if none + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_first_device(enum uclass_id id, struct device **devp); + +/** + * uclass_next_device() - Get the next device in a uclass + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the same uclass, or NULL if none + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_next_device(struct device **devp); + +/** + * uclass_foreach_dev() - Helper function to iteration through devices + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. + * + * @pos: struct device * to hold the current device. Set to NULL when there + * are no more devices. + * uc: uclass to scan + */ +#define uclass_foreach_dev(pos, uc) \ + for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos), \ + uclass_node); \ + prefetch(pos->uclass_node.next), \ + &pos->uclass_node != (&(uc)->dev_head); \ + pos = list_entry(pos->uclass_node.next, typeof(*pos), \ + uclass_node)) + +#endif diff --git a/include/dm/ut.h b/include/dm/ut.h new file mode 100644 index 0000000000..fa9eac0226 --- /dev/null +++ b/include/dm/ut.h @@ -0,0 +1,95 @@ +/* + * Simple unit test library for driver model + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_UT_H +#define __DM_UT_H + +struct dm_test_state; + +/** + * ut_fail() - Record failure of a unit test + * + * @dms: Test state + * @fname: Filename where the error occured + * @line: Line number where the error occured + * @func: Function name where the error occured + * @cond: The condition that failed + */ +void ut_fail(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond); + +/** + * ut_failf() - Record failure of a unit test + * + * @dms: Test state + * @fname: Filename where the error occured + * @line: Line number where the error occured + * @func: Function name where the error occured + * @cond: The condition that failed + * @fmt: printf() format string for the error, followed by args + */ +void ut_failf(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond, const char *fmt, ...) + __attribute__ ((format (__printf__, 6, 7))); + + +/* Assert that a condition is non-zero */ +#define ut_assert(cond) \ + if (!(cond)) { \ + ut_fail(dms, __FILE__, __LINE__, __func__, #cond); \ + return -1; \ + } + +/* Assert that a condition is non-zero, with printf() string */ +#define ut_assertf(cond, fmt, args...) \ + if (!(cond)) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, #cond, \ + fmt, ##args); \ + return -1; \ + } + +/* Assert that two int expressions are equal */ +#define ut_asserteq(expr1, expr2) { \ + unsigned int val1 = (expr1), val2 = (expr2); \ + \ + if (val1 != val2) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " == " #expr2, \ + "Expected %d, got %d", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that two string expressions are equal */ +#define ut_asserteq_str(expr1, expr2) { \ + const char *val1 = (expr1), *val2 = (expr2); \ + \ + if (strcmp(val1, val2)) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " = " #expr2, \ + "Expected \"%s\", got \"%s\"", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that two pointers are equal */ +#define ut_asserteq_ptr(expr1, expr2) { \ + const void *val1 = (expr1), *val2 = (expr2); \ + \ + if (val1 != val2) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " = " #expr2, \ + "Expected %p, got %p", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that an operation succeeds (returns 0) */ +#define ut_assertok(cond) ut_asserteq(0, cond) + +#endif diff --git a/include/dm/util.h b/include/dm/util.h new file mode 100644 index 0000000000..8be64a921d --- /dev/null +++ b/include/dm/util.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_UTIL_H + +void dm_warn(const char *fmt, ...); + +#ifdef DEBUG +void dm_dbg(const char *fmt, ...); +#else +static inline void dm_dbg(const char *fmt, ...) +{ +} +#endif + +struct list_head; + +/** + * list_count_items() - Count number of items in a list + * + * @param head: Head of list + * @return number of items, or 0 if empty + */ +int list_count_items(struct list_head *head); + +#endif diff --git a/include/dm9161.h b/include/dm9161.h deleted file mode 100644 index bd85e4287e..0000000000 --- a/include/dm9161.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * NOTE: DAVICOM ethernet Physical layer - * - * Version: @(#)DM9161.h 1.0.0 01/10/2001 - * - * Authors: ATMEL Rousset - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */ - -#define DM9161_BMCR 0 /* Basic Mode Control Register */ -#define DM9161_BMSR 1 /* Basic Mode Status Register */ -#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */ -#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */ -#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */ -#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */ -#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */ -#define DM9161_DSCR 16 /* Specified Configuration Register */ -#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */ -#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */ -#define DM9161_MDINTR 21 /* Specified Interrupt Register */ -#define DM9161_RECR 22 /* Specified Receive Error Counter Register */ -#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */ -#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */ - - -/* --Bit definitions: DM9161_BMCR */ -#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ -#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ -#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ -#define DM9161_AUTONEG (1 << 12) -#define DM9161_POWER_DOWN (1 << 11) -#define DM9161_ISOLATE (1 << 10) -#define DM9161_RESTART_AUTONEG (1 << 9) -#define DM9161_DUPLEX_MODE (1 << 8) -#define DM9161_COLLISION_TEST (1 << 7) - -/*--Bit definitions: DM9161_BMSR */ -#define DM9161_100BASE_TX (1 << 15) -#define DM9161_100BASE_TX_FD (1 << 14) -#define DM9161_100BASE_TX_HD (1 << 13) -#define DM9161_10BASE_T_FD (1 << 12) -#define DM9161_10BASE_T_HD (1 << 11) -#define DM9161_MF_PREAMB_SUPPR (1 << 6) -#define DM9161_AUTONEG_COMP (1 << 5) -#define DM9161_REMOTE_FAULT (1 << 4) -#define DM9161_AUTONEG_ABILITY (1 << 3) -#define DM9161_LINK_STATUS (1 << 2) -#define DM9161_JABBER_DETECT (1 << 1) -#define DM9161_EXTEND_CAPAB (1 << 0) - -/*--definitions: DM9161_PHYID1 */ -#define DM9161_PHYID1_OUI 0x606E -#define DM9161_LSB_MASK 0x3F - -/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */ -#define DM9161_NP (1 << 15) -#define DM9161_ACK (1 << 14) -#define DM9161_RF (1 << 13) -#define DM9161_FCS (1 << 10) -#define DM9161_T4 (1 << 9) -#define DM9161_TX_FDX (1 << 8) -#define DM9161_TX_HDX (1 << 7) -#define DM9161_10_FDX (1 << 6) -#define DM9161_10_HDX (1 << 5) -#define DM9161_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: DM9161_ANER */ -#define DM9161_PDF (1 << 4) -#define DM9161_LP_NP_ABLE (1 << 3) -#define DM9161_NP_ABLE (1 << 2) -#define DM9161_PAGE_RX (1 << 1) -#define DM9161_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: DM9161_DSCR */ -#define DM9161_BP4B5B (1 << 15) -#define DM9161_BP_SCR (1 << 14) -#define DM9161_BP_ALIGN (1 << 13) -#define DM9161_BP_ADPOK (1 << 12) -#define DM9161_REPEATER (1 << 11) -#define DM9161_TX (1 << 10) -#define DM9161_RMII_ENABLE (1 << 8) -#define DM9161_F_LINK_100 (1 << 7) -#define DM9161_SPLED_CTL (1 << 6) -#define DM9161_COLLED_CTL (1 << 5) -#define DM9161_RPDCTR_EN (1 << 4) -#define DM9161_SM_RST (1 << 3) -#define DM9161_MFP SC (1 << 2) -#define DM9161_SLEEP (1 << 1) -#define DM9161_RLOUT (1 << 0) - -/*--Bit definitions: DM9161_DSCSR */ -#define DM9161_100FDX (1 << 15) -#define DM9161_100HDX (1 << 14) -#define DM9161_10FDX (1 << 13) -#define DM9161_10HDX (1 << 12) - -/*--Bit definitions: DM9161_10BTCSR */ -#define DM9161_LP_EN (1 << 14) -#define DM9161_HBE (1 << 13) -#define DM9161_SQUELCH (1 << 12) -#define DM9161_JABEN (1 << 11) -#define DM9161_10BT_SER (1 << 10) -#define DM9161_POLR (1 << 0) - - -/*--Bit definitions: DM9161_MDINTR */ -#define DM9161_INTR_PEND (1 << 15) -#define DM9161_FDX_MASK (1 << 11) -#define DM9161_SPD_MASK (1 << 10) -#define DM9161_LINK_MASK (1 << 9) -#define DM9161_INTR_MASK (1 << 8) -#define DM9161_FDX_CHANGE (1 << 4) -#define DM9161_SPD_CHANGE (1 << 3) -#define DM9161_LINK_CHANGE (1 << 2) -#define DM9161_INTR_STATUS (1 << 0) - - -/****************** function prototypes **********************/ -unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac); -unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac); -unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67c13..c9bdf51a67 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,9 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); + + struct mmc_config cfg; }; struct dwmci_idmac { diff --git a/include/ec_commands.h b/include/ec_commands.h index 12811cc070..78baab1641 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,13 +42,19 @@ #define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 -#define EC_LPC_ADDR_HOST_PARAM 0x804 -#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ +/* Protocol version 2 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is + * EC_PROTO2_MAX_PARAM_SIZE */ +/* Protocol version 3 */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ -/* I/O addresses for host command params, old interface */ -#define EC_LPC_ADDR_OLD_PARAM 0x880 -#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */ +/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ #define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ @@ -122,8 +128,8 @@ #define EC_SWITCH_LID_OPEN 0x01 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 -/* Recovery requested via keyboard */ -#define EC_SWITCH_KEYBOARD_RECOVERY 0x08 +/* Was recovery requested via keyboard; now unused. */ +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ #define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ @@ -132,10 +138,13 @@ /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +/* Host command interface supports version 3 protocol */ +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ #define EC_WIRELESS_SWITCH_WLAN 0x01 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* * This header file is used in coreboot both in C and ACPI code. The ACPI code @@ -191,6 +200,9 @@ enum ec_status { EC_RES_UNAVAILABLE = 9, /* No response available */ EC_RES_TIMEOUT = 10, /* We got a timeout */ EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */ }; /* @@ -272,6 +284,105 @@ struct ec_lpc_host_args { */ #define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +/*****************************************************************************/ + +/* + * Protocol version 2 for I2C and SPI send a request this way: + * + * 0 EC_CMD_VERSION0 + (command version) + * 1 Command number + * 2 Length of params = N + * 3..N+2 Params, if any + * N+3 8-bit checksum of bytes 0..N+2 + * + * The corresponding response is: + * + * 0 Result code (EC_RES_*) + * 1 Length of params = M + * 2..M+1 Params, if any + * M+2 8-bit checksum of bytes 0..M+1 + */ +#define EC_PROTO2_REQUEST_HEADER_BYTES 3 +#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 +#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ + EC_PROTO2_REQUEST_TRAILER_BYTES) + +#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 +#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 +#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ + EC_PROTO2_RESPONSE_TRAILER_BYTES) + +/* Parameter length was limited by the LPC interface */ +#define EC_PROTO2_MAX_PARAM_SIZE 0xfc + +/* Maximum request and response packet sizes for protocol version 2 */ +#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) + +/*****************************************************************************/ + +/* + * Value written to legacy command port / prefix byte to indicate protocol + * 3+ structs are being used. Usage is bus-dependent. + */ +#define EC_COMMAND_PROTOCOL_3 0xda + +#define EC_HOST_REQUEST_VERSION 3 + +/* Version 3 request from host */ +struct ec_host_request { + /* Struct version (=3) + * + * EC will return EC_RES_INVALID_HEADER if it receives a header with a + * version it doesn't know how to parse. + */ + uint8_t struct_version; + + /* + * Checksum of request and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Command code */ + uint16_t command; + + /* Command version */ + uint8_t command_version; + + /* Unused byte in current protocol version; set to 0 */ + uint8_t reserved; + + /* Length of data which follows this header */ + uint16_t data_len; +} __packed; + +#define EC_HOST_RESPONSE_VERSION 3 + +/* Version 3 response from EC */ +struct ec_host_response { + /* Struct version (=3) */ + uint8_t struct_version; + + /* + * Checksum of response and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Result code (EC_RES_*) */ + uint16_t result; + + /* Length of data which follows this header */ + uint16_t data_len; + + /* Unused bytes in current protocol version; set to 0 */ + uint16_t reserved; +} __packed; + +/*****************************************************************************/ /* * Notes on commands: * @@ -411,6 +522,46 @@ struct ec_response_get_comms_status { uint32_t flags; /* Mask of enum ec_comms_status */ } __packed; +/* + * Fake a variety of responses, purely for testing purposes. + * FIXME: Would be nice to force checksum errors. + */ +#define EC_CMD_TEST_PROTOCOL 0x0a + +/* Tell the EC what to send back to us. */ +struct ec_params_test_protocol { + uint32_t ec_result; + uint32_t ret_len; + uint8_t buf[32]; +} __packed; + +/* Here it comes... */ +struct ec_response_test_protocol { + uint8_t buf[32]; +} __packed; + +/* Get prococol information */ +#define EC_CMD_GET_PROTOCOL_INFO 0x0b + +/* Flags for ec_response_get_protocol_info.flags */ +/* EC_RES_IN_PROGRESS may be returned if a command is slow */ +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) + +struct ec_response_get_protocol_info { + /* Fields which exist if at least protocol version 3 supported */ + + /* Bitmask of protocol versions supported (1 << n means version n)*/ + uint32_t protocol_versions; + + /* Maximum request packet size, in bytes */ + uint16_t max_request_packet_size; + + /* Maximum response packet size, in bytes */ + uint16_t max_response_packet_size; + + /* Flags; see EC_PROTOCOL_INFO_* */ + uint32_t flags; +} __packed; /*****************************************************************************/ /* Flash commands */ @@ -452,15 +603,15 @@ struct ec_params_flash_read { /* Write flash */ #define EC_CMD_FLASH_WRITE 0x12 +#define EC_VER_FLASH_WRITE 1 + +/* Version 0 of the flash command supported only 64 bytes of data */ +#define EC_FLASH_WRITE_VER0_SIZE 64 struct ec_params_flash_write { uint32_t offset; /* Byte offset to write */ uint32_t size; /* Size to write in bytes */ - /* - * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to - * use a power of 2 so writes stay aligned. - */ - uint8_t data[64]; + /* Followed by data to write */ } __packed; /* Erase flash */ @@ -536,7 +687,7 @@ struct ec_response_flash_protect { enum ec_flash_region { /* Region which holds read-only EC image */ - EC_FLASH_REGION_RO, + EC_FLASH_REGION_RO = 0, /* Region which holds rewritable EC image */ EC_FLASH_REGION_RW, /* @@ -544,6 +695,8 @@ enum ec_flash_region { * EC_FLASH_REGION_RO) */ EC_FLASH_REGION_WP_RO, + /* Number of regions */ + EC_FLASH_REGION_COUNT, }; struct ec_params_flash_region_info { @@ -726,6 +879,49 @@ enum lightbar_command { LIGHTBAR_NUM_CMDS }; +/*****************************************************************************/ +/* LED control commands */ + +#define EC_CMD_LED_CONTROL 0x29 + +enum ec_led_id { + EC_LED_ID_BATTERY_LED = 0, + EC_LED_ID_POWER_BUTTON_LED, + EC_LED_ID_ADAPTER_LED, +}; + +/* LED control flags */ +#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ + +enum ec_led_colors { + EC_LED_COLOR_RED = 0, + EC_LED_COLOR_GREEN, + EC_LED_COLOR_BLUE, + EC_LED_COLOR_YELLOW, + EC_LED_COLOR_WHITE, + + EC_LED_COLOR_COUNT +}; + +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ + + uint8_t brightness[EC_LED_COLOR_COUNT]; +} __packed; + +struct ec_response_led_control { + /* + * Available brightness value range. + * + * Range 0 means color channel not present. + * Range 1 means on/off control. + * Other values means the LED is control by PWM. + */ + uint8_t brightness_range[EC_LED_COLOR_COUNT]; +} __packed; + /*****************************************************************************/ /* Verified boot commands */ @@ -914,57 +1110,57 @@ struct ec_params_tmp006_set_calibration { } __packed; /*****************************************************************************/ -/* CROS_EC - Matrix KeyBoard Protocol */ +/* MKBP - Matrix KeyBoard Protocol */ /* * Read key state * - * Returns raw data for keyboard cols; see ec_response_cros_ec_info.cols for + * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for * expected response size. */ -#define EC_CMD_CROS_EC_STATE 0x60 +#define EC_CMD_MKBP_STATE 0x60 /* Provide information about the matrix : number of rows and columns */ -#define EC_CMD_CROS_EC_INFO 0x61 +#define EC_CMD_MKBP_INFO 0x61 -struct ec_response_cros_ec_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; uint8_t switches; } __packed; /* Simulate key press */ -#define EC_CMD_CROS_EC_SIMULATE_KEY 0x62 +#define EC_CMD_MKBP_SIMULATE_KEY 0x62 -struct ec_params_cros_ec_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; } __packed; /* Configure keyboard scanning */ -#define EC_CMD_CROS_EC_SET_CONFIG 0x64 -#define EC_CMD_CROS_EC_GET_CONFIG 0x65 +#define EC_CMD_MKBP_SET_CONFIG 0x64 +#define EC_CMD_MKBP_GET_CONFIG 0x65 /* flags */ -enum cros_ec_config_flags { - EC_CROS_EC_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ +enum mkbp_config_flags { + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; -enum cros_ec_config_valid { - EC_CROS_EC_VALID_SCAN_PERIOD = 1 << 0, - EC_CROS_EC_VALID_POLL_TIMEOUT = 1 << 1, - EC_CROS_EC_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_CROS_EC_VALID_OUTPUT_SETTLE = 1 << 4, - EC_CROS_EC_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_CROS_EC_VALID_DEBOUNCE_UP = 1 << 6, - EC_CROS_EC_VALID_FIFO_MAX_DEPTH = 1 << 7, +enum mkbp_config_valid { + EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, + EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, + EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, + EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, + EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, + EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, }; /* Configuration for our key scanning algorithm */ -struct ec_cros_ec_config { +struct ec_mkbp_config { uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum cros_ec_config_flags) */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ uint8_t valid_flags; /* which flags are valid */ uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ @@ -983,12 +1179,12 @@ struct ec_cros_ec_config { uint8_t fifo_max_depth; } __packed; -struct ec_params_cros_ec_set_config { - struct ec_cros_ec_config config; +struct ec_params_mkbp_set_config { + struct ec_mkbp_config config; } __packed; -struct ec_response_cros_ec_get_config { - struct ec_cros_ec_config config; +struct ec_response_mkbp_get_config { + struct ec_mkbp_config config; } __packed; /* Run the key scan emulation */ @@ -1144,7 +1340,7 @@ struct ec_response_gpio_get { #define EC_CMD_I2C_READ 0x94 struct ec_params_i2c_read { - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1158,7 +1354,7 @@ struct ec_response_i2c_read { struct ec_params_i2c_write { uint16_t data; - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1241,6 +1437,61 @@ struct ec_response_ldo_get { uint8_t state; } __packed; +/*****************************************************************************/ +/* Power info. */ + +/* + * Get power info. + */ +#define EC_CMD_POWER_INFO 0x9d + +struct ec_response_power_info { + uint32_t usb_dev_type; + uint16_t voltage_ac; + uint16_t voltage_system; + uint16_t current_system; + uint16_t usb_current_limit; +} __packed; + +/*****************************************************************************/ +/* I2C passthru command */ + +#define EC_CMD_I2C_PASSTHRU 0x9e + +/* Slave address is 10 (not 7) bit */ +#define EC_I2C_FLAG_10BIT (1 << 16) + +/* Read data; if not present, message is a write */ +#define EC_I2C_FLAG_READ (1 << 15) + +/* Mask for address */ +#define EC_I2C_ADDR_MASK 0x3ff + +#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ + +/* Any error */ +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) + +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __packed; + +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[]; + /* Data to write for all messages is concatenated here */ +} __packed; + +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ +} __packed; + + /*****************************************************************************/ /* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */ @@ -1257,7 +1508,16 @@ struct ec_response_ldo_get { #define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1 struct ec_params_current_limit { - uint32_t limit; + uint32_t limit; /* in mA */ +} __packed; + +/* + * Set maximum external power current. + */ +#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2 + +struct ec_params_ext_power_current_limit { + uint32_t limit; /* in mA */ } __packed; /*****************************************************************************/ diff --git a/include/ext4fs.h b/include/ext4fs.h index 2429380396..aacb147de2 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -134,6 +134,7 @@ int ext4fs_read(char *buf, unsigned len); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); int ext4fs_ls(const char *dirname); +int ext4fs_exists(const char *filename); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); diff --git a/include/faraday/ftsdc021.h b/include/faraday/ftsdc021.h deleted file mode 100644 index de8e250839..0000000000 --- a/include/faraday/ftsdc021.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2013 Faraday Technology - * Dante Su - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FTSDC021_H -#define __FTSDC021_H - -int ftsdc021_sdhci_init(u32 regbase); - -#endif /* __FTSDC021_H */ diff --git a/include/fat.h b/include/fat.h index f66996ec06..121306044d 100644 --- a/include/fat.h +++ b/include/fat.h @@ -190,6 +190,7 @@ file_read_func file_fat_read; int file_cd(const char *path); int file_fat_detectfs(void); int file_fat_ls(const char *dir); +int fat_exists(const char *filename); long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize); long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); diff --git a/include/fdtdec.h b/include/fdtdec.h index 433d6a7c02..3196cf6683 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -59,6 +59,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ @@ -78,8 +79,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ + COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */ + COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ @@ -87,6 +90,8 @@ enum fdt_compat_id { COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */ COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ + COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ + COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ COMPAT_COUNT, }; @@ -529,4 +534,22 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node, */ int fdtdec_decode_region(const void *blob, int node, const char *prop_name, void **ptrp, size_t *size); + +/* A flash map entry, containing an offset and length */ +struct fmap_entry { + uint32_t offset; + uint32_t length; +}; + +/** + * Read a flash entry from the fdt + * + * @param blob FDT blob + * @param node Offset of node to read + * @param name Name of node being read + * @param entry Place to put offset and size of this node + * @return 0 if ok, -ve on error + */ +int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, + struct fmap_entry *entry); #endif diff --git a/include/fs.h b/include/fs.h index 7d9403ed87..26de0539f7 100644 --- a/include/fs.h +++ b/include/fs.h @@ -43,6 +43,13 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); */ int fs_ls(const char *dirname); +/* + * Determine whether a file exists + * + * Returns 1 if the file exists, 0 if it doesn't exist. + */ +int fs_exists(const char *filename); + /* * Read file "filename" from the partition previously set by fs_set_blk_dev(), * to address "addr", starting at byte offset "offset", and reading "len" @@ -54,6 +61,16 @@ int fs_ls(const char *dirname); */ int fs_read(const char *filename, ulong addr, int offset, int len); +/* + * Write file "filename" to the partition previously set by fs_set_blk_dev(), + * from address "addr", starting at byte offset "offset", and writing "len" + * bytes. "offset" may be 0 to write to the start of the file. Note that not + * all filesystem types support offset!=0. + * + * Returns number of bytes read on success. Returns <= 0 on error. + */ +int fs_write(const char *filename, ulong addr, int offset, int len); + /* * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. @@ -62,6 +79,8 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype); int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index e03f9db5f2..72c0b2e94e 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -14,6 +14,14 @@ #include +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#endif + #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names @@ -93,6 +101,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 16cccc7708..2a36431146 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_PAGE_INTERLEAVING 0x1 #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_256B_INTERLEAVING 0x8 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89bcbd1700..a6e3a5dc9a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -13,6 +13,9 @@ #include #include +/* needed for the mmc_cfg definition */ +#include + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 @@ -155,6 +158,7 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 sdhc_clk; u8 max_bus_width; + struct mmc_config cfg; }; /* Select the correct accessors depending on endianess */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index be6c10715b..58a6efdfe0 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,20 @@ #include #include + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + /* * CSPR - Chip Select Property Register */ @@ -773,20 +787,22 @@ extern void init_early_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) +#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 915774cba8..8b63cdd88c 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -52,13 +52,32 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) + +#define INC_DCNT_THRESHOLD_25MV (0 << 4) +#define INC_DCNT_THRESHOLD_50MV (1 << 4) +#define DEC_DCNT_THRESHOLD_25MV (2 << 4) +#define DEC_DCNT_THRESHOLD_50MV (3 << 4) #else struct ccsr_usb_phy { - u8 res0[0x18]; + u32 config1; + u32 config2; + u32 config3; + u32 config4; + u32 config5; + u32 status1; u32 usb_enable_override; u8 res[0xe4]; }; -#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) +#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 #endif #endif /*_ASM_FSL_USB_H_ */ diff --git a/include/i2c.h b/include/i2c.h index f93a18366e..1b4078ed62 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -68,6 +68,7 @@ struct i2c_adapter { uint (*set_bus_speed)(struct i2c_adapter *adap, uint speed); int speed; + int waitdelay; int slaveaddr; int init_done; int hwadapnr; diff --git a/include/image.h b/include/image.h index 7de2bb2f81..6afd57bafd 100644 --- a/include/image.h +++ b/include/image.h @@ -99,9 +99,9 @@ struct lmb; #endif #ifdef CONFIG_OF_BOARD_SETUP -# define IMAAGE_OF_BOARD_SETUP 1 +# define IMAGE_OF_BOARD_SETUP 1 #else -# define IMAAGE_OF_BOARD_SETUP 0 +# define IMAGE_OF_BOARD_SETUP 0 #endif /* @@ -157,6 +157,7 @@ struct lmb; #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ #define IH_ARCH_ARM64 22 /* ARM64 */ +#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ /* * Image Types diff --git a/include/ks8721.h b/include/ks8721.h deleted file mode 100644 index 90ed178087..0000000000 --- a/include/ks8721.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * NOTE: MICREL ethernet Physical layer - * - * Version: KS8721.h - * - * Authors: Eric Benard (based on dm9161.h) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */ - -#define KS8721_BMCR 0 -#define KS8721_BMSR 1 -#define KS8721_PHYID1 2 -#define KS8721_PHYID2 3 -#define KS8721_ANAR 4 -#define KS8721_ANLPAR 5 -#define KS8721_ANER 6 -#define KS8721_RECR 15 -#define KS8721_MDINTR 27 -#define KS8721_100BT 31 - -/* --Bit definitions: KS8721_BMCR */ -#define KS8721_RESET (1 << 15) -#define KS8721_LOOPBACK (1 << 14) -#define KS8721_SPEED_SELECT (1 << 13) -#define KS8721_AUTONEG (1 << 12) -#define KS8721_POWER_DOWN (1 << 11) -#define KS8721_ISOLATE (1 << 10) -#define KS8721_RESTART_AUTONEG (1 << 9) -#define KS8721_DUPLEX_MODE (1 << 8) -#define KS8721_COLLISION_TEST (1 << 7) -#define KS8721_DISABLE (1 << 0) - -/*--Bit definitions: KS8721_BMSR */ -#define KS8721_100BASE_T4 (1 << 15) -#define KS8721_100BASE_TX_FD (1 << 14) -#define KS8721_100BASE_T4_HD (1 << 13) -#define KS8721_10BASE_T_FD (1 << 12) -#define KS8721_10BASE_T_HD (1 << 11) -#define KS8721_MF_PREAMB_SUPPR (1 << 6) -#define KS8721_AUTONEG_COMP (1 << 5) -#define KS8721_REMOTE_FAULT (1 << 4) -#define KS8721_AUTONEG_ABILITY (1 << 3) -#define KS8721_LINK_STATUS (1 << 2) -#define KS8721_JABBER_DETECT (1 << 1) -#define KS8721_EXTEND_CAPAB (1 << 0) - -/*--Bit definitions: KS8721_PHYID */ -#define KS8721_PHYID_OUI 0x0885 -#define KS8721_LSB_MASK 0x3F - -#define KS8721BL_MODEL 0x21 -#define KS8721_MODELMASK 0x3F0 -#define KS8721BL_REV 0x9 -#define KS8721_REVMASK 0xF - -/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */ -#define KS8721_NP (1 << 15) -#define KS8721_ACK (1 << 14) -#define KS8721_RF (1 << 13) -#define KS8721_PAUSE (1 << 10) -#define KS8721_T4 (1 << 9) -#define KS8721_TX_FDX (1 << 8) -#define KS8721_TX_HDX (1 << 7) -#define KS8721_10_FDX (1 << 6) -#define KS8721_10_HDX (1 << 5) -#define KS8721_AN_IEEE_802_3 0x0001 - -/****************** function prototypes **********************/ -unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac); -unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac); -unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char ks8721_initphy(AT91PS_EMAC p_mac); diff --git a/include/lcd.h b/include/lcd.h index 40e8d2a86b..5f84cd3c5b 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -223,6 +223,8 @@ typedef struct vidinfo { unsigned int logo_on; unsigned int logo_width; unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; unsigned long logo_addr; unsigned int rgb_mode; unsigned int resolution; @@ -311,6 +313,9 @@ int lcd_get_size(int *line_length); int lcd_dt_simplefb_add_node(void *blob); int lcd_dt_simplefb_enable_existing_node(void *blob); +/* Update the LCD / flush the cache */ +void lcd_sync(void); + /************************************************************************/ /* ** BITMAP DISPLAY SUPPORT */ /************************************************************************/ diff --git a/include/linker_lists.h b/include/linker_lists.h index 1eebb95fbb..997d149b71 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -8,6 +8,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + /* * There is no use in including this from ASM files, but that happens * anyway, e.g. PPC kgdb.S includes command.h which incluse us. @@ -97,9 +100,6 @@ * %u_boot_list_2_drivers_3 */ -#ifndef __LINKER_LISTS_H__ -#define __LINKER_LISTS_H__ - /** * ll_entry_declare() - Declare linker-generated array entry * @_type: Data type of the entry diff --git a/include/linux/fb.h b/include/linux/fb.h index 111372c9fd..652cf3bab7 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -612,6 +612,8 @@ struct fb_videomode { u32 flag; }; +int board_video_skip(void); + #endif /* __KERNEL__ */ #endif /* _LINUX_FB_H */ diff --git a/include/linux/mtd/inftl-user.h b/include/linux/mtd/inftl-user.h deleted file mode 100644 index 45220ed76f..0000000000 --- a/include/linux/mtd/inftl-user.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ - * - * Parts of INFTL headers shared with userspace - * - */ - -#ifndef __MTD_INFTL_USER_H__ -#define __MTD_INFTL_USER_H__ - -#define OSAK_VERSION 0x5120 -#define PERCENTUSED 98 - -#define SECTORSIZE 512 - -/* Block Control Information */ - -struct inftl_bci { - uint8_t ECCsig[6]; - uint8_t Status; - uint8_t Status1; -} __attribute__((packed)); - -struct inftl_unithead1 { - uint16_t virtualUnitNo; - uint16_t prevUnitNo; - uint8_t ANAC; - uint8_t NACs; - uint8_t parityPerField; - uint8_t discarded; -} __attribute__((packed)); - -struct inftl_unithead2 { - uint8_t parityPerField; - uint8_t ANAC; - uint16_t prevUnitNo; - uint16_t virtualUnitNo; - uint8_t NACs; - uint8_t discarded; -} __attribute__((packed)); - -struct inftl_unittail { - uint8_t Reserved[4]; - uint16_t EraseMark; - uint16_t EraseMark1; -} __attribute__((packed)); - -union inftl_uci { - struct inftl_unithead1 a; - struct inftl_unithead2 b; - struct inftl_unittail c; -}; - -struct inftl_oob { - struct inftl_bci b; - union inftl_uci u; -}; - - -/* INFTL Media Header */ - -struct INFTLPartition { - __u32 virtualUnits; - __u32 firstUnit; - __u32 lastUnit; - __u32 flags; - __u32 spareUnits; - __u32 Reserved0; - __u32 Reserved1; -} __attribute__((packed)); - -struct INFTLMediaHeader { - char bootRecordID[8]; - __u32 NoOfBootImageBlocks; - __u32 NoOfBinaryPartitions; - __u32 NoOfBDTLPartitions; - __u32 BlockMultiplierBits; - __u32 FormatFlags; - __u32 OsakVersion; - __u32 PercentUsed; - struct INFTLPartition Partitions[4]; -} __attribute__((packed)); - -/* Partition flag types */ -#define INFTL_BINARY 0x20000000 -#define INFTL_BDTL 0x40000000 -#define INFTL_LAST 0x80000000 - -#endif /* __MTD_INFTL_USER_H__ */ diff --git a/include/linux/mtd/jffs2-user.h b/include/linux/mtd/jffs2-user.h deleted file mode 100644 index d508ef0ae0..0000000000 --- a/include/linux/mtd/jffs2-user.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $ - * - * JFFS2 definitions for use in user space only - */ - -#ifndef __JFFS2_USER_H__ -#define __JFFS2_USER_H__ - -/* This file is blessed for inclusion by userspace */ -#include -#include -#include - -#undef cpu_to_je16 -#undef cpu_to_je32 -#undef cpu_to_jemode -#undef je16_to_cpu -#undef je32_to_cpu -#undef jemode_to_cpu - -extern int target_endian; - -#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); }) -#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); }) - -#define cpu_to_je16(x) ((jint16_t){t16(x)}) -#define cpu_to_je32(x) ((jint32_t){t32(x)}) -#define cpu_to_jemode(x) ((jmode_t){t32(x)}) - -#define je16_to_cpu(x) (t16((x).v16)) -#define je32_to_cpu(x) (t32((x).v32)) -#define jemode_to_cpu(x) (t32((x).m)) - -#endif /* __JFFS2_USER_H__ */ diff --git a/arch/arm/include/asm/omap_elm.h b/include/linux/mtd/omap_elm.h similarity index 100% rename from arch/arm/include/asm/omap_elm.h rename to include/linux/mtd/omap_elm.h diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h new file mode 100644 index 0000000000..22f6573969 --- /dev/null +++ b/include/linux/mtd/omap_gpmc.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, + * Rohit Choraria + * + * (C) Copyright 2013 Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_OMAP_GPMC_H +#define __ASM_OMAP_GPMC_H + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, +}; + +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ + u8 res7[12]; /* 0x224 */ + u32 testmomde_ctrl; /* 0x230 */ + u8 res8[12]; /* 0x234 */ + struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + +#endif /* __ASM_OMAP_GPMC_H */ diff --git a/include/linux/sizes.h b/include/linux/sizes.h new file mode 100644 index 0000000000..ce3e8150c1 --- /dev/null +++ b/include/linux/sizes.h @@ -0,0 +1,47 @@ +/* + * include/linux/sizes.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __LINUX_SIZES_H__ +#define __LINUX_SIZES_H__ + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __LINUX_SIZES_H__ */ diff --git a/include/mmc.h b/include/mmc.h index e1060b9ff2..42d01251b5 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -150,6 +150,7 @@ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 @@ -187,6 +188,9 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -247,20 +251,40 @@ struct mmc_data { uint blocksize; }; -struct mmc { - struct list_head link; - char name[32]; - void *priv; +/* forward decl. */ +struct mmc; + +struct mmc_ops { + int (*send_cmd)(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data); + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); + int (*getcd)(struct mmc *mmc); + int (*getwp)(struct mmc *mmc); +}; + +struct mmc_config { + const char *name; + const struct mmc_ops *ops; + uint host_caps; uint voltages; - uint version; - uint has_init; uint f_min; uint f_max; + uint b_max; + unsigned char part_type; +}; + +/* TODO struct mmc should be in mmc_private but it's hard to fix right now */ +struct mmc { + struct list_head link; + const struct mmc_config *cfg; /* provided configuration */ + uint version; + void *priv; + uint has_init; int high_capacity; uint bus_width; uint clock; uint card_caps; - uint host_caps; uint ocr; uint dsr; uint dsr_imp; @@ -280,13 +304,6 @@ struct mmc { u64 capacity_rpmb; u64 capacity_gp[4]; block_dev_desc_t block_dev; - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - void (*set_ios)(struct mmc *mmc); - int (*init)(struct mmc *mmc); - int (*getcd)(struct mmc *mmc); - int (*getwp)(struct mmc *mmc); - uint b_max; char op_cond_pending; /* 1 if we are waiting on an op_cond command */ char init_in_progress; /* 1 if we have done mmc_start_init() */ char preinit; /* start init as early as possible */ @@ -294,6 +311,8 @@ struct mmc { }; int mmc_register(struct mmc *mmc); +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); +void mmc_destroy(struct mmc *mmc); int mmc_initialize(bd_t *bis); int mmc_init(struct mmc *mmc); int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); @@ -310,8 +329,12 @@ int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -/* Function to send commands to open/close the specified boot partition */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); +/* Function to modify the RST_n_FUNCTION field of EXT_CSD */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); /** * Start device initialization and return immediately; it does not block on @@ -340,7 +363,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #ifdef CONFIG_GENERIC_MMC #ifdef CONFIG_MMC_SPI -#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) +#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) #else #define mmc_host_is_spi(mmc) 0 #endif @@ -349,4 +372,11 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); int mmc_legacy_init(int verbose); #endif +int board_mmc_init(bd_t *bis); + +/* Set block count limit because of 16 bit register limit on some hardware*/ +#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 +#endif + #endif /* _MMC_H_ */ diff --git a/include/nand.h b/include/nand.h index 84116f4937..fc735d1ec4 100644 --- a/include/nand.h +++ b/include/nand.h @@ -21,10 +21,16 @@ * at the same time, so do it here. When all drivers are * converted, this will go away. */ +#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC) +#define CONFIG_SYS_NAND_SELF_INIT +#endif +#else #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\ || defined(CONFIG_NAND_FSL_IFC) #define CONFIG_SYS_NAND_SELF_INIT #endif +#endif extern void nand_init(void); diff --git a/include/netdev.h b/include/netdev.h index f78d7fff22..c256881cee 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); +int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); @@ -86,10 +86,12 @@ int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr); +int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_initialize(bd_t *bis, unsigned long base_addr, int mode, unsigned long ctrl); +int zynq_gem_of_init(const void *blob); int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio); /* * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface diff --git a/include/os.h b/include/os.h index b65fba4301..0230a7f40d 100644 --- a/include/os.h +++ b/include/os.h @@ -83,6 +83,14 @@ int os_open(const char *pathname, int flags); */ int os_close(int fd); +/** + * Access to the OS unlink() system call + * + * \param pathname Path of file to delete + * \return 0 for success, other for error + */ +int os_unlink(const char *pathname); + /** * Access to the OS exit() system call * @@ -95,8 +103,12 @@ void os_exit(int exit_code) __attribute__((noreturn)); /** * Put tty into raw mode to mimic serial console better + * + * @param fd File descriptor of stdin (normally 0) + * @param allow_sigs Allow Ctrl-C, Ctrl-Z to generate signals rather than + * be handled by U-Boot */ -void os_tty_raw(int fd); +void os_tty_raw(int fd, bool allow_sigs); /** * Acquires some memory from the underlying os. @@ -113,7 +125,7 @@ void *os_malloc(size_t length); * * \param ptr Pointer to memory block to free */ -void *os_free(void *ptr); +void os_free(void *ptr); /** * Reallocate previously-allocated memory to increase/decrease space @@ -245,4 +257,23 @@ int os_write_ram_buf(const char *fname); */ int os_read_ram_buf(const char *fname); +/** + * Jump to a new executable image + * + * This uses exec() to run a new executable image, after putting it in a + * temporary file. The same arguments and environment are passed to this + * new image, with the addition of: + * + * -j Specifies the filename the image was written to. The + * calling image may want to delete this at some point. + * -m Specifies the file containing the sandbox memory + * (ram_buf) from this image, so that the new image can + * have access to this. It also means that the original + * memory filename passed to U-Boot will be left intact. + * + * @param dest Buffer containing executable image + * @param size Size of buffer + */ +int os_jump_to_image(const void *dest, int size); + #endif diff --git a/include/phy.h b/include/phy.h index 1f22fa180c..d3ecd6378b 100644 --- a/include/phy.h +++ b/include/phy.h @@ -234,6 +234,8 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_vitesse_init(void); +int board_phy_config(struct phy_device *phydev); + /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_TN2020 0x00a19410 diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 16e9016089..c2a772a895 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -8,6 +8,8 @@ #ifndef __MAX77686_H_ #define __MAX77686_H_ +#include + enum { MAX77686_REG_PMIC_ID = 0x0, MAX77686_REG_PMIC_INTSRC, diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h new file mode 100644 index 0000000000..2a9032a1f9 --- /dev/null +++ b/include/power/pfuze100_pmic.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE100_PMIC_H_ +#define __PFUZE100_PMIC_H_ + +/* PFUZE100 registers */ +enum { + PFUZE100_DEVICEID = 0x00, + PFUZE100_REVID = 0x03, + PFUZE100_FABID = 0x04, + + PFUZE100_SW1ABVOL = 0x20, + PFUZE100_SW1CVOL = 0x2e, + PFUZE100_SW2VOL = 0x35, + PFUZE100_SW3AVOL = 0x3c, + PFUZE100_SW3BVOL = 0x43, + PFUZE100_SW4VOL = 0x4a, + PFUZE100_SWBSTCON1 = 0x66, + PFUZE100_VREFDDRCON = 0x6a, + PFUZE100_VSNVSVOL = 0x6b, + PFUZE100_VGEN1VOL = 0x6c, + PFUZE100_VGEN2VOL = 0x6d, + PFUZE100_VGEN3VOL = 0x6e, + PFUZE100_VGEN4VOL = 0x6f, + PFUZE100_VGEN5VOL = 0x70, + PFUZE100_VGEN6VOL = 0x71, + + PMIC_NUM_OF_REGS = 0x7f, +}; + +/* + * LDO Configuration + */ + +/* VGEN1/2 Voltage Configuration */ +#define LDOA_0_80V 0 +#define LDOA_0_85V 1 +#define LDOA_0_90V 2 +#define LDOA_0_95V 3 +#define LDOA_1_00V 4 +#define LDOA_1_05V 5 +#define LDOA_1_10V 6 +#define LDOA_1_15V 7 +#define LDOA_1_20V 8 +#define LDOA_1_25V 9 +#define LDOA_1_30V 10 +#define LDOA_1_35V 11 +#define LDOA_1_40V 12 +#define LDOA_1_45V 13 +#define LDOA_1_50V 14 +#define LDOA_1_55V 15 + +/* VGEN3/4/5/6 Voltage Configuration */ +#define LDOB_1_80V 0 +#define LDOB_1_90V 1 +#define LDOB_2_00V 2 +#define LDOB_2_10V 3 +#define LDOB_2_20V 4 +#define LDOB_2_30V 5 +#define LDOB_2_40V 6 +#define LDOB_2_50V 7 +#define LDOB_2_60V 8 +#define LDOB_2_70V 9 +#define LDOB_2_80V 10 +#define LDOB_2_90V 11 +#define LDOB_3_00V 12 +#define LDOB_3_10V 13 +#define LDOB_3_20V 14 +#define LDOB_3_30V 15 + +#define LDO_VOL_MASK 0xf +#define LDO_EN 4 + +/* + * Boost Regulator + */ + +/* SWBST Output Voltage */ +#define SWBST_5_00V 0 +#define SWBST_5_05V 1 +#define SWBST_5_10V 2 +#define SWBST_5_15V 3 + +#define SWBST_VOL_MASK 0x3 +#define SWBST_MODE_MASK 0x6 +#define SWBST_MODE_OFF (2 << 0) +#define SWBST_MODE_PFM (2 << 1) +#define SWBST_MODE_AUTO (2 << 2) +#define SWBST_MODE_APS (2 << 3) + +#endif diff --git a/include/power/pmic.h b/include/power/pmic.h index 0e7aa31492..8f282dd2f2 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -8,7 +8,6 @@ #ifndef __CORE_PMIC_H_ #define __CORE_PMIC_H_ -#include #include #include #include diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 331b666459..5fcef9cebb 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -135,7 +135,7 @@ #define PLPRCR 0x00000284 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define HID2 1011 diff --git a/include/samsung/misc.h b/include/samsung/misc.h new file mode 100644 index 0000000000..ede6c1583a --- /dev/null +++ b/include/samsung/misc.h @@ -0,0 +1,29 @@ +#ifndef __SAMSUNG_MISC_COMMON_H__ +#define __SAMSUNG_MISC_COMMON_H__ + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void); +#endif + +#ifdef CONFIG_LCD_MENU +enum { + BOOT_MODE_INFO, + BOOT_MODE_THOR, + BOOT_MODE_UMS, + BOOT_MODE_DFU, + BOOT_MODE_EXIT, +}; + +void keys_init(void); +void check_boot_mode(void); +#endif /* CONFIG_LCD_MENU */ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void); +#endif + +#endif /* __SAMSUNG_MISC_COMMON_H__ */ diff --git a/include/sandboxfs.h b/include/sandboxfs.h index 8ea8cb7e2e..a51ad13044 100644 --- a/include/sandboxfs.h +++ b/include/sandboxfs.h @@ -25,6 +25,7 @@ long sandbox_fs_read_at(const char *filename, unsigned long pos, void sandbox_fs_close(void); int sandbox_fs_ls(const char *dirname); +int sandbox_fs_exists(const char *filename); int fs_read_sandbox(const char *filename, void *buf, int offset, int len); int fs_write_sandbox(const char *filename, void *buf, int offset, int len); diff --git a/include/sdhci.h b/include/sdhci.h index 74d06ae18a..aa4a0e9654 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -12,6 +12,7 @@ #include #include +#include /* * Controller registers @@ -244,9 +245,15 @@ struct sdhci_host { const struct sdhci_ops *ops; int index; + int bus_width; + struct fdt_gpio_state pwr_gpio; /* Power GPIO */ + struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */ + void (*set_control_reg)(struct sdhci_host *host); void (*set_clock)(int dev_index, unsigned int div); uint voltages; + + struct mmc_config cfg; }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h deleted file mode 100644 index c020115f86..0000000000 --- a/include/smiLynxEM.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 1997-2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * smiLynxEM.h - * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator - * - * - * modification history - * -------------------- - * 04-18-2002 Rewritten for U-Boot . - */ - -#ifndef _SMI_LYNX_EM_H_ -#define _SMI_LYNX_EM_H_ - -/* - * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external - */ -#define VIDEO_MEM_SIZE 0x400000 - -/* - * Supported video modes for SMI Lynx E/EM/EM+ - */ -#define VIDEO_MODES 7 -#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */ - /* VGA2:60/120Hz (pitch=1600) */ - /* SMI810:VGA1:75Hz (pitch=1600) */ - /* VGA2:75Hz (pitch=1600) */ -#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */ -#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */ -#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */ -#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */ -#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */ -#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */ - - -/* - * ISA mapped regs - */ -#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ -#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ -#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ -#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ -#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ -#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ -#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ -#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ -#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ -#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ -#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ - - -/* - * Video processor control - */ -typedef struct { - unsigned int control; - unsigned int colorKey; - unsigned int colorKeyMask; - unsigned int start; - unsigned short offset; - unsigned short width; - unsigned int fifoPrio; - unsigned int fifoERL; - unsigned int YUVtoRGB; -} SmiVideoProc; - -/* - * Video window control - */ -typedef struct { - unsigned short top; - unsigned short left; - unsigned short bottom; - unsigned short right; - unsigned int srcStart; - unsigned short width; - unsigned short offset; - unsigned char hStretch; - unsigned char vStretch; -} SmiVideoWin; - -/* - * Capture port control - */ -typedef struct { - unsigned int control; - unsigned short topClip; - unsigned short leftClip; - unsigned short srcHeight; - unsigned short srcWidth; - unsigned int srcBufStart1; - unsigned int srcBufStart2; - unsigned short srcOffset; - unsigned short fifoControl; -} SmiCapturePort; - - -/******************************************************************************/ -/* Export Graphic Driver Control */ -/******************************************************************************/ - -typedef struct { - unsigned int isaBase; - unsigned int pciBase; - unsigned int dprBase; - unsigned int vprBase; - unsigned int cprBase; - unsigned int frameAdrs; - unsigned int memSize; - unsigned int mode; - unsigned int gdfIndex; - unsigned int gdfBytesPP; - unsigned int fg; - unsigned int bg; - unsigned int plnSizeX; - unsigned int plnSizeY; - unsigned int winSizeX; - unsigned int winSizeY; - char modeIdent[80]; -} GraphicDevice; - -extern GraphicDevice smi; - - -/******************************************************************************/ -/* Export Graphic Functions */ -/******************************************************************************/ - -void *video_hw_init (void); /* returns GraphicDevice struct or NULL */ - -void video_hw_bitblt ( - unsigned int bpp, /* bytes per pixel */ - unsigned int src_x, /* source pos x */ - unsigned int src_y, /* source pos y */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y /* frame height */ - ); - -void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ); - -void video_set_lut ( - unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -#endif /*_SMI_LYNX_EM_H_ */ diff --git a/include/sound.h b/include/sound.h index a06ab85386..155e1b40e2 100644 --- a/include/sound.h +++ b/include/sound.h @@ -29,6 +29,15 @@ struct sound_codec_info { enum en_sound_codec codec_type; }; +/* + * Generates square wave sound data for 1 second + * + * @param data data buffer pointer + * @param size size of the buffer + * @param freq frequency of the wave + */ +void sound_create_square_wave(unsigned short *data, int size, uint32_t freq); + /* * Initialises audio sub system * @param blob Pointer of device tree node or NULL if none. diff --git a/include/spi_flash.h b/include/spi_flash.h index c488a25a15..5f7f531b92 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -54,7 +54,7 @@ enum spi_dual_flash { * @sector_size: Sector size of this device * @nr_sectors: No.of sectors on this device * @e_rd_cmd: Enum list for read commands - * @flags: Importent param, for flash specific behaviour + * @flags: Important param, for flash specific behaviour */ struct spi_flash_params { const char *name; @@ -90,11 +90,11 @@ extern const struct spi_flash_params spi_flash_params_table[]; * @memory_map: Address of read-only SPI flash access * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read - * @write: Flash write ops: Write len bytes from buf into offeset + * @write: Flash write ops: Write len bytes from buf into offset * Supported cmds: Page Program * @erase: Flash erase ops: Erase len bytes from offset * Supported cmds: Sector erase 4K, 32K, 64K - * return 0 - Sucess, 1 - Failure + * return 0 - Success, 1 - Failure */ struct spi_flash { struct spi_slave *spi; diff --git a/include/spl.h b/include/spl.h index 2bd6e16a0e..a7e41da7fd 100644 --- a/include/spl.h +++ b/include/spl.h @@ -11,10 +11,12 @@ #include #include + /* Boot type */ #define MMCSD_MODE_UNDEFINED 0 #define MMCSD_MODE_RAW 1 #define MMCSD_MODE_FAT 2 +#define MMCSD_MODE_EMMCBOOT 3 struct spl_image_info { const char *name; @@ -60,6 +62,16 @@ void spl_spi_load_image(void); /* Ethernet SPL functions */ void spl_net_load_image(const char *device); +/* USB SPL functions */ +void spl_usb_load_image(void); + +/* SATA SPL functions */ +void spl_sata_load_image(void); + +/* SPL FAT image functions */ +int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename); +int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/include/usb/mv_udc.h b/include/usb/ci_udc.h similarity index 73% rename from include/usb/mv_udc.h rename to include/usb/ci_udc.h index f6c7b5e898..0dee50461e 100644 --- a/include/usb/mv_udc.h +++ b/include/usb/ci_udc.h @@ -6,9 +6,9 @@ */ -#ifndef __MV_UDC_H__ -#define __MV_UDC_H__ +#ifndef __CI_UDC_H__ +#define __CI_UDC_H__ #define EP_MAX_PACKET_SIZE 0x200 #define EP0_MAX_PACKET_SIZE 64 -#endif /* __MV_UDC_H__ */ +#endif /* __CI_UDC_H__ */ diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 734c6cd2f7..70e48f88ee 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -10,6 +10,7 @@ #define __S3C_USB_GADGET #include +#include #include #include #include @@ -19,7 +20,7 @@ /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (4096*4) +#define DMA_BUFFER_SIZE (16*SZ_1K) #define EP0_FIFO_SIZE 64 #define EP_FIFO_SIZE 512 @@ -81,9 +82,6 @@ struct s3c_udc { struct s3c_plat_otg_data *pdata; - void *dma_buf[S3C_MAX_ENDPOINTS+1]; - dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1]; - int ep0state; struct s3c_ep ep[S3C_MAX_ENDPOINTS]; diff --git a/include/usb_ether.h b/include/usb_ether.h index 678c9dff25..35700a21b5 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -40,23 +40,25 @@ struct ueth_data { }; /* - * Function definitions for each USB ethernet driver go here, bracketed by - * #ifdef CONFIG_USB_ETHER_xxx...#endif + * Function definitions for each USB ethernet driver go here + * (declaration is unconditional, compilation is conditional) */ -#ifdef CONFIG_USB_ETHER_ASIX void asix_eth_before_probe(void); int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, struct ueth_data *ss); int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth); -#endif -#ifdef CONFIG_USB_ETHER_SMSC95XX +void mcs7830_eth_before_probe(void); +int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); +int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth); + void smsc95xx_eth_before_probe(void); int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, struct ueth_data *ss); int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth); -#endif #endif /* __USB_ETHER_H__ */ diff --git a/include/usbroothubdes.h b/include/usbroothubdes.h new file mode 100644 index 0000000000..adb70cd6af --- /dev/null +++ b/include/usbroothubdes.h @@ -0,0 +1,129 @@ +/* + * USB virtual root hub descriptors + * + * (C) Copyright 2014 + * Stephen Warren swarren@wwwdotorg.org + * + * Based on ohci-hcd.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __USBROOTHUBDES_H__ +#define __USBROOTHUBDES_H__ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01, /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + * Bit 7: Bus-powered + * 6: Self-powered, + * 5 Remote-wakwup, + * 4..0: resvd + */ + 0x00, /* __u8 MaxPower; */ + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff, /* __u8 ep_bInterval; 255 ms */ +}; + +#ifdef WANT_USB_ROOT_HUB_HUB_DES +static unsigned char root_hub_hub_des[] = { + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff, /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; +#endif + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 32, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '-', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'B', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +#endif diff --git a/include/uuid.h b/include/uuid.h new file mode 100644 index 0000000000..93027c1b28 --- /dev/null +++ b/include/uuid.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __UUID_H__ +#define __UUID_H__ + +/* This is structure is in big-endian */ +struct uuid { + unsigned int time_low; + unsigned short time_mid; + unsigned short time_hi_and_version; + unsigned char clock_seq_hi_and_reserved; + unsigned char clock_seq_low; + unsigned char node[6]; +} __packed; + +enum { + UUID_STR_FORMAT_STD, + UUID_STR_FORMAT_GUID +}; + +#define UUID_STR_LEN 36 +#define UUID_BIN_LEN sizeof(struct uuid) + +#define UUID_VERSION_MASK 0xf000 +#define UUID_VERSION_SHIFT 12 +#define UUID_VERSION 0x4 + +#define UUID_VARIANT_MASK 0xc0 +#define UUID_VARIANT_SHIFT 7 +#define UUID_VARIANT 0x1 + +int uuid_str_valid(const char *uuid); +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format); +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format); +void gen_rand_uuid(unsigned char *uuid_bin); +void gen_rand_uuid_str(char *uuid_str, int str_format); +#endif diff --git a/lib/Makefile b/lib/Makefile index 760340fbde..27e4f78bfd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -60,11 +60,8 @@ obj-$(CONFIG_REGEX) += slre.o obj-y += string.o obj-y += time.o obj-$(CONFIG_TRACE) += trace.o -obj-$(CONFIG_BOOTP_PXE) += uuid.o +obj-$(CONFIG_LIB_UUID) += uuid.o obj-y += vsprintf.o -obj-$(CONFIG_RANDOM_MACADDR) += rand.o -obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o -obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o +obj-$(CONFIG_LIB_RAND) += rand.o -# SEE README.arm-unaligned-accesses -$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2 diff --git a/lib/display_options.c b/lib/display_options.c index 4a972b08a4..4c0c886d61 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -87,11 +87,19 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, { /* linebuf as a union causes proper alignment */ union linebuf { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + uint64_t uq[MAX_LINE_LENGTH_BYTES/sizeof(uint64_t) + 1]; +#endif uint32_t ui[MAX_LINE_LENGTH_BYTES/sizeof(uint32_t) + 1]; uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1]; uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1]; } lb; int i; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + uint64_t x; +#else + uint32_t x; +#endif if (linelen*width > MAX_LINE_LENGTH_BYTES) linelen = MAX_LINE_LENGTH_BYTES / width; @@ -108,14 +116,21 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, /* Copy from memory into linebuf and print hex values */ for (i = 0; i < thislinelen; i++) { - uint32_t x; if (width == 4) x = lb.ui[i] = *(volatile uint32_t *)data; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (width == 8) + x = lb.uq[i] = *(volatile uint64_t *)data; +#endif else if (width == 2) x = lb.us[i] = *(volatile uint16_t *)data; else x = lb.uc[i] = *(volatile uint8_t *)data; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + printf(" %0*llx", width * 2, x); +#else printf(" %0*x", width * 2, x); +#endif data += width; } diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 207314fa72..33265ecfb2 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -32,6 +32,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), @@ -51,8 +52,10 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"), + COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"), + COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), @@ -60,6 +63,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"), COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"), COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), + COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"), + COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -616,3 +621,27 @@ int fdtdec_decode_region(const void *blob, int node, debug("%s: size=%zx\n", __func__, *size); return 0; } + +/** + * Read a flash entry from the fdt + * + * @param blob FDT blob + * @param node Offset of node to read + * @param name Name of node being read + * @param entry Place to put offset and size of this node + * @return 0 if ok, -ve on error + */ +int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, + struct fmap_entry *entry) +{ + u32 reg[2]; + + if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) { + debug("Node '%s' has bad/missing 'reg' property\n", name); + return -FDT_ERR_NOTFOUND; + } + entry->offset = reg[0]; + entry->length = reg[1]; + + return 0; +} diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile index f8eda06c9f..b6c80671b9 100644 --- a/lib/lzma/Makefile +++ b/lib/lzma/Makefile @@ -8,6 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D_LZMA_PROB32 +ccflags-y += -D_LZMA_PROB32 obj-y += LzmaDec.o LzmaTools.o diff --git a/lib/time.c b/lib/time.c index 8085aa40d1..73c3b6ad7f 100644 --- a/lib/time.c +++ b/lib/time.c @@ -60,6 +60,11 @@ static unsigned long long notrace tick_to_time(uint64_t tick) return tick; } +int __weak timer_init(void) +{ + return 0; +} + ulong __weak get_timer(ulong base) { return tick_to_time(get_ticks()) - base; diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c index e872591cd1..814ed18329 100644 --- a/lib/tizen/tizen.c +++ b/lib/tizen/tizen.c @@ -9,18 +9,25 @@ #include #include -#include "tizen_hd_logo.h" -#include "tizen_hd_logo_data.h" +#include "tizen_logo_16bpp.h" +#include "tizen_logo_16bpp_gzip.h" void get_tizen_logo_info(vidinfo_t *vid) { - switch (vid->resolution) { - case HD_RESOLUTION: - vid->logo_width = TIZEN_HD_LOGO_WIDTH; - vid->logo_height = TIZEN_HD_LOGO_HEIGHT; - vid->logo_addr = (ulong)tizen_hd_logo; + switch (vid->vl_bpix) { + case 4: + vid->logo_width = TIZEN_LOGO_16BPP_WIDTH; + vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT; + vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET; + vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET; +#if defined(CONFIG_VIDEO_BMP_GZIP) + vid->logo_addr = (ulong)tizen_logo_16bpp_gzip; +#else + vid->logo_addr = (ulong)tizen_logo_16bpp; +#endif break; default: + vid->logo_addr = 0; break; } } diff --git a/lib/tizen/tizen_hd_logo.h b/lib/tizen/tizen_hd_logo.h deleted file mode 100644 index 28377b75c9..0000000000 --- a/lib/tizen/tizen_hd_logo.h +++ /dev/null @@ -1,5057 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_H_ -#define _TIZEN_HD_LOGO_H_ - -unsigned char tizen_hd_logo[]={ -0x1f,0x8b,0x08,0x08,0xe0,0x6f,0x8f,0x4f,0x00,0x03,0x74,0x72,0x61,0x74,0x73,0x2e, -0x62,0x6d,0x70,0x00,0xbc,0x5c,0xe9,0x53,0x1c,0x57,0x92,0xaf,0x6a,0xa0,0x81,0xa6, -0xb9,0x1b,0x04,0x48,0x02,0x04,0x7d,0xd0,0xdd,0x1c,0x12,0xba,0xd1,0x61,0x59,0x48, -0x96,0x67,0xc6,0xf6,0x8e,0x2f,0xc5,0x44,0xec,0x7c,0xd9,0x88,0x89,0x99,0xfd,0x60, -0x8f,0x23,0xc6,0x3b,0xf6,0xce,0x8c,0x67,0x6d,0x79,0xac,0x70,0x6c,0x38,0x24,0x3c, -0x06,0x74,0x41,0x83,0x0c,0x36,0x97,0x04,0x88,0xc3,0x5c,0x7d,0x09,0x79,0x3d,0x92, -0x6c,0x61,0x4b,0x8a,0x18,0xeb,0x1f,0xd9,0x3f,0x60,0x2b,0xab,0x3b,0xab,0xf3,0x65, -0xbd,0x6a,0xba,0x25,0x79,0x2b,0x78,0x51,0xd5,0x55,0xaf,0xde,0xcb,0x97,0x99,0x2f, -0x7f,0x99,0xf9,0x5e,0x71,0xfc,0xc5,0xa5,0xc9,0x1c,0x05,0x8e,0x7d,0x5a,0x69,0xd1, -0xca,0xff,0xaa,0x8a,0xf2,0x9f,0xda,0x59,0x55,0x1a,0xf5,0xfb,0x1f,0x24,0x9f,0xf3, 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-0x2b,0xd0,0xa6,0x4a,0x06,0x22,0x60,0xac,0xc1,0xcb,0x51,0xd8,0x93,0x53,0x3e,0x9c, -0xd2,0xdd,0x64,0x9e,0x98,0xeb,0xd6,0x85,0x7c,0xcd,0x14,0x38,0xfd,0x43,0x71,0x78, -0x25,0xf8,0x96,0x01,0x8d,0xe8,0x8c,0x0a,0x3c,0x26,0xde,0xab,0x28,0x5e,0x3f,0x6c, -0xdd,0xbc,0x57,0xdf,0x3e,0xc1,0x43,0xc2,0xe3,0xe4,0xc2,0x61,0x15,0xf9,0xf1,0x5f, -0x69,0xd7,0x24,0x79,0xb6,0xa9,0x03,0x00,0x00 -}; - -#endif /* _TIZEN_HD_LOGO_H_ */ diff --git a/lib/tizen/tizen_hd_logo_data.h b/lib/tizen/tizen_hd_logo_data.h deleted file mode 100644 index 95e5f827eb..0000000000 --- a/lib/tizen/tizen_hd_logo_data.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_DATA_H_ -#define _TIZEN_HD_LOGO_DATA_H_ - -#define TIZEN_HD_LOGO_WIDTH 520 -#define TIZEN_HD_LOGO_HEIGHT 120 -#define TIZEN_HD_LOGO_BPP 32 - -#endif /* _TIZEN_HD_LOGO_DATA_H_ */ diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h new file mode 100644 index 0000000000..0057c11f0b --- /dev/null +++ b/lib/tizen/tizen_logo_16bpp.h @@ -0,0 +1,7935 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __TIZEN_LOGO_16BPP__ +#define __TIZEN_LOGO_16BPP__ + +#define TIZEN_LOGO_16BPP_WIDTH 452 +#define TIZEN_LOGO_16BPP_HEIGHT 140 + +/* Center align offsets for word "TIZEN" */ +#define TIZEN_LOGO_16BPP_X_OFFSET (16) +#define TIZEN_LOGO_16BPP_Y_OFFSET (-20) + +/* Format: BMP RGB565 16BPP 452x140 */ +unsigned char tizen_logo_16bpp[] = { +0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, +0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, +0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0xaf,0x09,0x0e,0x85,0x84,0x1a,0xae,0x9f,0x3d,0x13,0x7b,0x7a,0x3e,0xb1,0x4b,0x38, +0x3c,0xf3,0x96,0x18,0x21,0x23,0x24,0xd4,0x04,0x1d,0xec,0x3e,0x35,0xb0,0x3b,0x4e, +0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41, +0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3, +0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0, +0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48, +0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00}; +#endif diff --git a/lib/uuid.c b/lib/uuid.c index c48bf38362..f6b4423551 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -4,21 +4,58 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include -#include "common.h" +#include +#include +#include +#include +#include /* - * This is what a UUID string looks like. + * UUID - Universally Unique IDentifier - 128 bits unique number. + * There are 5 versions and one variant of UUID defined by RFC4122 + * specification. A UUID contains a set of fields. The set varies + * depending on the version of the UUID, as shown below: + * - time, MAC address(v1), + * - user ID(v2), + * - MD5 of name or URL(v3), + * - random data(v4), + * - SHA-1 of name or URL(v5), * - * x is a hexadecimal character. fields are separated by '-'s. When converting - * to a binary UUID, le means the field should be converted to little endian, - * and be means it should be converted to big endian. + * Layout of UUID: + * timestamp - 60-bit: time_low, time_mid, time_hi_and_version + * version - 4 bit (bit 4 through 7 of the time_hi_and_version) + * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low + * variant: - bit 6 and 7 of clock_seq_hi_and_reserved + * node - 48 bit + * + * source: https://www.ietf.org/rfc/rfc4122.txt + * + * UUID binary format (16 bytes): + * + * 4B-2B-2B-2B-6B (big endian - network byte order) + * + * UUID string is 36 length of characters (36 bytes): * * 0 9 14 19 24 * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + * be be be be be + * + * where x is a hexadecimal character. Fields are separated by '-'s. + * When converting to a binary UUID, le means the field should be converted + * to little endian and be means it should be converted to big endian. + * + * UUID is also used as GUID (Globally Unique Identifier) with the same binary + * format but it differs in string format like below. + * + * GUID: + * 0 9 14 19 24 + * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx * le le le be be + * + * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id. */ - int uuid_str_valid(const char *uuid) { int i, valid; @@ -37,33 +74,182 @@ int uuid_str_valid(const char *uuid) } } - if (i != 36 || !valid) + if (i != UUID_STR_LEN || !valid) return 0; return 1; } -void uuid_str_to_bin(const char *uuid, unsigned char *out) +/* + * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data. + * + * @param uuid_str - pointer to UUID or GUID string [37B] + * @param uuid_bin - pointer to allocated array for big endian output [16B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format) { uint16_t tmp16; uint32_t tmp32; uint64_t tmp64; - if (!uuid || !out) - return; + if (!uuid_str_valid(uuid_str)) + return -EINVAL; - tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16)); - memcpy(out, &tmp32, 4); + if (str_format == UUID_STR_FORMAT_STD) { + tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 9, NULL, 16)); - memcpy(out + 4, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 14, NULL, 16)); - memcpy(out + 6, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } else { + tmp32 = cpu_to_le32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_be16(simple_strtoul(uuid + 19, NULL, 16)); - memcpy(out + 8, &tmp16, 2); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16)); - memcpy(out + 10, (char *)&tmp64 + 2, 6); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } + + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 19, NULL, 16)); + memcpy(uuid_bin + 8, &tmp16, 2); + + tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16)); + memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6); + + return 0; } + +/* + * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID. + * + * @param uuid_bin - pointer to binary data of UUID (big endian) [16B] + * @param uuid_str - pointer to allocated array for output string [37B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) +{ + const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 *char_order; + int i; + + /* + * UUID and GUID bin data - always in big endian: + * 4B-2B-2B-2B-6B + * be be be be be + */ + if (str_format == UUID_STR_FORMAT_STD) + char_order = uuid_char_order; + else + char_order = guid_char_order; + + for (i = 0; i < 16; i++) { + sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]); + uuid_str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *uuid_str++ = '-'; + break; + } + } +} + +/* + * gen_rand_uuid() - this function generates a random binary UUID version 4. + * In this version all fields beside 4 bits of version and + * 2 bits of variant are randomly generated. + * + * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian. +*/ +#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) +void gen_rand_uuid(unsigned char *uuid_bin) +{ + struct uuid uuid; + unsigned int *ptr = (unsigned int *)&uuid; + int i; + + /* Set all fields randomly */ + for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) + *(ptr + i) = cpu_to_be32(rand()); + + clrsetbits_be16(&uuid.time_hi_and_version, + UUID_VERSION_MASK, + UUID_VERSION << UUID_VERSION_SHIFT); + + clrsetbits_8(&uuid.clock_seq_hi_and_reserved, + UUID_VARIANT_MASK, + UUID_VARIANT << UUID_VARIANT_SHIFT); + + memcpy(uuid_bin, &uuid, sizeof(struct uuid)); +} + +/* + * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string + * formats UUID or GUID. + * + * @param uuid_str - pointer to allocated array [37B]. + * @param - uuid output type: UUID - 0, GUID - 1 + */ +void gen_rand_uuid_str(char *uuid_str, int str_format) +{ + unsigned char uuid_bin[UUID_BIN_LEN]; + + /* Generate UUID (big endian) */ + gen_rand_uuid(uuid_bin); + + /* Convert UUID bin to UUID or GUID formated STRING */ + uuid_bin_to_str(uuid_bin, uuid_str, str_format); +} + +#ifdef CONFIG_CMD_UUID +int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char uuid[UUID_STR_LEN + 1]; + int str_format; + + if (!strcmp(argv[0], "uuid")) + str_format = UUID_STR_FORMAT_STD; + else + str_format = UUID_STR_FORMAT_GUID; + + if (argc > 2) + return CMD_RET_USAGE; + + gen_rand_uuid_str(uuid, str_format); + + if (argc == 1) + printf("%s\n", uuid); + else + setenv(argv[1], uuid); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "UUID - generate random Universally Unique Identifier", + "[]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. uuid uuid_env" +); + +U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "GUID - generate Globally Unique Identifier based on random UUID", + "[]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. guid guid_env" +); +#endif /* CONFIG_CMD_UUID */ +#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */ diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 82e5c13653..60874dae3e 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -750,6 +750,7 @@ repeat: ADDCH(str, '\0'); if (str > end) end[-1] = '\0'; + --str; } #else *str = '\0'; diff --git a/mkconfig b/mkconfig index b96c81fbc2..cd911a9dc7 100755 --- a/mkconfig +++ b/mkconfig @@ -23,7 +23,7 @@ options="" if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then # Automatic mode - line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' boards.cfg` + line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' $srctree/boards.cfg` if [ -z "$line" ] ; then echo "make: *** No rule to make target \`$2_config'. Stop." >&2 exit 1 @@ -55,7 +55,9 @@ CONFIG_NAME="${7%_config}" arch="$2" cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'` spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'` -if [ "$6" = "-" ] ; then +if [ "$6" = "" ] ; then + board= +elif [ "$6" = "-" ] ; then board=${BOARD_NAME} else board="$6" @@ -101,10 +103,10 @@ fi # # Create link to architecture specific headers # -if [ "$SRCTREE" != "$OBJTREE" ] ; then - mkdir -p ${OBJTREE}/include - LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/ - cd ${OBJTREE}/include +if [ -n "$KBUILD_SRC" ] ; then + mkdir -p ${objtree}/include + LNPREFIX=${srctree}/arch/${arch}/include/asm/ + cd ${objtree}/include mkdir -p asm else cd arch/${arch}/include @@ -123,8 +125,8 @@ if [ "${arch}" = "arm" ] ; then ln -s ${LNPREFIX}proc-armv asm/proc fi -if [ "$SRCTREE" = "$OBJTREE" ] ; then - cd ${SRCTREE}/include +if [ -z "$KBUILD_SRC" ] ; then + cd ${srctree}/include fi # @@ -177,8 +179,8 @@ echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h [ "${soc}" ] && echo "#define CONFIG_SYS_SOC \"${soc}\"" >> config.h +[ "${board}" ] && echo "#define CONFIG_BOARDDIR board/$BOARDDIR" >> config.h cat << EOF >> config.h -#define CONFIG_BOARDDIR board/$BOARDDIR #include #include #include diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile deleted file mode 100644 index 022a20555f..0000000000 --- a/nand_spl/board/amcc/acadia/Makefile +++ /dev/null @@ -1,103 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o cache.o -COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ - $(nandobj)System.map - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map -o $@ - -$(nandobj)System.map: $(nandobj)u-boot-spl - @$(NM) $< | \ - grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ - sort > $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)cache.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ - -$(obj)gpio.c: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@ - -$(obj)ndfc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ - -$(obj)resetvec.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ - -# from board directory -$(obj)memory.c: - @rm -f $@ - ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@ - -$(obj)pll.c: - @rm -f $@ - ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk deleted file mode 100644 index d9ff10d5c2..0000000000 --- a/nand_spl/board/amcc/acadia/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xf8004000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xf8008000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds deleted file mode 100644 index a7dac121d3..0000000000 --- a/nand_spl/board/amcc/acadia/u-boot.lds +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xf8004ffc : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - nand_boot.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile deleted file mode 100644 index d413a480ad..0000000000 --- a/nand_spl/board/amcc/bamboo/Makefile +++ /dev/null @@ -1,91 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o init.o resetvec.o -COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)ndfc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ - -$(obj)resetvec.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ - -# from board directory -$(obj)init.S: - @rm -f $@ - ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)sdram.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/bamboo/config.mk b/nand_spl/board/amcc/bamboo/config.mk deleted file mode 100644 index 6cc8fa30f3..0000000000 --- a/nand_spl/board/amcc/bamboo/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EP Reference Platform (Bamboo) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in i-cache here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c deleted file mode 100644 index df0dfc1a0d..0000000000 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void wait_init_complete(void) -{ - u32 val; - - do { - mfsdram(SDRAM0_MCSTS, val); - } while (!(val & 0x80000000)); -} - -/* - * phys_size_t initdram(int board_type) - * - * As the name already indicates, this function is called very early - * from start.S and configures the SDRAM with fixed values. This is needed, - * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has - * not enough free space to implement the complete I2C SPD DDR autodetection - * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM - * when booting from NAND flash. - * - * Note: - * As found out by Eugene O'Brien , the fixed - * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM - * modules are still plugged in. So it is recommended to remove the DIMM - * modules while using the NAND booting code with the fixed SDRAM setup! - */ -phys_size_t initdram(int board_type) -{ - /* - * Soft-reset SDRAM controller. - */ - mtsdr(SDR0_SRST, SDR0_SRST_DMC); - mtsdr(SDR0_SRST, 0x00000000); - - /* - * Disable memory controller. - */ - mtsdram(SDRAM0_CFG0, 0x00000000); - - /* - * Setup some default - */ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x00082001); - mtsdram(SDRAM0_TR0, 0x41094012); - mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ - - /* - * Enable the controller, then wait for DCEN to complete - */ - mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/ - wait_init_complete(); - - return CONFIG_SYS_MBYTES_SDRAM << 20; -} diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds deleted file mode 100644 index c432368175..0000000000 --- a/nand_spl/board/amcc/bamboo/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0x00800FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - sdram.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile deleted file mode 100644 index b2ef03f78b..0000000000 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ /dev/null @@ -1,96 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS := start.o -SOBJS += init.o -SOBJS += resetvec.o -COBJS := ddr2_fixed.o -COBJS += nand_boot.o -COBJS += nand_ecc.o -COBJS += ndfc.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)ndfc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ - -$(obj)resetvec.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ - -# from board directory -$(obj)init.S: - @rm -f $@ - ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)ddr2_fixed.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk deleted file mode 100644 index 780b7ae375..0000000000 --- a/nand_spl/board/amcc/canyonlands/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 460EX Reference Platform (Canyonlands) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE3003000 - -# PAD_TO used to generate a 128kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000 -PAD_TO = 0xE3023000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c deleted file mode 100644 index ce8515d513..0000000000 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * This code can configure those two Crucial SODIMM's: - * - * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) - * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) - * - */ - -#define TEST_ADDR 0x10000000 -#define TEST_MAGIC 0x11223344 - -static void wait_init_complete(void) -{ - u32 val; - - do { - mfsdram(SDRAM_MCSTAT, val); - } while (!(val & 0x80000000)); -} - -static void ddr_start(void) -{ - mtsdram(SDRAM_MCOPT2, 0x28000000); - wait_init_complete(); -} - -static void ddr_init_common(void) -{ - /* - * Reset the DDR-SDRAM controller. - */ - mtsdr(SDR0_SRST, SDR0_SRST0_DMC); - mtsdr(SDR0_SRST, 0x00000000); - - /* - * These values are cloned from a running NOR booting - * Canyonlands with SPD-DDR2 detection and calibration - * enabled. This will only work for the same memory - * configuration as used here: - * - */ - mtsdram(SDRAM_MCOPT2, 0x00000000); - mtsdram(SDRAM_MODT0, 0x01000000); - mtsdram(SDRAM_WRDTR, 0x82000823); - mtsdram(SDRAM_CLKTR, 0x40000000); - mtsdram(SDRAM_MB0CF, 0x00000201); - mtsdram(SDRAM_RTR, 0x06180000); - mtsdram(SDRAM_SDTR1, 0x80201000); - mtsdram(SDRAM_SDTR2, 0x42103243); - mtsdram(SDRAM_SDTR3, 0x0A0D0D16); - mtsdram(SDRAM_MMODE, 0x00000632); - mtsdram(SDRAM_MEMODE, 0x00000040); - mtsdram(SDRAM_INITPLR0, 0xB5380000); - mtsdram(SDRAM_INITPLR1, 0x82100400); - mtsdram(SDRAM_INITPLR2, 0x80820000); - mtsdram(SDRAM_INITPLR3, 0x80830000); - mtsdram(SDRAM_INITPLR4, 0x80810040); - mtsdram(SDRAM_INITPLR5, 0x80800532); - mtsdram(SDRAM_INITPLR6, 0x82100400); - mtsdram(SDRAM_INITPLR7, 0x8A080000); - mtsdram(SDRAM_INITPLR8, 0x8A080000); - mtsdram(SDRAM_INITPLR9, 0x8A080000); - mtsdram(SDRAM_INITPLR10, 0x8A080000); - mtsdram(SDRAM_INITPLR11, 0x80000432); - mtsdram(SDRAM_INITPLR12, 0x808103C0); - mtsdram(SDRAM_INITPLR13, 0x80810040); - mtsdram(SDRAM_RDCC, 0x40000000); - mtsdram(SDRAM_RQDC, 0x80000038); - mtsdram(SDRAM_RFDC, 0x00000257); - - mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ -} - -phys_size_t initdram(int board_type) -{ - /* - * First try init for this module: - * - * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) - */ - - ddr_init_common(); - - /* - * Crucial CT6464AC667.8FB - 512MB SO-DIMM - */ - mtdcr(SDRAM_R0BAS, 0x0000F800); - mtdcr(SDRAM_R1BAS, 0x0400F800); - mtsdram(SDRAM_MCOPT1, 0x05122000); - mtsdram(SDRAM_CODT, 0x02800021); - mtsdram(SDRAM_MB1CF, 0x00000201); - - ddr_start(); - - /* - * Now test if the dual-ranked module is really installed - * by checking an address in the upper 256MByte region - */ - out_be32((void *)TEST_ADDR, TEST_MAGIC); - if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) { - /* - * The test failed, so we assume that the single - * ranked module is installed: - * - * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) - */ - - ddr_init_common(); - - mtdcr(SDRAM_R0BAS, 0x0000F000); - mtsdram(SDRAM_MCOPT1, 0x05322000); - mtsdram(SDRAM_CODT, 0x00800021); - - ddr_start(); - } - - return CONFIG_SYS_MBYTES_SDRAM << 20; -} diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds deleted file mode 100644 index 6383b1a38f..0000000000 --- a/nand_spl/board/amcc/canyonlands/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xE3003FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - ddr2_fixed.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile deleted file mode 100644 index 5899b9efe8..0000000000 --- a/nand_spl/board/amcc/kilauea/Makefile +++ /dev/null @@ -1,92 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o cache.o -COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)44x_spd_ddr2.c: $(obj)ecc.h - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@ - -$(obj)cache.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ - -$(obj)ecc.h: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@ - -$(obj)ndfc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ - -$(obj)resetvec.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ - -# from drivers/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk deleted file mode 100644 index b596b1406c..0000000000 --- a/nand_spl/board/amcc/kilauea/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EX Reference Platform (Kilauea) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into SDRAM since we can't access the NAND -# controller at CS0 while running from this location. So we set -# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds deleted file mode 100644 index d7262e6c53..0000000000 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0x00800FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - nand_boot.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile deleted file mode 100644 index fea6c4e489..0000000000 --- a/nand_spl/board/amcc/sequoia/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -# -# (C) Copyright 2006-2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o init.o resetvec.o -COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)denali_data_eye.c: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@ - -$(obj)ndfc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ - -$(obj)resetvec.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ - -# from board directory -$(obj)init.S: - @rm -f $@ - ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@ - -$(obj)sdram.c: - @rm -f $@ - @rm -f $(obj)sdram.h - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@ - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk deleted file mode 100644 index ede7964d9f..0000000000 --- a/nand_spl/board/amcc/sequoia/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE0013000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xE0017000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds deleted file mode 100644 index 45c0162af6..0000000000 --- a/nand_spl/board/amcc/sequoia/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2006-2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xE0013FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - sdram.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index c49a6e0b8f..f4e7854d50 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -6,83 +6,66 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y PAD_TO := 0xfff04000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files -$(obj)start.S: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ +$(obj)/start.S: + ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@ -$(obj)nand_boot_fsl_elbc.c: - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ +$(obj)/nand_boot_fsl_elbc.c: + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)sdram.c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ +$(obj)/sdram.c: + ln -sf $(srctree)/board/$(BOARDDIR)/sdram.c $@ -$(obj)$(BOARD).c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ +$(obj)/$(BOARD).c: + ln -sf $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@ -$(obj)ns16550.c: - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ +$(obj)/ns16550.c: + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)spl_minimal.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ +$(obj)/spl_minimal.c: + ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ -$(obj)cache.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ +$(obj)/cache.c: + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)time.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@ +$(obj)/time.c: + ln -sf $(srctree)/arch/powerpc/lib/time.c $@ -$(obj)ticks.S: - ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +$(obj)/ticks.S: + ln -sf $(srctree)/arch/powerpc/lib/ticks.S $@ diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 62330815cc..c639b126fd 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -7,112 +7,89 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ + ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ + ln -s $(srctree)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@ diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 62330815cc..c639b126fd 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -7,112 +7,89 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ + ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ + ln -s $(srctree)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@ diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 62330815cc..c639b126fd 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -7,112 +7,89 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ + ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ + ln -s $(srctree)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@ diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index dbdfa19895..38f6726449 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -3,111 +3,89 @@ # # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y + PAD_TO := 0xfff01000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@ + ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@ + ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ + ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ + ln -s $(srctree)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ - ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@ + ln -sf $(srctree)/$(CPUDIR)/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ - ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@ + ln -sf $(srctree)/$(CPUDIR)/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ - ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@ + ln -sf $(srctree)/$(CPUDIR)/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@ diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 62330815cc..c639b126fd 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -7,112 +7,89 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -sf $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ + ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -sf $(srctree)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ + ln -s $(srctree)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ + ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@ diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index 90f132c34c..657f65fd22 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -7,91 +7,75 @@ # SPDX-License-Identifier: GPL-2.0+ # -NAND_SPL := y +include $(srctree)/$(src)/config.mk -include $(TOPDIR)/config.mk +nandobj := $(objtree)/nand_spl/ -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files -$(obj)start.S: +$(obj)/start.S: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ + ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ + ln -s $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)sdram.c: +$(obj)/sdram.c: @rm -f $@ - ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ + ln -s $(srctree)/board/$(BOARDDIR)/sdram.c $@ -$(obj)$(BOARD).c: +$(obj)/$(BOARD).c: @rm -f $@ - ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ + ln -s $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ - ln -s $(SRCTREE)/drivers/serial/ns16550.c $@ + ln -s $(srctree)/drivers/serial/ns16550.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ + ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@ + ln -s $(srctree)/arch/powerpc/lib/cache.c $@ -$(obj)time.c: +$(obj)/time.c: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@ + ln -s $(srctree)/arch/powerpc/lib/time.c $@ -$(obj)ticks.S: +$(obj)/ticks.S: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + ln -s $(srctree)/arch/powerpc/lib/ticks.S $@ diff --git a/board/sheldon/simpc8313/config.mk b/nand_spl/board/sheldon/simpc8313/config.mk similarity index 100% rename from board/sheldon/simpc8313/config.mk rename to nand_spl/board/sheldon/simpc8313/config.mk diff --git a/net/Makefile b/net/Makefile index 31aadc2ffc..942595021d 100644 --- a/net/Makefile +++ b/net/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_CMD_NET) += arp.o obj-$(CONFIG_CMD_NET) += bootp.o diff --git a/net/bootp.c b/net/bootp.c index 4300f1c2f1..189a003835 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -439,7 +439,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, *e++ = 17; *e++ = 0; /* type 0 - UUID */ - uuid_str_to_bin(uuid, e); + uuid_str_to_bin(uuid, e, UUID_STR_FORMAT_STD); e += 16; } else { printf("Invalid pxeuuid: %s\n", uuid); diff --git a/net/eth.c b/net/eth.c index c96e767e8e..32bd10c829 100644 --- a/net/eth.c +++ b/net/eth.c @@ -279,7 +279,7 @@ int eth_initialize(bd_t *bis) eth_current = NULL; bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile index ae56a82af3..5c2e804d90 100644 --- a/post/lib_powerpc/fpu/Makefile +++ b/post/lib_powerpc/fpu/Makefile @@ -5,20 +5,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += 20001122-1.o -obj-y += 20010114-2.o -obj-y += 20010226-1.o -obj-y += 980619-1.o -obj-y += acc1.o -obj-y += compare-fp-1.o -obj-y += fpu.o -obj-y += mul-subnormal-single-1.o -obj-y += darwin-ldouble.o +objs-before-objcopy := 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o \ + acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o +targets += $(objs-before-objcopy) -CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//) -CFLAGS += -mhard-float -fkeep-inline-functions +# remove -msoft-float flag +$(foreach m, $(objs-before-objcopy), $(eval CFLAGS_REMOVE_$m := -msoft-float)) +ccflags-y := -mhard-float -fkeep-inline-functions -$(obj)%.o: %.c - $(CC) $(ALL_CFLAGS) -o $@.fp $< -c - $(OBJCOPY) -R .gnu.attributes $@.fp $@ - rm -f $@.fp +# Do not delete intermidiate files (*.o) +.SECONDARY: $(call objectify, $(objs-before-objcopy)) + +obj-y := $(objs-before-objcopy:.o=_.o) + +OBJCOPYFLAGS := -R .gnu.attributes +$(obj)/%_.o: $(obj)/%.o FORCE + $(call if_changed,objcopy) diff --git a/rules.mk b/rules.mk deleted file mode 100644 index f4510b7cb6..0000000000 --- a/rules.mk +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2006-2013 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -######################################################################### - -_depend: $(obj).depend - -# Split the source files into two camps: those in the current directory, and -# those somewhere else. For the first camp we want to support CPPFLAGS_ -# and for the second we don't / can't. -PWD_SRCS := $(filter $(notdir $(SRCS)),$(SRCS)) -OTHER_SRCS := $(filter-out $(notdir $(SRCS)),$(SRCS)) - -# This is a list of dependency files to generate -DEPS := $(basename $(patsubst %,$(obj).depend.%,$(PWD_SRCS))) - -# Join all the dependencies into a single file, in three parts -# 1 .Concatenate all the generated depend files together -# 2. Add in the deps from OTHER_SRCS which we couldn't process -# 3. Add in the HOSTSRCS -$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \ - $(HOSTSRCS) - cat /dev/null $(DEPS) >$@ - @for f in $(OTHER_SRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ - done - @for f in $(HOSTSRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ - done - -MAKE_DEPEND = $(CC) -M $(CPPFLAGS) $(EXTRA_CPPFLAGS_DEP) \ - -MQ $(addsuffix .o,$(obj)$(basename $<)) $< >$@ - - -$(obj).depend.%: %.c - $(MAKE_DEPEND) - -$(obj).depend.%: %.S - $(MAKE_DEPEND) - -$(HOSTOBJS): $(obj)%.o: %.c - $(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c -$(NOPEDOBJS): $(obj)%.o: %.c - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c - -######################################################################### diff --git a/scripts/.gitignore b/scripts/.gitignore new file mode 100644 index 0000000000..82bc06ef98 --- /dev/null +++ b/scripts/.gitignore @@ -0,0 +1,4 @@ +# +# Generated files +# +docproc diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include new file mode 100644 index 0000000000..650457191a --- /dev/null +++ b/scripts/Kbuild.include @@ -0,0 +1,284 @@ +#### +# kbuild: Generic definitions + +# Convenient variables +comma := , +squote := ' +empty := +space := $(empty) $(empty) + +### +# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o +dot-target = $(dir $@).$(notdir $@) + +### +# The temporary file to save gcc -MD generated dependencies must not +# contain a comma +depfile = $(subst $(comma),_,$(dot-target).d) + +### +# filename of target with directory and extension stripped +basetarget = $(basename $(notdir $@)) + +### +# filename of first prerequisite with directory and extension stripped +baseprereq = $(basename $(notdir $<)) + +### +# Escape single quote for use in echo statements +escsq = $(subst $(squote),'\$(squote)',$1) + +### +# Easy method for doing a status message + kecho := : + quiet_kecho := echo +silent_kecho := : +kecho := $($(quiet)kecho) + +### +# filechk is used to check if the content of a generated file is updated. +# Sample usage: +# define filechk_sample +# echo $KERNELRELEASE +# endef +# version.h : Makefile +# $(call filechk,sample) +# The rule defined shall write to stdout the content of the new file. +# The existing file will be compared with the new one. +# - If no file exist it is created +# - If the content differ the new file is used +# - If they are equal no change, and no timestamp update +# - stdin is piped in from the first prerequisite ($<) so one has +# to specify a valid file as first prerequisite (often the kbuild file) +define filechk + $(Q)set -e; \ + $(kecho) ' CHK $@'; \ + mkdir -p $(dir $@); \ + $(filechk_$(1)) < $< > $@.tmp; \ + if [ -r $@ ] && cmp -s $@ $@.tmp; then \ + rm -f $@.tmp; \ + else \ + $(kecho) ' UPD $@'; \ + mv -f $@.tmp $@; \ + fi +endef + +###### +# gcc support functions +# See documentation in Documentation/kbuild/makefiles.txt + +# cc-cross-prefix +# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-) +# Return first prefix where a prefix$(CC) is found in PATH. +# If no $(CC) found in PATH with listed prefixes return nothing +cc-cross-prefix = \ + $(word 1, $(foreach c,$(1), \ + $(shell set -e; \ + if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \ + echo $(c); \ + fi))) + +# output directory for tests below +TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/) + +# try-run +# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise) +# Exit code chooses option. "$$TMP" is can be used as temporary file and +# is automatically cleaned up. +# modifed for U-Boot: prevent cc-option from leaving .*.su files +try-run = $(shell set -e; \ + TMP="$(TMPOUT).$$$$.tmp"; \ + TMPO="$(TMPOUT).$$$$.o"; \ + TMPSU="$(TMPOUT).$$$$.su"; \ + if ($(1)) >/dev/null 2>&1; \ + then echo "$(2)"; \ + else echo "$(3)"; \ + fi; \ + rm -f "$$TMP" "$$TMPO" "$$TMPSU") + +# as-option +# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,) + +as-option = $(call try-run,\ + $(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2)) + +# as-instr +# Usage: cflags-y += $(call as-instr,instr,option1,option2) + +as-instr = $(call try-run,\ + printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3)) + +# cc-option +# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586) + +cc-option = $(call try-run,\ + $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2)) + +# cc-option-yn +# Usage: flag := $(call cc-option-yn,-march=winchip-c6) +cc-option-yn = $(call try-run,\ + $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n) + +# cc-option-align +# Prefix align with either -falign or -malign +cc-option-align = $(subst -functions=0,,\ + $(call cc-option,-falign-functions=0,-malign-functions=0)) + +# cc-disable-warning +# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable) +cc-disable-warning = $(call try-run,\ + $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) + +# cc-version +# Usage gcc-ver := $(call cc-version) +cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC)) + +# cc-fullversion +# Usage gcc-ver := $(call cc-fullversion) +cc-fullversion = $(shell $(CONFIG_SHELL) \ + $(srctree)/scripts/gcc-version.sh -p $(CC)) + +# cc-ifversion +# Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1) +cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3)) + +# added for U-Boot +binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) + +# cc-ldoption +# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) +cc-ldoption = $(call try-run,\ + $(CC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2)) + +# ld-option +# Usage: LDFLAGS += $(call ld-option, -X) +ld-option = $(call try-run,\ + $(CC) -x c /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2)) + +# ar-option +# Usage: KBUILD_ARFLAGS := $(call ar-option,D) +# Important: no spaces around options +ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2)) + +###### + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= +# Usage: +# $(Q)$(MAKE) $(build)=dir +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj= +# Usage: +# $(Q)$(MAKE) $(modbuiltin)=dir +modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj + +# Prefix -I with $(srctree) if it is not an absolute path. +# skip if -I has no parameter +addtree = $(if $(patsubst -I%,%,$(1)), \ +$(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1)) + +# Find all -I options and call addtree +flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o))) + +# echo command. +# Short version is used, if $(quiet) equals `quiet_', otherwise full one. +echo-cmd = $(if $($(quiet)cmd_$(1)),\ + echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';) + +# printing commands +cmd = @$(echo-cmd) $(cmd_$(1)) + +# Add $(obj)/ for paths that are not absolute +objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o))) + +### +# if_changed - execute command if any prerequisite is newer than +# target, or command line has changed +# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies +# including used config symbols +# if_changed_rule - as if_changed but execute rule instead +# See Documentation/kbuild/makefiles.txt for more info + +ifneq ($(KBUILD_NOCMDDEP),1) +# Check if both arguments has same arguments. Result is empty string if equal. +# User may override this check using make KBUILD_NOCMDDEP=1 +arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \ + $(filter-out $(cmd_$@), $(cmd_$(1))) ) +else +arg-check = $(if $(strip $(cmd_$@)),,1) +endif + +# >'< substitution is for echo to work, +# >$< substitution to preserve $ when reloading .cmd file +# note: when using inline perl scripts [perl -e '...$$t=1;...'] +# in $(cmd_xxx) double $$ your perl vars +make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1)))))) + +# Find any prerequisites that is newer than target or that does not exist. +# PHONY targets skipped in both cases. +any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^) + +# Execute command if command has changed or prerequisite(s) are updated. +# +if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ + @set -e; \ + $(echo-cmd) $(cmd_$(1)); \ + echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) + +# Execute the command and also postprocess generated .d dependencies file. +if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \ + @set -e; \ + $(echo-cmd) $(cmd_$(1)); \ + scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\ + rm -f $(depfile); \ + mv -f $(dot-target).tmp $(dot-target).cmd) + +# Usage: $(call if_changed_rule,foo) +# Will check if $(cmd_foo) or any of the prerequisites changed, +# and if so will execute $(rule_foo). +if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \ + @set -e; \ + $(rule_$(1))) + +### +# why - tell why a a target got build +# enabled by make V=2 +# Output (listed in the order they are checked): +# (1) - due to target is PHONY +# (2) - due to target missing +# (3) - due to: file1.h file2.h +# (4) - due to command line change +# (5) - due to missing .cmd file +# (6) - due to target not in $(targets) +# (1) PHONY targets are always build +# (2) No target, so we better build it +# (3) Prerequisite is newer than target +# (4) The command line stored in the file named dir/.target.cmd +# differed from actual command line. This happens when compiler +# options changes +# (5) No dir/.target.cmd file (used to store command line) +# (6) No dir/.target.cmd file and target not listed in $(targets) +# This is a good hint that there is a bug in the kbuild file +ifeq ($(KBUILD_VERBOSE),2) +why = \ + $(if $(filter $@, $(PHONY)),- due to target is PHONY, \ + $(if $(wildcard $@), \ + $(if $(strip $(any-prereq)),- due to: $(any-prereq), \ + $(if $(arg-check), \ + $(if $(cmd_$@),- due to command line change, \ + $(if $(filter $@, $(targets)), \ + - due to missing .cmd file, \ + - due to $(notdir $@) not in $$(targets) \ + ) \ + ) \ + ) \ + ), \ + - due to target missing \ + ) \ + ) + +echo-why = $(call escsq, $(strip $(why))) +endif diff --git a/scripts/Makefile b/scripts/Makefile new file mode 100644 index 0000000000..242e3a06fc --- /dev/null +++ b/scripts/Makefile @@ -0,0 +1,16 @@ +### +# scripts contains sources for various helper programs used throughout +# the kernel for the build process. +# --------------------------------------------------------------------------- +# docproc: Used in Documentation/DocBook + +# The following hostprogs-y programs are only build on demand +hostprogs-y += docproc + +# These targets are used internally to avoid "is up to date" messages +PHONY += build_docproc +build_docproc: scripts/docproc + @: + +# Let clean descend into subdirs +subdir- += basic diff --git a/scripts/Makefile.build b/scripts/Makefile.build index e3354aaa3f..36346fd161 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -1,66 +1,506 @@ -# our default target -.PHONY: all -all: +# ========================================================================== +# Building +# ========================================================================== -include $(TOPDIR)/config.mk +# Modified for U-Boot +ifeq ($(CONFIG_TPL_BUILD),y) + src := $(patsubst tpl/%,%,$(obj)) +else + ifeq ($(CONFIG_SPL_BUILD),y) + src := $(patsubst spl/%,%,$(obj)) + else + src := $(obj) + endif +endif -LIB := $(obj)built-in.o -LIBGCC = $(obj)libgcc.o -SRCS := +PHONY := __build +__build: -include Makefile +# Init all relevant variables used in kbuild files so +# 1) they have correct type +# 2) they do not inherit any value from the environment +obj-y := +obj-m := +lib-y := +lib-m := +always := +targets := +subdir-y := +subdir-m := +EXTRA_AFLAGS := +EXTRA_CFLAGS := +EXTRA_CPPFLAGS := +EXTRA_LDFLAGS := +asflags-y := +ccflags-y := +cppflags-y := +ldflags-y := -# Going forward use the following -obj-y := $(sort $(obj-y)) -extra-y := $(sort $(extra-y)) -lib-y := $(sort $(lib-y)) +subdir-asflags-y := +subdir-ccflags-y := -subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) -obj-y := $(patsubst %/, %/built-in.o, $(obj-y)) -subdir-obj-y := $(filter %/built-in.o, $(obj-y)) -subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y)) +# Read auto.conf if it exists, otherwise ignore +-include include/config/auto.conf -SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \ - $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) -OBJS := $(addprefix $(obj),$(obj-y)) +# Added for U-Boot: Load U-Boot configuration +ifeq ($(CONFIG_TPL_BUILD),y) + -include include/tpl-autoconf.mk +else + ifeq ($(CONFIG_SPL_BUILD),y) + -include include/spl-autoconf.mk + else + -include include/autoconf.mk + endif +endif -# $(obj-dirs) is a list of directories that contain object files -obj-dirs := $(dir $(OBJS)) +include scripts/Kbuild.include + +# For backward compatibility check that these variables do not change +save-cflags := $(CFLAGS) + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile) +include $(kbuild-file) + +# Added for U-Boot +asflags-y += $(PLATFORM_CPPFLAGS) +ccflags-y += $(PLATFORM_CPPFLAGS) +cppflags-y += $(PLATFORM_CPPFLAGS) + +# If the save-* variables changed error out +ifeq ($(KBUILD_NOPEDANTIC),) + ifneq ("$(save-cflags)","$(CFLAGS)") + $(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y) + endif +endif + +# +# make W=... settings +# +# W=1 - warnings that may be relevant and does not occur too often +# W=2 - warnings that occur quite often but may still be relevant +# W=3 - the more obscure warnings, can most likely be ignored +# +# $(call cc-option, -W...) handles gcc -W.. options which +# are not supported by all versions of the compiler +ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS +warning- := $(empty) + +warning-1 := -Wextra -Wunused -Wno-unused-parameter +warning-1 += -Wmissing-declarations +warning-1 += -Wmissing-format-attribute +warning-1 += -Wmissing-prototypes +warning-1 += -Wold-style-definition +warning-1 += $(call cc-option, -Wmissing-include-dirs) +warning-1 += $(call cc-option, -Wunused-but-set-variable) +warning-1 += $(call cc-disable-warning, missing-field-initializers) + +warning-2 := -Waggregate-return +warning-2 += -Wcast-align +warning-2 += -Wdisabled-optimization +warning-2 += -Wnested-externs +warning-2 += -Wshadow +warning-2 += $(call cc-option, -Wlogical-op) +warning-2 += $(call cc-option, -Wmissing-field-initializers) + +warning-3 := -Wbad-function-cast +warning-3 += -Wcast-qual +warning-3 += -Wconversion +warning-3 += -Wpacked +warning-3 += -Wpadded +warning-3 += -Wpointer-arith +warning-3 += -Wredundant-decls +warning-3 += -Wswitch-default +warning-3 += $(call cc-option, -Wpacked-bitfield-compat) +warning-3 += $(call cc-option, -Wvla) + +warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) + +ifeq ("$(strip $(warning))","") + $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown) +endif + +KBUILD_CFLAGS += $(warning) +endif + +include scripts/Makefile.lib + +ifdef host-progs +ifneq ($(hostprogs-y),$(host-progs)) +$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!) +hostprogs-y += $(host-progs) +endif +endif + +# Do not include host rules unless needed +ifneq ($(hostprogs-y)$(hostprogs-m),) +include scripts/Makefile.host +endif + +# Uncommented for U-Boot +# We need to create output dicrectory for SPL and TPL even for in-tree build +#ifneq ($(KBUILD_SRC),) +# Create output directory if not already present +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) # Create directories for object files if directory does not exist # Needed when obj-y := dir/file.o syntax is used _dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) +#endif -LGOBJS := $(addprefix $(obj),$(sort $(lib-y))) - -all: $(LIB) $(addprefix $(obj),$(extra-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -ifneq ($(strip $(lib-y)),) -all: $(LIBGCC) - -$(LIBGCC): $(obj).depend $(LGOBJS) - $(call cmd_link_o_target, $(LGOBJS)) +ifndef obj +$(warning kbuild: Makefile.build is included improperly) endif -ifneq ($(subdir-obj-y),) +# =========================================================================== + +ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),) +lib-target := $(obj)/lib.a +endif + +ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),) +builtin-target := $(obj)/built-in.o +endif + +modorder-target := $(obj)/modules.order + +# We keep a list of all modules in $(MODVERDIR) + +__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \ + $(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \ + $(subdir-ym) $(always) + @: + +# Linus' kernel sanity checking tool +ifneq ($(KBUILD_CHECKSRC),0) + ifeq ($(KBUILD_CHECKSRC),2) + quiet_cmd_force_checksrc = CHECK $< + cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; + else + quiet_cmd_checksrc = CHECK $< + cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; + endif +endif + +# Do section mismatch analysis for each module/built-in.o +ifdef CONFIG_DEBUG_SECTION_MISMATCH + cmd_secanalysis = ; scripts/mod/modpost $@ +endif + +# Compile C sources (.c) +# --------------------------------------------------------------------------- + +# Default is built-in, unless we know otherwise +modkern_cflags = \ + $(if $(part-of-module), \ + $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \ + $(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL)) +quiet_modtag := $(empty) $(empty) + +$(real-objs-m) : part-of-module := y +$(real-objs-m:.o=.i) : part-of-module := y +$(real-objs-m:.o=.s) : part-of-module := y +$(real-objs-m:.o=.lst): part-of-module := y + +$(real-objs-m) : quiet_modtag := [M] +$(real-objs-m:.o=.i) : quiet_modtag := [M] +$(real-objs-m:.o=.s) : quiet_modtag := [M] +$(real-objs-m:.o=.lst): quiet_modtag := [M] + +$(obj-m) : quiet_modtag := [M] + +# Default for not multi-part modules +modname = $(basetarget) + +$(multi-objs-m) : modname = $(modname-multi) +$(multi-objs-m:.o=.i) : modname = $(modname-multi) +$(multi-objs-m:.o=.s) : modname = $(modname-multi) +$(multi-objs-m:.o=.lst) : modname = $(modname-multi) +$(multi-objs-y) : modname = $(modname-multi) +$(multi-objs-y:.o=.i) : modname = $(modname-multi) +$(multi-objs-y:.o=.s) : modname = $(modname-multi) +$(multi-objs-y:.o=.lst) : modname = $(modname-multi) + +quiet_cmd_cc_s_c = CC $(quiet_modtag) $@ +cmd_cc_s_c = $(CC) $(c_flags) -fverbose-asm -S -o $@ $< + +$(obj)/%.s: $(src)/%.c FORCE + $(call if_changed_dep,cc_s_c) + +quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@ +cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $< + +$(obj)/%.i: $(src)/%.c FORCE + $(call if_changed_dep,cc_i_c) + +cmd_gensymtypes = \ + $(CPP) -D__GENKSYMS__ $(c_flags) $< | \ + $(GENKSYMS) $(if $(1), -T $(2)) \ + $(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \ + $(if $(KBUILD_PRESERVE),-p) \ + -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null)) + +quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@ +cmd_cc_symtypes_c = \ + set -e; \ + $(call cmd_gensymtypes,true,$@) >/dev/null; \ + test -s $@ || rm -f $@ + +$(obj)/%.symtypes : $(src)/%.c FORCE + $(call cmd,cc_symtypes_c) + +# C (.c) files +# The C file is compiled and updated dependency information is generated. +# (See cmd_cc_o_c + relevant part of rule_cc_o_c) + +quiet_cmd_cc_o_c = CC $(quiet_modtag) $@ + +ifndef CONFIG_MODVERSIONS +cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< + +else +# When module versioning is enabled the following steps are executed: +# o compile a .tmp_.o from .c +# o if .tmp_.o doesn't contain a __ksymtab version, i.e. does +# not export symbols, we just rename .tmp_.o to .o and +# are done. +# o otherwise, we calculate symbol versions using the good old +# genksyms on the preprocessed source and postprocess them in a way +# that they are usable as a linker script +# o generate .o from .tmp_.o using the linker to +# replace the unresolved symbols __crc_exported_symbol with +# the actual value of the checksum generated by genksyms + +cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $< +cmd_modversions = \ + if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \ + $(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \ + > $(@D)/.tmp_$(@F:.o=.ver); \ + \ + $(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \ + -T $(@D)/.tmp_$(@F:.o=.ver); \ + rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \ + else \ + mv -f $(@D)/.tmp_$(@F) $@; \ + fi; +endif + +ifdef CONFIG_FTRACE_MCOUNT_RECORD +ifdef BUILD_C_RECORDMCOUNT +ifeq ("$(origin RECORDMCOUNT_WARN)", "command line") + RECORDMCOUNT_FLAGS = -w +endif +# Due to recursion, we must skip empty.o. +# The empty.o file is created in the make process in order to determine +# the target endianness and word size. It is made before all other C +# files, including recordmcount. +sub_cmd_record_mcount = \ + if [ $(@) != "scripts/mod/empty.o" ]; then \ + $(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \ + fi; +recordmcount_source := $(srctree)/scripts/recordmcount.c \ + $(srctree)/scripts/recordmcount.h +else +sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \ + "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \ + "$(if $(CONFIG_64BIT),64,32)" \ + "$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \ + "$(LD)" "$(NM)" "$(RM)" "$(MV)" \ + "$(if $(part-of-module),1,0)" "$(@)"; +recordmcount_source := $(srctree)/scripts/recordmcount.pl +endif +cmd_record_mcount = \ + if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then \ + $(sub_cmd_record_mcount) \ + fi; +endif + +define rule_cc_o_c + $(call echo-cmd,checksrc) $(cmd_checksrc) \ + $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \ + $(cmd_modversions) \ + $(call echo-cmd,record_mcount) \ + $(cmd_record_mcount) \ + scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > \ + $(dot-target).tmp; \ + rm -f $(depfile); \ + mv -f $(dot-target).tmp $(dot-target).cmd +endef + +# Built-in and composite module parts +$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + +# Single-part modules are special since we need to mark them in $(MODVERDIR) + +$(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + @{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod) + +quiet_cmd_cc_lst_c = MKLST $@ + cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \ + $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \ + System.map $(OBJDUMP) > $@ + +$(obj)/%.lst: $(src)/%.c FORCE + $(call if_changed_dep,cc_lst_c) + +# Compile assembler sources (.S) +# --------------------------------------------------------------------------- + +modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL) + +$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE) +$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE) + +quiet_cmd_as_s_S = CPP $(quiet_modtag) $@ +cmd_as_s_S = $(CPP) $(a_flags) -o $@ $< + +$(obj)/%.s: $(src)/%.S FORCE + $(call if_changed_dep,as_s_S) + +quiet_cmd_as_o_S = AS $(quiet_modtag) $@ +cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $< + +$(obj)/%.o: $(src)/%.S FORCE + $(call if_changed_dep,as_o_S) + +targets += $(real-objs-y) $(real-objs-m) $(lib-y) +targets += $(extra-y) $(MAKECMDGOALS) $(always) + +# Linker scripts preprocessor (.lds.S -> .lds) +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds_S = LDS $@ + cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + +$(obj)/%.lds: $(src)/%.lds.S FORCE + $(call if_changed_dep,cpp_lds_S) + +# ASN.1 grammar +# --------------------------------------------------------------------------- +quiet_cmd_asn1_compiler = ASN.1 $@ + cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \ + $(subst .h,.c,$@) $(subst .c,.h,$@) + +.PRECIOUS: $(objtree)/$(obj)/%-asn1.c $(objtree)/$(obj)/%-asn1.h + +$(obj)/%-asn1.c $(obj)/%-asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler + $(call cmd,asn1_compiler) + +# Build the compiled-in targets +# --------------------------------------------------------------------------- + +# To build objects in subdirs, we need to descend into the directories +$(sort $(subdir-obj-y)): $(subdir-ym) ; + +# +# Rule to compile a set of .o files into one .o file +# +ifdef builtin-target +quiet_cmd_link_o_target = LD $@ +# If the list of objects to link is empty, just create an empty built-in.o +cmd_link_o_target = $(if $(strip $(obj-y)),\ + $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \ + $(cmd_secanalysis),\ + rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@) + +$(builtin-target): $(obj-y) FORCE + $(call if_changed,link_o_target) + +targets += $(builtin-target) +endif # builtin-target + +# +# Rule to create modules.order file +# +# Create commands to either record .ko file or cat modules.order from +# a subdirectory +modorder-cmds = \ + $(foreach m, $(modorder), \ + $(if $(filter %/modules.order, $m), \ + cat $m;, echo kernel/$m;)) + +$(modorder-target): $(subdir-ym) FORCE + $(Q)(cat /dev/null; $(modorder-cmds)) > $@ + +# +# Rule to compile a set of .o files into one .a file +# +ifdef lib-target +quiet_cmd_link_l_target = AR $@ +cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y) + +$(lib-target): $(lib-y) FORCE + $(call if_changed,link_l_target) + +targets += $(lib-target) +endif + +# +# Rule to link composite objects +# +# Composite objects are specified in kbuild makefile as follows: +# -objs := +# or +# -y := +link_multi_deps = \ +$(filter $(addprefix $(obj)/, \ +$($(subst $(obj)/,,$(@:.o=-objs))) \ +$($(subst $(obj)/,,$(@:.o=-y)))), $^) + +quiet_cmd_link_multi-y = LD $@ +cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis) + +quiet_cmd_link_multi-m = LD [M] $@ +cmd_link_multi-m = $(cmd_link_multi-y) + +# We would rather have a list of rules like +# foo.o: $(foo-objs) +# but that's not so easy, so we rather make all composite objects depend +# on the set of all their parts +$(multi-used-y) : %.o: $(multi-objs-y) FORCE + $(call if_changed,link_multi-y) + +$(multi-used-m) : %.o: $(multi-objs-m) FORCE + $(call if_changed,link_multi-m) + @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod) + +targets += $(multi-used-y) $(multi-used-m) + + # Descending -$(subdir-obj-y): $(subdir-y) +# --------------------------------------------------------------------------- -$(subdir-y): FORCE - $(MAKE) -C $@ -f $(TOPDIR)/scripts/Makefile.build +PHONY += $(subdir-ym) +$(subdir-ym): + $(Q)$(MAKE) $(build)=$@ + +# Add FORCE to the prequisites of a target to force it to be always rebuilt. +# --------------------------------------------------------------------------- + +PHONY += FORCE + +FORCE: + +# Read all saved command lines and dependencies for the $(targets) we +# may be building above, using $(if_changed{,_dep}). As an +# optimization, we don't need to read them if the target does not +# exist, we will rebuild anyway in that case. + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + include $(cmd_files) endif -######################################################################### +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable se we can use it in if_changed and friends. -# defines $(obj).depend target - -include $(TOPDIR)/rules.mk - -sinclude $(obj).depend - -######################################################################### - -.PHONY: FORCE +.PHONY: $(PHONY) diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean new file mode 100644 index 0000000000..d6dcd47f6f --- /dev/null +++ b/scripts/Makefile.clean @@ -0,0 +1,109 @@ +# ========================================================================== +# Cleaning up +# ========================================================================== + +src := $(obj) + +PHONY := __clean +__clean: + +# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile) + +# Figure out what we need to build from the various variables +# ========================================================================== + +__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) +subdir-y += $(__subdir-y) +__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m))) +subdir-m += $(__subdir-m) +__subdir-n := $(patsubst %/,%,$(filter %/, $(obj-n))) +subdir-n += $(__subdir-n) +__subdir- := $(patsubst %/,%,$(filter %/, $(obj-))) +subdir- += $(__subdir-) + +# Subdirectories we need to descend into + +subdir-ym := $(sort $(subdir-y) $(subdir-m)) +subdir-ymn := $(sort $(subdir-ym) $(subdir-n) $(subdir-)) + +# Add subdir path + +subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn)) + +# Temporal work-around for U-Boot + +subdir-ymn := $(foreach f, $(subdir-ymn), \ + $(if $(wildcard $(srctree)/$f/Makefile),$f)) + +# build a list of files to remove, usually relative to the current +# directory + +__clean-files := $(extra-y) $(always) \ + $(targets) $(clean-files) \ + $(host-progs) \ + $(hostprogs-y) $(hostprogs-m) $(hostprogs-) + +__clean-files := $(filter-out $(no-clean-files), $(__clean-files)) + +# as clean-files is given relative to the current directory, this adds +# a $(obj) prefix, except for absolute paths + +__clean-files := $(wildcard \ + $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \ + $(filter /%, $(__clean-files))) + +# as clean-dirs is given relative to the current directory, this adds +# a $(obj) prefix, except for absolute paths + +__clean-dirs := $(wildcard \ + $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs))) \ + $(filter /%, $(clean-dirs))) + +# ========================================================================== + +quiet_cmd_clean = CLEAN $(obj) + cmd_clean = rm -f $(__clean-files) +quiet_cmd_cleandir = CLEAN $(__clean-dirs) + cmd_cleandir = rm -rf $(__clean-dirs) + + +__clean: $(subdir-ymn) +ifneq ($(strip $(__clean-files)),) + +$(call cmd,clean) +endif +ifneq ($(strip $(__clean-dirs)),) + +$(call cmd,cleandir) +endif +ifneq ($(strip $(clean-rule)),) + +$(clean-rule) +endif + @: + + +# =========================================================================== +# Generic stuff +# =========================================================================== + +# Descending +# --------------------------------------------------------------------------- + +PHONY += $(subdir-ymn) +$(subdir-ymn): + $(Q)$(MAKE) $(clean)=$@ + +# If quiet is set, only print short version of command + +cmd = @$(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))' &&) $(cmd_$(1)) + + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable se we can use it in if_changed and friends. + +.PHONY: $(PHONY) diff --git a/scripts/Makefile.host b/scripts/Makefile.host new file mode 100644 index 0000000000..1ac414fd50 --- /dev/null +++ b/scripts/Makefile.host @@ -0,0 +1,170 @@ +# ========================================================================== +# Building binaries on the host system +# Binaries are used during the compilation of the kernel, for example +# to preprocess a data file. +# +# Both C and C++ are supported, but preferred language is C for such utilities. +# +# Sample syntax (see Documentation/kbuild/makefiles.txt for reference) +# hostprogs-y := bin2hex +# Will compile bin2hex.c and create an executable named bin2hex +# +# hostprogs-y := lxdialog +# lxdialog-objs := checklist.o lxdialog.o +# Will compile lxdialog.c and checklist.c, and then link the executable +# lxdialog, based on checklist.o and lxdialog.o +# +# hostprogs-y := qconf +# qconf-cxxobjs := qconf.o +# qconf-objs := menu.o +# Will compile qconf as a C++ program, and menu as a C program. +# They are linked as C++ code to the executable qconf + +# hostprogs-y := conf +# conf-objs := conf.o libkconfig.so +# libkconfig-objs := expr.o type.o +# Will create a shared library named libkconfig.so that consists of +# expr.o and type.o (they are both compiled as C code and the object files +# are made as position independent code). +# conf.c is compiled as a C program, and conf.o is linked together with +# libkconfig.so as the executable conf. +# Note: Shared libraries consisting of C++ files are not supported + +__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m)) + +# C code +# Executables compiled from a single .c file +host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m))) + +# C executables linked based on several .o files +host-cmulti := $(foreach m,$(__hostprogs),\ + $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m)))) + +# Object (.o) files compiled from .c files +host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs))) + +# C++ code +# C++ executables compiled from at least on .cc file +# and zero or more .c files +host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m))) + +# C++ Object (.o) files compiled from .cc files +host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs))) + +# Shared libaries (only .c supported) +# Shared libraries (.so) - all .so files referenced in "xxx-objs" +host-cshlib := $(sort $(filter %.so, $(host-cobjs))) +# Remove .so files from "xxx-objs" +host-cobjs := $(filter-out %.so,$(host-cobjs)) + +#Object (.o) files used by the shared libaries +host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs)))) + +# output directory for programs/.o files +# hostprogs-y := tools/build may have been specified. Retrieve directory +host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f)))) +# directory of .o files from prog-objs notation +host-objdirs += $(foreach f,$(host-cmulti), \ + $(foreach m,$($(f)-objs), \ + $(if $(dir $(m)),$(dir $(m))))) +# directory of .o files from prog-cxxobjs notation +host-objdirs += $(foreach f,$(host-cxxmulti), \ + $(foreach m,$($(f)-cxxobjs), \ + $(if $(dir $(m)),$(dir $(m))))) + +host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs)))) + + +__hostprogs := $(addprefix $(obj)/,$(__hostprogs)) +host-csingle := $(addprefix $(obj)/,$(host-csingle)) +host-cmulti := $(addprefix $(obj)/,$(host-cmulti)) +host-cobjs := $(addprefix $(obj)/,$(host-cobjs)) +host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti)) +host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs)) +host-cshlib := $(addprefix $(obj)/,$(host-cshlib)) +host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs)) +host-objdirs := $(addprefix $(obj)/,$(host-objdirs)) + +obj-dirs += $(host-objdirs) + +##### +# Handle options to gcc. Support building with separate output directory + +_hostc_flags = $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \ + $(HOSTCFLAGS_$(basetarget).o) +_hostcxx_flags = $(HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \ + $(HOSTCXXFLAGS_$(basetarget).o) + +ifeq ($(KBUILD_SRC),) +__hostc_flags = $(_hostc_flags) +__hostcxx_flags = $(_hostcxx_flags) +else +__hostc_flags = -I$(obj) $(call flags,_hostc_flags) +__hostcxx_flags = -I$(obj) $(call flags,_hostcxx_flags) +endif + +hostc_flags = -Wp,-MD,$(depfile) $(__hostc_flags) +hostcxx_flags = -Wp,-MD,$(depfile) $(__hostcxx_flags) + +##### +# Compile programs on the host + +# Create executable from a single .c file +# host-csingle -> Executable +quiet_cmd_host-csingle = HOSTCC $@ + cmd_host-csingle = $(HOSTCC) $(hostc_flags) -o $@ $< \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-csingle): $(obj)/%: $(src)/%.c FORCE + $(call if_changed_dep,host-csingle) + +# Link an executable based on list of .o files, all plain c +# host-cmulti -> executable +quiet_cmd_host-cmulti = HOSTLD $@ + cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \ + $(addprefix $(obj)/,$($(@F)-objs)) \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE + $(call if_changed,host-cmulti) + +# Create .o file from a single .c file +# host-cobjs -> .o +quiet_cmd_host-cobjs = HOSTCC $@ + cmd_host-cobjs = $(HOSTCC) $(hostc_flags) -c -o $@ $< +$(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,host-cobjs) + +# Link an executable based on list of .o files, a mixture of .c and .cc +# host-cxxmulti -> executable +quiet_cmd_host-cxxmulti = HOSTLD $@ + cmd_host-cxxmulti = $(HOSTCXX) $(HOSTLDFLAGS) -o $@ \ + $(foreach o,objs cxxobjs,\ + $(addprefix $(obj)/,$($(@F)-$(o)))) \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE + $(call if_changed,host-cxxmulti) + +# Create .o file from a single .cc (C++) file +quiet_cmd_host-cxxobjs = HOSTCXX $@ + cmd_host-cxxobjs = $(HOSTCXX) $(hostcxx_flags) -c -o $@ $< +$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE + $(call if_changed_dep,host-cxxobjs) + +# Compile .c file, create position independent .o file +# host-cshobjs -> .o +quiet_cmd_host-cshobjs = HOSTCC -fPIC $@ + cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $< +$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,host-cshobjs) + +# Link a shared library, based on position independent .o files +# *.o -> .so shared library (host-cshlib) +quiet_cmd_host-cshlib = HOSTLLD -shared $@ + cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \ + $(addprefix $(obj)/,$($(@F:.so=-objs))) \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE + $(call if_changed,host-cshlib) + +targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\ + $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs) + diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib new file mode 100644 index 0000000000..d568fde2cc --- /dev/null +++ b/scripts/Makefile.lib @@ -0,0 +1,373 @@ +# Backward compatibility +asflags-y += $(EXTRA_AFLAGS) +ccflags-y += $(EXTRA_CFLAGS) +cppflags-y += $(EXTRA_CPPFLAGS) +ldflags-y += $(EXTRA_LDFLAGS) + +# +# flags that take effect in sub directories +export KBUILD_SUBDIR_ASFLAGS := $(KBUILD_SUBDIR_ASFLAGS) $(subdir-asflags-y) +export KBUILD_SUBDIR_CCFLAGS := $(KBUILD_SUBDIR_CCFLAGS) $(subdir-ccflags-y) + +# Figure out what we need to build from the various variables +# =========================================================================== + +# When an object is listed to be built compiled-in and modular, +# only build the compiled-in version + +obj-m := $(filter-out $(obj-y),$(obj-m)) + +# Libraries are always collected in one lib file. +# Filter out objects already built-in + +lib-y := $(filter-out $(obj-y), $(sort $(lib-y) $(lib-m))) + + +# Handle objects in subdirs +# --------------------------------------------------------------------------- +# o if we encounter foo/ in $(obj-y), replace it by foo/built-in.o +# and add the directory to the list of dirs to descend into: $(subdir-y) +# o if we encounter foo/ in $(obj-m), remove it from $(obj-m) +# and add the directory to the list of dirs to descend into: $(subdir-m) + +# Determine modorder. +# Unfortunately, we don't have information about ordering between -y +# and -m subdirs. Just put -y's first. +modorder := $(patsubst %/,%/modules.order, $(filter %/, $(obj-y)) $(obj-m:.o=.ko)) + +__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) +subdir-y += $(__subdir-y) +__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m))) +subdir-m += $(__subdir-m) +obj-y := $(patsubst %/, %/built-in.o, $(obj-y)) +obj-m := $(filter-out %/, $(obj-m)) + +# Subdirectories we need to descend into + +subdir-ym := $(sort $(subdir-y) $(subdir-m)) + +# if $(foo-objs) exists, foo.o is a composite object +multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) +multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) +multi-used := $(multi-used-y) $(multi-used-m) +single-used-m := $(sort $(filter-out $(multi-used-m),$(obj-m))) + +# Build list of the parts of our composite objects, our composite +# objects depend on those (obviously) +multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y))) +multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y))) +multi-objs := $(multi-objs-y) $(multi-objs-m) + +# $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to +# tell kbuild to descend +subdir-obj-y := $(filter %/built-in.o, $(obj-y)) + +# $(obj-dirs) is a list of directories that contain object files +obj-dirs := $(dir $(multi-objs) $(obj-y)) + +# Replace multi-part objects by their individual parts, look at local dir only +real-objs-y := $(foreach m, $(filter-out $(subdir-obj-y), $(obj-y)), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) $(extra-y) +real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) + +# Add subdir path + +extra-y := $(addprefix $(obj)/,$(extra-y)) +always := $(addprefix $(obj)/,$(always)) +targets := $(addprefix $(obj)/,$(targets)) +modorder := $(addprefix $(obj)/,$(modorder)) +obj-y := $(addprefix $(obj)/,$(obj-y)) +obj-m := $(addprefix $(obj)/,$(obj-m)) +lib-y := $(addprefix $(obj)/,$(lib-y)) +subdir-obj-y := $(addprefix $(obj)/,$(subdir-obj-y)) +real-objs-y := $(addprefix $(obj)/,$(real-objs-y)) +real-objs-m := $(addprefix $(obj)/,$(real-objs-m)) +single-used-m := $(addprefix $(obj)/,$(single-used-m)) +multi-used-y := $(addprefix $(obj)/,$(multi-used-y)) +multi-used-m := $(addprefix $(obj)/,$(multi-used-m)) +multi-objs-y := $(addprefix $(obj)/,$(multi-objs-y)) +multi-objs-m := $(addprefix $(obj)/,$(multi-objs-m)) +subdir-ym := $(addprefix $(obj)/,$(subdir-ym)) +obj-dirs := $(addprefix $(obj)/,$(obj-dirs)) + +# These flags are needed for modversions and compiling, so we define them here +# already +# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will +# end up in (or would, if it gets compiled in) +# Note: Files that end up in two or more modules are compiled without the +# KBUILD_MODNAME definition. The reason is that any made-up name would +# differ in different configs. +name-fix = $(subst $(comma),_,$(subst -,_,$1)) +basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))" +modname_flags = $(if $(filter 1,$(words $(modname))),\ + -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))") + +orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \ + $(ccflags-y) $(CFLAGS_$(basetarget).o) +_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags)) +_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \ + $(asflags-y) $(AFLAGS_$(basetarget).o) +_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F)) + +# +# Enable gcov profiling flags for a file, directory or for all files depending +# on variables GCOV_PROFILE_obj.o, GCOV_PROFILE and CONFIG_GCOV_PROFILE_ALL +# (in this order) +# +ifeq ($(CONFIG_GCOV_KERNEL),y) +_c_flags += $(if $(patsubst n%,, \ + $(GCOV_PROFILE_$(basetarget).o)$(GCOV_PROFILE)$(CONFIG_GCOV_PROFILE_ALL)), \ + $(CFLAGS_GCOV)) +endif + +# If building the kernel in a separate objtree expand all occurrences +# of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/'). + +ifeq ($(KBUILD_SRC),) +__c_flags = $(_c_flags) +__a_flags = $(_a_flags) +__cpp_flags = $(_cpp_flags) +else + +# -I$(obj) locates generated .h files +# $(call addtree,-I$(obj)) locates .h files in srctree, from generated .c files +# and locates generated .h files +# FIXME: Replace both with specific CFLAGS* statements in the makefiles +__c_flags = $(call addtree,-I$(obj)) $(call flags,_c_flags) +__a_flags = $(call flags,_a_flags) +__cpp_flags = $(call flags,_cpp_flags) +endif + +# Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE +c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__c_flags) $(modkern_cflags) \ + -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags) + +a_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__a_flags) $(modkern_aflags) + +cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__cpp_flags) + +ld_flags = $(LDFLAGS) $(ldflags-y) + +# Modified for U-Boot +dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ + -I$(srctree)/arch/$(ARCH)/dts \ + -undef -D__DTS__ + +# Finds the multi-part object the current object will be linked into +modname-multi = $(sort $(foreach m,$(multi-used),\ + $(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=)))) + +ifdef REGENERATE_PARSERS + +# GPERF +# --------------------------------------------------------------------------- +quiet_cmd_gperf = GPERF $@ + cmd_gperf = gperf -t --output-file $@ -a -C -E -g -k 1,3,$$ -p -t $< + +.PRECIOUS: $(src)/%.hash.c_shipped +$(src)/%.hash.c_shipped: $(src)/%.gperf + $(call cmd,gperf) + +# LEX +# --------------------------------------------------------------------------- +LEX_PREFIX = $(if $(LEX_PREFIX_${baseprereq}),$(LEX_PREFIX_${baseprereq}),yy) + +quiet_cmd_flex = LEX $@ + cmd_flex = flex -o$@ -L -P $(LEX_PREFIX) $< + +.PRECIOUS: $(src)/%.lex.c_shipped +$(src)/%.lex.c_shipped: $(src)/%.l + $(call cmd,flex) + +# YACC +# --------------------------------------------------------------------------- +YACC_PREFIX = $(if $(YACC_PREFIX_${baseprereq}),$(YACC_PREFIX_${baseprereq}),yy) + +quiet_cmd_bison = YACC $@ + cmd_bison = bison -o$@ -t -l -p $(YACC_PREFIX) $< + +.PRECIOUS: $(src)/%.tab.c_shipped +$(src)/%.tab.c_shipped: $(src)/%.y + $(call cmd,bison) + +quiet_cmd_bison_h = YACC $@ + cmd_bison_h = bison -o/dev/null --defines=$@ -t -l -p $(YACC_PREFIX) $< + +.PRECIOUS: $(src)/%.tab.h_shipped +$(src)/%.tab.h_shipped: $(src)/%.y + $(call cmd,bison_h) + +endif + +# Shipped files +# =========================================================================== + +quiet_cmd_shipped = SHIPPED $@ +cmd_shipped = cat $< > $@ + +$(obj)/%: $(src)/%_shipped + $(call cmd,shipped) + +# Commands useful for building a boot image +# =========================================================================== +# +# Use as following: +# +# target: source(s) FORCE +# $(if_changed,ld/objcopy/gzip) +# +# and add target to extra-y so that we know we have to +# read in the saved command line + +# Linking +# --------------------------------------------------------------------------- + +quiet_cmd_ld = LD $@ +cmd_ld = $(LD) $(LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) \ + $(filter-out FORCE,$^) -o $@ + +# Objcopy +# --------------------------------------------------------------------------- + +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ + +# Gzip +# --------------------------------------------------------------------------- + +quiet_cmd_gzip = GZIP $@ +cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ + (rm -f $@ ; false) + +# DTC +# --------------------------------------------------------------------------- + +# Generate an assembly file to wrap the output of the device tree compiler +quiet_cmd_dt_S_dtb= DTB $@ +# Modified for U-Boot +cmd_dt_S_dtb= \ +( \ + echo '.section .dtb.init.rodata,"a"'; \ + echo '.global __dtb_$(*F)_begin'; \ + echo '__dtb_$(*F)_begin:'; \ + echo '.incbin "$<" '; \ + echo '__dtb_$(*F)_end:'; \ + echo '.global __dtb_$(*F)_end'; \ +) > $@ + +$(obj)/%.dtb.S: $(obj)/%.dtb + $(call cmd,dt_S_dtb) + +quiet_cmd_dtc = DTC $@ +# Modified for U-Boot +cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + dtc -O dtb -o $@ -b 0 \ + -i $(dir $<) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + +# Bzip2 +# --------------------------------------------------------------------------- + +# Bzip2 and LZMA do not include size in file... so we have to fake that; +# append the size as a 32-bit littleendian number as gzip does. +size_append = printf $(shell \ +dec_size=0; \ +for F in $1; do \ + fsize=$$(stat -c "%s" $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ +done; \ +printf "%08x\n" $$dec_size | \ + sed 's/\(..\)/\1 /g' | { \ + read ch0 ch1 ch2 ch3; \ + for ch in $$ch3 $$ch2 $$ch1 $$ch0; do \ + printf '%s%03o' '\\' $$((0x$$ch)); \ + done; \ + } \ +) + +quiet_cmd_bzip2 = BZIP2 $@ +cmd_bzip2 = (cat $(filter-out FORCE,$^) | \ + bzip2 -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +# Lzma +# --------------------------------------------------------------------------- + +quiet_cmd_lzma = LZMA $@ +cmd_lzma = (cat $(filter-out FORCE,$^) | \ + lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_lzo = LZO $@ +cmd_lzo = (cat $(filter-out FORCE,$^) | \ + lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_lz4 = LZ4 $@ +cmd_lz4 = (cat $(filter-out FORCE,$^) | \ + lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +# U-Boot mkimage +# --------------------------------------------------------------------------- + +MKIMAGE := $(srctree)/scripts/mkuboot.sh + +# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces +# the number of overrides in arch makefiles +UIMAGE_ARCH ?= $(SRCARCH) +UIMAGE_COMPRESSION ?= $(if $(2),$(2),none) +UIMAGE_OPTS-y ?= +UIMAGE_TYPE ?= kernel +UIMAGE_LOADADDR ?= arch_must_set_this +UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR) +UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)' +UIMAGE_IN ?= $< +UIMAGE_OUT ?= $@ + +quiet_cmd_uimage = UIMAGE $(UIMAGE_OUT) + cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \ + -C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \ + -T $(UIMAGE_TYPE) \ + -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \ + -n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT) + +# XZ +# --------------------------------------------------------------------------- +# Use xzkern to compress the kernel image and xzmisc to compress other things. +# +# xzkern uses a big LZMA2 dictionary since it doesn't increase memory usage +# of the kernel decompressor. A BCJ filter is used if it is available for +# the target architecture. xzkern also appends uncompressed size of the data +# using size_append. The .xz format has the size information available at +# the end of the file too, but it's in more complex format and it's good to +# avoid changing the part of the boot code that reads the uncompressed size. +# Note that the bytes added by size_append will make the xz tool think that +# the file is corrupt. This is expected. +# +# xzmisc doesn't use size_append, so it can be used to create normal .xz +# files. xzmisc uses smaller LZMA2 dictionary than xzkern, because a very +# big dictionary would increase the memory usage too much in the multi-call +# decompression mode. A BCJ filter isn't used either. +quiet_cmd_xzkern = XZKERN $@ +cmd_xzkern = (cat $(filter-out FORCE,$^) | \ + sh $(srctree)/scripts/xz_wrap.sh && \ + $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_xzmisc = XZMISC $@ +cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ + xz --check=crc32 --lzma2=dict=1MiB) > $@ || \ + (rm -f $@ ; false) + +# misc stuff +# --------------------------------------------------------------------------- +quote:=" diff --git a/scripts/basic/.gitignore b/scripts/basic/.gitignore new file mode 100644 index 0000000000..a776371a35 --- /dev/null +++ b/scripts/basic/.gitignore @@ -0,0 +1 @@ +fixdep diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile new file mode 100644 index 0000000000..4fcef87bb8 --- /dev/null +++ b/scripts/basic/Makefile @@ -0,0 +1,15 @@ +### +# Makefile.basic lists the most basic programs used during the build process. +# The programs listed herein are what are needed to do the basic stuff, +# such as fix file dependencies. +# This initial step is needed to avoid files to be recompiled +# when kernel configuration changes (which is what happens when +# .config is included by main Makefile. +# --------------------------------------------------------------------------- +# fixdep: Used to generate dependency information during build process + +hostprogs-y := fixdep +always := $(hostprogs-y) + +# fixdep is needed to compile other host programs +$(addprefix $(obj)/,$(filter-out fixdep,$(always))): $(obj)/fixdep diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c new file mode 100644 index 0000000000..078fe1d64e --- /dev/null +++ b/scripts/basic/fixdep.c @@ -0,0 +1,462 @@ +/* + * "Optimize" a list of dependencies as spit out by gcc -MD + * for the kernel build + * =========================================================================== + * + * Author Kai Germaschewski + * Copyright 2002 by Kai Germaschewski + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * + * Introduction: + * + * gcc produces a very nice and correct list of dependencies which + * tells make when to remake a file. + * + * To use this list as-is however has the drawback that virtually + * every file in the kernel includes autoconf.h. + * + * If the user re-runs make *config, autoconf.h will be + * regenerated. make notices that and will rebuild every file which + * includes autoconf.h, i.e. basically all files. This is extremely + * annoying if the user just changed CONFIG_HIS_DRIVER from n to m. + * + * So we play the same trick that "mkdep" played before. We replace + * the dependency on autoconf.h by a dependency on every config + * option which is mentioned in any of the listed prequisites. + * + * kconfig populates a tree in include/config/ with an empty file + * for each config symbol and when the configuration is updated + * the files representing changed config options are touched + * which then let make pick up the changes and the files that use + * the config symbols are rebuilt. + * + * So if the user changes his CONFIG_HIS_DRIVER option, only the objects + * which depend on "include/linux/config/his/driver.h" will be rebuilt, + * so most likely only his driver ;-) + * + * The idea above dates, by the way, back to Michael E Chastain, AFAIK. + * + * So to get dependencies right, there are two issues: + * o if any of the files the compiler read changed, we need to rebuild + * o if the command line given to the compile the file changed, we + * better rebuild as well. + * + * The former is handled by using the -MD output, the later by saving + * the command line used to compile the old object and comparing it + * to the one we would now use. + * + * Again, also this idea is pretty old and has been discussed on + * kbuild-devel a long time ago. I don't have a sensibly working + * internet connection right now, so I rather don't mention names + * without double checking. + * + * This code here has been based partially based on mkdep.c, which + * says the following about its history: + * + * Copyright abandoned, Michael Chastain, . + * This is a C version of syncdep.pl by Werner Almesberger. + * + * + * It is invoked as + * + * fixdep + * + * and will read the dependency file + * + * The transformed dependency snipped is written to stdout. + * + * It first generates a line + * + * cmd_ = + * + * and then basically copies the ..d file to stdout, in the + * process filtering out the dependency on autoconf.h and adding + * dependencies on include/config/my/option.h for every + * CONFIG_MY_OPTION encountered in any of the prequisites. + * + * It will also filter out all the dependencies on *.ver. We need + * to make sure that the generated version checksum are globally up + * to date before even starting the recursive build, so it's too late + * at this point anyway. + * + * The algorithm to grep for "CONFIG_..." is bit unusual, but should + * be fast ;-) We don't even try to really parse the header files, but + * merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will + * be picked up as well. It's not a problem with respect to + * correctness, since that can only give too many dependencies, thus + * we cannot miss a rebuild. Since people tend to not mention totally + * unrelated CONFIG_ options all over the place, it's not an + * efficiency problem either. + * + * (Note: it'd be easy to port over the complete mkdep state machine, + * but I don't think the added complexity is worth it) + */ +/* + * Note 2: if somebody writes HELLO_CONFIG_BOOM in a file, it will depend onto + * CONFIG_BOOM. This could seem a bug (not too hard to fix), but please do not + * fix it! Some UserModeLinux files (look at arch/um/) call CONFIG_BOOM as + * UML_CONFIG_BOOM, to avoid conflicts with /usr/include/linux/autoconf.h, + * through arch/um/include/uml-config.h; this fixdep "bug" makes sure that + * those files will have correct dependencies. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INT_CONF ntohl(0x434f4e46) +#define INT_ONFI ntohl(0x4f4e4649) +#define INT_NFIG ntohl(0x4e464947) +#define INT_FIG_ ntohl(0x4649475f) + +char *target; +char *depfile; +char *cmdline; + +static void usage(void) +{ + fprintf(stderr, "Usage: fixdep \n"); + exit(1); +} + +/* + * Print out the commandline prefixed with cmd_ := + */ +static void print_cmdline(void) +{ + printf("cmd_%s := %s\n\n", target, cmdline); +} + +struct item { + struct item *next; + unsigned int len; + unsigned int hash; + char name[0]; +}; + +#define HASHSZ 256 +static struct item *hashtab[HASHSZ]; + +static unsigned int strhash(const char *str, unsigned int sz) +{ + /* fnv32 hash */ + unsigned int i, hash = 2166136261U; + + for (i = 0; i < sz; i++) + hash = (hash ^ str[i]) * 0x01000193; + return hash; +} + +/* + * Lookup a value in the configuration string. + */ +static int is_defined_config(const char *name, int len, unsigned int hash) +{ + struct item *aux; + + for (aux = hashtab[hash % HASHSZ]; aux; aux = aux->next) { + if (aux->hash == hash && aux->len == len && + memcmp(aux->name, name, len) == 0) + return 1; + } + return 0; +} + +/* + * Add a new value to the configuration string. + */ +static void define_config(const char *name, int len, unsigned int hash) +{ + struct item *aux = malloc(sizeof(*aux) + len); + + if (!aux) { + perror("fixdep:malloc"); + exit(1); + } + memcpy(aux->name, name, len); + aux->len = len; + aux->hash = hash; + aux->next = hashtab[hash % HASHSZ]; + hashtab[hash % HASHSZ] = aux; +} + +/* + * Clear the set of configuration strings. + */ +static void clear_config(void) +{ + struct item *aux, *next; + unsigned int i; + + for (i = 0; i < HASHSZ; i++) { + for (aux = hashtab[i]; aux; aux = next) { + next = aux->next; + free(aux); + } + hashtab[i] = NULL; + } +} + +/* + * Record the use of a CONFIG_* word. + */ +static void use_config(const char *m, int slen) +{ + unsigned int hash = strhash(m, slen); + int c, i; + + if (is_defined_config(m, slen, hash)) + return; + + define_config(m, slen, hash); + + printf(" $(wildcard include/config/"); + for (i = 0; i < slen; i++) { + c = m[i]; + if (c == '_') + c = '/'; + else + c = tolower(c); + putchar(c); + } + printf(".h) \\\n"); +} + +static void parse_config_file(const char *map, size_t len) +{ + const int *end = (const int *) (map + len); + /* start at +1, so that p can never be < map */ + const int *m = (const int *) map + 1; + const char *p, *q; + + for (; m < end; m++) { + if (*m == INT_CONF) { p = (char *) m ; goto conf; } + if (*m == INT_ONFI) { p = (char *) m-1; goto conf; } + if (*m == INT_NFIG) { p = (char *) m-2; goto conf; } + if (*m == INT_FIG_) { p = (char *) m-3; goto conf; } + continue; + conf: + if (p > map + len - 7) + continue; + if (memcmp(p, "CONFIG_", 7)) + continue; + for (q = p + 7; q < map + len; q++) { + if (!(isalnum(*q) || *q == '_')) + goto found; + } + continue; + + found: + if (!memcmp(q - 7, "_MODULE", 7)) + q -= 7; + if( (q-p-7) < 0 ) + continue; + use_config(p+7, q-p-7); + } +} + +/* test is s ends in sub */ +static int strrcmp(char *s, char *sub) +{ + int slen = strlen(s); + int sublen = strlen(sub); + + if (sublen > slen) + return 1; + + return memcmp(s + slen - sublen, sub, sublen); +} + +static void do_config_file(const char *filename) +{ + struct stat st; + int fd; + void *map; + + fd = open(filename, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "fixdep: error opening config file: "); + perror(filename); + exit(2); + } + fstat(fd, &st); + if (st.st_size == 0) { + close(fd); + return; + } + map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); + if ((long) map == -1) { + perror("fixdep: mmap"); + close(fd); + return; + } + + parse_config_file(map, st.st_size); + + munmap(map, st.st_size); + + close(fd); +} + +/* + * Important: The below generated source_foo.o and deps_foo.o variable + * assignments are parsed not only by make, but also by the rather simple + * parser in scripts/mod/sumversion.c. + */ +static void parse_dep_file(void *map, size_t len) +{ + char *m = map; + char *end = m + len; + char *p; + char s[PATH_MAX]; + int is_target; + int saw_any_target = 0; + int is_first_dep = 0; + + clear_config(); + + while (m < end) { + /* Skip any "white space" */ + while (m < end && (*m == ' ' || *m == '\\' || *m == '\n')) + m++; + /* Find next "white space" */ + p = m; + while (p < end && *p != ' ' && *p != '\\' && *p != '\n') + p++; + /* Is the token we found a target name? */ + is_target = (*(p-1) == ':'); + /* Don't write any target names into the dependency file */ + if (is_target) { + /* The /next/ file is the first dependency */ + is_first_dep = 1; + } else { + /* Save this token/filename */ + memcpy(s, m, p-m); + s[p - m] = 0; + + /* Ignore certain dependencies */ + if (strrcmp(s, "include/generated/autoconf.h") && + strrcmp(s, "arch/um/include/uml-config.h") && + strrcmp(s, "include/linux/kconfig.h") && + strrcmp(s, ".ver")) { + /* + * Do not list the source file as dependency, + * so that kbuild is not confused if a .c file + * is rewritten into .S or vice versa. Storing + * it in source_* is needed for modpost to + * compute srcversions. + */ + if (is_first_dep) { + /* + * If processing the concatenation of + * multiple dependency files, only + * process the first target name, which + * will be the original source name, + * and ignore any other target names, + * which will be intermediate temporary + * files. + */ + if (!saw_any_target) { + saw_any_target = 1; + printf("source_%s := %s\n\n", + target, s); + printf("deps_%s := \\\n", + target); + } + is_first_dep = 0; + } else + printf(" %s \\\n", s); + do_config_file(s); + } + } + /* + * Start searching for next token immediately after the first + * "whitespace" character that follows this token. + */ + m = p + 1; + } + + if (!saw_any_target) { + fprintf(stderr, "fixdep: parse error; no targets found\n"); + exit(1); + } + + printf("\n%s: $(deps_%s)\n\n", target, target); + printf("$(deps_%s):\n", target); +} + +static void print_deps(void) +{ + struct stat st; + int fd; + void *map; + + fd = open(depfile, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "fixdep: error opening depfile: "); + perror(depfile); + exit(2); + } + if (fstat(fd, &st) < 0) { + fprintf(stderr, "fixdep: error fstat'ing depfile: "); + perror(depfile); + exit(2); + } + if (st.st_size == 0) { + fprintf(stderr,"fixdep: %s is empty\n",depfile); + close(fd); + return; + } + map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); + if ((long) map == -1) { + perror("fixdep: mmap"); + close(fd); + return; + } + + parse_dep_file(map, st.st_size); + + munmap(map, st.st_size); + + close(fd); +} + +static void traps(void) +{ + static char test[] __attribute__((aligned(sizeof(int)))) = "CONF"; + int *p = (int *)test; + + if (*p != INT_CONF) { + fprintf(stderr, "fixdep: sizeof(int) != 4 or wrong endianness? %#x\n", + *p); + exit(2); + } +} + +int main(int argc, char *argv[]) +{ + traps(); + + if (argc != 4) + usage(); + + depfile = argv[1]; + target = argv[2]; + cmdline = argv[3]; + + print_cmdline(); + print_deps(); + + return 0; +} diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 88c5bc7735..3fed5e4694 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -6,6 +6,7 @@ # Licensed under the terms of the GNU GPL License version 2 use strict; +use POSIX; my $P = $0; $P =~ s@.*/@@g; @@ -27,13 +28,20 @@ my $summary = 1; my $mailback = 0; my $summary_file = 0; my $show_types = 0; +my $fix = 0; +my $fix_inplace = 0; my $root; my %debug; +my %camelcase = (); +my %use_type = (); +my @use = (); my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; my $max_line_length = 80; +my $ignore_perl_version = 0; +my $minimum_perl_version = 5.10.0; sub help { my ($exitcode) = @_; @@ -51,6 +59,7 @@ Options: --terse one line per report -f, --file treat FILE as regular source file --subjective, --strict enable more subjective tests + --types TYPE(,TYPE2...) show only these comma separated message types --ignore TYPE(,TYPE2...) ignore various comma separated message types --max-line-length=n set the maximum line length, if exceeded, warn --show-types show the message "types" in the output @@ -63,6 +72,16 @@ Options: is all off) --test-only=WORD report only warnings/errors containing WORD literally + --fix EXPERIMENTAL - may create horrible results + If correctable single-line errors exist, create + ".EXPERIMENTAL-checkpatch-fixes" + with potential errors corrected to the preferred + checkpatch style + --fix-inplace EXPERIMENTAL - may create horrible results + Is the same as --fix, but overwrites the input + file. It's your fault if there's no backup or git + --ignore-perl-version override checking of perl version. expect + runtime errors. -h, --help, --version display this help and exit When FILE is - read standard input. @@ -108,13 +127,16 @@ GetOptions( 'subjective!' => \$check, 'strict!' => \$check, 'ignore=s' => \@ignore, + 'types=s' => \@use, 'show-types!' => \$show_types, 'max-line-length=i' => \$max_line_length, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, 'summary-file!' => \$summary_file, - + 'fix!' => \$fix, + 'fix-inplace!' => \$fix_inplace, + 'ignore-perl-version!' => \$ignore_perl_version, 'debug=s' => \%debug, 'test-only=s' => \$tst_only, 'h|help' => \$help, @@ -123,26 +145,54 @@ GetOptions( help(0) if ($help); +$fix = 1 if ($fix_inplace); + my $exit = 0; +if ($^V && $^V lt $minimum_perl_version) { + printf "$P: requires at least perl version %vd\n", $minimum_perl_version; + if (!$ignore_perl_version) { + exit(1); + } +} + if ($#ARGV < 0) { print "$P: no input files\n"; exit(1); } -@ignore = split(/,/, join(',',@ignore)); -foreach my $word (@ignore) { - $word =~ s/\s*\n?$//g; - $word =~ s/^\s*//g; - $word =~ s/\s+/ /g; - $word =~ tr/[a-z]/[A-Z]/; +sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; - next if ($word =~ m/^\s*#/); - next if ($word =~ m/^\s*$/); + my @array = split(/,/, join(',', @$arrayRef)); + foreach my $word (@array) { + $word =~ s/\s*\n?$//g; + $word =~ s/^\s*//g; + $word =~ s/\s+/ /g; + $word =~ tr/[a-z]/[A-Z]/; - $ignore_type{$word}++; + next if ($word =~ m/^\s*#/); + next if ($word =~ m/^\s*$/); + + $hashRef->{$word}++; + } } +sub hash_show_words { + my ($hashRef, $prefix) = @_; + + if ($quiet == 0 && keys %$hashRef) { + print "NOTE: $prefix message types:"; + foreach my $word (sort keys %$hashRef) { + print " $word"; + } + print "\n\n"; + } +} + +hash_save_array_words(\%ignore_type, \@ignore); +hash_save_array_words(\%use_type, \@use); + my $dbg_values = 0; my $dbg_possible = 0; my $dbg_type = 0; @@ -198,6 +248,11 @@ our $Sparse = qr{ __ref| __rcu }x; +our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)}; +our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)}; +our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)}; +our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)}; +our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit}; # Notes to $Attribute: # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check @@ -219,7 +274,7 @@ our $Attribute = qr{ __deprecated| __read_mostly| __kprobes| - __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| + $InitAttribute| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| @@ -230,20 +285,26 @@ our $Inline = qr{inline|__always_inline|noinline}; our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; our $Lval = qr{$Ident(?:$Member)*}; +our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u}; +our $Binary = qr{(?i)0b[01]+$Int_type?}; +our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; +our $Int = qr{[0-9]+$Int_type?}; our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; our $Float = qr{$Float_hex|$Float_dec|$Float_int}; -our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; +our $Constant = qr{$Float|$Binary|$Hex|$Int}; our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; our $Compare = qr{<=|>=|==|!=|<|>}; +our $Arithmetic = qr{\+|-|\*|\/|%}; our $Operators = qr{ <=|>=|==|!=| =>|->|<<|>>|<|>|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% + &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic }x; our $NonptrType; +our $NonptrTypeWithAttr; our $Type; our $Declare; @@ -269,12 +330,14 @@ our $typeTypedefs = qr{(?x: our $logFunctions = qr{(?x: printk(?:_ratelimited|_once|)| - [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| WARN(?:_RATELIMIT|_ONCE|)| panic| debug| printf| - MODULE_[A-Z_]+ + puts| + MODULE_[A-Z_]+| + seq_vprintf|seq_printf|seq_puts )}; our $signature_tags = qr{(?xi: @@ -283,6 +346,7 @@ our $signature_tags = qr{(?xi: Tested-by:| Reviewed-by:| Reported-by:| + Suggested-by:| To:| Cc: )}; @@ -307,6 +371,12 @@ our @typeList = ( qr{${Ident}_handler}, qr{${Ident}_handler_fn}, ); +our @typeListWithAttr = ( + @typeList, + qr{struct\s+$InitAttribute\s+$Ident}, + qr{union\s+$InitAttribute\s+$Ident}, +); + our @modifierList = ( qr{fastcall}, ); @@ -320,6 +390,7 @@ our $allowed_asm_includes = qr{(?x: sub build_types { my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; + my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)"; $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; $NonptrType = qr{ (?:$Modifier\s+|const\s+)* @@ -330,6 +401,15 @@ sub build_types { ) (?:\s+$Modifier|\s+const)* }x; + $NonptrTypeWithAttr = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${allWithAttr}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; $Type = qr{ $NonptrType (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? @@ -339,7 +419,6 @@ sub build_types { } build_types(); - our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; # Using $balanced_parens, $LvalOrFunc, or $FuncArg @@ -359,10 +438,95 @@ sub deparenthesize { return $string; } +sub seed_camelcase_file { + my ($file) = @_; + + return if (!(-f $file)); + + local $/; + + open(my $include_file, '<', "$file") + or warn "$P: Can't read '$file' $!\n"; + my $text = <$include_file>; + close($include_file); + + my @lines = split('\n', $text); + + foreach my $line (@lines) { + next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + } +} + +my $camelcase_seeded = 0; +sub seed_camelcase_includes { + return if ($camelcase_seeded); + + my $files; + my $camelcase_cache = ""; + my @include_files = (); + + $camelcase_seeded = 1; + + if (-e ".git") { + my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; + } else { + my $last_mod_date = 0; + $files = `find $root/include -name "*.h"`; + @include_files = split('\n', $files); + foreach my $file (@include_files) { + my $date = POSIX::strftime("%Y%m%d%H%M", + localtime((stat $file)[9])); + $last_mod_date = $date if ($last_mod_date < $date); + } + $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date"; + } + + if ($camelcase_cache ne "" && -f $camelcase_cache) { + open(my $camelcase_file, '<', "$camelcase_cache") + or warn "$P: Can't read '$camelcase_cache' $!\n"; + while (<$camelcase_file>) { + chomp; + $camelcase{$_} = 1; + } + close($camelcase_file); + + return; + } + + if (-e ".git") { + $files = `git ls-files "include/*.h"`; + @include_files = split('\n', $files); + } + + foreach my $file (@include_files) { + seed_camelcase_file($file); + } + + if ($camelcase_cache ne "") { + unlink glob ".checkpatch-camelcase.*"; + open(my $camelcase_file, '>', "$camelcase_cache") + or warn "$P: Can't write '$camelcase_cache' $!\n"; + foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) { + print $camelcase_file ("$_\n"); + } + close($camelcase_file); + } +} + $chk_signoff = 0 if ($file); my @rawlines = (); my @lines = (); +my @fixed = (); my $vname; for my $filename (@ARGV) { my $FILE; @@ -390,6 +554,7 @@ for my $filename (@ARGV) { } @rawlines = (); @lines = (); + @fixed = (); } exit($exit); @@ -398,7 +563,7 @@ sub top_of_kernel_tree { my ($root) = @_; my @tree_check = ( - "COPYING", "CREDITS", "Kbuild", "Makefile", + "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", "README", "Documentation", "arch", "include", "drivers", "fs", "init", "ipc", "kernel", "lib", "scripts", ); @@ -430,7 +595,7 @@ sub parse_email { $comment = $2 if defined $2; $formatted_email =~ s/$address.*$//; $name = $formatted_email; - $name =~ s/^\s+|\s+$//g; + $name = trim($name); $name =~ s/^\"|\"$//g; # If there's a name left after stripping spaces and # leading quotes, and the address doesn't have both @@ -445,9 +610,9 @@ sub parse_email { } } - $name =~ s/^\s+|\s+$//g; + $name = trim($name); $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; + $address = trim($address); $address =~ s/^\<|\>$//g; if ($name =~ /[^\w \-]/i) { ##has "must quote" chars @@ -463,9 +628,9 @@ sub format_email { my $formatted_email; - $name =~ s/^\s+|\s+$//g; + $name = trim($name); $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; + $address = trim($address); if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(? 0); + + return !defined $ignore_type{$_[0]}; } sub report { @@ -1280,19 +1454,25 @@ sub ERROR { if (report("ERROR", $_[0], $_[1])) { our $clean = 0; our $cnt_error++; + return 1; } + return 0; } sub WARN { if (report("WARNING", $_[0], $_[1])) { our $clean = 0; our $cnt_warn++; + return 1; } + return 0; } sub CHK { if ($check && report("CHECK", $_[0], $_[1])) { our $clean = 0; our $cnt_chk++; + return 1; } + return 0; } sub check_absolute_file { @@ -1323,6 +1503,53 @@ sub check_absolute_file { } } +sub trim { + my ($string) = @_; + + $string =~ s/^\s+|\s+$//g; + + return $string; +} + +sub ltrim { + my ($string) = @_; + + $string =~ s/^\s+//; + + return $string; +} + +sub rtrim { + my ($string) = @_; + + $string =~ s/\s+$//; + + return $string; +} + +sub string_find_replace { + my ($string, $find, $replace) = @_; + + $string =~ s/$find/$replace/g; + + return $string; +} + +sub tabify { + my ($leading) = @_; + + my $source_indent = 8; + my $max_spaces_before_tab = $source_indent - 1; + my $spaces_to_tab = " " x $source_indent; + + #convert leading spaces to tabs + 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g; + #Remove spaces before a tab + 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g; + + return "$leading"; +} + sub pos_last_openparen { my ($line) = @_; @@ -1400,7 +1627,7 @@ sub process { my %suppress_export; my $suppress_statement = 0; - my %camelcase = (); + my %signatures = (); # Pre-scan the patch sanitizing the lines. # Pre-scan the patch looking for any __setup documentation. @@ -1408,12 +1635,16 @@ sub process { my @setup_docs = (); my $setup_docs = 0; + my $camelcase_file_seeded = 0; + sanitise_line_reset(); my $line; foreach my $rawline (@rawlines) { $linenr++; $line = $rawline; + push(@fixed, $rawline) if ($fix); + if ($rawline=~/^\+\+\+\s+(\S+)/) { $setup_docs = 0; if ($1 =~ m@Documentation/kernel-parameters.txt$@) { @@ -1491,6 +1722,8 @@ sub process { $linenr = 0; foreach my $line (@lines) { $linenr++; + my $sline = $line; #copy of $line + $sline =~ s/$;/ /g; #with comments as spaces my $rawline = $rawlines[$linenr - 1]; @@ -1546,11 +1779,11 @@ sub process { # extract the filename as it passes if ($line =~ /^diff --git.*?(\S+)$/) { $realfile = $1; - $realfile =~ s@^([^/]*)/@@; + $realfile =~ s@^([^/]*)/@@ if (!$file); $in_commit_log = 0; } elsif ($line =~ /^\+\+\+\s+(\S+)/) { $realfile = $1; - $realfile =~ s@^([^/]*)/@@; + $realfile =~ s@^([^/]*)/@@ if (!$file); $in_commit_log = 0; $p1_prefix = $1; @@ -1578,7 +1811,8 @@ sub process { # Check for incorrect file permissions if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { my $permhere = $here . "FILE: $realfile\n"; - if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) { + if ($realfile !~ m@scripts/@ && + $realfile !~ /\.(py|pl|awk|sh)$/) { ERROR("EXECUTE_PERMISSIONS", "do not set execute permissions for source files\n" . $permhere); } @@ -1604,16 +1838,29 @@ sub process { "Non-standard signature: $sign_off\n" . $herecurr); } if (defined $space_before && $space_before ne "") { - WARN("BAD_SIGN_OFF", - "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } } if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { - WARN("BAD_SIGN_OFF", - "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } + } if (!defined $space_after || $space_after ne " ") { - WARN("BAD_SIGN_OFF", - "Use a single space after $ucfirst_sign_off\n" . $herecurr); + if (WARN("BAD_SIGN_OFF", + "Use a single space after $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } } my ($email_name, $email_address, $comment) = parse_email($email); @@ -1634,6 +1881,17 @@ sub process { "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); } } + +# Check for duplicate signatures + my $sig_nospace = $line; + $sig_nospace =~ s/\s//g; + $sig_nospace = lc($sig_nospace); + if (defined $signatures{$sig_nospace}) { + WARN("BAD_SIGN_OFF", + "Duplicate signature\n" . $herecurr); + } else { + $signatures{$sig_nospace} = 1; + } } # Check for wrappage within a valid hunk of the file @@ -1698,16 +1956,33 @@ sub process { #trailing whitespace if ($line =~ /^\+.*\015/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("DOS_LINE_ENDINGS", - "DOS line endings\n" . $herevet); - + if (ERROR("DOS_LINE_ENDINGS", + "DOS line endings\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/[\s\015]+$//; + } } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("TRAILING_WHITESPACE", - "trailing whitespace\n" . $herevet); + if (ERROR("TRAILING_WHITESPACE", + "trailing whitespace\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/\s+$//; + } + $rpt_cleaners = 1; } +# Check for FSF mailing addresses. + if ($rawline =~ /\bwrite to the Free/i || + $rawline =~ /\b59\s+Temple\s+Pl/i || + $rawline =~ /\b51\s+Franklin\s+St/i) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + my $msg_type = \&ERROR; + $msg_type = \&CHK if ($file); + &{$msg_type}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) + } + # check for Kconfig help text having a real description # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. @@ -1768,6 +2043,33 @@ sub process { "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); } +# check for DT compatible documentation + if (defined $root && $realfile =~ /\.dts/ && + $rawline =~ /^\+\s*compatible\s*=/) { + my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; + + foreach my $compat (@compats) { + my $compat2 = $compat; + my $dt_path = $root . "/Documentation/devicetree/bindings/"; + $compat2 =~ s/\,[a-z]*\-/\,<\.\*>\-/; + `grep -Erq "$compat|$compat2" $dt_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr); + } + + my $vendor = $compat; + my $vendor_path = $dt_path . "vendor-prefixes.txt"; + next if (! -f $vendor_path); + $vendor =~ s/^([a-zA-Z0-9]+)\,.*/$1/; + `grep -Eq "$vendor" $vendor_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string vendor \"$vendor\" appears un-documented -- check $vendor_path\n" . $herecurr); + } + } + } + # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); @@ -1783,24 +2085,24 @@ sub process { } # Check for user-visible strings broken across lines, which breaks the ability -# to grep for the string. Limited to strings used as parameters (those -# following an open parenthesis), which almost completely eliminates false -# positives, as well as warning only once per parameter rather than once per -# line of the string. Make an exception when the previous string ends in a -# newline (multiple lines in one string constant) or \n\t (common in inline -# assembly to indent the instruction on the following line). +# to grep for the string. Make exceptions when the previous string ends in a +# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{' +# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value if ($line =~ /^\+\s*"/ && $prevline =~ /"\s*$/ && - $prevline =~ /\(/ && - $prevrawline !~ /\\n(?:\\t)*"\s*$/) { + $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) { WARN("SPLIT_STRING", "quoted string split across lines\n" . $hereprev); } # check for spaces before a quoted newline if ($rawline =~ /^.*\".*\s\\n/) { - WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", - "unnecessary whitespace before a quoted newline\n" . $herecurr); + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", + "unnecessary whitespace before a quoted newline\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/^(\+.*\".*)\s+\\n/$1\\n/; + } + } # check for adding lines without a newline. @@ -1831,16 +2133,25 @@ sub process { if ($rawline =~ /^\+\s* \t\s*\S/ || $rawline =~ /^\+\s* \s*/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("CODE_INDENT", - "code indent should use tabs where possible\n" . $herevet); $rpt_cleaners = 1; + if (ERROR("CODE_INDENT", + "code indent should use tabs where possible\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } } # check for space before tabs. if ($rawline =~ /^\+/ && $rawline =~ / \t/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("SPACE_BEFORE_TAB", - "please, no space before tabs\n" . $herevet); + if (WARN("SPACE_BEFORE_TAB", + "please, no space before tabs\n" . $herevet) && + $fix) { + while ($fixed[$linenr - 1] =~ + s/(^\+.*) {8,8}+\t/$1\t\t/) {} + while ($fixed[$linenr - 1] =~ + s/(^\+.*) +\t/$1\t/) {} + } } # check for && or || at the start of a line @@ -1868,24 +2179,42 @@ sub process { if ($newindent ne $goodtabindent && $newindent ne $goodspaceindent) { - CHK("PARENTHESIS_ALIGNMENT", - "Alignment should match open parenthesis\n" . $hereprev); + + if (CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev) && + $fix && $line =~ /^\+/) { + $fixed[$linenr - 1] =~ + s/^\+[ \t]*/\+$goodtabindent/; + } } } } - if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { - CHK("SPACING", - "No space is necessary after a cast\n" . $hereprev); + if ($line =~ /^\+.*\*[ \t]*\)[ \t]+(?!$Assignment|$Arithmetic)/) { + if (CHK("SPACING", + "No space is necessary after a cast\n" . $hereprev) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(\+.*\*[ \t]*\))[ \t]+/$1/; + } } if ($realfile =~ m@^(drivers/net/|net/)@ && - $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && - $prevrawline =~ /^\+[ \t]*$/) { + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/) { WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); } + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*/ && #starting /* + $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */ + $rawline =~ /^\+/ && #line is new + $rawline !~ /^\+[ \t]*\*/) { #no leading * + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments start with * on subsequent lines\n" . $hereprev); + } + if ($realfile =~ m@^(drivers/net/|net/)@ && $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ @@ -1900,10 +2229,13 @@ sub process { # 1) within comments # 2) indented preprocessor commands # 3) hanging labels - if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { + if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("LEADING_SPACE", - "please, no spaces at the start of a line\n" . $herevet); + if (WARN("LEADING_SPACE", + "please, no spaces at the start of a line\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } } # check we are in a valid C source file if not then ignore this hunk @@ -1944,7 +2276,7 @@ sub process { $realline_next); #print "LINE<$line>\n"; if ($linenr >= $suppress_statement && - $realcnt && $line =~ /.\s*\S/) { + $realcnt && $sline =~ /.\s*\S/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0); $stat =~ s/\n./\n /g; @@ -2193,7 +2525,7 @@ sub process { $prev_values = substr($curr_values, -1); #ignore lines not being added - if ($line=~/^[^\+]/) {next;} + next if ($line =~ /^[^\+]/); # TEST: allow direct testing of the type matcher. if ($dbg_type) { @@ -2244,8 +2576,15 @@ sub process { # no C99 // comments if ($line =~ m{//}) { - ERROR("C99_COMMENTS", - "do not use C99 // comments\n" . $herecurr); + if (ERROR("C99_COMMENTS", + "do not use C99 // comments\n" . $herecurr) && + $fix) { + my $line = $fixed[$linenr - 1]; + if ($line =~ /\/\/(.*)$/) { + my $comment = trim($1); + $fixed[$linenr - 1] =~ s@\/\/(.*)$@/\* $comment \*/@; + } + } } # Remove C99 comments. $line =~ s@//.*@@; @@ -2297,16 +2636,22 @@ sub process { } # check for global initialisers. - if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { - ERROR("GLOBAL_INITIALISERS", - "do not initialise globals to 0 or NULL\n" . - $herecurr); + if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/; + } } # check for static initialisers. - if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { - ERROR("INITIALISED_STATIC", - "do not initialise statics to 0 or NULL\n" . - $herecurr); + if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) { + if (ERROR("INITIALISED_STATIC", + "do not initialise statics to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/; + } } # check for static const char * arrays. @@ -2323,10 +2668,22 @@ sub process { $herecurr); } -# check for declarations of struct pci_device_id - if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { - WARN("DEFINE_PCI_DEVICE_TABLE", - "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); +# check for function declarations without arguments like "int foo()" + if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) { + if (ERROR("FUNCTION_WITHOUT_ARGS", + "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/; + } + } + +# check for uses of DEFINE_PCI_DEVICE_TABLE + if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) { + if (WARN("DEFINE_PCI_DEVICE_TABLE", + "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /; + } } # check for new typedefs, only function parameters and sparse annotations @@ -2344,7 +2701,7 @@ sub process { # (char*[ const]) while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { #print "AA<$1>\n"; - my ($from, $to) = ($2, $2); + my ($ident, $from, $to) = ($1, $2, $2); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2354,15 +2711,22 @@ sub process { while ($to =~ s/\*\s+\*/\*\*/) { } - #print "from<$from> to<$to>\n"; +## print "1: from<$from> to<$to> ident<$ident>\n"; if ($from ne $to) { - ERROR("POINTER_LOCATION", - "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); + if (ERROR("POINTER_LOCATION", + "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) && + $fix) { + my $sub_from = $ident; + my $sub_to = $ident; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$linenr - 1] =~ + s@\Q$sub_from\E@$sub_to@; + } } } while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { #print "BB<$1>\n"; - my ($from, $to, $ident) = ($2, $2, $3); + my ($match, $from, $to, $ident) = ($1, $2, $2, $3); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2374,10 +2738,18 @@ sub process { # Modifiers should have spaces. $to =~ s/(\b$Modifier$)/$1 /; - #print "from<$from> to<$to> ident<$ident>\n"; +## print "2: from<$from> to<$to> ident<$ident>\n"; if ($from ne $to && $ident !~ /^$Modifier$/) { - ERROR("POINTER_LOCATION", - "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); + if (ERROR("POINTER_LOCATION", + "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) && + $fix) { + + my $sub_from = $match; + my $sub_to = $match; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$linenr - 1] =~ + s@\Q$sub_from\E@$sub_to@; + } } } @@ -2434,8 +2806,12 @@ sub process { } if ($line =~ /\bpr_warning\s*\(/) { - WARN("PREFER_PR_LEVEL", - "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); + if (WARN("PREFER_PR_LEVEL", + "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\bpr_warning\b/pr_warn/; + } } if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { @@ -2463,9 +2839,72 @@ sub process { } # missing space after union, struct or enum definition - if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { - WARN("SPACING", - "missing space after $1 definition\n" . $herecurr); + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) { + if (WARN("SPACING", + "missing space after $1 definition\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/; + } + } + +# Function pointer declarations +# check spacing between type, funcptr, and args +# canonical declaration is "type (*funcptr)(args...)" +# +# the $Declare variable will capture all spaces after the type +# so check it for trailing missing spaces or multiple spaces + if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)$Ident(\s*)\)(\s*)\(/) { + my $declare = $1; + my $pre_pointer_space = $2; + my $post_pointer_space = $3; + my $funcname = $4; + my $post_funcname_space = $5; + my $pre_args_space = $6; + + if ($declare !~ /\s$/) { + WARN("SPACING", + "missing space after return type\n" . $herecurr); + } + +# unnecessary space "type (*funcptr)(args...)" + elsif ($declare =~ /\s{2,}$/) { + WARN("SPACING", + "Multiple spaces after return type\n" . $herecurr); + } + +# unnecessary space "type ( *funcptr)(args...)" + if (defined $pre_pointer_space && + $pre_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer open parenthesis\n" . $herecurr); + } + +# unnecessary space "type (* funcptr)(args...)" + if (defined $post_pointer_space && + $post_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr )(args...)" + if (defined $post_funcname_space && + $post_funcname_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr) (args...)" + if (defined $pre_args_space && + $pre_args_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer arguments\n" . $herecurr); + } + + if (show_type("SPACING") && $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*$Declare)\(\s*\*\s*($Ident)\s*\)\s*\(/rtrim($1) . " " . "\(\*$2\)\("/ex; + } } # check for spacing round square brackets; allowed: @@ -2477,8 +2916,12 @@ sub process { if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && $prefix !~ /[{,]\s+$/) { - ERROR("BRACKET_SPACE", - "space prohibited before open square bracket '['\n" . $herecurr); + if (ERROR("BRACKET_SPACE", + "space prohibited before open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(\+.*?)\s+\[/$1\[/; + } } } @@ -2495,7 +2938,6 @@ sub process { __attribute__|format|__extension__| asm|__asm__)$/x) { - # cpp #define statements have non-optional spaces, ie # if there is a space between the name and the open # parenthesis it is simply not a parameter group. @@ -2509,32 +2951,53 @@ sub process { } elsif ($ctx =~ /$Type$/) { } else { - WARN("SPACING", - "space prohibited between function name and open parenthesis '('\n" . $herecurr); + if (WARN("SPACING", + "space prohibited between function name and open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\b$name\s+\(/$name\(/; + } } } -# check for whitespace before a non-naked semicolon - if ($line =~ /^\+.*\S\s+;/) { - CHK("SPACING", - "space prohibited before semicolon\n" . $herecurr); - } - # Check operator spacing. if (!($line=~/\#\s*include/)) { + my $fixed_line = ""; + my $line_fixed = 0; + my $ops = qr{ <<=|>>=|<=|>=|==|!=| \+=|-=|\*=|\/=|%=|\^=|\|=|&=| =>|->|<<|>>|<|>|=|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| - \?|: + \?:|\?|: }x; my @elements = split(/($ops|;)/, $opline); + +## print("element count: <" . $#elements . ">\n"); +## foreach my $el (@elements) { +## print("el: <$el>\n"); +## } + + my @fix_elements = (); my $off = 0; + foreach my $el (@elements) { + push(@fix_elements, substr($rawline, $off, length($el))); + $off += length($el); + } + + $off = 0; + my $blank = copy_spacing($opline); + my $last_after = -1; for (my $n = 0; $n < $#elements; $n += 2) { + + my $good = $fix_elements[$n] . $fix_elements[$n + 1]; + +## print("n: <$n> good: <$good>\n"); + $off += length($elements[$n]); # Pick up the preceding and succeeding characters. @@ -2591,8 +3054,11 @@ sub process { } elsif ($op eq ';') { if ($ctx !~ /.x[WEBC]/ && $cc !~ /^\\/ && $cc !~ /^;/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } } # // is a comment @@ -2603,15 +3069,25 @@ sub process { # : when part of a bitfield } elsif ($op eq '->' || $opv eq ':B') { if ($ctx =~ /Wx.|.xW/) { - ERROR("SPACING", - "spaces prohibited around that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "spaces prohibited around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } # , must have a space on the right. } elsif ($op eq ',') { if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + $last_after = $n; + } } # '*' as part of a type definition -- reported already. @@ -2625,34 +3101,56 @@ sub process { $opv eq '*U' || $opv eq '-U' || $opv eq '&U' || $opv eq '&&U') { if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { - ERROR("SPACING", - "space required before that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required before that '$op' $at\n" . $hereptr)) { + if ($n != $last_after + 2) { + $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } } if ($op eq '*' && $cc =~/\s*$Modifier\b/) { # A unary '*' may be const } elsif ($ctx =~ /.xW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } # unary ++ and unary -- are allowed no space on one side. } elsif ($op eq '++' or $op eq '--') { if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { - ERROR("SPACING", - "space required one side of that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space required one side of that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } } if ($ctx =~ /Wx[BE]/ || ($ctx =~ /Wx./ && $cc =~ /^;/)) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } } if ($ctx =~ /ExW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } - # << and >> may either have or not have spaces both sides } elsif ($op eq '<<' or $op eq '>>' or $op eq '&' or $op eq '^' or $op eq '|' or @@ -2661,17 +3159,25 @@ sub process { $op eq '%') { if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { - ERROR("SPACING", - "need consistent spacing around '$op' $at\n" . - $hereptr); + if (ERROR("SPACING", + "need consistent spacing around '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } # A colon needs no spaces before when it is # terminating a case value or a label. } elsif ($opv eq ':C' || $opv eq ':L') { if ($ctx =~ /Wx./) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } } # All the others need spaces both sides. @@ -2684,21 +3190,49 @@ sub process { ($op eq '>' && $ca =~ /<\S+\@\S+$/)) { - $ok = 1; - } - - # Ignore ?: - if (($opv eq ':O' && $ca =~ /\?$/) || - ($op eq '?' && $cc =~ /^:/)) { - $ok = 1; + $ok = 1; } + # messages are ERROR, but ?: are CHK if ($ok == 0) { - ERROR("SPACING", - "spaces required around that '$op' $at\n" . $hereptr); + my $msg_type = \&ERROR; + $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + + if (&{$msg_type}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } } } $off += length($elements[$n + 1]); + +## print("n: <$n> GOOD: <$good>\n"); + + $fixed_line = $fixed_line . $good; + } + + if (($#elements % 2) == 0) { + $fixed_line = $fixed_line . $fix_elements[$#elements]; + } + + if ($fix && $line_fixed && $fixed_line ne $fixed[$linenr - 1]) { + $fixed[$linenr - 1] = $fixed_line; + } + + + } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;\s*$/) { + if (WARN("SPACING", + "space prohibited before semicolon\n" . $herecurr) && + $fix) { + 1 while $fixed[$linenr - 1] =~ + s/^(\+.*\S)\s+;/$1;/; } } @@ -2727,63 +3261,87 @@ sub process { #need space before brace following if, while, etc if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || $line =~ /do{/) { - ERROR("SPACING", - "space required before the open brace '{'\n" . $herecurr); + if (ERROR("SPACING", + "space required before the open brace '{'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/^(\+.*(?:do|\))){/$1 {/; + } } +## # check for blank lines before declarations +## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ && +## $prevrawline =~ /^.\s*$/) { +## WARN("SPACING", +## "No blank lines before declarations\n" . $hereprev); +## } +## + # closing brace should have a space following it when it has anything # on the line if ($line =~ /}(?!(?:,|;|\)))\S/) { - ERROR("SPACING", - "space required after that close brace '}'\n" . $herecurr); + if (ERROR("SPACING", + "space required after that close brace '}'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/}((?!(?:,|;|\)))\S)/} $1/; + } } # check spacing on square brackets if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { - ERROR("SPACING", - "space prohibited after that open square bracket '['\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited after that open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\[\s+/\[/; + } } if ($line =~ /\s\]/) { - ERROR("SPACING", - "space prohibited before that close square bracket ']'\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited before that close square bracket ']'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\s+\]/\]/; + } } # check spacing on parentheses if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && $line !~ /for\s*\(\s+;/) { - ERROR("SPACING", - "space prohibited after that open parenthesis '('\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited after that open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\(\s+/\(/; + } } if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && $line !~ /for\s*\(.*;\s+\)/ && $line !~ /:\s+\)/) { - ERROR("SPACING", - "space prohibited before that close parenthesis ')'\n" . $herecurr); + if (ERROR("SPACING", + "space prohibited before that close parenthesis ')'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\s+\)/\)/; + } } #goto labels aren't indented, allow a single space however if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { - WARN("INDENTED_LABEL", - "labels should not be indented\n" . $herecurr); + if (WARN("INDENTED_LABEL", + "labels should not be indented\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.)\s+/$1/; + } } # Return is not a function. - if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { my $spacing = $1; - my $value = $2; - - # Flatten any parentheses - $value =~ s/\(/ \(/g; - $value =~ s/\)/\) /g; - while ($value =~ s/\[[^\[\]]*\]/1/ || - $value !~ /(?:$Ident|-?$Constant)\s* - $Compare\s* - (?:$Ident|-?$Constant)/x && - $value =~ s/\([^\(\)]*\)/1/) { - } -#print "value<$value>\n"; - if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { + if ($^V && $^V ge 5.10.0 && + $stat =~ /^.\s*return\s*$balanced_parens\s*;\s*$/) { ERROR("RETURN_PARENTHESES", "return is not a function, parentheses are not required\n" . $herecurr); @@ -2792,6 +3350,21 @@ sub process { "space required before the open parenthesis '('\n" . $herecurr); } } + +# if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($^V && $^V ge 5.10.0 && + $line =~ /\bif\s*((?:\(\s*){2,})/) { + my $openparens = $1; + my $count = $openparens =~ tr@\(@\(@; + my $msg = ""; + if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) { + my $comp = $4; #Not $1 because of $LvalOrFunc + $msg = " - maybe == should be = ?" if ($comp eq "=="); + WARN("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses$msg\n" . $herecurr); + } + } + # Return of what appears to be an errno should normally be -'ve if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { my $name = $1; @@ -2802,8 +3375,13 @@ sub process { } # Need a space before open parenthesis after if, while etc - if ($line=~/\b(if|while|for|switch)\(/) { - ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); + if ($line =~ /\b(if|while|for|switch)\(/) { + if (ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\b(if|while|for|switch)\(/$1 \(/; + } } # Check for illegal assignment in if conditional -- and check for trailing @@ -2830,6 +3408,7 @@ sub process { } } if (!defined $suppress_whiletrailers{$linenr} && + defined($stat) && defined($cond) && $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { my ($s, $c) = ($stat, $cond); @@ -2927,23 +3506,54 @@ sub process { } } -#CamelCase +#Specific variable tests while ($line =~ m{($Constant|$Lval)}g) { my $var = $1; - if ($var !~ /$Constant/ && - $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && - $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && - !defined $camelcase{$var}) { - $camelcase{$var} = 1; - WARN("CAMELCASE", - "Avoid CamelCase: <$var>\n" . $herecurr); + +#gcc binary extension + if ($var =~ /^$Binary$/) { + if (WARN("GCC_BINARY_CONSTANT", + "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) && + $fix) { + my $hexval = sprintf("0x%x", oct($var)); + $fixed[$linenr - 1] =~ + s/\b$var\b/$hexval/; + } + } + +#CamelCase + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore Page variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && +#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show) + $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) { + while ($var =~ m{($Ident)}g) { + my $word = $1; + next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/); + if ($check) { + seed_camelcase_includes(); + if (!$file && !$camelcase_file_seeded) { + seed_camelcase_file($realfile); + $camelcase_file_seeded = 1; + } + } + if (!defined $camelcase{$word}) { + $camelcase{$word} = 1; + CHK("CAMELCASE", + "Avoid CamelCase: <$word>\n" . $herecurr); + } + } } } #no spaces allowed after \ in define - if ($line=~/\#\s*define.*\\\s$/) { - WARN("WHITESPACE_AFTER_LINE_CONTINUATION", - "Whitepspace after \\ makes next lines useless\n" . $herecurr); + if ($line =~ /\#\s*define.*\\\s+$/) { + if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION", + "Whitespace after \\ makes next lines useless\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\s+$//; + } } #warn if is #included and is available (uses RAW line) @@ -3014,15 +3624,17 @@ sub process { if ($dstat ne '' && $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); - $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo + $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz $dstat !~ /^'X'$/ && # character constants $dstat !~ /$exceptions/ && $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) $dstat !~ /^for\s*$Constant$/ && # for (...) $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() $dstat !~ /^do\s*{/ && # do {... - $dstat !~ /^\({/) # ({... + $dstat !~ /^\({/ && # ({... + $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) { $ctx =~ s/\n*$//; my $herectx = $here . "\n"; @@ -3222,11 +3834,11 @@ sub process { } # check for unnecessary blank lines around braces - if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) { + if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) { CHK("BRACES", "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); } - if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { CHK("BRACES", "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); } @@ -3254,6 +3866,53 @@ sub process { } } +# check for bad placement of section $InitAttribute (e.g.: __initdata) + if ($line =~ /(\b$InitAttribute\b)/) { + my $attr = $1; + if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) { + my $ptr = $1; + my $var = $2; + if ((($ptr =~ /\b(union|struct)\s+$attr\b/ && + ERROR("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr)) || + ($ptr !~ /\b(union|struct)\s+$attr\b/ && + WARN("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr))) && + $fix) { + $fixed[$linenr - 1] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e; + } + } + } + +# check for $InitAttributeData (ie: __initdata) with const + if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) { + my $attr = $1; + $attr =~ /($InitAttributePrefix)(.*)/; + my $attr_prefix = $1; + my $attr_type = $2; + if (ERROR("INIT_ATTRIBUTE", + "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/$InitAttributeData/${attr_prefix}initconst/; + } + } + +# check for $InitAttributeConst (ie: __initconst) without const + if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) { + my $attr = $1; + if (ERROR("INIT_ATTRIBUTE", + "Use of $attr requires a separate use of const\n" . $herecurr) && + $fix) { + my $lead = $fixed[$linenr - 1] =~ + /(^\+\s*(?:static\s+))/; + $lead = rtrim($1); + $lead = "$lead " if ($lead !~ /^\+$/); + $lead = "${lead}const "; + $fixed[$linenr - 1] =~ s/(^\+\s*(?:static\s+))/$lead/; + } + } + # prefer usleep_range over udelay if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { # ignore udelay's < 10, however @@ -3271,6 +3930,18 @@ sub process { } } +# check for comparisons of jiffies + if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) { + WARN("JIFFIES_COMPARISON", + "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr); + } + +# check for comparisons of get_jiffies_64() + if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) { + WARN("JIFFIES_COMPARISON", + "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr); + } + # warn about #ifdefs in C files # if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { # print "#ifdef in C files should be avoided\n"; @@ -3280,8 +3951,13 @@ sub process { # warn about spacing in #ifdefs if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { - ERROR("SPACING", - "exactly one space required after that #$1\n" . $herecurr); + if (ERROR("SPACING", + "exactly one space required after that #$1\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /; + } + } # check for spinlock_t definitions without a comment. @@ -3296,8 +3972,8 @@ sub process { # check for memory barriers without a comment. if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { if (!ctx_has_comment($first_line, $linenr)) { - CHK("MEMORY_BARRIER", - "memory barrier without comment\n" . $herecurr); + WARN("MEMORY_BARRIER", + "memory barrier without comment\n" . $herecurr); } } # check of hardware specific defines @@ -3321,33 +3997,54 @@ sub process { } # Check for __inline__ and __inline, prefer inline - if ($line =~ /\b(__inline__|__inline)\b/) { - WARN("INLINE", - "plain inline is preferred over $1\n" . $herecurr); + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b(__inline__|__inline)\b/) { + if (WARN("INLINE", + "plain inline is preferred over $1\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b(__inline__|__inline)\b/inline/; + + } } # Check for __attribute__ packed, prefer __packed - if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { WARN("PREFER_PACKED", "__packed is preferred over __attribute__((packed))\n" . $herecurr); } +# Check for new packed members, warn to use care + if ($line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) { + WARN("NEW_PACKED", + "Adding new packed members is to be done with care\n" . $herecurr); + } # Check for __attribute__ aligned, prefer __aligned - if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { WARN("PREFER_ALIGNED", "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); } # Check for __attribute__ format(printf, prefer __printf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { - WARN("PREFER_PRINTF", - "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { + if (WARN("PREFER_PRINTF", + "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; + + } } # Check for __attribute__ format(scanf, prefer __scanf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { - WARN("PREFER_SCANF", - "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { + if (WARN("PREFER_SCANF", + "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; + } } # check for sizeof(&) @@ -3358,8 +4055,11 @@ sub process { # check for sizeof without parenthesis if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { - WARN("SIZEOF_PARENTHESIS", - "sizeof $1 should be sizeof($1)\n" . $herecurr); + if (WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex; + } } # check for line continuations in quoted strings with odd counts of " @@ -3374,6 +4074,18 @@ sub process { "struct spinlock should be spinlock_t\n" . $herecurr); } +# check for seq_printf uses that could be seq_puts + if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) { + my $fmt = get_quoted_string($line, $rawline); + if ($fmt ne "" && $fmt !~ /[^\\]\%/) { + if (WARN("PREFER_SEQ_PUTS", + "Prefer seq_puts to seq_printf\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bseq_printf\b/seq_puts/; + } + } + } + # Check for misused memsets if ($^V && $^V ge 5.10.0 && defined $stat && @@ -3392,6 +4104,16 @@ sub process { } } +# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) + if ($^V && $^V ge 5.10.0 && + $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) { + if (WARN("PREFER_ETHER_ADDR_COPY", + "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/; + } + } + # typecasts on min/max could be min_t/max_t if ($^V && $^V ge 5.10.0 && defined $stat && @@ -3432,6 +4154,33 @@ sub process { } } +# check for naked sscanf + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /\bsscanf\b/ && + ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && + $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ && + $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + WARN("NAKED_SSCANF", + "unchecked sscanf return value\n" . "$here\n$stat_real\n"); + } + +# check for new externs in .h files. + if ($realfile =~ /\.h$/ && + $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) { + if (CHK("AVOID_EXTERNS", + "extern prototypes should be avoided in .h files\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(.*)\bextern\b\s*(.*)/$1$2/; + } + } + # check for new externs in .c files. if ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) @@ -3478,16 +4227,65 @@ sub process { "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); } +# alloc style +# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { + CHK("ALLOC_SIZEOF_STRUCT", + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +# check for krealloc arg reuse + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { + WARN("KREALLOC_ARG_REUSE", + "Reusing the krealloc arg is almost always a bug\n" . $herecurr); + } + # check for alloc argument mismatch if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { WARN("ALLOC_ARRAY_ARGS", "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); } +# check for GFP_NOWAIT use + if ($line =~ /\b__GFP_NOFAIL\b/) { + WARN("__GFP_NOFAIL", + "Use of __GFP_NOFAIL is deprecated, no new users should be added\n" . $herecurr); + } + # check for multiple semicolons if ($line =~ /;\s*;\s*$/) { - WARN("ONE_SEMICOLON", - "Statements terminations use 1 semicolon\n" . $herecurr); + if (WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\s*;\s*){2,}$/;/g; + } + } + +# check for case / default statements not preceeded by break/fallthrough/switch + if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { + my $has_break = 0; + my $has_statement = 0; + my $count = 0; + my $prevline = $linenr; + while ($prevline > 1 && $count < 3 && !$has_break) { + $prevline--; + my $rline = $rawlines[$prevline - 1]; + my $fline = $lines[$prevline - 1]; + last if ($fline =~ /^\@\@/); + next if ($fline =~ /^\-/); + next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/); + $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i); + next if ($fline =~ /^.[\s$;]*$/); + $has_statement = 1; + $count++; + $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/); + } + if (!$has_break && $has_statement) { + WARN("MISSING_BREAK", + "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr); + } } # check for switch/default statements without a break; @@ -3505,9 +4303,12 @@ sub process { } # check for gcc specific __FUNCTION__ - if ($line =~ /__FUNCTION__/) { - WARN("USE_FUNC", - "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); + if ($line =~ /\b__FUNCTION__\b/) { + if (WARN("USE_FUNC", + "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__FUNCTION__\b/__func__/g; + } } # check for use of yield() @@ -3516,6 +4317,33 @@ sub process { "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); } +# check for comparisons against true and false + if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) { + my $lead = $1; + my $arg = $2; + my $test = $3; + my $otype = $4; + my $trail = $5; + my $op = "!"; + + ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i); + + my $type = lc($otype); + if ($type =~ /^(?:true|false)$/) { + if (("$test" eq "==" && "$type" eq "true") || + ("$test" eq "!=" && "$type" eq "false")) { + $op = ""; + } + + CHK("BOOL_COMPARISON", + "Using comparison to $otype is error prone\n" . $herecurr); + +## maybe suggesting a correct construct would better +## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr); + + } + } + # check for semaphores initialized locked if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { WARN("CONSIDER_COMPLETION", @@ -3592,6 +4420,12 @@ sub process { "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); } +# Use of __ARCH_HAS_ or ARCH_HAVE_ is wrong. + if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) { + ERROR("DEFINE_ARCH_HAS", + "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr); + } + # check for %L{u,d,i} in strings my $string; while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { @@ -3685,12 +4519,42 @@ sub process { } } - if ($quiet == 0 && keys %ignore_type) { - print "NOTE: Ignored message types:"; - foreach my $ignore (sort keys %ignore_type) { - print " $ignore"; - } - print "\n\n"; + hash_show_words(\%use_type, "Used"); + hash_show_words(\%ignore_type, "Ignored"); + + if ($clean == 0 && $fix && "@rawlines" ne "@fixed") { + my $newfile = $filename; + $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace); + my $linecount = 0; + my $f; + + open($f, '>', $newfile) + or die "$P: Can't open $newfile for write\n"; + foreach my $fixed_line (@fixed) { + $linecount++; + if ($file) { + if ($linecount > 3) { + $fixed_line =~ s/^\+//; + print $f $fixed_line. "\n"; + } + } else { + print $f $fixed_line . "\n"; + } + } + close($f); + + if (!$quiet) { + print << "EOM"; +Wrote EXPERIMENTAL --fix correction(s) to '$newfile' + +Do _NOT_ trust the results written to this file. +Do _NOT_ submit these changes without inspecting them for correctness. + +This EXPERIMENTAL file is simply a convenience to help rewrite patches. +No warranties, expressed or implied... + +EOM + } } if ($clean == 1 && $quiet == 0) { @@ -3701,7 +4565,7 @@ sub process { $vname has style problems, please review. If any of these errors are false positives, please report -them to the maintainer, see boards.cfg. +them to the maintainer, see CHECKPATCH in MAINTAINERS. EOM } diff --git a/tools/kernel-doc/docproc.c b/scripts/docproc.c similarity index 90% rename from tools/kernel-doc/docproc.c rename to scripts/docproc.c index a9b49c59a0..2b69eaf5b6 100644 --- a/tools/kernel-doc/docproc.c +++ b/scripts/docproc.c @@ -65,13 +65,14 @@ FILELINE * docsection; #define MAXLINESZ 2048 #define MAXFILES 250 -#define KERNELDOCPATH "tools/kernel-doc/" +#define KERNELDOCPATH "scripts/" #define KERNELDOC "kernel-doc" #define DOCBOOK "-docbook" #define LIST "-list" #define FUNCTION "-function" #define NOFUNCTION "-nofunction" #define NODOCSECTIONS "-no-doc-sections" +#define SHOWNOTFOUND "-show-not-found" static char *srctree, *kernsrctree; @@ -153,7 +154,7 @@ int symfilecnt = 0; static void add_new_symbol(struct symfile *sym, char * symname) { sym->symbollist = - realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *)); + realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *)); sym->symbollist[sym->symbolcnt++].name = strdup(symname); } @@ -214,7 +215,7 @@ static void find_export_symbols(char * filename) char *p; char *e; if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) || - ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) { + ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) { /* Skip EXPORT_SYMBOL{_GPL} */ while (isalnum(*p) || *p == '_') p++; @@ -290,27 +291,28 @@ static void extfunc(char * filename) { docfunctions(filename, FUNCTION); } static void singfunc(char * filename, char * line) { char *vec[200]; /* Enough for specific functions */ - int i, idx = 0; - int startofsym = 1; + int i, idx = 0; + int startofsym = 1; vec[idx++] = KERNELDOC; vec[idx++] = DOCBOOK; + vec[idx++] = SHOWNOTFOUND; - /* Split line up in individual parameters preceded by FUNCTION */ - for (i=0; line[i]; i++) { - if (isspace(line[i])) { - line[i] = '\0'; - startofsym = 1; - continue; - } - if (startofsym) { - startofsym = 0; - vec[idx++] = FUNCTION; - vec[idx++] = &line[i]; - } - } + /* Split line up in individual parameters preceded by FUNCTION */ + for (i=0; line[i]; i++) { + if (isspace(line[i])) { + line[i] = '\0'; + startofsym = 1; + continue; + } + if (startofsym) { + startofsym = 0; + vec[idx++] = FUNCTION; + vec[idx++] = &line[i]; + } + } for (i = 0; i < idx; i++) { - if (strcmp(vec[i], FUNCTION)) - continue; + if (strcmp(vec[i], FUNCTION)) + continue; consume_symbol(vec[i + 1]); } vec[idx++] = filename; @@ -325,7 +327,8 @@ static void singfunc(char * filename, char * line) */ static void docsect(char *filename, char *line) { - char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */ + /* kerneldoc -docbook -show-not-found -function "section" file NULL */ + char *vec[7]; char *s; for (s = line; *s; s++) @@ -341,10 +344,11 @@ static void docsect(char *filename, char *line) vec[0] = KERNELDOC; vec[1] = DOCBOOK; - vec[2] = FUNCTION; - vec[3] = line; - vec[4] = filename; - vec[5] = NULL; + vec[2] = SHOWNOTFOUND; + vec[3] = FUNCTION; + vec[4] = line; + vec[5] = filename; + vec[6] = NULL; exec_kernel_doc(vec); } @@ -456,14 +460,14 @@ static void parse_file(FILE *infile) break; case 'D': while (*s && !isspace(*s)) s++; - *s = '\0'; - symbolsonly(line+2); - break; + *s = '\0'; + symbolsonly(line+2); + break; case 'F': /* filename */ while (*s && !isspace(*s)) s++; *s++ = '\0'; - /* function names */ + /* function names */ while (isspace(*s)) s++; singlefunctions(line +2, s); @@ -511,11 +515,11 @@ int main(int argc, char *argv[]) } /* Open file, exit on error */ infile = fopen(argv[2], "r"); - if (infile == NULL) { - fprintf(stderr, "docproc: "); - perror(argv[2]); - exit(2); - } + if (infile == NULL) { + fprintf(stderr, "docproc: "); + perror(argv[2]); + exit(2); + } if (strcmp("doc", argv[1]) == 0) { /* Need to do this in two passes. diff --git a/scripts/gcc-stack-usage.sh b/scripts/gcc-stack-usage.sh new file mode 100644 index 0000000000..27ac928969 --- /dev/null +++ b/scripts/gcc-stack-usage.sh @@ -0,0 +1,18 @@ +#!/bin/sh +# Test for gcc '-fstack-usage' support +# Copyright (C) 2013, Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +TMP="$$" + +cat </dev/null 2>&1 \ + && echo "y" +int main(void) +{ + return 0; +} +END + +rm -f $TMP $TMP.su diff --git a/tools/kernel-doc/kernel-doc b/scripts/kernel-doc similarity index 96% rename from tools/kernel-doc/kernel-doc rename to scripts/kernel-doc index cbbf34c27c..c881b8cb3e 100755 --- a/tools/kernel-doc/kernel-doc +++ b/scripts/kernel-doc @@ -137,6 +137,8 @@ use strict; # should document the "Context:" of the function, e.g. whether the functions # can be called form interrupts. Unlike other sections you can end it with an # empty line. +# A non-void function should have a "Return:" section describing the return +# value(s). # Example-sections should contain the string EXAMPLE so that they are marked # appropriately in DocBook. # @@ -245,6 +247,7 @@ my $dohighlight = ""; my $verbose = 0; my $output_mode = "man"; +my $output_preformatted = 0; my $no_doc_sections = 0; my %highlights = %highlights_man; my $blankline = $blankline_man; @@ -254,6 +257,7 @@ my $man_date = ('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December')[(localtime)[4]] . " " . ((localtime)[5]+1900); +my $show_not_found = 0; # Essentially these are globals. # They probably want to be tidied up, made more localised or something. @@ -295,9 +299,10 @@ my $doc_special = "\@\%\$\&"; my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start. my $doc_end = '\*/'; my $doc_com = '\s*\*\s*'; +my $doc_com_body = '\s*\* ?'; my $doc_decl = $doc_com . '(\w+)'; my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)'; -my $doc_content = $doc_com . '(.*)'; +my $doc_content = $doc_com_body . '(.*)'; my $doc_block = $doc_com . 'DOC:\s*(.*)?'; my %constants; @@ -313,6 +318,7 @@ my $section_default = "Description"; # default section my $section_intro = "Introduction"; my $section = $section_default; my $section_context = "Context"; +my $section_return = "Return"; my $undescribed = "-- undescribed --"; @@ -364,6 +370,8 @@ while ($ARGV[0] =~ m/^-(.*)/) { usage(); } elsif ($cmd eq '-no-doc-sections') { $no_doc_sections = 1; + } elsif ($cmd eq '-show-not-found') { + $show_not_found = 1; } } @@ -384,8 +392,8 @@ sub usage { sub get_kernel_version() { my $version = 'unknown kernel version'; - if (defined($ENV{'U_BOOT_VERSION'})) { - $version = $ENV{'U_BOOT_VERSION'}; + if (defined($ENV{'UBOOTVERSION'})) { + $version = $ENV{'UBOOTVERSION'}; } return $version; } @@ -432,7 +440,7 @@ sub dump_doc_section { my $contents = join "\n", @_; if ($no_doc_sections) { - return; + return; } if (($function_only == 0) || @@ -485,8 +493,13 @@ sub output_highlight { $contents =~ s/\s+$//; } foreach $line (split "\n", $contents) { + if (! $output_preformatted) { + $line =~ s/^\s*//; + } if ($line eq ""){ - print $lineprefix, local_unescape($blankline); + if (! $output_preformatted) { + print $lineprefix, local_unescape($blankline); + } } else { $line =~ s/\\\\\\/\&/g; if ($output_mode eq "man" && substr($line, 0, 1) eq ".") { @@ -902,10 +915,12 @@ sub output_section_xml(%) { print "$section\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { print "\n"; } output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; if ($section =~ m/EXAMPLE/i) { print "\n"; } else { @@ -1208,10 +1223,12 @@ sub output_blockhead_xml(%) { } if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { print "\n"; } output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; if ($section =~ m/EXAMPLE/i) { print "\n"; } else { @@ -1287,10 +1304,12 @@ sub output_function_gnome { print "\n $section\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { } print "\n"; output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; print "\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; @@ -1734,7 +1753,7 @@ sub dump_struct($$) { # strip kmemcheck_bitfield_{begin,end}.*; $members =~ s/kmemcheck_bitfield_.*?;//gos; # strip attributes - $members =~ s/__aligned\s*\(\d+\)//gos; + $members =~ s/__aligned\s*\(.+\)//gos; create_parameterlist($members, ';', $file); check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested); @@ -2025,6 +2044,28 @@ sub check_sections($$$$$$) { } } +## +# Checks the section describing the return value of a function. +sub check_return_section { + my $file = shift; + my $declaration_name = shift; + my $return_type = shift; + + # Ignore an empty return type (It's a macro) + # Ignore functions with a "void" return type. (But don't ignore "void *") + if (($return_type eq "") || ($return_type =~ /void\s*\w*\s*$/)) { + return; + } + + if (!defined($sections{$section_return}) || + $sections{$section_return} eq "") { + print STDERR "Warning(${file}:$.): " . + "No description found for return value of " . + "'$declaration_name'\n"; + ++$warnings; + } +} + ## # takes a function prototype and the name of the current file being # processed and spits out all the details stored in the global @@ -2041,7 +2082,6 @@ sub dump_function($$) { $prototype =~ s/^__inline +//; $prototype =~ s/^__always_inline +//; $prototype =~ s/^noinline +//; - $prototype =~ s/__devinit +//; $prototype =~ s/__init +//; $prototype =~ s/__init_or_module +//; $prototype =~ s/__must_check +//; @@ -2088,14 +2128,22 @@ sub dump_function($$) { create_parameterlist($args, ',', $file); } else { - print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n"; - ++$errors; + print STDERR "Warning(${file}:$.): cannot understand function prototype: '$prototype'\n"; return; } my $prms = join " ", @parameterlist; check_sections($file, $declaration_name, "function", $sectcheck, $prms, ""); + # This check emits a lot of warnings at the moment, because many + # functions don't have a 'Return' doc section. So until the number + # of warnings goes sufficiently down, the check is only performed in + # verbose mode. + # TODO: always perform the check. + if ($verbose) { + check_return_section($file, $declaration_name, $return_type); + } + output_declaration($declaration_name, 'function', {'function' => $declaration_name, @@ -2305,6 +2353,9 @@ sub process_file($) { $section_counter = 0; while () { + while (s/\\\s*$//) { + $_ .= ; + } if ($state == 0) { if (/$doc_start/o) { $state = 1; # next line is always the function name @@ -2332,7 +2383,7 @@ sub process_file($) { $descr= $1; $descr =~ s/^\s*//; $descr =~ s/\s*$//; - $descr =~ s/\s+/ /; + $descr =~ s/\s+/ /g; $declaration_purpose = xml_escape($descr); $in_purpose = 1; } else { @@ -2424,9 +2475,7 @@ sub process_file($) { # Continued declaration purpose chomp($declaration_purpose); $declaration_purpose .= " " . xml_escape($1); - } elsif ($section =~ m/^Example/) { - $_ =~ s/^\s*\*//; - $contents .= $_; + $declaration_purpose =~ s/\s+/ /g; } else { $contents .= $1 . "\n"; } @@ -2489,6 +2538,9 @@ sub process_file($) { } if ($initial_section_counter == $section_counter) { print STDERR "Warning(${file}): no structured comments found\n"; + if (($function_only == 1) && ($show_not_found == 1)) { + print STDERR " Was looking for '$_'.\n" for keys %function_table; + } if ($output_mode eq "xml") { # The template wants at least one RefEntry here; make one. print "\n"; diff --git a/scripts/mkmakefile b/scripts/mkmakefile new file mode 100644 index 0000000000..0cc0442607 --- /dev/null +++ b/scripts/mkmakefile @@ -0,0 +1,59 @@ +#!/bin/sh +# Generates a small Makefile used in the root of the output +# directory, to allow make to be started from there. +# The Makefile also allow for more convinient build of external modules + +# Usage +# $1 - Kernel src directory +# $2 - Output directory +# $3 - version +# $4 - patchlevel + + +test ! -r $2/Makefile -o -O $2/Makefile || exit 0 +# Only overwrite automatically generated Makefiles +# (so we do not overwrite kernel Makefile) +if test -e $2/Makefile && ! grep -q Automatically $2/Makefile +then + exit 0 +fi +if [ "${quiet}" != "silent_" ]; then + echo " GEN $2/Makefile" +fi + +cat << EOF > $2/Makefile +# Automatically generated by $0: don't edit + +VERSION = $3 +PATCHLEVEL = $4 + +lastword = \$(word \$(words \$(1)),\$(1)) +makedir := \$(dir \$(call lastword,\$(MAKEFILE_LIST))) + +ifeq ("\$(origin V)", "command line") +VERBOSE := \$(V) +endif +ifneq (\$(VERBOSE),1) +Q := @ +endif + +MAKEARGS := -C $1 +MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$(makedir)) + +MAKEFLAGS += --no-print-directory + +.PHONY: all \$(MAKECMDGOALS) + +all := \$(filter-out all Makefile,\$(MAKECMDGOALS)) + +all: + \$(Q)\$(MAKE) \$(MAKEARGS) \$(all) + +Makefile:; + +\$(all): all + @: + +%/: all + @: +EOF diff --git a/spl/Makefile b/spl/Makefile index c7b626c4bc..430fcafbf2 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -14,9 +14,21 @@ # Based on top-level Makefile. # +src := $(obj) + +# Create output directory if not already present +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) + +include $(srctree)/scripts/Kbuild.include + CONFIG_SPL_BUILD := y export CONFIG_SPL_BUILD +KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD +ifeq ($(CONFIG_TPL_BUILD),y) +KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD +endif + ifeq ($(CONFIG_TPL_BUILD),y) export CONFIG_TPL_BUILD SPL_BIN := u-boot-tpl @@ -24,17 +36,39 @@ else SPL_BIN := u-boot-spl endif -include $(TOPDIR)/config.mk +include include/config.mk -# We want the final binaries in this directory ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(OBJTREE)/tpl/ -SPLTREE := $(TPLTREE) + -include include/tpl-autoconf.mk else -obj := $(OBJTREE)/spl/ + -include include/spl-autoconf.mk endif -HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n) +include $(srctree)/config.mk + +# Enable garbage collection of un-used sections for SPL +KBUILD_CFLAGS += -ffunction-sections -fdata-sections +LDFLAGS_FINAL += --gc-sections + +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ + $(NOSTDINC_FLAGS) +c_flags := $(KBUILD_CFLAGS) $(cpp_flags) + +# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL) +quiet_cmd_autoconf = GEN $@ + cmd_autoconf = \ + $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ + rm $@.tmp + +include/tpl-autoconf.mk: include/config.h + $(call cmd,autoconf) + +include/spl-autoconf.mk: include/config.h + $(call cmd,autoconf) + +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) ifdef CONFIG_SPL_START_S_PATH START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%) @@ -47,110 +81,112 @@ head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o -LIBS-y += arch/$(ARCH)/lib/ +libs-y += arch/$(ARCH)/lib/ -LIBS-y += $(CPUDIR)/ +libs-y += $(CPUDIR)/ ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/ +libs-y += $(CPUDIR)/$(SOC)/ endif -LIBS-y += board/$(BOARDDIR)/ -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ +libs-y += board/$(BOARDDIR)/ +libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ -LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/ -LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ -LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ -LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ -LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ -LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ -LIBS-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ -LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ -LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ -LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ -LIBS-y += fs/ -LIBS-$(CONFIG_SPL_FPGA_SUPPORT) += drivers/fpga/ -LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \ - drivers/power/pmic/ -LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/ -LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ -LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/ -LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ -LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/ -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/ -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/ -LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/ -LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/ -LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ -LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ +libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/ +libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ +libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ +libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ +libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ +libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ +libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ +libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ +libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ +libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ +libs-y += fs/ +libs-$(CONFIG_SPL_FPGA_SUPPORT) += drivers/fpga/ +libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ +libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ +libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/ +libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ +libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ +libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/ +libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ +libs-$(CONFIG_SPL_NET_SUPPORT) += net/ +libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/ +libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/ +libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/ +libs-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/ +libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ +libs-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ +libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/ +libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/ +libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/ ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) -LIBS-y += arch/$(ARCH)/imx-common/ +libs-y += arch/$(ARCH)/imx-common/ endif -LIBS-$(CONFIG_ARM) += arch/arm/cpu/ -LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ +libs-$(CONFIG_ARM) += arch/arm/cpu/ +libs-$(CONFIG_PPC) += arch/powerpc/cpu/ -LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) +head-y := $(addprefix $(obj)/,$(head-y)) +libs-y := $(addprefix $(obj)/,$(libs-y)) +u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) + +libs-y := $(patsubst %/, %/built-in.o, $(libs-y)) # Add GCC lib -ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o -PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a +PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) endif -START := $(addprefix $(SPLTREE)/,$(head-y)) -LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y))) - -__START := $(subst $(obj),,$(START)) -__LIBS := $(subst $(obj),,$(LIBS)) +u-boot-spl-init := $(head-y) +u-boot-spl-main := $(libs-y) # Linker Script ifdef CONFIG_SPL_LDSCRIPT # need to strip off double quotes -LDSCRIPT := $(addprefix $(SRCTREE)/,$(CONFIG_SPL_LDSCRIPT:"%"=%)) +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%)) endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds + LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) $(error could not find linker script) endif -build := -f $(TOPDIR)/scripts/Makefile.build -C - # Special flags for CPP when processing the linker script. # Pass the version down so we can handle backwards compatibility # on the fly. LDPPFLAGS += \ - -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ - -include $(OBJTREE)/include/config.h \ + -include $(srctree)/include/u-boot/u-boot.lds.h \ + -include $(objtree)/include/config.h \ -DCPUDIR=$(CPUDIR) \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -$(OBJTREE)/MLO: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mkimage -T omapimage \ - -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) -$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \ - -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ +MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE) -$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $@ +MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE) -ALL-y += $(obj)$(SPL_BIN).bin +MLO MLO.byteswap: $(obj)/u-boot-spl.bin + $(call if_changed,mkimage) + +ALL-y += $(obj)/$(SPL_BIN).bin ifdef CONFIG_SAMSUNG -ALL-y += $(obj)$(BOARD)-spl.bin +ALL-y += $(obj)/$(BOARD)-spl.bin endif all: $(ALL-y) @@ -161,32 +197,60 @@ VAR_SIZE_PARAM = --vs else VAR_SIZE_PARAM = endif -$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) $< $@ +$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin + $(if $(wildcard $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\ + $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\ + $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ endif -$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) - $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@ +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -GEN_UBOOT = \ - cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map $(SPL_BIN).map -o $(SPL_BIN) +OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJCFLAGS) -O binary -$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds - $(GEN_UBOOT) +$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE + $(call if_changed,objcopy) -$(START): - @: +LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SPL_TEXT_BASE),) +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) +endif -$(LIBS): depend - $(MAKE) $(build) $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) +quiet_cmd_u-boot-spl = LD $@ + cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ + $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \ + $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \ + $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN) -$(obj)u-boot-spl.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ +$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds + $(call cmd,u-boot-spl) -depend: $(obj).depend -.PHONY: depend +$(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ; -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +PHONY += $(u-boot-spl-dirs) +$(u-boot-spl-dirs): + $(Q)$(MAKE) $(build)=$@ + +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< + +$(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE + $(call if_changed_dep,cpp_lds) + +# read all saved command lines + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard $(obj)/.*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + $(cmd_files): ; # Do not try to update included dependency files + include $(cmd_files) +endif + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/test/command_ut.c b/test/command_ut.c index 0e83db0cca..aaa1ee25d0 100644 --- a/test/command_ut.c +++ b/test/command_ut.c @@ -7,6 +7,9 @@ #define DEBUG #include +#ifdef CONFIG_SANDBOX +#include +#endif static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; " "setenv list ${list}3\0" @@ -15,7 +18,7 @@ static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; " static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("%s: Testing commands\n", __func__); - run_command("env default -f", 0); + run_command("env default -f -a", 0); /* run a single command */ run_command("setenv single 1", 0); @@ -58,6 +61,114 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) "setenv list ${list}3", strlen("setenv list 1"), 0); assert(!strcmp("1", getenv("list"))); +#ifdef CONFIG_SYS_HUSH_PARSER + /* Test the 'test' command */ + +#define HUSH_TEST(name, expr, expected_result) \ + run_command("if test " expr " ; then " \ + "setenv " #name "_" #expected_result " y; else " \ + "setenv " #name "_" #expected_result " n; fi", 0); \ + assert(!strcmp(#expected_result, getenv(#name "_" #expected_result))); \ + setenv(#name "_" #expected_result, NULL); + + /* Basic operators */ + HUSH_TEST(streq, "aaa = aaa", y); + HUSH_TEST(streq, "aaa = bbb", n); + + HUSH_TEST(strneq, "aaa != bbb", y); + HUSH_TEST(strneq, "aaa != aaa", n); + + HUSH_TEST(strlt, "aaa < bbb", y); + HUSH_TEST(strlt, "bbb < aaa", n); + + HUSH_TEST(strgt, "bbb > aaa", y); + HUSH_TEST(strgt, "aaa > bbb", n); + + HUSH_TEST(eq, "123 -eq 123", y); + HUSH_TEST(eq, "123 -eq 456", n); + + HUSH_TEST(ne, "123 -ne 456", y); + HUSH_TEST(ne, "123 -ne 123", n); + + HUSH_TEST(lt, "123 -lt 456", y); + HUSH_TEST(lt_eq, "123 -lt 123", n); + HUSH_TEST(lt, "456 -lt 123", n); + + HUSH_TEST(le, "123 -le 456", y); + HUSH_TEST(le_eq, "123 -le 123", y); + HUSH_TEST(le, "456 -le 123", n); + + HUSH_TEST(gt, "456 -gt 123", y); + HUSH_TEST(gt_eq, "123 -gt 123", n); + HUSH_TEST(gt, "123 -gt 456", n); + + HUSH_TEST(ge, "456 -ge 123", y); + HUSH_TEST(ge_eq, "123 -ge 123", y); + HUSH_TEST(ge, "123 -ge 456", n); + + HUSH_TEST(z, "-z \"\"", y); + HUSH_TEST(z, "-z \"aaa\"", n); + + HUSH_TEST(n, "-n \"aaa\"", y); + HUSH_TEST(n, "-n \"\"", n); + + /* Inversion of simple tests */ + HUSH_TEST(streq_inv, "! aaa = aaa", n); + HUSH_TEST(streq_inv, "! aaa = bbb", y); + + HUSH_TEST(streq_inv_inv, "! ! aaa = aaa", y); + HUSH_TEST(streq_inv_inv, "! ! aaa = bbb", n); + + /* Binary operators */ + HUSH_TEST(or_0_0, "aaa != aaa -o bbb != bbb", n); + HUSH_TEST(or_0_1, "aaa != aaa -o bbb = bbb", y); + HUSH_TEST(or_1_0, "aaa = aaa -o bbb != bbb", y); + HUSH_TEST(or_1_1, "aaa = aaa -o bbb = bbb", y); + + HUSH_TEST(and_0_0, "aaa != aaa -a bbb != bbb", n); + HUSH_TEST(and_0_1, "aaa != aaa -a bbb = bbb", n); + HUSH_TEST(and_1_0, "aaa = aaa -a bbb != bbb", n); + HUSH_TEST(and_1_1, "aaa = aaa -a bbb = bbb", y); + + /* Inversion within binary operators */ + HUSH_TEST(or_0_0_inv, "! aaa != aaa -o ! bbb != bbb", y); + HUSH_TEST(or_0_1_inv, "! aaa != aaa -o ! bbb = bbb", y); + HUSH_TEST(or_1_0_inv, "! aaa = aaa -o ! bbb != bbb", y); + HUSH_TEST(or_1_1_inv, "! aaa = aaa -o ! bbb = bbb", n); + + HUSH_TEST(or_0_0_inv_inv, "! ! aaa != aaa -o ! ! bbb != bbb", n); + HUSH_TEST(or_0_1_inv_inv, "! ! aaa != aaa -o ! ! bbb = bbb", y); + HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y); + HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y); + + setenv("ut_var_nonexistent", NULL); + setenv("ut_var_exists", "1"); + HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_nonexistent\"", y); + HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_exists\"", n); + setenv("ut_var_exists", NULL); + + run_command("setenv ut_var_space \" \"", 0); + assert(!strcmp(getenv("ut_var_space"), " ")); + run_command("setenv ut_var_test $ut_var_space", 0); + assert(!getenv("ut_var_test")); + run_command("setenv ut_var_test \"$ut_var_space\"", 0); + assert(!strcmp(getenv("ut_var_test"), " ")); + run_command("setenv ut_var_test \" 1${ut_var_space}${ut_var_space} 2 \"", 0); + assert(!strcmp(getenv("ut_var_test"), " 1 2 ")); + setenv("ut_var_space", NULL); + setenv("ut_var_test", NULL); + +#ifdef CONFIG_SANDBOX + /* File existence */ + HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n); + run_command("sb save host - creating_this_file_breaks_uboot_unit_test 0 1", 0); + HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", y); + /* Perhaps this could be replaced by an "rm" shell command one day */ + assert(!os_unlink("creating_this_file_breaks_uboot_unit_test")); + HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n); +#endif +#endif + printf("%s: Everything went swimmingly\n", __func__); return 0; } diff --git a/test/dm/.gitignore b/test/dm/.gitignore new file mode 100644 index 0000000000..b741b8ab00 --- /dev/null +++ b/test/dm/.gitignore @@ -0,0 +1 @@ +/test.dtb diff --git a/test/dm/Makefile b/test/dm/Makefile new file mode 100644 index 0000000000..4e9afe6c9c --- /dev/null +++ b/test/dm/Makefile @@ -0,0 +1,18 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CMD_DM) += cmd_dm.o +obj-$(CONFIG_DM_TEST) += test-driver.o +obj-$(CONFIG_DM_TEST) += test-fdt.o +obj-$(CONFIG_DM_TEST) += test-main.o +obj-$(CONFIG_DM_TEST) += test-uclass.o +obj-$(CONFIG_DM_TEST) += ut.o + +# Tests for particular subsystems - when enabling driver model for a new +# subsystem you must add sandbox tests here. +obj-$(CONFIG_DM_TEST) += core.o +obj-$(CONFIG_DM_TEST) += ut.o +obj-$(CONFIG_DM_GPIO) += gpio.o diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c new file mode 100644 index 0000000000..a03fe20f0d --- /dev/null +++ b/test/dm/cmd_dm.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int display_succ(struct device *in, char *buf) +{ + int len; + int ip = 0; + char local[16]; + struct device *pos, *n, *prev = NULL; + + printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in)); + if (in->flags & DM_FLAG_ACTIVATED) + puts(" - activated"); + puts("\n"); + + if (list_empty(&in->child_head)) + return 0; + + len = strlen(buf); + strncpy(local, buf, sizeof(local)); + snprintf(local + len, 2, "|"); + if (len && local[len - 1] == '`') + local[len - 1] = ' '; + + list_for_each_entry_safe(pos, n, &in->child_head, sibling_node) { + if (ip++) + display_succ(prev, local); + prev = pos; + } + + snprintf(local + len, 2, "`"); + display_succ(prev, local); + + return 0; +} + +static int dm_dump(struct device *dev) +{ + if (!dev) + return -EINVAL; + return display_succ(dev, ""); +} + +static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct device *root; + + root = dm_root(); + printf("ROOT %08x\n", map_to_sysmem(root)); + return dm_dump(root); +} + +static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct uclass *uc; + int ret; + int id; + + for (id = 0; id < UCLASS_COUNT; id++) { + struct device *dev; + + ret = uclass_get(id, &uc); + if (ret) + continue; + + printf("uclass %d: %s\n", id, uc->uc_drv->name); + for (ret = uclass_first_device(id, &dev); + dev; + ret = uclass_next_device(&dev)) { + printf(" %s @ %08x:\n", dev->name, + map_to_sysmem(dev)); + } + puts("\n"); + } + + return 0; +} + +static int do_dm_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return dm_test_main(); +} + +static cmd_tbl_t test_commands[] = { + U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""), + U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""), + U_BOOT_CMD_MKENT(test, 1, 1, do_dm_test, "", ""), +}; + +static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *test_cmd; + int ret; + + if (argc != 2) + return CMD_RET_USAGE; + test_cmd = find_cmd_tbl(argv[1], test_commands, + ARRAY_SIZE(test_commands)); + argc -= 2; + argv += 2; + if (!test_cmd || argc > test_cmd->maxargs) + return CMD_RET_USAGE; + + ret = test_cmd->cmd(test_cmd, flag, argc, argv); + + return cmd_process_error(test_cmd, ret); +} + +U_BOOT_CMD( + dm, 2, 1, do_dm, + "Driver model low level access", + "tree Dump driver model tree\n" + "dm uclass Dump list of instances for each uclass\n" + "dm test Run tests" +); diff --git a/test/dm/core.c b/test/dm/core.c new file mode 100644 index 0000000000..14a57c3106 --- /dev/null +++ b/test/dm/core.c @@ -0,0 +1,544 @@ +/* + * Tests for the core driver model code + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + TEST_INTVAL1 = 0, + TEST_INTVAL2 = 3, + TEST_INTVAL3 = 6, + TEST_INTVAL_MANUAL = 101112, +}; + +static const struct dm_test_pdata test_pdata[] = { + { .ping_add = TEST_INTVAL1, }, + { .ping_add = TEST_INTVAL2, }, + { .ping_add = TEST_INTVAL3, }, +}; + +static const struct dm_test_pdata test_pdata_manual = { + .ping_add = TEST_INTVAL_MANUAL, +}; + +U_BOOT_DEVICE(dm_test_info1) = { + .name = "test_drv", + .platdata = &test_pdata[0], +}; + +U_BOOT_DEVICE(dm_test_info2) = { + .name = "test_drv", + .platdata = &test_pdata[1], +}; + +U_BOOT_DEVICE(dm_test_info3) = { + .name = "test_drv", + .platdata = &test_pdata[2], +}; + +static struct driver_info driver_info_manual = { + .name = "test_manual_drv", + .platdata = &test_pdata_manual, +}; + +/* Test that binding with platdata occurs correctly */ +static int dm_test_autobind(struct dm_test_state *dms) +{ + struct device *dev; + + /* + * We should have a single class (UCLASS_ROOT) and a single root + * device with no children. + */ + ut_assert(dms->root); + ut_asserteq(1, list_count_items(&gd->uclass_root)); + ut_asserteq(0, list_count_items(&gd->dm_root->child_head)); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]); + + ut_assertok(dm_scan_platdata()); + + /* We should have our test class now at least, plus more children */ + ut_assert(1 < list_count_items(&gd->uclass_root)); + ut_assert(0 < list_count_items(&gd->dm_root->child_head)); + + /* Our 3 dm_test_infox children should be bound to the test uclass */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]); + + /* No devices should be probed */ + list_for_each_entry(dev, &gd->dm_root->child_head, sibling_node) + ut_assert(!(dev->flags & DM_FLAG_ACTIVATED)); + + /* Our test driver should have been bound 3 times */ + ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] == 3); + + return 0; +} +DM_TEST(dm_test_autobind, 0); + +/* Test that autoprobe finds all the expected devices */ +static int dm_test_autoprobe(struct dm_test_state *dms) +{ + int expected_base_add; + struct device *dev; + struct uclass *uc; + int i; + + ut_assertok(uclass_get(UCLASS_TEST, &uc)); + ut_assert(uc); + + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]); + + /* The root device should not be activated until needed */ + ut_assert(!(dms->root->flags & DM_FLAG_ACTIVATED)); + + /* + * We should be able to find the three test devices, and they should + * all be activated as they are used (lazy activation, required by + * U-Boot) + */ + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED), + "Driver %d/%s already activated", i, dev->name); + + /* This should activate it */ + ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assert(dev->flags & DM_FLAG_ACTIVATED); + + /* Activating a device should activate the root device */ + if (!i) + ut_assert(dms->root->flags & DM_FLAG_ACTIVATED); + } + + /* Our 3 dm_test_infox children should be passed to post_probe */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]); + + /* Also we can check the per-device data */ + expected_base_add = 0; + for (i = 0; i < 3; i++) { + struct dm_test_uclass_perdev_priv *priv; + struct dm_test_pdata *pdata; + + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + + priv = dev->uclass_priv; + ut_assert(priv); + ut_asserteq(expected_base_add, priv->base_add); + + pdata = dev->platdata; + expected_base_add += pdata->ping_add; + } + + return 0; +} +DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA); + +/* Check that we see the correct platdata in each device */ +static int dm_test_platdata(struct dm_test_state *dms) +{ + const struct dm_test_pdata *pdata; + struct device *dev; + int i; + + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + pdata = dev->platdata; + ut_assert(pdata->ping_add == test_pdata[i].ping_add); + } + + return 0; +} +DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA); + +/* Test that we can bind, probe, remove, unbind a driver */ +static int dm_test_lifecycle(struct dm_test_state *dms) +{ + int op_count[DM_TEST_OP_COUNT]; + struct device *dev, *test_dev; + int pingret; + int ret; + + memcpy(op_count, dm_testdrv_op_count, sizeof(op_count)); + + ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, + &dev)); + ut_assert(dev); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] + == op_count[DM_TEST_OP_BIND] + 1); + ut_assert(!dev->priv); + + /* Probe the device - it should fail allocating private data */ + dms->force_fail_alloc = 1; + ret = device_probe(dev); + ut_assert(ret == -ENOMEM); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE] + == op_count[DM_TEST_OP_PROBE] + 1); + ut_assert(!dev->priv); + + /* Try again without the alloc failure */ + dms->force_fail_alloc = 0; + ut_assertok(device_probe(dev)); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE] + == op_count[DM_TEST_OP_PROBE] + 2); + ut_assert(dev->priv); + + /* This should be device 3 in the uclass */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev == test_dev); + + /* Try ping */ + ut_assertok(test_ping(dev, 100, &pingret)); + ut_assert(pingret == 102); + + /* Now remove device 3 */ + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]); + ut_assertok(device_remove(dev)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]); + + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]); + ut_assertok(device_unbind(dev)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]); + + return 0; +} +DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); + +/* Test that we can bind/unbind and the lists update correctly */ +static int dm_test_ordering(struct dm_test_state *dms) +{ + struct device *dev, *dev_penultimate, *dev_last, *test_dev; + int pingret; + + ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, + &dev)); + ut_assert(dev); + + /* Bind two new devices (numbers 4 and 5) */ + ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, + &dev_penultimate)); + ut_assert(dev_penultimate); + ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, + &dev_last)); + ut_assert(dev_last); + + /* Now remove device 3 */ + ut_assertok(device_remove(dev)); + ut_assertok(device_unbind(dev)); + + /* The device numbering should have shifted down one */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev_penultimate == test_dev); + ut_assertok(uclass_find_device(UCLASS_TEST, 4, &test_dev)); + ut_assert(dev_last == test_dev); + + /* Add back the original device 3, now in position 5 */ + ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, &dev)); + ut_assert(dev); + + /* Try ping */ + ut_assertok(test_ping(dev, 100, &pingret)); + ut_assert(pingret == 102); + + /* Remove 3 and 4 */ + ut_assertok(device_remove(dev_penultimate)); + ut_assertok(device_unbind(dev_penultimate)); + ut_assertok(device_remove(dev_last)); + ut_assertok(device_unbind(dev_last)); + + /* Our device should now be in position 3 */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev == test_dev); + + /* Now remove device 3 */ + ut_assertok(device_remove(dev)); + ut_assertok(device_unbind(dev)); + + return 0; +} +DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA); + +/* Check that we can perform operations on a device (do a ping) */ +int dm_check_operations(struct dm_test_state *dms, struct device *dev, + uint32_t base, struct dm_test_priv *priv) +{ + int expected; + int pingret; + + /* Getting the child device should allocate platdata / priv */ + ut_assertok(testfdt_ping(dev, 10, &pingret)); + ut_assert(dev->priv); + ut_assert(dev->platdata); + + expected = 10 + base; + ut_asserteq(expected, pingret); + + /* Do another ping */ + ut_assertok(testfdt_ping(dev, 20, &pingret)); + expected = 20 + base; + ut_asserteq(expected, pingret); + + /* Now check the ping_total */ + priv = dev->priv; + ut_asserteq(DM_TEST_START_TOTAL + 10 + 20 + base * 2, + priv->ping_total); + + return 0; +} + +/* Check that we can perform operations on devices */ +static int dm_test_operations(struct dm_test_state *dms) +{ + struct device *dev; + int i; + + /* + * Now check that the ping adds are what we expect. This is using the + * ping-add property in each node. + */ + for (i = 0; i < ARRAY_SIZE(test_pdata); i++) { + uint32_t base; + + ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev)); + + /* + * Get the 'reg' property, which tells us what the ping add + * should be. We don't use the platdata because we want + * to test the code that sets that up (testfdt_drv_probe()). + */ + base = test_pdata[i].ping_add; + debug("dev=%d, base=%d\n", i, base); + + ut_assert(!dm_check_operations(dms, dev, base, dev->priv)); + } + + return 0; +} +DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA); + +/* Remove all drivers and check that things work */ +static int dm_test_remove(struct dm_test_state *dms) +{ + struct device *dev; + int i; + + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assertf(dev->flags & DM_FLAG_ACTIVATED, + "Driver %d/%s not activated", i, dev->name); + ut_assertok(device_remove(dev)); + ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED), + "Driver %d/%s should have deactivated", i, + dev->name); + ut_assert(!dev->priv); + } + + return 0; +} +DM_TEST(dm_test_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); + +/* Remove and recreate everything, check for memory leaks */ +static int dm_test_leak(struct dm_test_state *dms) +{ + int i; + + for (i = 0; i < 2; i++) { + struct mallinfo start, end; + struct device *dev; + int ret; + int id; + + start = mallinfo(); + if (!start.uordblks) + puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n"); + + ut_assertok(dm_scan_platdata()); + ut_assertok(dm_scan_fdt(gd->fdt_blob)); + + /* Scanning the uclass is enough to probe all the devices */ + for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) { + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + ut_assertok(ret); + } + + /* Don't delete the root class, since we started with that */ + for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) { + struct uclass *uc; + + uc = uclass_find(id); + if (!uc) + continue; + ut_assertok(uclass_destroy(uc)); + } + + end = mallinfo(); + ut_asserteq(start.uordblks, end.uordblks); + } + + return 0; +} +DM_TEST(dm_test_leak, 0); + +/* Test uclass init/destroy methods */ +static int dm_test_uclass(struct dm_test_state *dms) +{ + struct uclass *uc; + + ut_assertok(uclass_get(UCLASS_TEST, &uc)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); + ut_assert(uc->priv); + + ut_assertok(uclass_destroy(uc)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); + + return 0; +} +DM_TEST(dm_test_uclass, 0); + +/** + * create_children() - Create children of a parent node + * + * @dms: Test system state + * @parent: Parent device + * @count: Number of children to create + * @key: Key value to put in first child. Subsequence children + * receive an incrementing value + * @child: If not NULL, then the child device pointers are written into + * this array. + * @return 0 if OK, -ve on error + */ +static int create_children(struct dm_test_state *dms, struct device *parent, + int count, int key, struct device *child[]) +{ + struct device *dev; + int i; + + for (i = 0; i < count; i++) { + struct dm_test_pdata *pdata; + + ut_assertok(device_bind_by_name(parent, &driver_info_manual, + &dev)); + pdata = calloc(1, sizeof(*pdata)); + pdata->ping_add = key + i; + dev->platdata = pdata; + if (child) + child[i] = dev; + } + + return 0; +} + +#define NODE_COUNT 10 + +static int dm_test_children(struct dm_test_state *dms) +{ + struct device *top[NODE_COUNT]; + struct device *child[NODE_COUNT]; + struct device *grandchild[NODE_COUNT]; + struct device *dev; + int total; + int ret; + int i; + + /* We don't care about the numbering for this test */ + dms->skip_post_probe = 1; + + ut_assert(NODE_COUNT > 5); + + /* First create 10 top-level children */ + ut_assertok(create_children(dms, dms->root, NODE_COUNT, 0, top)); + + /* Now a few have their own children */ + ut_assertok(create_children(dms, top[2], NODE_COUNT, 2, NULL)); + ut_assertok(create_children(dms, top[5], NODE_COUNT, 5, child)); + + /* And grandchildren */ + for (i = 0; i < NODE_COUNT; i++) + ut_assertok(create_children(dms, child[i], NODE_COUNT, 50 * i, + i == 2 ? grandchild : NULL)); + + /* Check total number of devices */ + total = NODE_COUNT * (3 + NODE_COUNT); + ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_BIND]); + + /* Try probing one of the grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, + NODE_COUNT * 3 + 2 * NODE_COUNT, &dev)); + ut_asserteq_ptr(grandchild[0], dev); + + /* + * This should have probed the child and top node also, for a total + * of 3 nodes. + */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Probe the other grandchildren */ + for (i = 1; i < NODE_COUNT; i++) + ut_assertok(device_probe(grandchild[i])); + + ut_asserteq(2 + NODE_COUNT, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Probe everything */ + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + ut_assertok(ret); + + ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Remove a top-level child and check that the children are removed */ + ut_assertok(device_remove(top[2])); + ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_REMOVE]); + dm_testdrv_op_count[DM_TEST_OP_REMOVE] = 0; + + /* Try one with grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev)); + ut_asserteq_ptr(dev, top[5]); + ut_assertok(device_remove(dev)); + ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT), + dm_testdrv_op_count[DM_TEST_OP_REMOVE]); + + /* Try the same with unbind */ + ut_assertok(device_unbind(top[2])); + ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + dm_testdrv_op_count[DM_TEST_OP_UNBIND] = 0; + + /* Try one with grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev)); + ut_asserteq_ptr(dev, top[6]); + ut_assertok(device_unbind(top[5])); + ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT), + dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + + return 0; +} +DM_TEST(dm_test_children, 0); diff --git a/test/dm/gpio.c b/test/dm/gpio.c new file mode 100644 index 0000000000..bf632bca54 --- /dev/null +++ b/test/dm/gpio.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that sandbox GPIOs work correctly */ +static int dm_test_gpio(struct dm_test_state *dms) +{ + unsigned int offset, gpio; + struct dm_gpio_ops *ops; + struct device *dev; + const char *name; + int offset_count; + char buf[80]; + + /* + * We expect to get 3 banks. One is anonymous (just numbered) and + * comes from platdata. The other two are named a (20 gpios) + * and b (10 gpios) and come from the device tree. See + * test/dm/test.dts. + */ + ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "extra-gpios"); + ut_asserteq(4, offset); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 20 + 4, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_str("b", name); + ut_asserteq(10, offset_count); + + /* Get the operations for this device */ + ops = gpio_get_ops(dev); + ut_assert(ops->get_state); + + /* Cannot get a value until it is reserved */ + ut_asserteq(-1, ops->get_value(dev, offset)); + + /* + * Now some tests that use the 'sandbox' back door. All GPIOs + * should default to input, include b4 that we are using here. + */ + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: in: 0 [ ]", buf); + + /* Change it to an output */ + sandbox_gpio_set_direction(dev, offset, 1); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: out: 0 [ ]", buf); + + sandbox_gpio_set_value(dev, offset, 1); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: out: 1 [ ]", buf); + + ut_assertok(ops->request(dev, offset, "testing")); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: out: 1 [x] testing", buf); + + /* Change the value a bit */ + ut_asserteq(1, ops->get_value(dev, offset)); + ut_assertok(ops->set_value(dev, offset, 0)); + ut_asserteq(0, ops->get_value(dev, offset)); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: out: 0 [x] testing", buf); + ut_assertok(ops->set_value(dev, offset, 1)); + ut_asserteq(1, ops->get_value(dev, offset)); + + /* Make it an input */ + ut_assertok(ops->direction_input(dev, offset)); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: in: 1 [x] testing", buf); + sandbox_gpio_set_value(dev, offset, 0); + ut_asserteq(0, sandbox_gpio_get_value(dev, offset)); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: in: 0 [x] testing", buf); + + ut_assertok(ops->free(dev, offset)); + ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: in: 0 [ ]", buf); + + /* Check the 'a' bank also */ + ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "base-gpios"); + ut_asserteq(15, offset); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 15, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_str("a", name); + ut_asserteq(20, offset_count); + + /* And the anonymous bank */ + ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "gpio_sandbox"); + ut_asserteq(14, offset); + ut_asserteq(14, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_ptr(NULL, name); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT, offset_count); + + return 0; +} +DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh new file mode 100755 index 0000000000..ef5aca5ac3 --- /dev/null +++ b/test/dm/test-dm.sh @@ -0,0 +1,7 @@ +#!/bin/sh + +NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) +dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb +make O=sandbox sandbox_config +make O=sandbox -s -j${NUM_CPUS} +./sandbox/u-boot -d test/dm/test.dtb -c "dm test" diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c new file mode 100644 index 0000000000..c4be8a12d7 --- /dev/null +++ b/test/dm/test-driver.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +int dm_testdrv_op_count[DM_TEST_OP_COUNT]; +static struct dm_test_state *dms = &global_test_state; + +static int testdrv_ping(struct device *dev, int pingval, int *pingret) +{ + const struct dm_test_pdata *pdata = dev_get_platdata(dev); + struct dm_test_priv *priv = dev_get_priv(dev); + + *pingret = pingval + pdata->ping_add; + priv->ping_total += *pingret; + + return 0; +} + +static const struct test_ops test_ops = { + .ping = testdrv_ping, +}; + +static int test_bind(struct device *dev) +{ + /* Private data should not be allocated */ + ut_assert(!dev_get_priv(dev)); + + dm_testdrv_op_count[DM_TEST_OP_BIND]++; + return 0; +} + +static int test_probe(struct device *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + /* Private data should be allocated */ + ut_assert(priv); + + dm_testdrv_op_count[DM_TEST_OP_PROBE]++; + priv->ping_total += DM_TEST_START_TOTAL; + return 0; +} + +static int test_remove(struct device *dev) +{ + /* Private data should still be allocated */ + ut_assert(dev_get_priv(dev)); + + dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; + return 0; +} + +static int test_unbind(struct device *dev) +{ + /* Private data should not be allocated */ + ut_assert(!dev->priv); + + dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; + return 0; +} + +U_BOOT_DRIVER(test_drv) = { + .name = "test_drv", + .id = UCLASS_TEST, + .ops = &test_ops, + .bind = test_bind, + .probe = test_probe, + .remove = test_remove, + .unbind = test_unbind, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), +}; + +U_BOOT_DRIVER(test2_drv) = { + .name = "test2_drv", + .id = UCLASS_TEST, + .ops = &test_ops, + .bind = test_bind, + .probe = test_probe, + .remove = test_remove, + .unbind = test_unbind, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), +}; + +static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret) +{ + *pingret = pingval + 2; + + return 0; +} + +static const struct test_ops test_manual_ops = { + .ping = test_manual_drv_ping, +}; + +static int test_manual_bind(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_BIND]++; + + return 0; +} + +static int test_manual_probe(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PROBE]++; + if (!dms->force_fail_alloc) + dev->priv = calloc(1, sizeof(struct dm_test_priv)); + if (!dev->priv) + return -ENOMEM; + + return 0; +} + +static int test_manual_remove(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; + return 0; +} + +static int test_manual_unbind(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; + return 0; +} + +U_BOOT_DRIVER(test_manual_drv) = { + .name = "test_manual_drv", + .id = UCLASS_TEST, + .ops = &test_manual_ops, + .bind = test_manual_bind, + .probe = test_manual_probe, + .remove = test_manual_remove, + .unbind = test_manual_unbind, +}; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c new file mode 100644 index 0000000000..e1d982fd7d --- /dev/null +++ b/test/dm/test-fdt.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret) +{ + const struct dm_test_pdata *pdata = dev->platdata; + struct dm_test_priv *priv = dev_get_priv(dev); + + *pingret = pingval + pdata->ping_add; + priv->ping_total += *pingret; + + return 0; +} + +static const struct test_ops test_ops = { + .ping = testfdt_drv_ping, +}; + +static int testfdt_ofdata_to_platdata(struct device *dev) +{ + struct dm_test_pdata *pdata = dev_get_platdata(dev); + + pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "ping-add", -1); + pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + + return 0; +} + +static int testfdt_drv_probe(struct device *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + priv->ping_total += DM_TEST_START_TOTAL; + + return 0; +} + +static const struct device_id testfdt_ids[] = { + { + .compatible = "denx,u-boot-fdt-test", + .data = DM_TEST_TYPE_FIRST }, + { + .compatible = "google,another-fdt-test", + .data = DM_TEST_TYPE_SECOND }, + { } +}; + +U_BOOT_DRIVER(testfdt_drv) = { + .name = "testfdt_drv", + .of_match = testfdt_ids, + .id = UCLASS_TEST_FDT, + .ofdata_to_platdata = testfdt_ofdata_to_platdata, + .probe = testfdt_drv_probe, + .ops = &test_ops, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), +}; + +/* From here is the testfdt uclass code */ +int testfdt_ping(struct device *dev, int pingval, int *pingret) +{ + const struct test_ops *ops = device_get_ops(dev); + + if (!ops->ping) + return -ENOSYS; + + return ops->ping(dev, pingval, pingret); +} + +UCLASS_DRIVER(testfdt) = { + .name = "testfdt", + .id = UCLASS_TEST_FDT, +}; + +/* Test that FDT-based binding works correctly */ +static int dm_test_fdt(struct dm_test_state *dms) +{ + const int num_drivers = 3; + struct device *dev; + struct uclass *uc; + int ret; + int i; + + ret = dm_scan_fdt(gd->fdt_blob); + ut_assert(!ret); + + ret = uclass_get(UCLASS_TEST_FDT, &uc); + ut_assert(!ret); + + /* These are num_drivers compatible root-level device tree nodes */ + ut_asserteq(num_drivers, list_count_items(&uc->dev_head)); + + /* Each should have no platdata / priv */ + for (i = 0; i < num_drivers; i++) { + ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev); + ut_assert(!ret); + ut_assert(!dev_get_priv(dev)); + ut_assert(!dev->platdata); + } + + /* + * Now check that the ping adds are what we expect. This is using the + * ping-add property in each node. + */ + for (i = 0; i < num_drivers; i++) { + uint32_t base; + + ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev); + ut_assert(!ret); + + /* + * Get the 'reg' property, which tells us what the ping add + * should be. We don't use the platdata because we want + * to test the code that sets that up (testfdt_drv_probe()). + */ + base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + debug("dev=%d, base=%d: %s\n", i, base, + fdt_get_name(gd->fdt_blob, dev->of_offset, NULL)); + + ut_assert(!dm_check_operations(dms, dev, base, + dev_get_priv(dev))); + } + + return 0; +} +DM_TEST(dm_test_fdt, 0); diff --git a/test/dm/test-main.c b/test/dm/test-main.c new file mode 100644 index 0000000000..828ed46f8e --- /dev/null +++ b/test/dm/test-main.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct dm_test_state global_test_state; + +/* Get ready for testing */ +static int dm_test_init(struct dm_test_state *dms) +{ + memset(dms, '\0', sizeof(*dms)); + gd->dm_root = NULL; + memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); + + ut_assertok(dm_init()); + dms->root = dm_root(); + + return 0; +} + +/* Ensure all the test devices are probed */ +static int do_autoprobe(struct dm_test_state *dms) +{ + struct device *dev; + int ret; + + /* Scanning the uclass is enough to probe all the devices */ + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + + return ret; +} + +static int dm_test_destroy(struct dm_test_state *dms) +{ + int id; + + for (id = 0; id < UCLASS_COUNT; id++) { + struct uclass *uc; + + /* + * If the uclass doesn't exist we don't want to create it. So + * check that here before we call uclass_find_device()/ + */ + uc = uclass_find(id); + if (!uc) + continue; + ut_assertok(uclass_destroy(uc)); + } + + return 0; +} + +int dm_test_main(void) +{ + struct dm_test *tests = ll_entry_start(struct dm_test, dm_test); + const int n_ents = ll_entry_count(struct dm_test, dm_test); + struct dm_test_state *dms = &global_test_state; + struct dm_test *test; + + /* + * If we have no device tree, or it only has a root node, then these + * tests clearly aren't going to work... + */ + if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { + puts("Please run with test device tree:\n" + " dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb\n" + " ./u-boot -d test/dm/test.dtb\n"); + ut_assert(gd->fdt_blob); + } + + printf("Running %d driver model tests\n", n_ents); + + for (test = tests; test < tests + n_ents; test++) { + printf("Test: %s\n", test->name); + ut_assertok(dm_test_init(dms)); + + if (test->flags & DM_TESTF_SCAN_PDATA) + ut_assertok(dm_scan_platdata()); + if (test->flags & DM_TESTF_PROBE_TEST) + ut_assertok(do_autoprobe(dms)); + if (test->flags & DM_TESTF_SCAN_FDT) + ut_assertok(dm_scan_fdt(gd->fdt_blob)); + + if (test->func(dms)) + break; + + ut_assertok(dm_test_destroy(dms)); + } + + printf("Failures: %d\n", dms->fail_count); + + return 0; +} diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c new file mode 100644 index 0000000000..8b564b89d9 --- /dev/null +++ b/test/dm/test-uclass.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct dm_test_state *dms = &global_test_state; + +int test_ping(struct device *dev, int pingval, int *pingret) +{ + const struct test_ops *ops = device_get_ops(dev); + + if (!ops->ping) + return -ENOSYS; + + return ops->ping(dev, pingval, pingret); +} + +static int test_post_bind(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++; + + return 0; +} + +static int test_pre_unbind(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++; + + return 0; +} + +static int test_post_probe(struct device *dev) +{ + struct device *prev = list_entry(dev->uclass_node.prev, struct device, + uclass_node); + struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv; + struct uclass *uc = dev->uclass; + + dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]++; + ut_assert(priv); + ut_assert(device_active(dev)); + priv->base_add = 0; + if (dms->skip_post_probe) + return 0; + if (&prev->uclass_node != &uc->dev_head) { + struct dm_test_uclass_perdev_priv *prev_uc_priv + = prev->uclass_priv; + struct dm_test_pdata *pdata = prev->platdata; + + ut_assert(pdata); + ut_assert(prev_uc_priv); + priv->base_add = prev_uc_priv->base_add + pdata->ping_add; + } + + return 0; +} + +static int test_pre_remove(struct device *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++; + + return 0; +} + +static int test_init(struct uclass *uc) +{ + dm_testdrv_op_count[DM_TEST_OP_INIT]++; + ut_assert(uc->priv); + + return 0; +} + +static int test_destroy(struct uclass *uc) +{ + dm_testdrv_op_count[DM_TEST_OP_DESTROY]++; + + return 0; +} + +UCLASS_DRIVER(test) = { + .name = "test", + .id = UCLASS_TEST, + .post_bind = test_post_bind, + .pre_unbind = test_pre_unbind, + .post_probe = test_post_probe, + .pre_remove = test_pre_remove, + .init = test_init, + .destroy = test_destroy, + .priv_auto_alloc_size = sizeof(struct dm_test_uclass_priv), + .per_device_auto_alloc_size = sizeof(struct dm_test_uclass_perdev_priv), +}; diff --git a/test/dm/test.dts b/test/dm/test.dts new file mode 100644 index 0000000000..ec5364f7c7 --- /dev/null +++ b/test/dm/test.dts @@ -0,0 +1,59 @@ +/dts-v1/; + +/ { + model = "sandbox"; + compatible = "sandbox"; + #address-cells = <1>; + #size-cells = <0>; + + a-test { + reg = <0>; + compatible = "denx,u-boot-fdt-test"; + ping-add = <0>; + }; + + junk { + reg = <1>; + compatible = "not,compatible"; + }; + + no-compatible { + reg = <2>; + }; + + b-test { + reg = <3>; + compatible = "denx,u-boot-fdt-test"; + ping-add = <3>; + }; + + some-bus { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + ping-add = <4>; + c-test { + compatible = "denx,u-boot-fdt-test"; + reg = <5>; + ping-add = <5>; + }; + }; + + d-test { + reg = <6>; + ping-add = <6>; + compatible = "google,another-fdt-test"; + }; + + base-gpios { + compatible = "sandbox,gpio"; + gpio-bank-name = "a"; + num-gpios = <20>; + }; + + extra-gpios { + compatible = "sandbox,gpio"; + gpio-bank-name = "b"; + num-gpios = <10>; + }; +}; diff --git a/test/dm/ut.c b/test/dm/ut.c new file mode 100644 index 0000000000..8b69bc2ab1 --- /dev/null +++ b/test/dm/ut.c @@ -0,0 +1,33 @@ +/* + * Simple unit test library for driver model + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct dm_test_state; + +void ut_fail(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond) +{ + printf("%s:%d, %s(): %s\n", fname, line, func, cond); + dms->fail_count++; +} + +void ut_failf(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond, const char *fmt, ...) +{ + va_list args; + + printf("%s:%d, %s(): %s: ", fname, line, func, cond); + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); + putc('\n'); + dms->fail_count++; +} diff --git a/tools/.gitignore b/tools/.gitignore index cd2f041cc2..2a90dfe83a 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -6,6 +6,7 @@ /dumpimage /mkenvimage /mkimage +/mkexynosspl /mpc86x_clk /mxsboot /ncb @@ -15,8 +16,5 @@ /xway-swap-bytes /*.exe /easylogo/easylogo -/env/crc32.c -/env/fw_printenv /gdb/gdbcont /gdb/gdbsend -/kernel-doc/docproc diff --git a/tools/Makefile b/tools/Makefile index 328cea319e..097cc1df17 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -5,14 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -TOOLSUBDIRS = kernel-doc - -# -# Include this after HOSTOS HOSTARCH check -# so that we can act intelligently. -# -include $(TOPDIR)/config.mk - # # toolchains targeting win32 generate .exe files # @@ -32,6 +24,9 @@ CONFIG_NETCONSOLE = y CONFIG_SHA1_CHECK_UB_IMG = y endif +subdir-$(HOST_TOOLS_ALL) += easylogo +subdir-$(HOST_TOOLS_ALL) += gdb + # Merge all the different vars for envcrc into one ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y @@ -43,86 +38,115 @@ ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) -# Generated executable files -BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) -BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) -BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) -BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) -BIN_FILES-y += dumpimage$(SFX) -BIN_FILES-y += mkenvimage$(SFX) -BIN_FILES-y += mkimage$(SFX) -BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX) -BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX) -BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX) -BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) -BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) -BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) -BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX) -BIN_FILES-y += proftool(SFX) -BIN_FILES-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX) +# TODO: CONFIG_CMD_LICENSE does not work +hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX) -# Source files which exist outside the tools directory -EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o -EXT_OBJ_FILES-y += common/image.o -EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o -EXT_OBJ_FILES-y += common/image-sig.o -EXT_OBJ_FILES-y += lib/crc32.o -EXT_OBJ_FILES-y += lib/md5.o -EXT_OBJ_FILES-y += lib/sha1.o +hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) +hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) +HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic -# Source files located in the tools directory -NOPED_OBJ_FILES-y += aisimage.o -NOPED_OBJ_FILES-y += default_image.o -NOPED_OBJ_FILES-y += dumpimage.o -NOPED_OBJ_FILES-y += fit_image.o -NOPED_OBJ_FILES-y += image-host.o -NOPED_OBJ_FILES-y += imximage.o -NOPED_OBJ_FILES-y += kwbimage.o -NOPED_OBJ_FILES-y += imagetool.o -NOPED_OBJ_FILES-y += mkenvimage.o -NOPED_OBJ_FILES-y += mkimage.o -NOPED_OBJ_FILES-y += mxsimage.o -NOPED_OBJ_FILES-y += omapimage.o -NOPED_OBJ_FILES-y += os_support.o -NOPED_OBJ_FILES-y += pblimage.o -NOPED_OBJ_FILES-y += proftool.o -NOPED_OBJ_FILES-y += ublimage.o -NOPED_OBJ_FILES-y += relocate-rela.o -OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o -OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o -OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o -OBJ_FILES-$(CONFIG_EXYNOS_SPL) += mkexynosspl.o -OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o -OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o -OBJ_FILES-$(CONFIG_MX23) += mxsboot.o -OBJ_FILES-$(CONFIG_MX28) += mxsboot.o -OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o -OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o -OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o -OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o -OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o +hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) +envcrc$(SFX)-objs := crc32.o env_embedded.o envcrc.o sha1.o + +hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) +HOSTCFLAGS_gen_eth_addr$(SFX).o := -pedantic + +hostprogs-$(CONFIG_CMD_LOADS) += img2srec$(SFX) +HOSTCFLAGS_img2srec$(SFX).o := -pedantic + +hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) +HOSTCFLAGS_xway-swap-bytes$(SFX).o := -pedantic + +hostprogs-y += mkenvimage$(SFX) +mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o + +hostprogs-y += dumpimage$(SFX) mkimage$(SFX) + +FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := image-sig.o +# Flattened device tree objects +LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o +RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o + +# common objs for dumpimage and mkimage +dumpimage-mkimage-objs := aisimage.o \ + $(FIT_SIG_OBJS-y) \ + crc32.o \ + default_image.o \ + fit_image.o \ + image-fit.o \ + image-host.o \ + image.o \ + imagetool.o \ + imximage.o \ + kwbimage.o \ + md5.o \ + mxsimage.o \ + omapimage.o \ + os_support.o \ + pblimage.o \ + sha1.o \ + ublimage.o \ + $(LIBFDT_OBJS) \ + $(RSA_OBJS-y) + +dumpimage$(SFX)-objs := $(dumpimage-mkimage-objs) dumpimage.o +mkimage$(SFX)-objs := $(dumpimage-mkimage-objs) mkimage.o + +# TODO(sjg@chromium.org): Is this correct on Mac OS? + +# MXSImage needs LibSSL +ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) +HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto +HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto +# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +# the mxsimage support within tools/mxsimage.c . +HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS +endif + +ifdef CONFIG_FIT_SIGNATURE +HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto +HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto + +# This affects include/image.h, but including the board config file +# is tricky, so manually define this options here. +HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE +endif + +hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX) +hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX) +HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic + +hostprogs-$(CONFIG_MX23) += mxsboot$(SFX) +hostprogs-$(CONFIG_MX28) += mxsboot$(SFX) +HOSTCFLAGS_mxsboot$(SFX).o := -pedantic + +hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX) +hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) + +ubsha1$(SFX)-objs := os_support.o sha1.o ubsha1.o + +HOSTCFLAGS_ubsha1.o := -pedantic + +hostprogs-$(CONFIG_KIRKWOOD) += kwboot$(SFX) +hostprogs-y += proftool$(SFX) +hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX) + +# We build some files with extra pedantic flags to try to minimize things +# that won't build on some weird host compiler -- though there are lots of +# exceptions for files that aren't complaint. +HOSTCFLAGS_crc32.o := -pedantic +HOSTCFLAGS_md5.o := -pedantic +HOSTCFLAGS_sha1.o := -pedantic # Don't build by default -#ifeq ($(ARCH),ppc) -#BIN_FILES-y += mpc86x_clk$(SFX) -#OBJ_FILES-y += mpc86x_clk.o -#endif +#hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX) +#HOSTCFLAGS_mpc86x_clk$(SFX).o := -pedantic -# Flattened device tree objects -LIBFDT_OBJ_FILES-y += fdt.o -LIBFDT_OBJ_FILES-y += fdt_ro.o -LIBFDT_OBJ_FILES-y += fdt_rw.o -LIBFDT_OBJ_FILES-y += fdt_strerror.o -LIBFDT_OBJ_FILES-y += fdt_wip.o - -# RSA objects -RSA_OBJ_FILES-$(CONFIG_FIT_SIGNATURE) += rsa-sign.o +always := $(hostprogs-y) # Generated LCD/video logo -LOGO_H = $(OBJTREE)/include/bmp_logo.h -LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h +LOGO_H = $(objtree)/include/bmp_logo.h +LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H) LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H) @@ -130,197 +154,52 @@ LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H) # Generic logo ifeq ($(LOGO_BMP),) -LOGO_BMP= logos/denx.bmp +LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp # Use board logo and fallback to vendor -ifneq ($(wildcard logos/$(BOARD).bmp),) -LOGO_BMP= logos/$(BOARD).bmp +ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),) +LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp else -ifneq ($(wildcard logos/$(VENDOR).bmp),) -LOGO_BMP= logos/$(VENDOR).bmp +ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),) +LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp endif endif endif # !LOGO_BMP -# now $(obj) is defined -HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/lib/rsa/,$(RSA_OBJ_FILES-y:.o=.c)) -BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) -LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) -RSA_OBJS := $(addprefix $(obj),$(RSA_OBJ_FILES-y)) - -# We cannot check CONFIG_FIT_SIGNATURE here since it is not set on the host -FIT_SIG_OBJ_FILES := image-sig.o -FIT_SIG_OBJS := $(addprefix $(obj),$(FIT_SIG_OBJ_FILES)) - -HOSTOBJS := $(addprefix $(obj),$(OBJ_FILES-y)) -NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y)) - # # Use native tools and options # Define __KERNEL_STRICT_NAMES to prevent typedef overlaps # Define _GNU_SOURCE to obtain the getline prototype from stdio.h # -HOSTCPPFLAGS = -include $(SRCTREE)/include/libfdt_env.h \ - -idirafter $(SRCTREE)/include \ - -idirafter $(SRCTREE)/arch/$(ARCH)/include \ - -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/lib/libfdt \ - -I $(SRCTREE)/tools \ +HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \ + $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \ + -I$(srctree)/lib/libfdt \ + -I$(srctree)/tools \ -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ -DUSE_HOSTCC \ -D__KERNEL_STRICT_NAMES \ -D_GNU_SOURCE +__build: $(LOGO-y) -all: $(obj).depend $(BINS) $(LOGO-y) subdirs +$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@ -$(obj)bin2header$(SFX): $(obj)bin2header.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ +$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@ -$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ +# Let clean descend into subdirs +subdir- += env -$(obj)proftool(SFX): $(obj)proftool.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ +ifneq ($(CROSS_BUILD_TOOLS),) +HOSTCC = $(CC) -$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ +quiet_cmd_crosstools_strip = STRIP $^ + cmd_crosstools_strip = $(STRIP) $^; touch $@ +$(obj)/.strip: $(call objectify,$(filter $(always),$(hostprogs-y))) + $(call cmd,crosstools_strip) -$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)img2srec$(SFX): $(obj)img2srec.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)dumpimage$(SFX): $(obj)aisimage.o \ - $(FIT_SIG_OBJS) \ - $(obj)crc32.o \ - $(obj)default_image.o \ - $(obj)fit_image.o \ - $(obj)image-fit.o \ - $(obj)image.o \ - $(obj)image-host.o \ - $(obj)imagetool.o \ - $(obj)imximage.o \ - $(obj)kwbimage.o \ - $(obj)dumpimage.o \ - $(obj)md5.o \ - $(obj)mxsimage.o \ - $(obj)omapimage.o \ - $(obj)os_support.o \ - $(obj)pblimage.o \ - $(obj)sha1.o \ - $(obj)ublimage.o \ - $(LIBFDT_OBJS) \ - $(RSA_OBJS) - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS) - $(HOSTSTRIP) $@ - -$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \ - $(obj)os_support.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mkimage$(SFX): $(obj)aisimage.o \ - $(FIT_SIG_OBJS) \ - $(obj)crc32.o \ - $(obj)default_image.o \ - $(obj)fit_image.o \ - $(obj)image-fit.o \ - $(obj)image-host.o \ - $(obj)image.o \ - $(obj)imagetool.o \ - $(obj)imximage.o \ - $(obj)kwbimage.o \ - $(obj)md5.o \ - $(obj)mkimage.o \ - $(obj)mxsimage.o \ - $(obj)omapimage.o \ - $(obj)os_support.o \ - $(obj)pblimage.o \ - $(obj)sha1.o \ - $(obj)ublimage.o \ - $(LIBFDT_OBJS) \ - $(RSA_OBJS) - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS) - $(HOSTSTRIP) $@ - -$(obj)mk$(BOARD)spl$(SFX): $(obj)mkexynosspl.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mxsboot$(SFX): $(obj)mxsboot.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)ncb$(SFX): $(obj)ncb.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -$(obj)kwboot$(SFX): $(obj)kwboot.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)relocate-rela$(SFX): $(obj)relocate-rela.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -# Some of the tool objects need to be accessed from outside the tools directory -$(obj)%.o: $(SRCTREE)/common/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/%.c - $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/rsa/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -subdirs: -ifeq ($(TOOLSUBDIRS),) - @: -else - @for dir in $(TOOLSUBDIRS) ; do \ - $(MAKE) \ - HOSTOS=$(HOSTOS) \ - HOSTARCH=$(HOSTARCH) \ - -C $$dir || exit 1 ; \ - done +always += .strip endif - -$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@ - -$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +clean-files += .strip diff --git a/tools/crc32.c b/tools/crc32.c new file mode 100644 index 0000000000..aed7112f6a --- /dev/null +++ b/tools/crc32.c @@ -0,0 +1 @@ +#include "../lib/crc32.c" diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile index d8e28b0e12..10aba2ba66 100644 --- a/tools/easylogo/Makefile +++ b/tools/easylogo/Makefile @@ -1,11 +1,3 @@ -include $(TOPDIR)/config.mk +hostprogs-y := easylogo -all: $(obj)easylogo - -$(obj)easylogo: $(SRCTREE)/tools/easylogo/easylogo.c - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $^ - -clean: - rm -f $(obj)easylogo - -.PHONY: all clean +always := $(hostprogs-y) diff --git a/tools/env/.gitignore b/tools/env/.gitignore new file mode 100644 index 0000000000..804abacc6e --- /dev/null +++ b/tools/env/.gitignore @@ -0,0 +1,2 @@ +fw_printenv +fw_printenv_unstripped diff --git a/tools/env/Makefile b/tools/env/Makefile index 27892f74d0..fcb752ddb4 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -5,39 +5,30 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c -HOSTSRCS += $(SRCTREE)/lib/ctype.c $(SRCTREE)/lib/linux_string.c -HOSTSRCS += $(SRCTREE)/common/env_attr.c $(SRCTREE)/common/env_flags.c -HEADERS := fw_env.h $(OBJTREE)/include/config.h +# fw_printenv is supposed to run on the target system, which means it should be +# built with cross tools. Although it may look weird, we only replace "HOSTCC" +# with "CC" here for the maximum code reuse of scripts/Makefile.host. +HOSTCC = $(CC) # Compile for a hosted environment on the target -HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ - -idirafter $(SRCTREE)/arch/$(ARCH)/include \ - -idirafter $(OBJTREE)/include \ - -idirafter $(SRCTREE)/tools/env \ +HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \ + -idirafter $(srctree)/tools/env \ -DUSE_HOSTCC \ -DTEXT_BASE=$(TEXT_BASE) ifeq ($(MTD_VERSION),old) -HOSTCPPFLAGS += -DMTD_OLD +HOST_EXTRACFLAGS += -DMTD_OLD endif -all: $(obj)fw_printenv +always := fw_printenv +hostprogs-y := fw_printenv_unstripped -# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED -$(obj)fw_printenv: $(HOSTSRCS) $(HEADERS) - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS) - $(HOSTSTRIP) $@ +fw_printenv_unstripped-objs := fw_env.o fw_env_main.o \ + crc32.o ctype.o linux_string.o \ + env_attr.o env_flags.o -clean: - rm -f $(obj)fw_printenv +quiet_cmd_strip = STRIP $@ + cmd_strip = $(STRIP) -o $@ $< -######################################################################### - -include $(TOPDIR)/rules.mk - -sinclude $(obj).depend - -######################################################################### +$(obj)/fw_printenv: $(obj)/fw_printenv_unstripped FORCE + $(call if_changed,strip) diff --git a/tools/env/README b/tools/env/README index 1020b57b05..24e31bc9f8 100644 --- a/tools/env/README +++ b/tools/env/README @@ -2,11 +2,10 @@ This is a demo implementation of a Linux command line tool to access the U-Boot's environment variables. -In the current version, there is an issue in cross-compilation. In order to cross-compile fw_printenv, run - make HOSTCC= env + make CROSS_COMPILE= env in the root directory of the U-Boot distribution. For example, - make HOSTCC=arm-linux-gcc env + make CROSS_COMPILE=arm-linux- env For the run-time utility configuration uncomment the line #define CONFIG_FILE "/etc/fw_env.config" diff --git a/tools/env/crc32.c b/tools/env/crc32.c new file mode 100644 index 0000000000..34f8178e33 --- /dev/null +++ b/tools/env/crc32.c @@ -0,0 +1 @@ +#include "../../lib/crc32.c" diff --git a/tools/env/ctype.c b/tools/env/ctype.c new file mode 100644 index 0000000000..21050e9373 --- /dev/null +++ b/tools/env/ctype.c @@ -0,0 +1 @@ +#include "../../lib/ctype.c" diff --git a/tools/env/env_attr.c b/tools/env/env_attr.c new file mode 100644 index 0000000000..502d4c900b --- /dev/null +++ b/tools/env/env_attr.c @@ -0,0 +1 @@ +#include "../../common/env_attr.c" diff --git a/tools/env/env_flags.c b/tools/env/env_flags.c new file mode 100644 index 0000000000..b261cb8e39 --- /dev/null +++ b/tools/env/env_flags.c @@ -0,0 +1 @@ +#include "../../common/env_flags.c" diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 577ce2de47..d228cc34da 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -863,9 +863,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, if (mtd_type != MTD_ABSENT) ioctl(fd, MEMLOCK, &erase); - processed += blocklen; + processed += erasesize; block_seek = 0; - blockstart += blocklen; + blockstart += erasesize; } if (write_total > count) @@ -1246,9 +1246,10 @@ static int parse_config () strcpy (DEVNAME (0), DEVICE1_NAME); DEVOFFSET (0) = DEVICE1_OFFSET; ENVSIZE (0) = ENV1_SIZE; - /* Default values are: erase-size=env-size, #sectors=1 */ + /* Default values are: erase-size=env-size */ DEVESIZE (0) = ENVSIZE (0); - ENVSECTORS (0) = 1; + /* #sectors=env-size/erase-size (rounded up) */ + ENVSECTORS (0) = (ENVSIZE(0) + DEVESIZE(0) - 1) / DEVESIZE(0); #ifdef DEVICE1_ESIZE DEVESIZE (0) = DEVICE1_ESIZE; #endif @@ -1260,9 +1261,10 @@ static int parse_config () strcpy (DEVNAME (1), DEVICE2_NAME); DEVOFFSET (1) = DEVICE2_OFFSET; ENVSIZE (1) = ENV2_SIZE; - /* Default values are: erase-size=env-size, #sectors=1 */ + /* Default values are: erase-size=env-size */ DEVESIZE (1) = ENVSIZE (1); - ENVSECTORS (1) = 1; + /* #sectors=env-size/erase-size (rounded up) */ + ENVSECTORS (1) = (ENVSIZE(1) + DEVESIZE(1) - 1) / DEVESIZE(1); #ifdef DEVICE2_ESIZE DEVESIZE (1) = DEVICE2_ESIZE; #endif @@ -1320,8 +1322,8 @@ static int get_config (char *fname) DEVESIZE(i) = ENVSIZE(i); if (rc < 5) - /* Default - 1 sector */ - ENVSECTORS (i) = 1; + /* Assume enough env sectors to cover the environment */ + ENVSECTORS (i) = (ENVSIZE(i) + DEVESIZE(i) - 1) / DEVESIZE(i); i++; } diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 90e499da1e..c9b9f6a160 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -1,7 +1,7 @@ # Configuration file for fw_(printenv/setenv) utility. # Up to two entries are valid, in this case the redundant # environment sector is assumed present. -# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash. +# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash. # Futhermore, if the Flash sector size is ommitted, this value is assumed to # be the same as the Environment size, which is valid for NOR and SPI-dataflash diff --git a/tools/env/linux_string.c b/tools/env/linux_string.c new file mode 100644 index 0000000000..6c01addadf --- /dev/null +++ b/tools/env/linux_string.c @@ -0,0 +1 @@ +#include "../../lib/linux_string.c" diff --git a/tools/env_embedded.c b/tools/env_embedded.c new file mode 100644 index 0000000000..59a6357195 --- /dev/null +++ b/tools/env_embedded.c @@ -0,0 +1 @@ +#include "../common/env_embedded.c" diff --git a/tools/fdt.c b/tools/fdt.c new file mode 100644 index 0000000000..1eafc56d76 --- /dev/null +++ b/tools/fdt.c @@ -0,0 +1 @@ +#include "../lib/libfdt/fdt.c" diff --git a/tools/fdt_ro.c b/tools/fdt_ro.c new file mode 100644 index 0000000000..9005fe3ca3 --- /dev/null +++ b/tools/fdt_ro.c @@ -0,0 +1 @@ +#include "../lib/libfdt/fdt_ro.c" diff --git a/tools/fdt_rw.c b/tools/fdt_rw.c new file mode 100644 index 0000000000..adc3fdfbea --- /dev/null +++ b/tools/fdt_rw.c @@ -0,0 +1 @@ +#include "../lib/libfdt/fdt_rw.c" diff --git a/tools/fdt_strerror.c b/tools/fdt_strerror.c new file mode 100644 index 0000000000..d0b58220a4 --- /dev/null +++ b/tools/fdt_strerror.c @@ -0,0 +1 @@ +#include "../lib/libfdt/fdt_strerror.c" diff --git a/tools/fdt_wip.c b/tools/fdt_wip.c new file mode 100644 index 0000000000..7810f07079 --- /dev/null +++ b/tools/fdt_wip.c @@ -0,0 +1 @@ +#include "../lib/libfdt/fdt_wip.c" diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index dd98fb65c0..451332031e 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -8,49 +8,39 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +ifneq ($(HOSTOS),cygwin) -BINS = gdbsend gdbcont +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) -COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o - -HOSTOBJS := $(addprefix $(obj),$(COBJS)) -HOSTSRCS := $(COBJS:.o=.c) -BINS := $(addprefix $(obj),$(BINS)) +ifeq ($(HOSTOS),darwin) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif # # Use native tools and options # -HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include +HOST_EXTRACFLAGS := -I$(BFD_ROOT_DIR)/include -pedantic -ifeq ($(HOSTOS),cygwin) +hostprogs-y := gdbsend gdbcont -all: -$(obj).depend: +gdbsend-objs := gdbsend.o error.o remote.o serial.o +gdbcont-objs := gdbcont.o error.o remote.o serial.o -else # ! CYGWIN - -all: $(obj).depend $(BINS) - -$(obj)gdbsend: $(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -$(obj)gdbcont: $(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -clean: - rm -f $(HOSTOBJS) - -distclean: clean - rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +always := $(hostprogs-y) endif # cygwin diff --git a/tools/image-fit.c b/tools/image-fit.c new file mode 100644 index 0000000000..037e5cc8d7 --- /dev/null +++ b/tools/image-fit.c @@ -0,0 +1 @@ +#include "../common/image-fit.c" diff --git a/tools/image-sig.c b/tools/image-sig.c new file mode 100644 index 0000000000..e45419f321 --- /dev/null +++ b/tools/image-sig.c @@ -0,0 +1 @@ +#include "../common/image-sig.c" diff --git a/tools/image.c b/tools/image.c new file mode 100644 index 0000000000..0f9bacc702 --- /dev/null +++ b/tools/image.c @@ -0,0 +1 @@ +#include "../common/image.c" diff --git a/tools/scripts/README b/tools/kermit/README similarity index 94% rename from tools/scripts/README rename to tools/kermit/README index dbc4425afd..c3b491aa55 100644 --- a/tools/scripts/README +++ b/tools/kermit/README @@ -8,7 +8,7 @@ This directory contains scripts that help to perform certain actions that need to be done frequently when working with U-Boot. -They are meant as EXAMPLE code, so it is very likely that you will +They are meant as EXAMPLE code, so it is very likely that you will have to modify them before use. diff --git a/tools/scripts/dot.kermrc b/tools/kermit/dot.kermrc similarity index 100% rename from tools/scripts/dot.kermrc rename to tools/kermit/dot.kermrc diff --git a/tools/scripts/flash_param b/tools/kermit/flash_param similarity index 100% rename from tools/scripts/flash_param rename to tools/kermit/flash_param diff --git a/tools/scripts/send_cmd b/tools/kermit/send_cmd similarity index 100% rename from tools/scripts/send_cmd rename to tools/kermit/send_cmd diff --git a/tools/scripts/send_image b/tools/kermit/send_image similarity index 100% rename from tools/scripts/send_image rename to tools/kermit/send_image diff --git a/tools/kernel-doc/Makefile b/tools/kernel-doc/Makefile deleted file mode 100644 index eb56e2e753..0000000000 --- a/tools/kernel-doc/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (C) 2012 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -all: $(obj)docproc - -$(obj)docproc: docproc.c - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -clean: - rm -rf docproc - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/md5.c b/tools/md5.c new file mode 100644 index 0000000000..befaa321c7 --- /dev/null +++ b/tools/md5.c @@ -0,0 +1 @@ +#include "../lib/md5.c" diff --git a/tools/patman/README b/tools/patman/README index 59f1776f54..b3aba136b8 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -217,8 +217,10 @@ Series-changes: n to update the log there and then, knowing that the script will do the rest. - Cc: Their Name - This copies a single patch to another email address. +Patch-cc: Their Name + This copies a single patch to another email address. Note that the + Cc: used by git send-email is ignored by patman, but will be + interpreted by git send-email if you use it. Series-process-log: sort, uniq This tells patman to sort and/or uniq the change logs. It is @@ -246,8 +248,9 @@ Where Patches Are Sent Once the patches are created, patman sends them using git send-email. The whole series is sent to the recipients in Series-to: and Series-cc. -You can Cc individual patches to other people with the Cc: tag. Tags in the -subject are also picked up to Cc patches. For example, a commit like this: +You can Cc individual patches to other people with the Patch-cc: tag. Tags +in the subject are also picked up to Cc patches. For example, a commit like +this: >>>> commit 10212537b85ff9b6e09c82045127522c0f0db981 @@ -258,16 +261,16 @@ Date: Mon Nov 7 23:18:44 2011 -0500 This should make sending out e-mails to the right people easier. - Cc: sandbox, mikef, ag - Cc: afleming + Patch-cc: sandbox, mikef, ag + Patch-cc: afleming <<<< will create a patch which is copied to x86, arm, sandbox, mikef, ag and afleming. -If you have a cover letter it will get sent to the union of the CC lists of -all of the other patches. If you want to sent it to additional people you -can add a tag: +If you have a cover letter it will get sent to the union of the Patch-cc +lists of all of the other patches. If you want to sent it to additional +people you can add a tag: Cover-letter-cc: diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 684204c63f..c4017e0e6d 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -36,7 +36,7 @@ re_series_tag = re.compile('^Series-([a-z-]*): *(.*)') re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)') # Commit tags that we want to collect and keep -re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)') +re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc): (.*)') # The start of a new commit in the git log re_commit = re.compile('^commit ([0-9a-f]*)$') @@ -267,7 +267,7 @@ class PatchStream: if (tag_match.group(1) == 'Tested-by' and tag_match.group(2).find(os.getenv('USER') + '@') != -1): self.warn.append("Ignoring %s" % line) - elif tag_match.group(1) == 'Cc': + elif tag_match.group(1) == 'Patch-cc': self.commit.AddCc(tag_match.group(2).split(',')) else: self.tags.append(line); diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index 93b4c3923e..670b9fd73a 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -120,7 +120,7 @@ int main(int argc, char **argv) } if (rela_start > rela_end || rela_start < text_base || - (rela_end - rela_start) % 24) { + (rela_end - rela_start) % sizeof(Elf64_Rela)) { fprintf(stderr, "%s: bad rela bounds\n", argv[0]); return 3; } diff --git a/tools/rsa-sign.c b/tools/rsa-sign.c new file mode 100644 index 0000000000..150bbe151e --- /dev/null +++ b/tools/rsa-sign.c @@ -0,0 +1 @@ +#include "../lib/rsa/rsa-sign.c" diff --git a/tools/scripts/make-asm-offsets b/tools/scripts/make-asm-offsets deleted file mode 100755 index 4c33756d66..0000000000 --- a/tools/scripts/make-asm-offsets +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/sh - -# Adapted from Linux kernel's "Kbuild": -# commit 1cdf25d704f7951d02a04064c97db547d6021872 -# Author: Christoph Lameter - -mkdir -p $(dirname $2) - -# Default sed regexp - multiline due to syntax constraints -SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \ - s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \ - s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:->::; p;}" - -(set -e - echo "#ifndef __ASM_OFFSETS_H__" - echo "#define __ASM_OFFSETS_H__" - echo "/*" - echo " * DO NOT MODIFY." - echo " *" - echo " * This file was generated by $(basename $0)" - echo " *" - echo " */" - echo "" - sed -ne "${SED_CMD}" $1 - echo "" - echo "#endif" ) > $2 diff --git a/tools/sha1.c b/tools/sha1.c new file mode 100644 index 0000000000..0d717dfa44 --- /dev/null +++ b/tools/sha1.c @@ -0,0 +1 @@ +#include "../lib/sha1.c"