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arm/km: ethernet support for mgcoge3un

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The phy is also configured with "RGMII clock transitions when data
stable" and "Class A driver for the direct backplane connection".

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Valentin Longchamp 2011-06-16 18:11:15 +05:30 committed by Albert ARIBAUD
parent 680cfaf805
commit 8f2827fc43
1 changed files with 38 additions and 1 deletions
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39
board/keymile/km_arm/km_arm.c
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@ -335,7 +335,42 @@ void dram_init_banksize(void)
}
}
/* Configure and enable MV88E1118 PHY */
#if defined(CONFIG_MGCOGE3UN)
#define PHY_LED_SEL 0x18
#define PHY_LED0_LINK (0x5)
#define PHY_LED1_ACT (0x8<<4)
#define PHY_LED2_INT (0xe<<8)
#define PHY_SPEC_CTRL 0x1c
#define PHY_RGMII_CLK_STABLE (0x1<<10)
#define PHY_CLSA (0x1<<1)
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
{
char *name = "egiga0";
unsigned short reg;
if (miiphy_set_current_dev(name))
return;
/* RGMII clk transition on data stable */
if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
printf("Error reading PHY spec ctrl reg\n");
if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
printf("Error writing PHY LED reg\n");
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#else
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
{
char *name = "egiga0";
@ -346,6 +381,8 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#endif
#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var(void)