MIPS: add support for Broadcom MIPS BCM6362 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
This commit is contained in:
Álvaro Fernández Rojas
Daniel Schwierzeck
parent
1b075ba016
commit
8f240a3b45
186
arch/mips/dts/brcm,bcm6362.dtsi
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186
arch/mips/dts/brcm,bcm6362.dtsi
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/*
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* Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm6362-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/power-domain/bcm6362-power-domain.h>
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#include <dt-bindings/reset/bcm6362-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm6362";
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aliases {
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spi0 = &lsspi;
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spi1 = &hsspi;
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};
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cpus {
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reg = <0x10000000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu@1 {
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compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <1>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133333333>;
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};
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk: periph-clk {
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compatible = "brcm,bcm6345-clk";
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reg = <0x10000004 0x4>;
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#clock-cells = <1>;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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pll_cntl: syscon@10000008 {
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compatible = "syscon";
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reg = <0x10000008 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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periph_rst: reset-controller@10000010 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x10000010 0x4>;
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#reset-cells = <1>;
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};
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wdt: watchdog@1000005c {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x1000005c 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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gpio1: gpio-controller@10000080 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000080 0x4>, <0x10000088 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpio0: gpio-controller@10000084 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000084 0x4>, <0x1000008c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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uart0: serial@10000100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000100 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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uart1: serial@10000120 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000120 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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lsspi: spi@10000800 {
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compatible = "brcm,bcm6358-spi";
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reg = <0x10000800 0x70c>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&periph_clk BCM6362_CLK_SPI>;
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resets = <&periph_rst BCM6362_RST_SPI>;
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spi-max-frequency = <20000000>;
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num-cs = <8>;
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status = "disabled";
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};
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hsspi: spi@10001000 {
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compatible = "brcm,bcm6328-hsspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10001000 0x600>;
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clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
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clock-names = "hsspi", "pll";
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resets = <&periph_rst BCM6362_RST_SPI>;
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spi-max-frequency = <50000000>;
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num-cs = <8>;
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status = "disabled";
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};
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leds: led-controller@10001900 {
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compatible = "brcm,bcm6328-leds";
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reg = <0x10001900 0x24>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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periph_pwr: power-controller@10001848 {
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compatible = "brcm,bcm6328-power-domain";
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reg = <0x10001848 0x4>;
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#power-domain-cells = <1>;
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};
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memory-controller@10003000 {
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compatible = "brcm,bcm6328-mc";
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reg = <0x10003000 0x864>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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@ -12,6 +12,7 @@ config SYS_SOC
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default "bcm6348" if SOC_BMIPS_BCM6348
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default "bcm6358" if SOC_BMIPS_BCM6358
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default "bcm6368" if SOC_BMIPS_BCM6368
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default "bcm6362" if SOC_BMIPS_BCM6362
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default "bcm63268" if SOC_BMIPS_BCM63268
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choice
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@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368
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help
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This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
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config SOC_BMIPS_BCM6362
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bool "BMIPS BCM6362 family"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select MIPS_TUNE_4KC
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select MIPS_L1_CACHE_SHIFT_4
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select SWAP_IO_SPACE
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select SYSRESET_SYSCON
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help
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This supports BMIPS BCM6362 family including BCM6361 and BCM6362.
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config SOC_BMIPS_BCM63268
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bool "BMIPS BCM63268 family"
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select SUPPORTS_BIG_ENDIAN
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25
include/configs/bmips_bcm6362.h
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25
include/configs/bmips_bcm6362.h
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/*
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* Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_BMIPS_BCM6362_H
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#define __CONFIG_BMIPS_BCM6362_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#endif /* __CONFIG_BMIPS_BCM6362_H */
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33
include/dt-bindings/clock/bcm6362-clock.h
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33
include/dt-bindings/clock/bcm6362-clock.h
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/*
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* Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
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#define __DT_BINDINGS_CLOCK_BCM6362_H
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#define BCM6362_CLK_GLESS 0
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#define BCM6362_CLK_ADSL_QPROC 1
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#define BCM6362_CLK_ADSL_AFE 2
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#define BCM6362_CLK_ADSL 3
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#define BCM6362_CLK_MIPS 4
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#define BCM6362_CLK_WLAN_OCP 5
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#define BCM6362_CLK_SWPKT_USB 7
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#define BCM6362_CLK_SWPKT_SAR 8
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#define BCM6362_CLK_SAR 9
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#define BCM6362_CLK_ROBOSW 10
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#define BCM6362_CLK_PCM 11
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#define BCM6362_CLK_USBD 12
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#define BCM6362_CLK_USBH 13
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#define BCM6362_CLK_IPSEC 14
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#define BCM6362_CLK_SPI 15
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#define BCM6362_CLK_HSSPI 16
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#define BCM6362_CLK_PCIE 17
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#define BCM6362_CLK_FAP 18
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#define BCM6362_CLK_PHYMIPS 19
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#define BCM6362_CLK_NAND 20
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#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */
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25
include/dt-bindings/power-domain/bcm6362-power-domain.h
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25
include/dt-bindings/power-domain/bcm6362-power-domain.h
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/*
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* Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
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#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
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#define BCM6362_PWR_SAR 0
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#define BCM6362_PWR_IPSEC 1
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#define BCM6362_PWR_MIPS 2
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#define BCM6362_PWR_DECT 3
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#define BCM6362_PWR_USBH 4
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#define BCM6362_PWR_USBD 5
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#define BCM6362_PWR_ROBOSW 6
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#define BCM6362_PWR_PCM 7
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#define BCM6362_PWR_PERIPH 8
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#define BCM6362_PWR_ADSL_PHY 9
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#define BCM6362_PWR_GMII_PADS 10
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#define BCM6362_PWR_FAP 11
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#define BCM6362_PWR_PCIE 12
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#define BCM6362_PWR_WLAN_PADS 13
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#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */
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28
include/dt-bindings/reset/bcm6362-reset.h
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28
include/dt-bindings/reset/bcm6362-reset.h
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/*
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* Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM6362_H
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#define __DT_BINDINGS_RESET_BCM6362_H
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#define BCM6362_RST_SPI 0
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#define BCM6362_RST_IPSEC 1
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#define BCM6362_RST_EPHY 2
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#define BCM6362_RST_SAR 3
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#define BCM6362_RST_ENETSW 4
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#define BCM6362_RST_USBD 5
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#define BCM6362_RST_USBH 6
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#define BCM6362_RST_PCM 7
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#define BCM6362_RST_PCIE_CORE 8
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#define BCM6362_RST_PCIE 9
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#define BCM6362_RST_PCIE_EXT 10
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#define BCM6362_RST_WLAN_SHIM 11
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#define BCM6362_RST_DDR_PHY 12
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#define BCM6362_RST_FAP 13
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#define BCM6362_RST_WLAN_UBUS 14
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#endif /* __DT_BINDINGS_RESET_BCM6362_H */
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