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Cleanup: fix "MHz" spelling

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2008-10-19 02:35:50 +02:00
parent 08ef89ecd1
commit 8ed44d91c8
44 changed files with 98 additions and 98 deletions
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2
cpu/ixp/npe/miiphy.c
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@@ -32,7 +32,7 @@
| Date Description of Change BY
| --------- --------------------- ---
| 05-May-99 Created MKW
| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
| 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
| better match OPB speed. Also modified delay times. JWB
| 29-Jul-99 Added Full duplex support MKW
| 24-Aug-99 Removed printf from dp83843_duplex() JWB

4
cpu/mips/incaip_clock.c
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@@ -33,8 +33,8 @@
*
* RETURNS:
* 150.000.000 for 150 MHz
* 133.333.333 for 133 Mhz (= 400MHz/3)
* 100.000.000 for 100 Mhz (= 400MHz/4)
* 133.333.333 for 133 MHz (= 400MHz/3)
* 100.000.000 for 100 MHz (= 400MHz/4)
* NOTE:
* This functions should be used by the hardware driver to get the correct
* frequency of the CPU. Don't use the macros, which are set to init the CPU

2
cpu/mpc8220/i2cCore.c
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@@ -440,7 +440,7 @@ STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb)
return OK;
}
/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls
/* FDR table base on 33MHz - more detail please refer to Odini2c_dividers.xls
FDR FDR scl sda scl2tap2
510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5
000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0

4
cpu/mpc83xx/spd_sdram.c
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@@ -314,7 +314,7 @@ long int spd_sdram()
+ (spd.clk_cycle & 0x0f));
max_data_rate = max_bus_clk * 2;
debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
@@ -401,7 +401,7 @@ long int spd_sdram()
}
}
debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
/*

2
cpu/mpc8xx/fec.c
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@@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx)
* * the MII management interface clock must be less than or equal
* * to 2.5 MHz.
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
* * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
* * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/

2
cpu/mpc8xx/serial.c
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@@ -70,7 +70,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
if(divisor/16>0x1000) {
/* bad divisor, assume 50Mhz clock and 9600 baud */
/* bad divisor, assume 50MHz clock and 9600 baud */
divisor=(50*1000*1000 + 8*9600)/16/9600;
}

2
cpu/ppc4xx/4xx_pci.c
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@@ -286,7 +286,7 @@ void pci_405gp_init(struct pci_controller *hose)
#endif /* CONFIG_SYS_PCI_CLASSCODE */
/*--------------------------------------------------------------------------+
* If PCI speed = 66Mhz, set 66Mhz capable bit.
* If PCI speed = 66MHz, set 66MHz capable bit.
*--------------------------------------------------------------------------*/
if (bd->bi_pci_busfreq >= 66000000) {
pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);

2
cpu/ppc4xx/miiphy.c
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@@ -301,7 +301,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
/* set clock (50MHz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \

2
cpu/ppc4xx/speed.c
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@@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
* to make sure it is within the proper range.
* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
* Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
* Note freqVCO is calculated in MHz to avoid errors introduced by rounding.
*/
if (sysInfo->pllFwdDiv == 1) {
sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;

2
cpu/s3c44b0/cpu.c
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@@ -256,7 +256,7 @@ void i2c_init(int speed, int slaveaddr)
/*
Enable ACK, IICCLK=MCLK/16, enable interrupt
75Mhz/16/(12+1) = 390625 Hz
75MHz/16/(12+1) = 390625 Hz
*/
rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
IICCON = rIICCON;