diff --git a/arch/arm/dts/versal-clk.dtsi b/arch/arm/dts/versal-clk.dtsi
index 8363a089b7..0c04d9af68 100644
--- a/arch/arm/dts/versal-clk.dtsi
+++ b/arch/arm/dts/versal-clk.dtsi
@@ -80,6 +80,10 @@
 	};
 };
 
+&cpu0 {
+	clocks = <&versal_clk ACPU>;
+};
+
 &can0 {
 	clocks = <&versal_clk CAN0_REF>, <&versal_clk LPD_LSBUS>;
 	power-domains = <&versal_firmware PD_CAN_FD_0>;
diff --git a/arch/arm/dts/versal.dtsi b/arch/arm/dts/versal.dtsi
index 393271cabb..54647924ca 100644
--- a/arch/arm/dts/versal.dtsi
+++ b/arch/arm/dts/versal.dtsi
@@ -23,6 +23,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
+			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0>;
 		};
 
@@ -30,10 +31,36 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
+			operating-points-v2 = <&cpu_opp_table>;
 			reg = <1>;
 		};
 	};
 
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 {
+			opp-hz = /bits/ 64 <1199999988>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <599999994>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <399999996>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <299999997>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+	};
+
 	dcc: dcc {
 		compatible = "arm,dcc";
 		status = "disabled";