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Merge branch 'master' of git://git.denx.de/u-boot-dm

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This commit is contained in:
Tom Rini
2015-01-30 09:24:42 -05:00
parent 0f274f5376 85df958ce2
commit 8e3da9dd11
185 changed files with 4646 additions and 1619 deletions
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27
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
int func01, func23;
/* High-Speed I2C */
if (flags & PINMUX_FLAG_HS_MODE) {
func01 = 4;
func23 = 4;
} else {
func01 = 2;
func23 = 3;
}
switch (peripheral) {
case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));

2
arch/arm/cpu/tegra20-common/pmu.c
View File

@@ -52,7 +52,7 @@ int pmu_set_nominal(void)
debug("%s: Cannot find DVC I2C bus\n", __func__);
return ret;
}
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find DVC I2C chip\n", __func__);
return ret;

31
arch/arm/dts/exynos4.dtsi
View File

@@ -51,56 +51,64 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <0 0 0>;
reg = <0x13860000 0x100>;
interrupts = <0 56 0>;
};
i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <1 1 0>;
reg = <0x13870000 0x100>;
interrupts = <1 57 0>;
};
i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <2 2 0>;
reg = <0x13880000 0x100>;
interrupts = <2 58 0>;
};
i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <3 3 0>;
reg = <0x13890000 0x100>;
interrupts = <3 59 0>;
};
i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <4 4 0>;
reg = <0x138a0000 0x100>;
interrupts = <4 60 0>;
};
i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <5 5 0>;
reg = <0x138b0000 0x100>;
interrupts = <5 61 0>;
};
i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <6 6 0>;
reg = <0x138c0000 0x100>;
interrupts = <6 62 0>;
};
i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <7 7 0>;
reg = <0x138d0000 0x100>;
interrupts = <7 63 0>;
};
sdhci@12510000 {
@@ -143,11 +151,4 @@
interrupts = <0 131 0>;
};
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

2
arch/arm/dts/exynos4210-origen.dts
View File

@@ -36,7 +36,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0xA2 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4210-trats.dts
View File

@@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {

12
arch/arm/dts/exynos4210-universal_c210.dts
View File

@@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {
@@ -43,10 +43,10 @@
soft-spi {
compatible = "u-boot,soft-spi";
cs-gpio = <&gpio 235 0>; /* Y43 */
sclk-gpio = <&gpio 225 0>; /* Y31 */
mosi-gpio = <&gpio 227 0>; /* Y33 */
miso-gpio = <&gpio 224 0>; /* Y30 */
cs-gpio = <&gpy4 3 0>;
sclk-gpio = <&gpy3 1 0>;
mosi-gpio = <&gpy3 3 0>;
miso-gpio = <&gpy3 0 0>;
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;

9
arch/arm/dts/exynos4412-odroid.dts
View File

@@ -16,6 +16,13 @@
aliases {
i2c0 = "/i2c@13860000";
i2c1 = "/i2c@13870000";
i2c2 = "/i2c@13880000";
i2c3 = "/i2c@13890000";
i2c4 = "/i2c@138a0000";
i2c5 = "/i2c@138b0000";
i2c6 = "/i2c@138c0000";
i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc2 = "sdhci@12530000";
@@ -51,7 +58,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 122 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

6
arch/arm/dts/exynos4412-trats2.dts
View File

@@ -416,7 +416,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@@ -427,7 +427,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x7a 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
@@ -437,7 +437,7 @@
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;

4
arch/arm/dts/exynos5.dtsi
View File

@@ -6,6 +6,7 @@
*/
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "samsung,exynos5";
@@ -247,7 +248,4 @@
u-boot,dm-pre-reloc;
id = <3>;
};
gpio: gpio {
};
};

8
arch/arm/dts/exynos5250-arndale.dts
View File

@@ -15,6 +15,14 @@
compatible = "samsung,arndale", "samsung,exynos5250";
aliases {
i2c0 = "/i2c@12c60000";
i2c1 = "/i2c@12c70000";
i2c2 = "/i2c@12c80000";
i2c3 = "/i2c@12c90000";
i2c4 = "/i2c@12ca0000";
i2c5 = "/i2c@12cb0000";
i2c6 = "/i2c@12cc0000";
i2c7 = "/i2c@12cd0000";
serial0 = "/serial@12C20000";
console = "/serial@12C20000";
};

2
arch/arm/dts/exynos5250-smdk5250.dts
View File

@@ -146,6 +146,6 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
};

11
arch/arm/dts/exynos5250-snow.dts
View File

@@ -44,7 +44,8 @@
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
ec-interrupt = <&gpio 182 1>;
u-boot,i2c-offset-len = <0>;
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
};
power-regulator@48 {
@@ -68,7 +69,7 @@
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
ec-interrupt = <&gpio 182 1>;
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
optimise-flash-write;
status = "disabled";
};
@@ -76,7 +77,7 @@
sound@3830000 {
samsung,codec-type = "max98095";
codec-enable-gpio = <&gpio 0xb7 0>;
codec-enable-gpio = <&gpx1 7 GPIO_ACTIVE_HIGH>;
};
sound@12d60000 {
@@ -131,11 +132,11 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
};
tmu@10060000 {

8
arch/arm/dts/exynos5420-peach-pit.dts
View File

@@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5420", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@@ -108,7 +108,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@@ -124,11 +124,11 @@
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {

2
arch/arm/dts/exynos5422-odroidxu3.dts
View File

@@ -32,7 +32,7 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */
samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
serial@12C20000 {

10
arch/arm/dts/exynos5800-peach-pi.dts
View File

@@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5800", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@@ -32,7 +32,7 @@
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
arm-frequency = <1700000000>;
arm-frequency = <900000000>;
};
tmu@10060000 {
@@ -102,7 +102,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@@ -118,11 +118,11 @@
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {

5
arch/arm/dts/tegra114-dalmore.dts
View File

@@ -57,7 +57,7 @@
};
sdhci@78000400 {
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
@@ -68,8 +68,7 @@
};
usb@7d008000 {
/* SPDIF_IN: USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio 86 0>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
};

9
arch/arm/dts/tegra124-jetson-tk1.dts
View File

@@ -303,8 +303,9 @@
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
power-gpios = <&gpio 136 0>; /* gpio PR0 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -316,12 +317,12 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
regulators {

9
arch/arm/dts/tegra124-venice2.dts
View File

@@ -72,8 +72,9 @@
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 0>; /* gpio PV2 */
power-gpios = <&gpio 136 0>; /* gpio PR0 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
@@ -85,11 +86,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
};

10
arch/arm/dts/tegra20-colibri_t20_iris.dts
View File

@@ -22,16 +22,16 @@
};
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <15 100 25 80 25 10 15 10 100>;
@@ -43,7 +43,7 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
};

28
arch/arm/dts/tegra20-harmony.dts
View File

@@ -37,7 +37,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@@ -67,22 +67,22 @@
};
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
};
sdhci@c8000200 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@@ -100,10 +100,14 @@
vsyncx-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};

9
arch/arm/dts/tegra20-medcom-wide.dts
View File

@@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};

18
arch/arm/dts/tegra20-paz00.dts
View File

@@ -61,9 +61,9 @@
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 169 0>; /* gpio PV1 */
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -86,10 +86,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
nvidia,backlight-enable-gpios = <&gpio 164 0>; /* PU4 */
nvidia,lvds-shutdown-gpios = <&gpio 102 0>; /* PM6 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 4 0>; /* PA4 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};

22
arch/arm/dts/tegra20-seaboard.dts
View File

@@ -65,7 +65,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@@ -151,7 +151,7 @@
};
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
@@ -161,9 +161,9 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -186,10 +186,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};

9
arch/arm/dts/tegra20-tamonten.dtsi
View File

@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@@ -280,7 +281,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
@@ -476,8 +477,8 @@
};
sdhci@c8000600 {
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};

9
arch/arm/dts/tegra20-tec.dts
View File

@@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};

8
arch/arm/dts/tegra20-trimslice.dts
View File

@@ -62,7 +62,7 @@
};
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
@@ -76,8 +76,8 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -111,7 +111,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
};

18
arch/arm/dts/tegra20-ventana.dts
View File

@@ -61,9 +61,9 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -86,10 +86,14 @@
vsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};

2
arch/arm/dts/tegra20-whistler.dts
View File

@@ -66,7 +66,7 @@
sdhci@c8000400 {
status = "okay";
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};

10
arch/arm/dts/tegra30-apalis.dts
View File

@@ -243,13 +243,13 @@
sdhci@78000000 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
sdhci@78000600 {
@@ -262,20 +262,20 @@
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
nvidia,vbus-gpio = <&gpio 157 0>; /* PT5, USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
regulators {

10
arch/arm/dts/tegra30-beaver.dts
View File

@@ -196,9 +196,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -210,11 +210,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};

8
arch/arm/dts/tegra30-cardhu.dts
View File

@@ -185,9 +185,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -197,7 +197,7 @@
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};

6
arch/arm/dts/tegra30-colibri.dts
View File

@@ -64,7 +64,7 @@
sdhci@78000200 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio 23 1>; /* PC7, MMCD */
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
@@ -83,12 +83,12 @@
usb@7d004000 {
status = "okay";
phy_type = "utmi";
nvidia,vbus-gpio = <&gpio 234 0>; /* PDD2, VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 178 1>; /* PW2, USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};

4
arch/arm/dts/tegra30-tamonten.dtsi
View File

@@ -55,8 +55,8 @@
/* SD slot on the base board */
sdhci@78000400 {
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 67 0>; /* gpio PI3 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};

3
arch/arm/include/asm/arch-exynos/pinmux.h
View File

@@ -23,6 +23,9 @@ enum {
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
/* Flags for I2C */
PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**

0
arch/arm/include/asm/arch-pantheon/gpio.h Normal file
View File

7
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View File

@@ -10,6 +10,7 @@
#define __TEGRA_MMC_H_
#include <fdtdec.h>
#include <asm/gpio.h>
/* for mmc_config definition */
#include <mmc.h>
@@ -134,9 +135,9 @@ struct mmc_host {
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
struct fdt_gpio_state pwr_gpio; /* Power GPIO */
struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */

9
arch/arm/include/asm/arch-tegra20/display.h
View File

@@ -10,6 +10,7 @@
#include <asm/arch/dc.h>
#include <fdtdec.h>
#include <asm/gpio.h>
/* This holds information about a window which can be displayed */
struct disp_ctl_win {
@@ -72,10 +73,10 @@ struct fdt_panel_config {
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
struct gpio_desc backlight_en; /* GPIO for backlight enable */
struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise

15
arch/arm/include/asm/arch-zynq/gpio.h
View File

@@ -7,19 +7,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
inline int gpio_get_value(unsigned gpio)
{
return 0;
}
inline int gpio_set_value(unsigned gpio, int val)
{
return 0;
}
inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
#endif /* _ZYNQ_GPIO_H */

3
arch/blackfin/cpu/cpu.c
View File

@@ -24,6 +24,7 @@
#include "cpu.h"
#include "initcode.h"
#include "exports.h"
ulong bfin_poweron_retx;
DECLARE_GLOBAL_DATA_PTR;
@@ -121,7 +122,7 @@ static void display_global_data(void)
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
printf(" \\-bd: %p\n", gd->bd);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);

11
arch/sandbox/dts/sandbox.dts
View File

@@ -19,6 +19,7 @@
colour = "cyan";
sides = <3>;
character = <83>;
light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
};
square {
compatible = "demo-shape";
@@ -126,7 +127,7 @@
0x070b0067 0x070c0069>;
};
gpio_a: gpios {
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <1>;
@@ -134,6 +135,14 @@
num-gpios = <20>;
};
gpio_b: gpios@1 {
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <2>;
gpio-bank-name = "b";
num-gpios = <10>;
};
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;