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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-04-14 10:38:37 +02:00
commit 8dc16cf9dd
4 changed files with 12 additions and 9 deletions
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1
arch/arm/include/asm/arch-mx5/imx-regs.h
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@ -230,6 +230,7 @@
#define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2) #define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

1
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -346,6 +346,7 @@ struct cspi_regs {
#define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2) #define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

17
drivers/spi/mxc_spi.c
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@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
return -1; return -1;
} }
/* Reset spi */ /*
reg_write(&regs->ctrl, 0); * Reset SPI and set all CSs to master mode, if toggling
reg_write(&regs->ctrl, MXC_CSPICTRL_EN); * between slave and master mode we might see a glitch
* on the clock line
reg_ctrl = reg_read(&regs->ctrl); */
reg_ctrl = MXC_CSPICTRL_MODE_MASK;
reg_write(&regs->ctrl, reg_ctrl);
reg_ctrl |= MXC_CSPICTRL_EN;
reg_write(&regs->ctrl, reg_ctrl);
/* /*
* The following computation is taken directly from Freescale's code. * The following computation is taken directly from Freescale's code.
@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div); MXC_CSPICTRL_POSTDIV(post_div);
/* always set to master mode */
reg_ctrl |= 1 << (cs + 4);
/* We need to disable SPI before changing registers */ /* We need to disable SPI before changing registers */
reg_ctrl &= ~MXC_CSPICTRL_EN; reg_ctrl &= ~MXC_CSPICTRL_EN;

2
include/configs/mx6qsabre_common.h
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@ -148,7 +148,7 @@
#define CONFIG_BOOTCOMMAND \ #define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \ "mmc dev ${mmcdev};" \
"if mmc rescan ${mmcdev}; then " \ "if mmc rescan; then " \
"if run loadbootscript; then " \ "if run loadbootscript; then " \
"run bootscript; " \ "run bootscript; " \
"else " \ "else " \