mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
9a9865508f
commit
8d85808fa1
@ -146,44 +146,45 @@
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*/
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#define CONFIG_SYS_DDR_SIZE 512 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
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#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| 0x00010000 /* ODT_WR to CSn */ \
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| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
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| CSCONFIG_ROW_BIT_14 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80010202 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
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| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
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| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00620802 */
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#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
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| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
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| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
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| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
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| (13 << TIMING_CFG1_REFREC_SHIFT ) \
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| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
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| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
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| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (13 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3935d322 */
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#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
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| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
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| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
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| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
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| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (6 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x131088c8 */
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#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
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| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
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#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03E00100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
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| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x1432 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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#endif
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@ -216,7 +217,8 @@
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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@ -235,13 +237,14 @@
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#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
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| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
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| BR_V ) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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@ -249,7 +252,7 @@
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD )
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| OR_GPCM_EAD)
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/* 0xFE000FF7 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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@ -263,10 +266,12 @@
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* BCSR on the Local Bus
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*/
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#define CONFIG_SYS_BCSR 0xF8000000
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
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/* Access window base at BCSR base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
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/* Port size=8bit, MSEL=GPCM */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
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#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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/*
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@ -278,19 +283,19 @@
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
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#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_PS_8 /* 8 bit port */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */
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#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \
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| OR_FCM_BCTLD \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_RST \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR )
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| OR_FCM_EHTR)
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/* 0xFFFF919E */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
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@ -454,7 +459,8 @@ extern int board_pci_host_broken(void);
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#else
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@ -526,9 +532,11 @@ extern int board_pci_host_broken(void);
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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@ -555,53 +563,93 @@ extern int board_pci_host_broken(void);
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#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
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| BATU_BL_8M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* BCSR: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
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| BATU_BL_32M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#else
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@ -650,7 +698,8 @@ extern int board_pci_host_broken(void);
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
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"$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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