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pinctrl: uniphier: introduce capability flag

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The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones.  Having flags would be better than
adding new members every time a new SoC-specific capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2016-03-24 22:32:44 +09:00
parent 510454db04
commit 8cc92b996d
8 changed files with 29 additions and 27 deletions
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27
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
View File

@ -68,14 +68,33 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
unsigned muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
unsigned mux_bits = priv->socdata->mux_bits;
unsigned reg_stride = priv->socdata->reg_stride;
unsigned reg, reg_end, shift, mask;
unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
bool load_pinctrl;
u32 tmp;
/* some pins need input-enabling */
uniphier_pinconf_input_enable(dev, pin);
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
* Mode offset bit
* Normal 4 * n shift+3:shift
* Debug 4 * n shift+7:shift+4
*/
mux_bits = 4;
reg_stride = 8;
load_pinctrl = true;
} else {
/*
* Mode offset bit
* Normal 8 * n shift+3:shift
* Debug 8 * n + 4 shift+3:shift
*/
mux_bits = 8;
reg_stride = 4;
load_pinctrl = false;
}
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
reg_end = reg + reg_stride;
shift = pin * mux_bits % 32;
@ -94,7 +113,7 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
muxval >>= mux_bits;
}
if (priv->socdata->load_pinctrl)
if (load_pinctrl)
writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
}

3
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(ph1_ld4_groups),
.functions = ph1_ld4_functions,
.functions_count = ARRAY_SIZE(ph1_ld4_functions),
.mux_bits = 8,
.reg_stride = 4,
.load_pinctrl = false,
};
static int ph1_ld4_pinctrl_probe(struct udevice *dev)

3
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(ph1_ld6b_groups),
.functions = ph1_ld6b_functions,
.functions_count = ARRAY_SIZE(ph1_ld6b_functions),
.mux_bits = 8,
.reg_stride = 4,
.load_pinctrl = false,
};
static int ph1_ld6b_pinctrl_probe(struct udevice *dev)

4
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

@ -103,9 +103,7 @@ static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(ph1_pro4_groups),
.functions = ph1_pro4_functions,
.functions_count = ARRAY_SIZE(ph1_pro4_functions),
.mux_bits = 4,
.reg_stride = 8,
.load_pinctrl = true,
.caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
static int ph1_pro4_pinctrl_probe(struct udevice *dev)

4
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

@ -117,9 +117,7 @@ static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(ph1_pro5_groups),
.functions = ph1_pro5_functions,
.functions_count = ARRAY_SIZE(ph1_pro5_functions),
.mux_bits = 4,
.reg_stride = 8,
.load_pinctrl = true,
.caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
static int ph1_pro5_pinctrl_probe(struct udevice *dev)

3
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

@ -114,9 +114,6 @@ static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(proxstream2_groups),
.functions = proxstream2_functions,
.functions_count = ARRAY_SIZE(proxstream2_functions),
.mux_bits = 8,
.reg_stride = 4,
.load_pinctrl = false,
};
static int proxstream2_pinctrl_probe(struct udevice *dev)

3
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

@ -115,9 +115,6 @@ static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
.groups_count = ARRAY_SIZE(ph1_sld8_groups),
.functions = ph1_sld8_functions,
.functions_count = ARRAY_SIZE(ph1_sld8_functions),
.mux_bits = 8,
.reg_stride = 4,
.load_pinctrl = false,
};
static int ph1_sld8_pinctrl_probe(struct udevice *dev)

9
drivers/pinctrl/uniphier/pinctrl-uniphier.h
View File

@ -7,6 +7,7 @@
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
@ -59,8 +60,7 @@ struct uniphier_pinctrl_group {
* @functions_count: number of pinmux functions
* @mux_bits: bit width of each pinmux register
* @reg_stride: stride of pinmux register address
* @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
* values in pinmux registers to become really effective
* @caps: SoC-specific capability flag
*/
struct uniphier_pinctrl_socdata {
const struct uniphier_pinctrl_pin *pins;
@ -69,9 +69,8 @@ struct uniphier_pinctrl_socdata {
int groups_count;
const char * const *functions;
int functions_count;
unsigned mux_bits;
unsigned reg_stride;
bool load_pinctrl;
unsigned caps;
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \