mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
This commit is contained in:
Vignesh R
Jagan Teki
parent
0c6f187cdb
commit
8c927809ea
@ -291,6 +291,7 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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return mtd->priv;
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}
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#ifndef CONFIG_SPI_FLASH_BAR
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static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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{
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size_t i;
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@ -365,6 +366,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
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nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
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}
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#endif /* !CONFIG_SPI_FLASH_BAR */
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/* Enable/disable 4-byte addressing mode. */
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static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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@ -499,6 +501,79 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
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DEFAULT_READY_WAIT_JIFFIES);
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}
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#ifdef CONFIG_SPI_FLASH_BAR
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/*
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* This "clean_bar" is necessary in a situation when one was accessing
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* spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
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*
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* After it the BA24 bit shall be cleared to allow access to correct
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* memory region after SW reset (by calling "reset" command).
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*
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* Otherwise, the BA24 bit may be left set and then after reset, the
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* ROM would read/write/erase SPL from 16 MiB * bank_sel address.
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*/
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static int clean_bar(struct spi_nor *nor)
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{
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u8 cmd, bank_sel = 0;
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if (nor->bank_curr == 0)
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return 0;
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cmd = nor->bank_write_cmd;
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nor->bank_curr = 0;
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write_enable(nor);
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return nor->write_reg(nor, cmd, &bank_sel, 1);
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}
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static int write_bar(struct spi_nor *nor, u32 offset)
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{
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u8 cmd, bank_sel;
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int ret;
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bank_sel = offset / SZ_16M;
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if (bank_sel == nor->bank_curr)
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goto bar_end;
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cmd = nor->bank_write_cmd;
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write_enable(nor);
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ret = nor->write_reg(nor, cmd, &bank_sel, 1);
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if (ret < 0) {
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debug("SF: fail to write bank register\n");
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return ret;
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}
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bar_end:
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nor->bank_curr = bank_sel;
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return nor->bank_curr;
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}
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static int read_bar(struct spi_nor *nor, const struct flash_info *info)
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{
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u8 curr_bank = 0;
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int ret;
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_SPANSION:
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nor->bank_read_cmd = SPINOR_OP_BRRD;
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nor->bank_write_cmd = SPINOR_OP_BRWR;
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break;
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default:
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nor->bank_read_cmd = SPINOR_OP_RDEAR;
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nor->bank_write_cmd = SPINOR_OP_WREAR;
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}
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ret = nor->read_reg(nor, nor->bank_read_cmd,
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&curr_bank, 1);
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if (ret) {
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debug("SF: fail to read bank addr register\n");
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return ret;
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}
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nor->bank_curr = curr_bank;
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return 0;
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}
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#endif
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/*
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* Initiate the erasure of a single sector
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*/
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@ -543,6 +618,11 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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len = instr->len;
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while (len) {
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = write_bar(nor, addr);
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if (ret < 0)
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return ret;
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#endif
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write_enable(nor);
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ret = spi_nor_erase_sector(nor, addr);
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@ -557,9 +637,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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goto erase_err;
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}
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erase_err:
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = clean_bar(nor);
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#endif
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write_disable(nor);
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erase_err:
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return ret;
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}
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@ -1144,8 +1227,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
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while (len) {
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loff_t addr = from;
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size_t read_len = len;
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ret = nor->read(nor, addr, len, buf);
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#ifdef CONFIG_SPI_FLASH_BAR
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u32 remain_len;
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ret = write_bar(nor, addr);
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if (ret < 0)
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return log_ret(ret);
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remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
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if (len < remain_len)
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read_len = len;
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else
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read_len = remain_len;
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#endif
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ret = nor->read(nor, addr, read_len, buf);
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if (ret == 0) {
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/* We shouldn't see 0-length reads */
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ret = -EIO;
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@ -1162,18 +1260,49 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
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ret = 0;
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read_err:
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = clean_bar(nor);
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#endif
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return ret;
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}
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#ifdef CONFIG_SPI_FLASH_SST
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static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
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size_t *retlen, const u_char *buf)
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{
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size_t actual;
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int ret = 0;
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for (actual = 0; actual < len; actual++) {
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nor->program_opcode = SPINOR_OP_BP;
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write_enable(nor);
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/* write one byte. */
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ret = nor->write(nor, to, 1, buf + actual);
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if (ret < 0)
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goto sst_write_err;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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goto sst_write_err;
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to++;
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}
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sst_write_err:
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write_disable(nor);
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return ret;
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}
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static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
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size_t *retlen, const u_char *buf)
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{
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struct spi_nor *nor = mtd_to_spi_nor(mtd);
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struct spi_slave *spi = nor->spi;
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size_t actual;
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int ret;
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dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
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if (spi->mode & SPI_TX_BYTE)
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return sst_write_byteprogram(nor, to, len, retlen, buf);
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write_enable(nor);
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@ -1271,6 +1400,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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page_remain = min_t(size_t,
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nor->page_size - page_offset, len - i);
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = write_bar(nor, addr);
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if (ret < 0)
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return ret;
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#endif
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write_enable(nor);
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ret = nor->write(nor, addr, page_remain, buf + i);
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if (ret < 0)
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@ -1289,6 +1423,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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}
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write_err:
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = clean_bar(nor);
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#endif
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return ret;
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}
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@ -2532,12 +2669,20 @@ int spi_nor_scan(struct spi_nor *nor)
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/* already configured from SFDP */
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} else if (info->addr_width) {
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nor->addr_width = info->addr_width;
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} else if (mtd->size > 0x1000000) {
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} else if (mtd->size > SZ_16M) {
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#ifndef CONFIG_SPI_FLASH_BAR
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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info->flags & SPI_NOR_4B_OPCODES)
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spi_nor_set_4byte_opcodes(nor, info);
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#else
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/* Configure the BAR - discover bank cmds and read current bank */
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nor->addr_width = 3;
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ret = read_bar(nor, info);
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if (ret < 0)
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return ret;
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#endif
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} else {
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nor->addr_width = 3;
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}
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@ -2569,3 +2714,14 @@ int spi_nor_scan(struct spi_nor *nor)
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return 0;
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}
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/* U-Boot specific functions, need to extend MTD to support these */
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int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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if (sr < 0)
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return sr;
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return (sr >> 2) & 7;
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}
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@ -105,6 +105,7 @@
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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#define SPINOR_OP_BRRD 0x16 /* Bank register read */
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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/* Used for Micron flashes only. */
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@ -256,6 +257,9 @@ struct flash_info;
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* @read_opcode: the read opcode
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* @read_dummy: the dummy needed by the read operation
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* @program_opcode: the program opcode
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* @bank_read_cmd: Bank read cmd
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* @bank_write_cmd: Bank write cmd
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* @bank_curr: Current flash bank
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* @sst_write_second: used by the SST write operation
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* @flags: flag options for the current SPI-NOR (SNOR_F_*)
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* @read_proto: the SPI protocol for read operations
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@ -291,6 +295,11 @@ struct spi_nor {
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u8 read_opcode;
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u8 read_dummy;
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u8 program_opcode;
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 bank_read_cmd;
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u8 bank_write_cmd;
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u8 bank_curr;
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#endif
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enum spi_nor_protocol read_proto;
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enum spi_nor_protocol write_proto;
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enum spi_nor_protocol reg_proto;
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