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Merge branch 'u-boot-stm32_20190827' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

Browse Source 
- Fixes and update related to STM32MP1 platforms
This commit is contained in:
Tom Rini
2019-08-27 13:19:47 -04:00
parent e4b8dd9b34 06d1dd2cdc
commit 8c56ea5c1e
63 changed files with 2082 additions and 903 deletions
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1
arch/arm/Kconfig
View File

@@ -1567,6 +1567,7 @@ config ARCH_STM32MP
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
imply OF_LIBFDT_OVERLAY
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
imply USE_PREBOOT
help

119
arch/arm/dts/stih407-clock.dtsi
View File

@@ -1,38 +1,29 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih407-clks.h>
/ {
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* A9 PLL.
*/
@@ -62,35 +53,22 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@090ff000 {
clockgen-a@90ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
@@ -101,6 +79,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,6 +91,7 @@
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0";
clock-critical = <CLK_IC_LMI0>;
};
};
@@ -126,9 +106,10 @@
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@09103000 {
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -139,6 +120,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
@@ -194,6 +176,27 @@
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
clock-critical = <CLK_PROC_STFE>,
<CLK_ICN_CPU>,
<CLK_TX_ICN_DMU>,
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
};
};
@@ -210,7 +213,7 @@
"clk-s-d0-fs0-ch3";
};
clockgen-d0@09104000 {
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
@@ -244,13 +247,7 @@
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;

200
arch/arm/dts/stih407-family.dtsi
View File

@@ -1,10 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
@@ -20,7 +17,13 @@
#size-cells = <1>;
ranges;
dmu_reserved: rproc@44000000 {
gp0_reserved: rproc@45000000 {
compatible = "shared-dma-pool";
reg = <0x45000000 0x00400000>;
no-map;
};
delta_reserved: rproc@44000000 {
compatible = "shared-dma-pool";
reg = <0x44000000 0x01000000>;
no-map;
@@ -47,6 +50,7 @@
clocks = <&clk_m_a9>;
clock-names = "cpu";
clock-latency = <100000>;
cpu0-supply = <&pwm_regulator>;
st,syscfg = <&syscfg_core 0x8e0>;
};
cpu@1 {
@@ -65,19 +69,19 @@
};
};
intc: interrupt-controller@08761000 {
intc: interrupt-controller@8761000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x08761000 0x1000>, <0x08760100 0x100>;
};
scu@08760000 {
scu@8760000 {
compatible = "arm,cortex-a9-scu";
reg = <0x08760000 0x1000>;
};
timer@08760200 {
timer@8760200 {
interrupt-parent = <&intc>;
compatible = "arm,cortex-a9-global-timer";
reg = <0x08760200 0x100>;
@@ -85,7 +89,7 @@
clocks = <&arm_periph_clk>;
};
l2: cache-controller {
l2: cache-controller@8762000 {
compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>;
@@ -118,24 +122,28 @@
ranges;
compatible = "simple-bus";
restart {
restart: restart-controller@0 {
compatible = "st,stih407-restart";
reg = <0 0>;
st,syscfg = <&syscfg_sbc_reg>;
status = "okay";
};
powerdown: powerdown-controller {
powerdown: powerdown-controller@0 {
compatible = "st,stih407-powerdown";
reg = <0 0>;
#reset-cells = <1>;
};
softreset: softreset-controller {
softreset: softreset-controller@0 {
compatible = "st,stih407-softreset";
reg = <0 0>;
#reset-cells = <1>;
};
picophyreset: picophyreset-controller {
picophyreset: picophyreset-controller@0 {
compatible = "st,stih407-picophyreset";
reg = <0 0>;
#reset-cells = <1>;
};
@@ -167,6 +175,13 @@
syscfg_core: core-syscfg@92b0000 {
compatible = "st,stih407-core-syscfg", "syscon";
reg = <0x92b0000 0x1000>;
sti_sasg_codec: sti-sasg-codec {
compatible = "st,stih407-sas-codec";
#sound-dai-cells = <1>;
status = "disabled";
st,syscfg = <&syscfg_core>;
};
};
syscfg_lpm: lpm-syscfg@94b5100 {
@@ -174,8 +189,9 @@
reg = <0x94b5100 0x1000>;
};
irq-syscfg {
irq-syscfg@0 {
compatible = "st,stih407-irq-syscfg";
reg = <0 0>;
st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
@@ -187,22 +203,21 @@
vtg_main: sti-vtg-main@8d02800 {
compatible = "st,vtg";
reg = <0x8d02800 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
};
vtg_aux: sti-vtg-aux@8d00200 {
compatible = "st,vtg";
reg = <0x8d00200 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
serial@9830000 {
compatible = "st,asc";
reg = <0x9830000 0x2c>;
interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial0>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
/* Pinctrl moved out to a per-board configuration */
status = "disabled";
};
@@ -210,7 +225,7 @@
serial@9831000 {
compatible = "st,asc";
reg = <0x9831000 0x2c>;
interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial1>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
@@ -221,7 +236,7 @@
serial@9832000 {
compatible = "st,asc";
reg = <0x9832000 0x2c>;
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
@@ -233,7 +248,7 @@
sbc_serial0: serial@9530000 {
compatible = "st,asc";
reg = <0x9530000 0x2c>;
interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial0>;
clocks = <&clk_sysin>;
@@ -244,7 +259,7 @@
serial@9531000 {
compatible = "st,asc";
reg = <0x9531000 0x2c>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&clk_sysin>;
@@ -374,8 +389,9 @@
status = "disabled";
};
usb2_picophy0: phy1 {
usb2_picophy0: phy1@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -383,12 +399,13 @@
reset-names = "global", "port";
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0 0>;
phy_port0: port@9b22000 {
reg = <0x9b22000 0xff>,
@@ -458,6 +475,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -470,6 +489,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -482,6 +503,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -494,6 +517,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -507,6 +532,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi10_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -519,6 +546,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi11_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -531,16 +560,18 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi12_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmc0: sdhci@09060000 {
mmc0: sdhci@9060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
status = "disabled";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0>;
@@ -550,12 +581,12 @@
bus-width = <8>;
};
mmc1: sdhci@09080000 {
mmc1: sdhci@9080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
status = "disabled";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
@@ -563,7 +594,6 @@
clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
resets = <&softreset STIH407_MMC1_SOFTRESET>;
reset-names = "softreset";
bus-width = <4>;
};
@@ -590,7 +620,7 @@
compatible = "st,ahci";
reg = <0x9b20000 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
@@ -613,7 +643,7 @@
compatible = "st,ahci";
reg = <0x9b28000 0x1000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&phy_port1 PHY_TYPE_SATA>;
@@ -654,11 +684,12 @@
dwc3: dwc3@9900000 {
compatible = "snps,dwc3";
reg = <0x09900000 0x100000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
dr_mode = "peripheral";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb2_picophy0>,
<&phy_port2 PHY_TYPE_USB3>;
snps,dis_u3_susphy_quirk;
};
};
@@ -667,7 +698,7 @@
compatible = "st,sti-pwm";
#pwm-cells = <2>;
reg = <0x9810000 0x68>;
interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
clock-names = "pwm";
@@ -682,6 +713,7 @@
compatible = "st,sti-pwm";
#pwm-cells = <2>;
reg = <0x9510000 0x68>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_chan0_default
&pinctrl_pwm1_chan1_default
@@ -694,14 +726,14 @@
status = "disabled";
};
rng10: rng@08a89000 {
rng10: rng@8a89000 {
compatible = "st,rng";
reg = <0x08a89000 0x1000>;
clocks = <&clk_sysin>;
status = "okay";
};
rng11: rng@08a8a000 {
rng11: rng@8a8a000 {
compatible = "st,rng";
reg = <0x08a8a000 0x1000>;
clocks = <&clk_sysin>;
@@ -720,8 +752,8 @@
resets = <&softreset STIH407_ETH1_SOFTRESET>;
reset-names = "stmmaceth";
interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
<GIC_SPI 99 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
/* DMA Bus Mode */
@@ -735,26 +767,14 @@
<&clk_s_c0_flexgen CLK_ETH_PHY>;
};
cec: sti-cec@094a087c {
compatible = "st,stih-cec";
reg = <0x94a087c 0x64>;
clocks = <&clk_sysin>;
clock-names = "cec-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
interrupt-names = "cec-irq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cec0_default>;
resets = <&softreset STIH407_LPM_SOFTRESET>;
};
rng10: rng@08a89000 {
rng10: rng@8a89000 {
compatible = "st,rng";
reg = <0x08a89000 0x1000>;
clocks = <&clk_sysin>;
status = "okay";
};
rng11: rng@08a8a000 {
rng11: rng@8a8a000 {
compatible = "st,rng";
reg = <0x08a8a000 0x1000>;
clocks = <&clk_sysin>;
@@ -764,7 +784,7 @@
mailbox0: mailbox@8f00000 {
compatible = "st,stih407-mailbox";
reg = <0x8f00000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
mbox-name = "a9";
status = "okay";
@@ -794,9 +814,24 @@
status = "okay";
};
st231_delta: st231-delta@44000000 {
st231_gp0: st231-gp0@0 {
compatible = "st,st231-rproc";
memory-region = <&dmu_reserved>;
reg = <0 0>;
memory-region = <&gp0_reserved>;
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
clock-frequency = <600000000>;
st,syscfg = <&syscfg_core 0x22c>;
#mbox-cells = <1>;
mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
};
st231_delta: st231-delta@0 {
compatible = "st,st231-rproc";
reg = <0 0>;
memory-region = <&delta_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
@@ -819,7 +854,7 @@
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
};
@@ -837,9 +872,11 @@
<&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
status = "disabled";
};
/* fdma free running */
@@ -850,20 +887,15 @@
<0x8e77000 0x1000>,
<0x8e78000 0x8000>;
reg-names = "slimcore", "dmem", "peripherals", "imem";
interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
clocks = <&clk_s_c0_flexgen CLK_FDMA>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
};
sti_sasg_codec: sti-sasg-codec {
compatible = "st,stih407-sas-codec";
#sound-dai-cells = <1>;
status = "disabled";
st,syscfg = <&syscfg_core>;
};
sti_uni_player0: sti-uni-player@8d80000 {
@@ -875,7 +907,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
assigned-clock-rates = <50000000>;
reg = <0x8d80000 0x158>;
interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 2 0 1>;
dma-names = "tx";
@@ -891,7 +923,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
assigned-clock-rates = <50000000>;
reg = <0x8d81000 0x158>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 3 0 1>;
dma-names = "tx";
@@ -907,7 +939,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
assigned-clock-rates = <50000000>;
reg = <0x8d82000 0x158>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 4 0 1>;
dma-names = "tx";
@@ -923,7 +955,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
assigned-clock-rates = <50000000>;
reg = <0x8d85000 0x158>;
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 7 0 1>;
dma-names = "tx";
@@ -935,7 +967,7 @@
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d83000 0x158>;
interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 5 0 1>;
dma-names = "rx";
@@ -947,32 +979,22 @@
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d84000 0x158>;
interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 6 0 1>;
dma-names = "rx";
status = "disabled";
};
rc: rc@09518000 {
compatible = "st,comms-irb";
reg = <0x09518000 0x234>;
interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>;
rx-mode = "infrared";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir
&pinctrl_uhf
&pinctrl_tx
&pinctrl_tx_od>;
clocks = <&clk_sysin>;
resets = <&softreset STIH407_IRB_SOFTRESET>;
status = "disabled";
};
socinfo {
compatible = "st,stih407-socinfo";
st,syscfg = <&syscfg_core>;
delta0@0 {
compatible = "st,st-delta";
reg = <0 0>;
clock-names = "delta",
"delta-st231",
"delta-flash-promip";
clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
<&clk_s_c0_flexgen CLK_ST231_DMU>,
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
};
};
};

129
arch/arm/dts/stih407-pinctrl.dtsi
View File

@@ -1,10 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -45,18 +42,18 @@
};
soc {
pin-controller-sbc {
pin-controller-sbc@961f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
reg = <0x0961f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09610000 0x6000>;
pio0: gpio@09610000 {
pio0: gpio@9610000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -64,7 +61,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO0";
};
pio1: gpio@09611000 {
pio1: gpio@9611000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -72,7 +69,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO1";
};
pio2: gpio@09612000 {
pio2: gpio@9612000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -80,7 +77,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO2";
};
pio3: gpio@09613000 {
pio3: gpio@9613000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -88,7 +85,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO3";
};
pio4: gpio@09614000 {
pio4: gpio@9614000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -97,7 +94,7 @@
st,bank-name = "PIO4";
};
pio5: gpio@09615000 {
pio5: gpio@9615000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -369,18 +366,18 @@
};
};
pin-controller-front0 {
pin-controller-front0@920f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0920f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09200000 0x10000>;
pio10: pio@09200000 {
pio10: pio@9200000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -388,7 +385,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO10";
};
pio11: pio@09201000 {
pio11: pio@9201000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -396,7 +393,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO11";
};
pio12: pio@09202000 {
pio12: pio@9202000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -404,7 +401,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO12";
};
pio13: pio@09203000 {
pio13: pio@9203000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -412,7 +409,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO13";
};
pio14: pio@09204000 {
pio14: pio@9204000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -420,7 +417,7 @@
reg = <0x4000 0x100>;
st,bank-name = "PIO14";
};
pio15: pio@09205000 {
pio15: pio@9205000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -428,7 +425,7 @@
reg = <0x5000 0x100>;
st,bank-name = "PIO15";
};
pio16: pio@09206000 {
pio16: pio@9206000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -436,7 +433,7 @@
reg = <0x6000 0x100>;
st,bank-name = "PIO16";
};
pio17: pio@09207000 {
pio17: pio@9207000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -444,7 +441,7 @@
reg = <0x7000 0x100>;
st,bank-name = "PIO17";
};
pio18: pio@09208000 {
pio18: pio@9208000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -452,7 +449,7 @@
reg = <0x8000 0x100>;
st,bank-name = "PIO18";
};
pio19: pio@09209000 {
pio19: pio@9209000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -465,19 +462,16 @@
serial0 {
pinctrl_serial0: serial0-0 {
st,pins {
tx = <&pio17 0 ALT1 OUT>;
rx = <&pio17 1 ALT1 IN>;
tx = <&pio17 0 ALT1 OUT>;
rx = <&pio17 1 ALT1 IN>;
};
};
pinctrl_serial0_rts: serial0_rts {
st,pins {
rts = <&pio17 3 ALT1 OUT>;
};
};
pinctrl_serial0_cts: serial0_cts {
pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
st,pins {
tx = <&pio17 0 ALT1 OUT>;
rx = <&pio17 1 ALT1 IN>;
cts = <&pio17 2 ALT1 IN>;
rts = <&pio17 3 ALT1 OUT>;
};
};
};
@@ -932,18 +926,18 @@
};
};
pin-controller-front1 {
pin-controller-front1@921f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0921f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09210000 0x10000>;
pio20: pio@09210000 {
pio20: pio@9210000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -965,18 +959,18 @@
};
};
pin-controller-rear {
pin-controller-rear@922f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-rear-pinctrl";
st,syscfg = <&syscfg_rear>;
reg = <0x0922f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09220000 0x6000>;
pio30: gpio@09220000 {
pio30: gpio@9220000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -984,7 +978,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO30";
};
pio31: gpio@09221000 {
pio31: gpio@9221000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -992,7 +986,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO31";
};
pio32: gpio@09222000 {
pio32: gpio@9222000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1000,7 +994,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO32";
};
pio33: gpio@09223000 {
pio33: gpio@9223000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1008,7 +1002,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO33";
};
pio34: gpio@09224000 {
pio34: gpio@9224000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1016,7 +1010,7 @@
reg = <0x4000 0x100>;
st,bank-name = "PIO34";
};
pio35: gpio@09225000 {
pio35: gpio@9225000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1026,41 +1020,6 @@
st,retime-pin-mask = <0x7f>;
};
dvo {
pinctrl_dvo: dvo {
st,pins {
hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>;
d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
};
};
};
i2c4 {
pinctrl_i2c4_default: i2c4-default {
st,pins {
@@ -1195,18 +1154,18 @@
};
};
pin-controller-flash {
pin-controller-flash@923f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-flash-pinctrl";
st,syscfg = <&syscfg_flash>;
reg = <0x0923f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09230000 0x3000>;
pio40: gpio@09230000 {
pio40: gpio@9230000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1214,7 +1173,7 @@
reg = <0 0x100>;
st,bank-name = "PIO40";
};
pio41: gpio@09231000 {
pio41: gpio@9231000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1222,7 +1181,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO41";
};
pio42: gpio@09232000 {
pio42: gpio@9232000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

17
arch/arm/dts/stih410-b2260-u-boot.dtsi
View File

@@ -9,8 +9,25 @@
soc {
st_dwc3: dwc3@8f94000 {
dwc3: dwc3@9900000 {
dr_mode = "peripheral";
phys = <&usb2_picophy0>;
};
};
ohci0: usb@9a03c00 {
compatible = "generic-ohci";
};
ehci0: usb@9a03e00 {
compatible = "generic-ehci";
};
ohci1: usb@9a83c00 {
compatible = "generic-ohci";
};
ehci1: usb@9a83e00 {
compatible = "generic-ehci";
};
};
};

142
arch/arm/dts/stih410-b2260.dts
View File

@@ -1,10 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 STMicroelectronics (R&D) Limited.
* Author: Patrice Chotard <patrice.chotard@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "stih410.dtsi"
@@ -15,68 +12,79 @@
compatible = "st,stih410-b2260", "st,stih410";
chosen {
bootargs = "console=ttyAS1,115200";
linux,stdout-path = &uart1;
bootargs = "clk_ignore_unused";
stdout-path = &uart1;
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
aliases {
ttyAS1 = &uart1;
serial1 = &uart1;
ethernet0 = &ethernet0;
};
soc {
leds {
compatible = "gpio-leds";
user_green_1 {
label = "User_green_1";
gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user_green_2 {
label = "User_green_2";
gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user_green_3 {
label = "User_green_3";
gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user_green_4 {
label = "User_green_4";
gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi_yellow {
label = "Wifi_yellow";
gpios = <&pio4 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "wifi-activity";
default-state = "off";
};
bt_blue {
label = "Bluetooth_blue";
gpios = <&pio3 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
leds {
compatible = "gpio-leds";
user_green_1 {
label = "User_green_1";
gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user_green_2 {
label = "User_green_2";
gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user_green_3 {
label = "User_green_3";
gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user_green_4 {
label = "User_green_4";
gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2260";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
/* DAC */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
};
soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
label = "LS-UART0";
pinctrl-names = "default", "no-hw-flowctrl";
pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
pinctrl-1 = <&pinctrl_serial0>;
rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@@ -119,14 +127,14 @@
status = "okay";
};
mmc0: sdhci@09060000 {
mmc0: sdhci@9060000 {
pinctrl-0 = <&pinctrl_sd0>;
bus-width = <4>;
status = "okay";
};
/* high speed expansion connector */
mmc1: sdhci@09080000 {
mmc1: sdhci@9080000 {
status = "okay";
};
@@ -138,11 +146,11 @@
status = "okay";
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
status = "okay";
};
@@ -183,17 +191,17 @@
sti_uni_player0: sti-uni-player@8d80000 {
status = "okay";
};
/* SSC11 to HDMI */
hdmiddc: i2c@9541000 {
/* HDMI V1.3a supports Standard mode only */
clock-frequency = <100000>;
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <1>;
st,i2c-min-sda-pulse-width-us = <5>;
status = "okay";
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
phy_port1: port@9b2a000 {
st,osc-force-ext;
};
@@ -202,25 +210,5 @@
sata1: sata@9b28000 {
status = "okay";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2260";
status = "okay";
simple-audio-card,dai-link@0 {
/* DAC */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
};
};
};

110
arch/arm/dts/stih410-clock.dtsi
View File

@@ -1,12 +1,25 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih410-clks.h>
/ {
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
clock-output-names = "CLK_SYSIN";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -14,27 +27,6 @@
compatible = "st,stih410-clk", "simple-bus";
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
clock-output-names = "CLK_SYSIN";
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* A9 PLL.
*/
@@ -64,35 +56,19 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@090ff000 {
clockgen-a@90ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
@@ -134,7 +110,7 @@
clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@09103000 {
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -208,11 +184,27 @@
"clk-clust-hades",
"clk-hwpe-hades",
"clk-fc-hades";
clock-critical = <CLK_ICN_CPU>,
clock-critical = <CLK_PROC_STFE>,
<CLK_ICN_CPU>,
<CLK_TX_ICN_DMU>,
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
};
};
@@ -229,7 +221,7 @@
"clk-s-d0-fs0-ch3";
};
clockgen-d0@09104000 {
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
@@ -265,13 +257,7 @@
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;

7
arch/arm/dts/stih410-pinctrl.dtsi
View File

@@ -1,16 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
/ {
soc {
pin-controller-rear {
pin-controller-rear@922f080 {
usb0 {
pinctrl_usb0: usb2-0 {

227
arch/arm/dts/stih410.dtsi
View File

@@ -1,67 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
bdisp0 = &bdisp0;
};
cpus {
cpu@0 {
st,syscfg = <&syscfg_core 0x8e0>;
st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
clocks = <&clk_m_a9>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
clocks = <&clk_m_a9>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@1500000000 {
opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
opp-hz = /bits/ 64 <1500000000>;
clock-latency-ns = <10000000>;
opp-suspend;
};
opp@1200000000 {
opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <10000000>;
};
opp@800000000 {
opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <10000000>;
};
opp@400000000 {
opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <10000000>;
};
};
soc {
syscfg_opp: @08a6583c {
compatible = "syscon";
reg = <0x08a6583c 0x8>;
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -71,8 +25,9 @@
status = "disabled";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -83,15 +38,14 @@
};
ohci0: usb@9a03c00 {
compatible = "generic-ohci";
compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
reset-names = "power", "softreset";
phys = <&usb2_picophy1>;
phy-names = "usb";
@@ -99,9 +53,9 @@
};
ehci0: usb@9a03e00 {
compatible = "generic-ehci";
compatible = "st,st-ehci-300x";
reg = <0x9a03e00 0x100>;
interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
@@ -116,15 +70,14 @@
};
ohci1: usb@9a83c00 {
compatible = "generic-ohci";
compatible = "st,st-ohci-300x";
reg = <0x9a83c00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
reset-names = "power", "softreset";
phys = <&usb2_picophy2>;
phy-names = "usb";
@@ -132,9 +85,9 @@
};
ehci1: usb@9a83e00 {
compatible = "generic-ehci";
compatible = "st,st-ehci-300x";
reg = <0x9a83e00 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
@@ -142,18 +95,18 @@
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
reset-names = "power", "softreset";
phys = <&usb2_picophy2>;
phy-names = "usb";
status = "disabled";
};
sti-display-subsystem {
sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
@@ -243,10 +196,10 @@
sti_hdmi: sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
#sound-dai-cells = <0>;
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq";
clock-names = "pix",
"tmds",
@@ -262,7 +215,7 @@
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
hdmi,hpd-gpio = <&pio5 3>;
hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
@@ -283,24 +236,7 @@
<&clk_s_d2_quadfs 1>;
};
sti-dvo@8d00400 {
compatible = "st,stih407-dvo";
status = "disabled";
reg = <0x8d00400 0x200>;
reg-names = "dvo-reg";
clock-names = "dvo_pix",
"dvo",
"main_parent",
"aux_parent";
clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
<&clk_s_d2_flexgen CLK_DVO>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dvo>;
};
sti-hqvdp@9c000000 {
sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
@@ -315,7 +251,7 @@
bdisp0:bdisp@9f10000 {
compatible = "st,stih407-bdisp";
reg = <0x9f10000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "bdisp";
clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
};
@@ -324,8 +260,8 @@
compatible = "st,st-hva";
reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
reg-names = "hva_registers", "hva_esram";
interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
<GIC_SPI 59 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_hva";
clocks = <&clk_s_c0_flexgen CLK_HVA>;
};
@@ -338,66 +274,7 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
g1@8c80000 {
compatible = "st,g1";
reg = <0x8c80000 0x194>;
interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
};
temp0{
compatible = "st,stih407-thermal";
reg = <0x91a0000 0x28>;
clock-names = "thermal";
clocks = <&clk_sysin>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
delta0 {
compatible = "st,delta";
clock-names = "delta", "delta-st231", "delta-flash-promip";
clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
<&clk_s_c0_flexgen CLK_ST231_DMU>,
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
};
h264pp0: h264pp@8c00000 {
compatible = "st,h264pp";
reg = <0x8c00000 0x20000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
clock-names = "clk_h264pp_0";
clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
};
mali: mali@09f00000 {
compatible = "arm,mali-400";
reg = <0x09f00000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
<GIC_SPI 50 IRQ_TYPE_NONE>,
<GIC_SPI 41 IRQ_TYPE_NONE>,
<GIC_SPI 45 IRQ_TYPE_NONE>,
<GIC_SPI 42 IRQ_TYPE_NONE>,
<GIC_SPI 46 IRQ_TYPE_NONE>,
<GIC_SPI 43 IRQ_TYPE_NONE>,
<GIC_SPI 47 IRQ_TYPE_NONE>,
<GIC_SPI 44 IRQ_TYPE_NONE>,
<GIC_SPI 48 IRQ_TYPE_NONE>;
interrupt-names = "IRQGP",
"IRQGPMMU",
"IRQPP0",
"IRQPPMMU0",
"IRQPP1",
"IRQPPMMU1",
"IRQPP2",
"IRQPPMMU2",
"IRQPP3",
"IRQPPMMU3";
clock-names = "gpu-clk";
clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
reset-names = "gpu";
resets = <&softreset STIH407_GPU_SOFTRESET>;
};
delta0 {
delta0@0 {
compatible = "st,st-delta";
clock-names = "delta",
"delta-st231",
@@ -407,51 +284,17 @@
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
};
h264pp0: h264pp@8c00000 {
compatible = "st,h264pp";
reg = <0x8c00000 0x20000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
clock-names = "clk_h264pp_0";
clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
};
mali: mali@09f00000 {
compatible = "arm,mali-400";
reg = <0x09f00000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
<GIC_SPI 50 IRQ_TYPE_NONE>,
<GIC_SPI 41 IRQ_TYPE_NONE>,
<GIC_SPI 45 IRQ_TYPE_NONE>,
<GIC_SPI 42 IRQ_TYPE_NONE>,
<GIC_SPI 46 IRQ_TYPE_NONE>,
<GIC_SPI 43 IRQ_TYPE_NONE>,
<GIC_SPI 47 IRQ_TYPE_NONE>,
<GIC_SPI 44 IRQ_TYPE_NONE>,
<GIC_SPI 48 IRQ_TYPE_NONE>;
interrupt-names = "IRQGP",
"IRQGPMMU",
"IRQPP0",
"IRQPPMMU0",
"IRQPP1",
"IRQPPMMU1",
"IRQPP2",
"IRQPPMMU2",
"IRQPP3",
"IRQPPMMU3";
clock-names = "gpu-clk";
clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
reset-names = "gpu";
resets = <&softreset STIH407_GPU_SOFTRESET>;
};
hva@8c85000{
compatible = "st,st-hva";
reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
reg-names = "hva_registers", "hva_esram";
interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
<GIC_SPI 59 IRQ_TYPE_NONE>;
clock-names = "clk_hva";
clocks = <&clk_s_c0_flexgen CLK_HVA>;
sti-cec@94a087c {
compatible = "st,stih-cec";
reg = <0x94a087c 0x64>;
clocks = <&clk_sysin>;
clock-names = "cec-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cec-irq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cec0_default>;
resets = <&softreset STIH407_LPM_SOFTRESET>;
hdmi-phandle = <&sti_hdmi>;
};
};
};

4
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
View File

@@ -16,7 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
@@ -89,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8

5
arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
View File

@@ -16,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
@@ -90,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8

234
arch/arm/dts/stm32mp157-pinctrl.dtsi
View File

@@ -25,8 +25,7 @@
reg = <0x0 0x400>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
status = "disabled";
};
gpiob: gpio@50003000 {
@@ -37,8 +36,7 @@
reg = <0x1000 0x400>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
status = "disabled";
};
gpioc: gpio@50004000 {
@@ -49,8 +47,7 @@
reg = <0x2000 0x400>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
status = "disabled";
};
gpiod: gpio@50005000 {
@@ -61,8 +58,7 @@
reg = <0x3000 0x400>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
status = "disabled";
};
gpioe: gpio@50006000 {
@@ -73,8 +69,7 @@
reg = <0x4000 0x400>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
status = "disabled";
};
gpiof: gpio@50007000 {
@@ -85,8 +80,7 @@
reg = <0x5000 0x400>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
status = "disabled";
};
gpiog: gpio@50008000 {
@@ -97,8 +91,7 @@
reg = <0x6000 0x400>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
status = "disabled";
};
gpioh: gpio@50009000 {
@@ -109,8 +102,7 @@
reg = <0x7000 0x400>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
status = "disabled";
};
gpioi: gpio@5000a000 {
@@ -121,8 +113,7 @@
reg = <0x8000 0x400>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
status = "disabled";
};
gpioj: gpio@5000b000 {
@@ -133,8 +124,7 @@
reg = <0x9000 0x400>;
clocks = <&rcc GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
status = "disabled";
};
gpiok: gpio@5000c000 {
@@ -145,8 +135,7 @@
reg = <0xa000 0x400>;
clocks = <&rcc GPIOK>;
st,bank-name = "GPIOK";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
status = "disabled";
};
adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
@@ -186,6 +175,47 @@
};
};
dcmi_pins_a: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
<STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
<STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
<STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
<STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
<STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
bias-disable;
};
};
dcmi_sleep_pins_a: dcmi-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
<STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
<STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
<STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
<STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
<STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
};
};
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -308,6 +338,13 @@
};
};
i2c1_pins_sleep_b: i2c1-3 {
pins {
pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
};
};
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@@ -325,16 +362,21 @@
};
};
i2c2_pins_b: i2c2-2 {
i2c2_pins_b1: i2c2-2 {
pins {
pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c2_pins_sleep_b1: i2c2-3 {
pins {
pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
};
};
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
@@ -353,6 +395,25 @@
};
};
i2s2_pins_a: i2s2-0 {
pins {
pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
<STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
<STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
i2s2_pins_sleep_a: i2s2-1 {
pins {
pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
<STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
<STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
};
};
ltdc_pins_a: ltdc-a-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
@@ -547,6 +608,12 @@
};
};
qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
};
};
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
@@ -565,6 +632,16 @@
};
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
<STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
@@ -583,6 +660,89 @@
};
};
qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
<STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
};
};
sai2a_pins_a: sai2a-0 {
pins {
pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
<STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
<STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai2a_sleep_pins_a: sai2a-1 {
pins {
pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
<STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
<STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
};
};
sai2b_pins_a: sai2b-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
<STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
<STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_a: sai2b-1 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
<STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
<STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
<STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
};
};
sai2b_pins_b: sai2b-2 {
pins {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_b: sai2b-3 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
};
sai4a_pins_a: sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai4a_sleep_pins_a: sai4a-1 {
pins {
pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -752,12 +912,6 @@
bias-disable;
};
};
usbotg_hs_pins_a: usbotg_hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
};
pinctrl_z: pin-controller-z@54004000 {
@@ -779,8 +933,22 @@
clocks = <&rcc GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
status = "disabled";
};
i2c2_pins_b2: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c2_pins_sleep_b2: i2c2-1 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
};
};
i2c4_pins_a: i2c4-0 {

14
arch/arm/dts/stm32mp157-u-boot.dtsi
View File

@@ -25,6 +25,11 @@
u-boot,dm-pre-reloc;
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
};
reboot {
u-boot,dm-pre-reloc;
};
@@ -106,6 +111,15 @@
u-boot,dm-pre-reloc;
};
&iwdg2 {
u-boot,dm-pre-reloc;
};
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
u-boot,dm-pre-proper;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

44
arch/arm/dts/stm32mp157a-avenger96.dts
View File

@@ -1,8 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
@@ -10,17 +7,19 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
#include "stm32mp157-pinctrl.dtsi"
#include "stm32mp157xac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
compatible = "st,stm32mp157a-avenger96", "st,stm32mp157";
compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
};
chosen {
@@ -28,6 +27,7 @@
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x40000000>;
};
@@ -109,7 +109,7 @@
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_b>;
pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@@ -151,10 +151,10 @@
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <2>;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -163,17 +163,17 @@
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <2>;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask_reset;
regulator-initial-mode = <8>;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -183,7 +183,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <8>;
regulator-initial-mode = <0>;
};
vdda: ldo1 {
@@ -204,8 +204,8 @@
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <0000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
@@ -233,6 +233,7 @@
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO6 0>;
interrupt-parent = <&pmic>;
regulator-enable-ramp-delay = <300000>;
};
vref_ddr: vref_ddr {
@@ -282,7 +283,10 @@
};
&pwr {
pwr-supply = <&vdd>;
pwr-regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
};
&rng1 {
@@ -294,8 +298,10 @@
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
st,sig-dir;
st,neg-edge;
@@ -325,12 +331,16 @@
};
&uart4 {
/* On Low speed expansion header */
label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
status = "okay";
};
&uart7 {
/* On Low speed expansion header */
label = "LS-UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
status = "okay";

4
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
View File

@@ -17,6 +17,8 @@
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
led {
red {
@@ -187,6 +189,8 @@
};
pins2 {
u-boot,dm-pre-reloc;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};

79
arch/arm/dts/stm32mp157a-dk1.dts
View File

@@ -7,7 +7,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
#include "stm32mp157-pinctrl.dtsi"
#include "stm32mp157xac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -28,6 +28,17 @@
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
};
led {
compatible = "gpio-leds";
blue {
@@ -65,6 +76,47 @@
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_pins_sleep_a>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
hdmi-transmitter@39 {
compatible = "sil,sii9022";
reg = <0x39>;
iovcc-supply = <&v3v3_hdmi>;
cvcc12-supply = <&v1v2_hdmi>;
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiog>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_pins_sleep_a>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
};
};
};
&i2c4 {
pinctrl-names = "default";
@@ -241,8 +293,31 @@
status = "okay";
};
&ltdc {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&sii9022_in>;
};
};
};
&m4_rproc {
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
status = "okay";
};
&pwr {
pwr-supply = <&vdd>;
pwr-regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
};
&rng1 {

6
arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
View File

@@ -4,3 +4,9 @@
*/
#include "stm32mp157a-dk1-u-boot.dtsi"
&i2c1 {
hdmi-transmitter@39 {
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
};
};

23
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
View File

@@ -15,31 +15,22 @@
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
led {
compatible = "gpio-leds";
red {
label = "stm32mp:red:status";
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
green {
label = "stm32mp:green:user";
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
default-state = "on";
};
orange {
label = "stm32mp:orange:status";
gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue {
label = "stm32mp:blue:user";
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
};
@@ -206,5 +197,7 @@
};
pins2 {
u-boot,dm-pre-reloc;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};

29
arch/arm/dts/stm32mp157c-ed1.dts
View File

@@ -6,7 +6,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
#include "stm32mp157-pinctrl.dtsi"
#include "stm32mp157xaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -23,6 +23,17 @@
reg = <0xC0000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpu_reserved: gpu@e8000000 {
reg = <0xe8000000 0x8000000>;
no-map;
};
};
aliases {
serial0 = &uart4;
};
@@ -45,6 +56,11 @@
status = "okay";
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
@@ -201,8 +217,17 @@
status = "okay";
};
&m4_rproc {
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
status = "okay";
};
&pwr {
pwr-supply = <&vdd>;
pwr-regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
};
&rng1 {

5
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
View File

@@ -17,14 +17,9 @@
};
&flash0 {
compatible = "jedec,spi-nor";
u-boot,dm-spl;
};
&flash1 {
compatible = "jedec,spi-nor";
};
&qspi {
u-boot,dm-spl;
};

109
arch/arm/dts/stm32mp157c-ev1.dts
View File

@@ -7,6 +7,7 @@
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
@@ -21,6 +22,51 @@
ethernet0 = &ethernet0;
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
joystick {
compatible = "gpio-keys";
#size-cells = <0>;
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
label = "JoySel";
linux,code = <KEY_ENTER>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
};
button-1 {
label = "JoyDown";
linux,code = <KEY_DOWN>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <1 IRQ_TYPE_EDGE_RISING>;
};
button-2 {
label = "JoyLeft";
linux,code = <KEY_LEFT>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
};
button-3 {
label = "JoyRight";
linux,code = <KEY_RIGHT>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
button-4 {
label = "JoyUp";
linux,code = <KEY_UP>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
};
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
@@ -35,6 +81,23 @@
status = "okay";
};
&dcmi {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmi_pins_a>;
pinctrl-1 = <&dcmi_sleep_pins_a>;
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
@@ -64,6 +127,7 @@
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
power-supply = <&v3v3>;
status = "okay";
port {
@@ -116,6 +180,31 @@
i2c-scl-falling-time-ns = <20>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&ov5640_pins>;
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&v2v8>;
powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
rotation = <180>;
status = "okay";
port {
ov5640_0: endpoint {
remote-endpoint = <&dcmi_0>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
stmfx: stmfx@42 {
compatible = "st,stmfx-0300";
reg = <0x42>;
@@ -130,7 +219,18 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
status = "disabled";
joystick_pins: joystick {
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
drive-push-pull;
bias-pull-down;
};
ov5640_pins: camera {
pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
drive-push-pull;
output-low;
};
};
};
};
@@ -165,14 +265,16 @@
};
&qspi {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -181,6 +283,7 @@
};
flash1: mx66l51235l@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -245,8 +348,6 @@
};
&usbotg_hs {
pinctrl-names = "default";
pinctrl-0 = <&usbotg_hs_pins_a>;
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";

200
arch/arm/dts/stm32mp157c.dtsi
View File

@@ -372,6 +372,17 @@
status = "disabled";
};
i2s2: audio-controller@4000b000 {
compatible = "st,stm32h7-i2s";
#sound-dai-cells = <0>;
reg = <0x4000b000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 39 0x400 0x01>,
<&dmamux1 40 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi3: spi@4000c000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -386,6 +397,17 @@
status = "disabled";
};
i2s3: audio-controller@4000c000 {
compatible = "st,stm32h7-i2s";
#sound-dai-cells = <0>;
reg = <0x4000c000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 61 0x400 0x01>,
<&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spdifrx: audio-controller@4000d000 {
compatible = "st,stm32h7-spdifrx";
#sound-dai-cells = <0>;
@@ -614,6 +636,17 @@
status = "disabled";
};
i2s1: audio-controller@44004000 {
compatible = "st,stm32h7-i2s";
#sound-dai-cells = <0>;
reg = <0x44004000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 37 0x400 0x01>,
<&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi4: spi@44005000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -715,6 +748,100 @@
status = "disabled";
};
sai1: sai@4400a000 {
compatible = "st,stm32h7-sai";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4400a000 0x400>;
reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI1_R>;
status = "disabled";
sai1a: audio-controller@4400a004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 87 0x400 0x01>;
status = "disabled";
};
sai1b: audio-controller@4400a024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 88 0x400 0x01>;
status = "disabled";
};
};
sai2: sai@4400b000 {
compatible = "st,stm32h7-sai";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4400b000 0x400>;
reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI2_R>;
status = "disabled";
sai2a: audio-controller@4400b004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 89 0x400 0x01>;
status = "disabled";
};
sai2b: audio-controller@4400b024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 90 0x400 0x01>;
status = "disabled";
};
};
sai3: sai@4400c000 {
compatible = "st,stm32h7-sai";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4400c000 0x400>;
reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI3_R>;
status = "disabled";
sai3a: audio-controller@4400c004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x04 0x1c>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 113 0x400 0x01>;
status = "disabled";
};
sai3b: audio-controller@4400c024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 114 0x400 0x01>;
status = "disabled";
};
};
dfsdm: dfsdm@4400d000 {
compatible = "st,stm32mp1-dfsdm";
reg = <0x4400d000 0x800>;
@@ -945,6 +1072,18 @@
status = "disabled";
};
dcmi: dcmi@4c006000 {
compatible = "st,stm32-dcmi";
reg = <0x4c006000 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
dmas = <&dmamux1 75 0x400 0x0d>;
dma-names = "tx";
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
@@ -1084,6 +1223,37 @@
status = "disabled";
};
sai4: sai@50027000 {
compatible = "st,stm32h7-sai";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50027000 0x400>;
reg = <0x50027000 0x4>, <0x500273f0 0x10>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI4_R>;
status = "disabled";
sai4a: audio-controller@50027004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x04 0x1c>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 99 0x400 0x01>;
status = "disabled";
};
sai4b: audio-controller@50027024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 100 0x400 0x01>;
status = "disabled";
};
};
dts: thermal@50028000 {
compatible = "st,stm32-thermal";
reg = <0x50028000 0x100>;
@@ -1242,6 +1412,16 @@
status = "disabled";
};
gpu: gpu@59000000 {
compatible = "vivante,gc";
reg = <0x59000000 0x800>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc GPU>, <&rcc GPU_K>;
clock-names = "bus" ,"core";
resets = <&rcc GPU_R>;
status = "disabled";
};
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
@@ -1363,4 +1543,24 @@
status = "disabled";
};
};
mlahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
m4_rproc: m4@10000000 {
compatible = "st,stm32mp1-m4";
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
resets = <&rcc MCU_R>;
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
status = "disabled";
};
};
};

90
arch/arm/dts/stm32mp157xaa-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP_PKG_AA>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@5000b000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@5000c000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
};
pinctrl_z: pin-controller-z@54004000 {
st,package = <STM32MP_PKG_AA>;
gpioz: gpio@54004000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
};
};
};

62
arch/arm/dts/stm32mp157xab-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,62 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP_PKG_AB>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <6>;
gpio-ranges = <&pinctrl 6 86 6>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl 6 102 10>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <2>;
gpio-ranges = <&pinctrl 0 112 2>;
};
};
};
};

78
arch/arm/dts/stm32mp157xac-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,78 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP_PKG_AC>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
pinctrl_z: pin-controller-z@54004000 {
st,package = <STM32MP_PKG_AC>;
gpioz: gpio@54004000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
};
};
};

62
arch/arm/dts/stm32mp157xad-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,62 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP_PKG_AD>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <6>;
gpio-ranges = <&pinctrl 6 86 6>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl 6 102 10>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <2>;
gpio-ranges = <&pinctrl 0 112 2>;
};
};
};
};

14
arch/arm/mach-stm32mp/Kconfig
View File

@@ -16,8 +16,9 @@ config SPL
select SPL_REGMAP
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
select SPL_SPI_LOAD
select SPL_SYSCON
select SPL_WATCHDOG_SUPPORT
select SPL_WATCHDOG_SUPPORT if WATCHDOG
imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
@@ -42,11 +43,15 @@ config TARGET_STM32MP1
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select SYS_ARCH_TIMER
imply BOOTCOUNT_LIMIT
imply BOOTSTAGE
imply CMD_BOOTCOUNT
imply CMD_BOOTSTAGE
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
imply SYSRESET_PSCI if STM32MP1_TRUSTED
imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
help
@@ -109,6 +114,13 @@ config CMD_STM32KEY
fuse public key hash in corresponding fuse used to authenticate
binary.
config PRE_CON_BUF_ADDR
default 0xC02FF000
config PRE_CON_BUF_SZ
default 4096
config BOOTSTAGE_STASH_ADDR
default 0xC3000000

3
arch/arm/mach-stm32mp/Makefile
View File

@@ -12,7 +12,8 @@ obj-y += spl.o
else
obj-y += bsec.o
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
endif
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o

34
arch/arm/mach-stm32mp/bsec.c
View File

@@ -364,15 +364,13 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
offs -= STM32_BSEC_OTP_OFFSET;
shadow = false;
}
if (offs < 0 || (offs % 4) || (size % 4))
return -EINVAL;
otp = offs / sizeof(u32);
if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
dev_err(dev, "wrong value for otp, max value : %i\n",
BSEC_OTP_MAX_VALUE);
return -EINVAL;
}
for (i = otp; i < (otp + nb_otp); i++) {
for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
u32 *addr = &((u32 *)buf)[i - otp];
if (shadow)
@@ -383,7 +381,10 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
if (ret)
break;
}
return ret;
if (ret)
return ret;
else
return (i - otp) * 4;
}
static int stm32mp_bsec_write(struct udevice *dev, int offset,
@@ -400,15 +401,13 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
offs -= STM32_BSEC_OTP_OFFSET;
shadow = false;
}
if (offs < 0 || (offs % 4) || (size % 4))
return -EINVAL;
otp = offs / sizeof(u32);
if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
dev_err(dev, "wrong value for otp, max value : %d\n",
BSEC_OTP_MAX_VALUE);
return -EINVAL;
}
for (i = otp; i < otp + nb_otp; i++) {
for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
u32 *val = &((u32 *)buf)[i - otp];
if (shadow)
@@ -418,7 +417,10 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
if (ret)
break;
}
return ret;
if (ret)
return ret;
else
return (i - otp) * 4;
}
static const struct misc_ops stm32mp_bsec_ops = {

1
arch/arm/mach-stm32mp/include/mach/stm32.h
View File

@@ -94,6 +94,7 @@ enum boot_device {
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
#define TAMP_BOOT_DEBUG_ON BIT(16)
enum forced_boot_mode {
BOOT_NORMAL = 0x00,