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serial: uartlite: Reset RX/TX in init

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Just to be sure that there is no pending data.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2014-01-21 07:29:47 +01:00
parent b44bd2c73c
commit 8c3bd6b596
1 changed files with 13 additions and 1 deletions
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14
drivers/serial/serial_xuartlite.c
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@ -18,10 +18,14 @@
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define ULITE_CONTROL_RST_TX 0x01
#define ULITE_CONTROL_RST_RX 0x02
struct uartlite {
unsigned int rx_fifo;
unsigned int tx_fifo;
unsigned int status;
unsigned int control;
};
static struct uartlite *userial_ports[4] = {
@ -75,8 +79,16 @@ static int uartlite_serial_tstc(const int port)
static int uartlite_serial_init(const int port)
{
if (userial_ports[port])
struct uartlite *regs = userial_ports[port];
if (regs) {
out_be32(&regs->control, 0);
out_be32(&regs->control,
ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
in_be32(&regs->control);
return 0;
}
return -1;
}