net: tsec: Adjust orders to avoid forward declaration of tsec_send()
Adjust static functions in a proper order so that forward declaration of tsec_send() can be avoided. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -21,8 +21,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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static int tsec_send(struct eth_device *dev, void *packet, int length);
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/* Default initializations for TSEC controllers. */
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static struct tsec_info_struct tsec_info[] = {
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@ -221,6 +219,109 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
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/*
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* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* errors
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*/
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static int tsec_send(struct eth_device *dev, void *packet, int length)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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uint16_t status;
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int result = 0;
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int i;
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/* Find an empty buffer descriptor */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx buffers full\n", dev->name);
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return result;
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}
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}
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out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
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out_be16(&priv->txbd[priv->tx_idx].length, length);
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status = in_be16(&priv->txbd[priv->tx_idx].status);
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out_be16(&priv->txbd[priv->tx_idx].status, status |
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
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/* Tell the DMA to go */
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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/* Wait for buffer to be transmitted */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx error\n", dev->name);
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return result;
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}
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}
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priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
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result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
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return result;
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}
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static int tsec_recv(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
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int length = in_be16(&priv->rxbd[priv->rx_idx].length);
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uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
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uchar *packet = net_rx_packets[priv->rx_idx];
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/* Send the packet up if there were no errors */
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if (!(status & RXBD_STATS))
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net_process_received_packet(packet, length - 4);
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else
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printf("Got error %x\n", (status & RXBD_STATS));
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out_be16(&priv->rxbd[priv->rx_idx].length, 0);
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status = RXBD_EMPTY;
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/* Set the wrap bit if this is the last element in the list */
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if ((priv->rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&priv->rxbd[priv->rx_idx].status, status);
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
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}
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if (in_be32(®s->ievent) & IEVENT_BSY) {
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out_be32(®s->ievent, IEVENT_BSY);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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}
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return -1;
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}
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/* Stop the interface */
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static void tsec_halt(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
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!= (IEVENT_GRSC | IEVENT_GTSC))
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;
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clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
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/* Shut down the PHY, as needed */
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phy_shutdown(priv->phydev);
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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/*
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* When MACCFG1[Rx_EN] is enabled during system boot as part
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@ -362,109 +463,6 @@ static void startup_tsec(struct eth_device *dev)
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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}
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/*
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* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* errors
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*/
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static int tsec_send(struct eth_device *dev, void *packet, int length)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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uint16_t status;
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int result = 0;
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int i;
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/* Find an empty buffer descriptor */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx buffers full\n", dev->name);
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return result;
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}
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}
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out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
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out_be16(&priv->txbd[priv->tx_idx].length, length);
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status = in_be16(&priv->txbd[priv->tx_idx].status);
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out_be16(&priv->txbd[priv->tx_idx].status, status |
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
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/* Tell the DMA to go */
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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/* Wait for buffer to be transmitted */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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debug("%s: tsec: tx error\n", dev->name);
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return result;
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}
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}
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priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
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result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
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return result;
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}
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static int tsec_recv(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
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int length = in_be16(&priv->rxbd[priv->rx_idx].length);
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uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
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uchar *packet = net_rx_packets[priv->rx_idx];
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/* Send the packet up if there were no errors */
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if (!(status & RXBD_STATS))
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net_process_received_packet(packet, length - 4);
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else
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printf("Got error %x\n", (status & RXBD_STATS));
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out_be16(&priv->rxbd[priv->rx_idx].length, 0);
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status = RXBD_EMPTY;
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/* Set the wrap bit if this is the last element in the list */
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if ((priv->rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&priv->rxbd[priv->rx_idx].status, status);
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
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}
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if (in_be32(®s->ievent) & IEVENT_BSY) {
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out_be32(®s->ievent, IEVENT_BSY);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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}
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return -1;
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}
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/* Stop the interface */
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static void tsec_halt(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
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!= (IEVENT_GRSC | IEVENT_GTSC))
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;
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clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
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/* Shut down the PHY, as needed */
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phy_shutdown(priv->phydev);
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}
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/*
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* Initializes data structures and registers for the controller,
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* and brings the interface up. Returns the link status, meaning
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