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Cleanup

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This commit is contained in:
wdenk 2004-10-11 23:10:30 +00:00
parent 4cfaf55e5c
commit 8b74bf31fe
9 changed files with 71 additions and 69 deletions
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6
board/nc650/nc650.c
View File

@ -195,8 +195,7 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
@ -209,9 +208,10 @@ static long int dram_size (long int mamr_value, long int *base,
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
void nand_init(void)
{
extern unsigned long nand_probe(unsigned long physadr);
unsigned long totlen = nand_probe(CFG_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif

36
doc/README.SBC8560
View File

@ -1,16 +1,17 @@
The port was tested on Wind River System Sbc8560 board <www.windriver.com>. U-Boot was
installed on the flash memory of the CPU card (no the SODIMM).
The port was tested on Wind River System Sbc8560 board
<www.windriver.com>. U-Boot was installed on the flash memory of the
CPU card (no the SODIMM).
NOTE: Please configure uboot compile to the proper PCI frequency and setup the
appropriate DIP switch settings.
NOTE: Please configure uboot compile to the proper PCI frequency and
setup the appropriate DIP switch settings.
SBC8560 board:
Make sure boards switches are set to their appropriate conditions. Refer
to the Engineering Reference Guide ERG-00300-002. Of particular
importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which select
the on-board FLASH device (Intel 28F128Jx); 2) The settings for the Clock SW9 (33 MHz
or 66 MHz).
Make sure boards switches are set to their appropriate conditions.
Refer to the Engineering Reference Guide ERG-00300-002. Of particular
importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
select the on-board FLASH device (Intel 28F128Jx); 2) The settings
for the Clock SW9 (33 MHz or 66 MHz).
Note: SW9 Settings: 66 MHz
4:1 ratio CCB clocks:SYSCLK
@ -24,20 +25,22 @@ or 66 MHz).
Flashing the FLASH device with the "Wind River ICE":
1) Properly connect and configure the Wind River ICE to the
target JTAG port. This includes running the SBC8560 register script.
Make sure target memory can be read and written.
1) Properly connect and configure the Wind River ICE to the target
JTAG port. This includes running the SBC8560 register script. Make
sure target memory can be read and written.
2) Build the u-boot image:
make distclean
make SBC8560_66_config or SBC8560_33_config
make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
Note: reference is made to the ELDK3.0 compiler. Further, it seems the ppc_8xx compiler is
required for the 85xx (no 85xx designated compiler in ELDK3.0)
Note: reference is made to the ELDK3.0 compiler. Further, it seems
the ppc_8xx compiler is required for the 85xx (no 85xx
designated compiler in ELDK3.0)
3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter).
The bin file should be converted from fffc0000 to ffffffff
3) Convert the uboot (.elf) file to a uboot.bin file (using
visionClick converter). The bin file should be converted from
fffc0000 to ffffffff
4) Setup the Flash Utility (tools menu) for:
@ -52,4 +55,3 @@ Flashing the FLASH device with the "Wind River ICE":
Select the start address from 0 with size of 4000
5) Erase and Program