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Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al

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This removes the following symbols:
   CONFIG_SYS_FSL_DSPI_BE
   CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
   CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
   CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
   CONFIG_SYS_FSL_DSP_DDR_ADDR
   CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
   CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
   CONFIG_SYS_FSL_ERRATUM_A008751
   CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
   CONFIG_SYS_FSL_ESDHC_NUM
   CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
   CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
   CONFIG_SYS_FSL_ISBC_VER
   CONFIG_SYS_FSL_QSPI_LE
   CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
   CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
   CONFIG_SYS_FSL_SRDS_NUM_PLLS
   CONFIG_SYS_FSL_WDOG_BE
   CONFIG_SYS_GP1DIR
   CONFIG_SYS_GP1ODR
   CONFIG_SYS_GP2DIR
   CONFIG_SYS_GP2ODR
   CONFIG_SYS_HALT_BEFOR_RAM_JUMP
   CONFIG_SYS_HMI_BASE
   FSL_QSPI_FLASH_NUM
   FSL_QSPI_FLASH_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-07-31 21:08:24 -04:00
parent 83505a7e9f
commit 8b549c0b23
24 changed files with 0 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
README
View File

@ -330,21 +330,6 @@ The following options need to be configured:
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
CONFIG_SYS_FSL_DSP_DDR_ADDR
This value denotes start offset of DDR memory which is
connected exclusively to the DSP cores.
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
This value denotes start offset of M2 memory
which is directly connected to the DSP core.
CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
This value denotes start offset of M3 memory which is directly
connected to the DSP core.
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL SoC's.
In this mode, a single differential clock is used to supply

5
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -94,8 +94,6 @@
#define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1088A)
@ -218,9 +216,6 @@
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FSL_QMAN_V3

6
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -166,12 +166,6 @@ struct sys_info {
};
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
#define CONFIG_SYS_FSL_FM1_ADDR \

3
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -79,9 +79,6 @@
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A

4
arch/m68k/cpu/mcf52x2/start.S
View File

@ -303,10 +303,6 @@ clear_bss:
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
/******************************************************************************/

4
arch/m68k/cpu/mcf530x/start.S
View File

@ -226,10 +226,6 @@ clear_bss:
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
/******************************************************************************/

10
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -137,19 +137,12 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#elif defined(CONFIG_ARCH_T4240)
@ -202,7 +195,6 @@
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
@ -212,7 +204,6 @@
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
@ -288,7 +279,6 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ISBC_VER 2
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE

13
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1464,7 +1464,6 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
@ -1477,8 +1476,6 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000
#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
@ -2576,20 +2573,10 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#if defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
#endif
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_SCFG_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \

1
include/configs/P2041RDB.h
View File

@ -326,7 +326,6 @@
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*

1
include/configs/T208xQDS.h
View File

@ -434,7 +434,6 @@
*/
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*

1
include/configs/T208xRDB.h
View File

@ -391,7 +391,6 @@
*/
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*

1
include/configs/T4240RDB.h
View File

@ -397,7 +397,6 @@
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif

7
include/configs/bk4r1.h
View File

@ -55,13 +55,6 @@
#define IMX_FEC1_BASE ENET1_BASE_ADDR
/* QSPI Configs*/
#ifdef CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE (SZ_16M)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
#endif
/* boot command, including the target-defined one if any */
/* Extra env settings (including the target-defined ones if any) */

1
include/configs/corenet_ds.h
View File

@ -319,7 +319,6 @@
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*

2
include/configs/eb_cpu5282.h
View File

@ -8,8 +8,6 @@
#ifndef _CONFIG_EB_CPU5282_H_
#define _CONFIG_EB_CPU5282_H_
#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
/*----------------------------------------------------------------------*
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/

5
include/configs/km/km-mpc8309.h
View File

@ -49,11 +49,6 @@
/* GPR_1 */
#define CONFIG_SYS_GPR1 0x50008060
#define CONFIG_SYS_GP1DIR 0x00000000
#define CONFIG_SYS_GP1ODR 0x00000000
#define CONFIG_SYS_GP2DIR 0xFF000000
#define CONFIG_SYS_GP2ODR 0x00000000
#define CONFIG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_PZ_MAXZ | \

4
include/configs/ls1021atsn.h
View File

@ -75,10 +75,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* QSPI */
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
/* PCIe */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

1
include/configs/m53menlo.h
View File

@ -38,7 +38,6 @@
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#endif
/*

1
include/configs/mx51evk.h
View File

@ -35,7 +35,6 @@
* MMC Configs
* */
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1

1
include/configs/mx53cx9020.h
View File

@ -18,7 +18,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* bootz: zImage/initrd.img support */

1
include/configs/mx53loco.h
View File

@ -15,7 +15,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1

1
include/configs/socrates.h
View File

@ -103,7 +103,6 @@
/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1

1
include/configs/usbarmory.h
View File

@ -21,7 +21,6 @@
/* SD/MMC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB */
#define CONFIG_MXC_USB_PORT 1

1
include/configs/vf610twr.h
View File

@ -21,7 +21,6 @@
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_FEC_MXC_PHYADDR 0