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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse Source 
fsl-qoriq: Fixes and updates on fsl-layerscape
mpc85xx: fixes and code cleanup
This commit is contained in:
Tom Rini 2022-04-27 09:19:41 -04:00
commit 8b2b125e95
85 changed files with 610 additions and 421 deletions
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1
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -7,7 +7,6 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008997 if USB
select SYS_FSL_ERRATUM_A009007 if USB
select SYS_FSL_ERRATUM_A009008 if USB
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798 if USB

34
arch/arm/cpu/armv8/Kconfig
View File

@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION
config SEC_FIRMWARE_ARMV8_PSCI
bool "PSCI implementation in secure monitor firmware"
depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
depends on ARMV8_PSCI=n
help
This config enables the ARMv8 PSCI implementation in secure monitor
firmware. This is a private PSCI implementation and different from
@ -131,6 +132,9 @@ config PSCI_RESET
Select Y here to make use of PSCI calls for system reset
config SYS_HAS_ARMV8_SECURE_BASE
bool
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
help
@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
A value 0 or no definition of it works for single cluster system.
System with multi-cluster should difine their own exact value.
config ARMV8_PSCI_RELOCATE
bool "Relocate PSCI code"
depends on ARMV8_PSCI
depends on SYS_HAS_ARMV8_SECURE_BASE
help
Relocate PSCI code, for example to a secure memory on the SoC. If not
set, the PSCI sections are placed together with the u-boot and the
regions will be marked as reserved before linux is started.
config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
depends on ARMV8_PSCI_RELOCATE
default 0x18000000 if ARCH_LS1028A
help
Address for placing the PSCI text, data and stack sections.
config ARMV8_EA_EL3_FIRST
bool "External aborts and SError interrupt exception are taken in EL3"
help
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
if SYS_HAS_ARMV8_SECURE_BASE
config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
depends on ARMV8_PSCI
help
Address for placing the PSCI text, data and stack sections.
If not defined, the PSCI sections are placed together with the u-boot
but platform can choose to place PSCI code image separately in other
places such as some secure RAM built-in SOC etc.
endif
endif

9
arch/arm/cpu/armv8/cpu-dt.c
View File

@ -8,9 +8,9 @@
#include <asm/psci.h>
#include <asm/system.h>
#include <asm/armv8/sec_firmware.h>
#include <linux/libfdt.h>
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
int psci_update_dt(void *fdt)
__weak int psci_update_dt(void *fdt)
{
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
@ -18,8 +18,10 @@ int psci_update_dt(void *fdt)
* number to support detecting PSCI dynamically and then switching
* the SMP boot method between PSCI and spin-table.
*/
if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) &&
sec_firmware_support_psci_version() == PSCI_INVALID_VER)
return 0;
fdt_psci(fdt);
#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
@ -30,4 +32,3 @@ int psci_update_dt(void *fdt)
return 0;
}
#endif

3
arch/arm/cpu/armv8/cpu.c
View File

@ -79,6 +79,9 @@ static void relocate_secure_section(void)
void armv8_setup_psci(void)
{
if (current_el() != 3)
return;
relocate_secure_section();
secure_ram_addr(psci_setup_vectors)();
secure_ram_addr(psci_arch_init)();

5
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -55,6 +55,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select RESV_RAM if GIC_V3_ITS
select SYS_HAS_ARMV8_SECURE_BASE
imply PANIC_HANG
config ARCH_LS1043A
@ -74,7 +75,6 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
@ -91,6 +91,7 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
select SYS_HAS_ARMV8_SECURE_BASE
imply CMD_PCI
imply ID_EEPROM
@ -112,7 +113,6 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
@ -335,6 +335,7 @@ menu "Layerscape architecture"
config FSL_LAYERSCAPE
bool
select ARM_SMCCC
config HAS_FEATURE_GIC64K_ALIGN
bool

49
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <linux/arm-smccc.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <fm_eth.h>
@ -768,7 +769,7 @@ enum boot_src __get_boot_src(u32 porsr1)
enum boot_src get_boot_src(void)
{
struct pt_regs regs;
struct arm_smccc_res res;
u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3)
@ -778,11 +779,9 @@ enum boot_src get_boot_src(void)
#endif
if (current_el() == 2) {
regs.regs[0] = SIP_SVC_RCW;
smc_call(&regs);
if (!regs.regs[0])
porsr1 = regs.regs[1];
arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res);
if (!res.a0)
porsr1 = res.a1;
}
if (current_el() == 3 || !porsr1) {
@ -1081,9 +1080,9 @@ static void config_core_prefetch(void)
char *buf = NULL;
char buffer[HWCONFIG_BUFFER_SIZE];
const char *prefetch_arg = NULL;
struct arm_smccc_res res;
size_t arglen;
unsigned int mask;
struct pt_regs regs;
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
@ -1101,11 +1100,10 @@ static void config_core_prefetch(void)
}
#define SIP_PREFETCH_DISABLE_64 0xC200FF13
regs.regs[0] = SIP_PREFETCH_DISABLE_64;
regs.regs[1] = mask;
smc_call(&regs);
arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0,
&res);
if (regs.regs[0])
if (res.a0)
printf("Prefetch disable config failed for mask ");
else
printf("Prefetch disable config passed for mask ");
@ -1345,25 +1343,20 @@ phys_size_t get_effective_memsize(void)
#ifdef CONFIG_TFABOOT
phys_size_t tfa_get_dram_size(void)
{
struct pt_regs regs;
phys_size_t dram_size = 0;
struct arm_smccc_res res;
regs.regs[0] = SMC_DRAM_BANK_INFO;
regs.regs[1] = -1;
smc_call(&regs);
if (regs.regs[0])
arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res);
if (res.a0)
return 0;
dram_size = regs.regs[1];
return dram_size;
return res.a1;
}
static int tfa_dram_init_banksize(void)
{
int i = 0, ret = 0;
struct pt_regs regs;
phys_size_t dram_size = tfa_get_dram_size();
struct arm_smccc_res res;
debug("dram_size %llx\n", dram_size);
@ -1371,19 +1364,15 @@ static int tfa_dram_init_banksize(void)
return -EINVAL;
do {
regs.regs[0] = SMC_DRAM_BANK_INFO;
regs.regs[1] = i;
smc_call(&regs);
if (regs.regs[0]) {
arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res);
if (res.a0) {
ret = -EINVAL;
break;
}
debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
regs.regs[2]);
gd->bd->bi_dram[i].start = regs.regs[1];
gd->bd->bi_dram[i].size = regs.regs[2];
debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
gd->bd->bi_dram[i].start = res.a1;
gd->bd->bi_dram[i].size = res.a2;
dram_size -= gd->bd->bi_dram[i].size;

10
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View File

@ -147,10 +147,14 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
cfg >>= sd_prctl_shift;
cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (cfg == 0) {
printf("SERDES%d is disabled\n", sd + 1);
} else {
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
}
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);

4
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019 NXP
* Copyright 2019-2022 NXP
*
* Extracted from armv8/start.S
*/
@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err)
ldr x0, =DCSR_DCFG_MBEESR2
str w1, [x0]
ret
ENDPROC(fsl_ocram_init)
ENDPROC(fsl_ocram_clear_ecc_err)
#endif
#ifdef CONFIG_FSL_LSCH3

11
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -302,6 +302,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
u64 boot_addr;
u64 *table = get_spin_tbl_addr();
int pos;
int ret;
boot_addr = simple_strtoull(argv[0], NULL, 16);
@ -326,16 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[])
asm volatile("sev");
} else {
/* Use PSCI to kick the core */
struct pt_regs regs;
printf("begin to kick cpu core #%d to address %llx\n",
nr, boot_addr);
regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
regs.regs[1] = nr;
regs.regs[2] = boot_addr;
regs.regs[3] = 0;
smc_call(&regs);
if (regs.regs[0])
ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0);
if (ret)
return -1;
}

3
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -206,6 +206,9 @@ static void erratum_a008997(void)
static void erratum_a009007(void)
{
if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
return;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
defined(CONFIG_ARCH_LS1012A)
void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;

19
arch/arm/cpu/armv8/sec_firmware.c
View File

@ -13,6 +13,7 @@
#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/kernel.h>
#include <linux/arm-smccc.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/types.h>
@ -374,29 +375,25 @@ bool sec_firmware_support_hwrng(void)
*/
int sec_firmware_get_random(uint8_t *rand, int bytes)
{
struct arm_smccc_res res;
unsigned long long num;
struct pt_regs regs;
int param1;
if (!bytes || bytes > 8) {
printf("Max Random bytes genration supported is 8\n");
return -1;
}
#define SIP_RNG_64 0xC200FF11
regs.regs[0] = SIP_RNG_64;
if (bytes <= 4)
param1 = 0;
else
param1 = 1;
regs.regs[1] = param1;
smc_call(&regs);
if (regs.regs[0])
#define SIP_RNG_64 0xC200FF11
arm_smccc_smc(SIP_RNG_64, param1, 0, 0, 0, 0, 0, 0, &res);
if (res.a0)
return -1;
num = regs.regs[1];
num = res.a1;
memcpy(rand, &num, bytes);
return 0;
@ -473,8 +470,8 @@ int fdt_fixup_kaslr(void *fdt)
return 0;
}
ret = sec_firmware_get_random(rand, 8);
if (ret < 0) {
err = sec_firmware_get_random(rand, 8);
if (err < 0) {
printf("WARNING: No random number to set kaslr-seed\n");
return 0;
}

4
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -143,8 +143,10 @@ int checkcpu (void)
printf("Core: ");
switch(ver) {
case PVR_VER_E500_V1:
puts("e500v1");
break;
case PVR_VER_E500_V2:
puts("e500");
puts("e500v2");
break;
case PVR_VER_E500MC:
puts("e500mc");

2
arch/powerpc/cpu/mpc85xx/resetvec.S
View File

@ -1,2 +1,2 @@
.section .resetvec,"ax"
b _start_e500
b _start

13
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -46,7 +46,6 @@
GOT_ENTRY(_FIXUP_TABLE_)
#ifndef MINIMAL_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
@ -71,9 +70,9 @@
*/
.section .bootpg,"ax"
.globl _start_e500
.globl _start
_start_e500:
_start:
/* Enable debug exception */
li r1,MSR_DE
mtmsr r1
@ -1128,16 +1127,12 @@ switch_as:
/*--------------------------------------------------------------*/
lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
addi r3,r3,_start_cont - _start
addi r3,r3,_start_cont - _start_cont
mtlr r3
blr
#endif
.text
.globl _start
_start:
.long 0x27051956 /* U-BOOT Magic Number */
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
@ -1604,7 +1599,7 @@ relocate_code:
* initialization, now running from RAM.
*/
addi r0,r10,in_ram - _start
addi r0,r10,in_ram - _start_cont
/*
* As IVPR is going to point RAM address,

97
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
View File

@ -1,97 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*/
#include "config.h"
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.text :
{
*(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
_end = .;
.bootpg ADDR(.text) - 0x1000 :
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss*)
*(.bss*)
*(COMMON)
} :bss
. = ALIGN(4);
__bss_end = . ;
PROVIDE (end = .);
}

68
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
View File

@ -1,68 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de
*
* Copyright 2009 Freescale Semiconductor, Inc.
*/
#include "config.h"
OUTPUT_ARCH(powerpc)
SECTIONS
{
. = 0xfff00000;
.text : {
*(.text*)
}
_etext = .;
.reloc : {
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
. = ALIGN(8);
.data : {
*(.rodata*)
*(.data*)
*(.sdata*)
}
_edata = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(8);
__init_begin = .;
__init_end = .;
_end = .;
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
start.o (.bootpg)
}
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
#else
#error unknown NAND controller
#endif
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
__bss_start = .;
.bss : {
*(.sbss*)
*(.bss*)
}
__bss_end = .;
}
ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");

20
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
View File

@ -18,6 +18,13 @@ PHDRS
#endif
SECTIONS
{
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg IMAGE_TEXT_BASE - 0x1000 :
{
KEEP(*(.bootpg))
} :text = 0xffff
#endif
. = IMAGE_TEXT_BASE;
.text : {
*(.text*)
@ -67,18 +74,13 @@ SECTIONS
__bss_end = .;
#endif
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg ADDR(.text) - 0x1000 :
{
KEEP(*(.bootpg))
} :text = 0xffff
#else
/* For nor and nand is needed the SPL with section .resetvec */
#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
#ifndef BOOT_PAGE_OFFSET
#define BOOT_PAGE_OFFSET 0x1000
#endif
.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
.bootpg IMAGE_TEXT_BASE + BOOT_PAGE_OFFSET :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
}
@ -90,7 +92,7 @@ SECTIONS
#else
#error unknown NAND controller
#endif
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
#endif

27
arch/powerpc/cpu/mpc85xx/u-boot.lds
View File

@ -11,12 +11,8 @@
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
OUTPUT_ARCH(powerpc)
ENTRY(_start_e500)
ENTRY(_start)
PHDRS
{
@ -27,8 +23,13 @@ PHDRS
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg CONFIG_SYS_TEXT_BASE - 0x1000 :
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = CONFIG_SYS_TEXT_BASE;
#endif
.text :
{
*(.text*)
@ -75,21 +76,15 @@ SECTIONS
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
. = ALIGN(4);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
. = ALIGN(4);
__init_end = .;
_end = .;
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg ADDR(.text) - 0x1000 :
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
#else
#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)

1
arch/powerpc/dts/fsl/p2020si-post.dtsi Symbolic link
View File

@ -0,0 +1 @@
../p2020-post.dtsi

1
arch/powerpc/dts/fsl/p2020si-pre.dtsi Symbolic link
View File

@ -0,0 +1 @@
../p2020.dtsi

2
arch/powerpc/dts/mpc8548-post.dtsi
View File

@ -27,7 +27,7 @@
};
&pcie {
compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;

2
arch/powerpc/dts/p1020-post.dtsi
View File

@ -37,7 +37,7 @@
last-interrupt-source = <255>;
};
esdhc: esdhc@2e000 {
esdhc: sdhc@2e000 {
compatible = "fsl,esdhc";
reg = <0x2e000 0x1000>;
/* Filled in by U-Boot */

100
arch/powerpc/dts/p2020-post.dtsi
View File

@ -14,8 +14,11 @@
bus-frequency = <0x0>;
usb@22000 {
compatible = "fsl-usb2-dr";
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
reg = <0x22000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <28 0x2 0 0>;
phy_type = "ulpi";
};
@ -31,9 +34,10 @@
last-interrupt-source = <255>;
};
esdhc: esdhc@2e000 {
compatible = "fsl,esdhc";
esdhc: sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2 0 0>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
@ -43,44 +47,126 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
interrupts = < 0x3b 0x02 0x00 0x00 >;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-gpio-0.dtsi"
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; /* 32 bytes */
cache-size = <0x80000>; /* L2,512K */
interrupts = <16 2 0 0>;
};
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-timer-0.dtsi"
ptp_clock@24e00 {
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
};
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
&pci2 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
interrupts = <24 2 0 0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <24 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
>;
};
};
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
interrupts = <25 2 0 0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
>;
};
};
/* PCIe controller base address 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
interrupts = <26 2 0 0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <26 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
>;
};
};
&lbc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
interrupts = <19 2 0 0>;
};

2
arch/powerpc/dts/p2020.dtsi
View File

@ -22,10 +22,12 @@
cpu0: PowerPC,P2020@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu1: PowerPC,P2020@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
};

5
arch/powerpc/dts/p2020rdb-pc.dts
View File

@ -15,6 +15,10 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
@ -45,7 +49,6 @@
/include/ "p2020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;

5
arch/powerpc/dts/p2020rdb-pc_36b.dts
View File

@ -15,6 +15,10 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
@ -45,7 +49,6 @@
/include/ "p2020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;

51
arch/powerpc/dts/pq3-duart-0.dtsi Normal file
View File

@ -0,0 +1,51 @@
/*
* PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2 0 0>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2 0 0>;
};

39
arch/powerpc/dts/pq3-etsec1-timer-0.dtsi Normal file
View File

@ -0,0 +1,39 @@
/*
* PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
ptp_clock@24e00 {
compatible = "fsl,etsec-ptp";
reg = <0x24e00 0xb0>;
interrupts = <68 2 0 0 69 2 0 0>;
};

41
arch/powerpc/dts/pq3-gpio-0.dtsi Normal file
View File

@ -0,0 +1,41 @@
/*
* PQ3 GPIO device tree stub [ controller @ offset 0xfc00 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
gpio-controller@fc00 {
#gpio-cells = <2>;
compatible = "fsl,pq3-gpio";
reg = <0xfc00 0x100>;
interrupts = <47 0x2 0 0>;
gpio-controller;
};

1
arch/powerpc/dts/pq3-i2c-0.dtsi
View File

@ -12,4 +12,5 @@ i2c@3000 {
u-boot,dm-pre-reloc;
reg = <0x3000 0x100>;
interrupts = <43 2 0 0>;
dfsrr;
};

1
arch/powerpc/dts/pq3-i2c-1.dtsi
View File

@ -12,4 +12,5 @@ i2c@3100 {
u-boot,dm-pre-reloc;
reg = <0x3100 0x100>;
interrupts = <43 2 0 0>;
dfsrr;
};

8
board/freescale/ls1043ardb/Kconfig
View File

@ -13,14 +13,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1043ardb"
config SYS_HAS_ARMV8_SECURE_BASE
bool "Enable secure address for PSCI image"
depends on ARMV8_PSCI
help
PSCI image can be re-located to secure RAM.
If enabled, please also define the value for ARMV8_SECURE_BASE,
for LS1043ARDB, it could be some address in OCRAM.
if FSL_LS_PPA
config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"

4
board/freescale/ls1046afrwy/MAINTAINERS
View File

@ -5,8 +5,4 @@ F: board/freescale/ls1046afrwy/
F: board/freescale/ls1046afrwy/ls1046afrwy.c
F: include/configs/ls1046afrwy.h
F: configs/ls1046afrwy_tfa_defconfig
LS1046AFRWY_SECURE_BOOT BOARD
M: Manish Tomar <manish.tomar@nxp.com>
S: Maintained
F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig

16
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -147,8 +147,10 @@ int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
#ifndef SDHC_WP_IS_GPIO
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP);
#endif
clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
@ -191,7 +193,7 @@ int checkboard(void)
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return -ENXIO;
return 0; /* Don't want to hang() on this error */
}
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
@ -216,6 +218,10 @@ int checkboard(void)
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
#ifdef __SW_BOOT_SD2
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
puts("sd");
#endif
#ifdef __SW_BOOT_SPI
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
puts("spi");
@ -353,9 +359,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
int err;
#endif
#endif
ft_cpu_setup(blob, bd);
@ -374,6 +380,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
@ -395,7 +402,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);

4
board/freescale/p1_p2_rdb_pc/spl.c
View File

@ -83,12 +83,15 @@ void board_init_r(gd_t *gd, ulong dest_addr)
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_ENV_SUPPORT
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
#ifdef CONFIG_SPL_ENV_SUPPORT
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@ -98,6 +101,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
#else
env_relocate();
#endif
#endif
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_init_all();

6
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
/* **M** - 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#endif /* RAMBOOT/SPL */

2
board/kontron/sl28/Makefile
View File

@ -6,6 +6,8 @@ endif
obj-y += common.o ddr.o
obj-$(CONFIG_ARMV8_PSCI) += psci.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_SPL_ATF) += spl_atf.o

42
board/kontron/sl28/psci.c Normal file
View File

@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/secure.h>
#include <asm/psci.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/system.h>
#define GPIO2_GPDIR 0x2310000
#define GPIO2_GPDAT 0x2310008
#define RSTCR 0x1e60000
#define RESET_REQ BIT(1)
u32 __secure psci_version(void)
{
return ARM_PSCI_VER_0_2;
}
void __secure psci_system_reset(void)
{
writel(RESET_REQ, RSTCR);
while (1)
wfi();
}
void __secure psci_system_off(void)
{
int i;
writel(0x02000000, GPIO2_GPDIR);
writel(0, GPIO2_GPDAT);
/* make sure the management controller has sampled the input */
for (i = 0; i < (1 << 11); i++)
asm("nop");
writel(RESET_REQ, RSTCR);
while (1)
wfi();
}

2
common/hwconfig.c
View File

@ -83,7 +83,9 @@ static const char *__hwconfig(const char *opt, size_t *arglen,
"and before environment is ready\n");
return NULL;
}
#if CONFIG_IS_ENABLED(ENV_SUPPORT)
env_hwconfig = env_get("hwconfig");
#endif
}
if (env_hwconfig) {

2
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -16,8 +16,6 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y

2
configs/P1010RDB-PA_NAND_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y

2
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -16,8 +16,6 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y

2
configs/P1010RDB-PB_NAND_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y

2
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -16,8 +16,6 @@ CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/P1020RDB-PC_NAND_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/P1020RDB-PD_NAND_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -16,8 +16,6 @@ CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/P2020RDB-PC_NAND_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/T1024RDB_NAND_defconfig
View File

@ -14,8 +14,6 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/T1042D4RDB_NAND_defconfig
View File

@ -11,8 +11,6 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/T2080QDS_NAND_defconfig
View File

@ -18,8 +18,6 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/T2080RDB_NAND_defconfig
View File

@ -17,8 +17,6 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/T2080RDB_revD_NAND_defconfig
View File

@ -18,8 +18,6 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_T2080RDB_REV_D=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

2
configs/kontron_sl28_defconfig
View File

@ -20,6 +20,8 @@ CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
CONFIG_ARMV8_PSCI_RELOCATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y

4
doc/README.mpc85xx
View File

@ -45,7 +45,7 @@ Note: Sequence number is in order of execution
A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
1) TLB entry to overcome e500 v1/v2 debug restriction
Location : Label "_start_e500"
Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
Properties : 256K, AS0, I, IPROT
@ -91,7 +91,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
1) TLB entry to overcome e500 v1/v2 debug restriction
Location : Label "_start_e500"
Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
#if defined(CONFIG_NXP_ESBC)
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW

2
drivers/cpu/Kconfig
View File

@ -9,7 +9,7 @@ config CPU
config CPU_MPC83XX
bool "Enable MPC83xx CPU driver"
depends on CPU
depends on CPU && MPC83xx
select CLK_MPC83XX
help
Support CPU cores for SoCs of the MPC83xx series.

4
drivers/ddr/fsl/options.c
View File

@ -761,7 +761,9 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
#if CONFIG_IS_ENABLED(ENV_SUPPORT)
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
#endif
buf[0] = '\0';
#if defined(CONFIG_SYS_FSL_DDR3) || \
@ -1408,7 +1410,9 @@ int fsl_use_spd(void)
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
#if CONFIG_IS_ENABLED(ENV_SUPPORT)
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
#endif
buf[0] = '\0';
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */

2
drivers/mmc/fsl_esdhc.c
View File

@ -724,7 +724,7 @@ static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
setbits_be32(&sysconf->sdhccr, 0x02000000);
#else
esdhc_write32(&regs->esdhcctl, 0x00000040);
esdhc_write32(&regs->esdhcctl, ESDHCCTL_SNOOP);
#endif
}

67
drivers/mmc/fsl_esdhc_spl.c
View File

@ -14,11 +14,12 @@
* on SDCard, so we must read the MBR to get the start address and code
* length of the u-boot image, then calculate the address of the env.
*/
#define ESDHC_BOOT_SIGNATURE_OFF 0x40
#define ESDHC_BOOT_SIGNATURE 0x424f4f54
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
#define MBRDBR_BOOT_SIG_55 0x1fe
#define MBRDBR_BOOT_SIG_AA 0x1ff
#define CONFIG_CFG_DATA_SECTOR 0
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
@ -60,8 +61,13 @@ void __noreturn mmc_boot(void)
#ifndef CONFIG_FSL_CORENET
uchar *tmp_buf;
u32 blklen;
u32 blk_off;
uchar val;
#ifndef CONFIG_SPL_FSL_PBL
u32 val32;
#endif
uint i, byte_num;
u32 sector;
#endif
u32 offset, code_len;
struct mmc *mmc;
@ -72,58 +78,83 @@ void __noreturn mmc_boot(void)
hang();
}
if (mmc_init(mmc)) {
puts("spl: mmc device init failed!\n");
hang();
}
#ifdef CONFIG_FSL_CORENET
offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
#else
blklen = mmc->read_bl_len;
if (blklen < 512)
blklen = 512;
tmp_buf = malloc(blklen);
if (!tmp_buf) {
puts("spl: malloc memory failed!!\n");
hang();
}
sector = 0;
again:
memset(tmp_buf, 0, blklen);
/*
* Read source addr from sd card
*/
err = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
blk_start = (sector * 512) / mmc->read_bl_len;
blk_off = (sector * 512) % mmc->read_bl_len;
blk_cnt = DIV_ROUND_UP(512, mmc->read_bl_len);
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, tmp_buf);
if (err != 1) {
puts("spl: mmc read failed!!\n");
hang();
}
val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
#ifdef CONFIG_SPL_FSL_PBL
val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_55);
if (0x55 != val) {
puts("spl: mmc signature is not valid!!\n");
puts("spl: mmc MBR/DBR signature is not valid!!\n");
hang();
}
val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_AA);
if (0xAA != val) {
puts("spl: mmc signature is not valid!!\n");
puts("spl: mmc MBR/DBR signature is not valid!!\n");
hang();
}
#else
/*
* Booting from On-Chip ROM (eSDHC or eSPI), Document Number: AN3659, Rev. 2, 06/2012.
* Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022)
* require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all.
*/
byte_num = 4;
val32 = 0;
for (i = 0; i < byte_num; i++) {
val = *(tmp_buf + blk_off + ESDHC_BOOT_SIGNATURE_OFF + i);
val32 = (val32 << 8) + val;
}
if (val32 != ESDHC_BOOT_SIGNATURE) {
/* BOOT signature may be on the first 24 sectors (each being 512 bytes) */
if (++sector < 24)
goto again;
puts("spl: mmc BOOT signature is not valid!!\n");
hang();
}
#endif
byte_num = 4;
offset = 0;
for (i = 0; i < byte_num; i++) {
val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i);
val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
offset = (offset << 8) + val;
}
offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
/* Get the code size from offset 0x48 */
byte_num = 4;
code_len = 0;
for (i = 0; i < byte_num; i++) {
val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i);
code_len = (code_len << 8) + val;
}
code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS;
#endif
/*
* Load U-Boot image from mmc into RAM
*/
#endif
code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,

2
drivers/mmc/mmc.c
View File

@ -132,7 +132,7 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
}
#endif
#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
const char *mmc_mode_name(enum bus_mode mode)
{
static const char *const names[] = {

4
drivers/mtd/nand/raw/Kconfig
View File

@ -158,6 +158,10 @@ config NAND_FSL_ELBC
help
Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
config NAND_FSL_ELBC_DT
bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
depends on NAND_FSL_ELBC
config NAND_FSL_IFC
bool "Support Freescale Integrated Flash Controller NAND driver"
select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT

105
drivers/mtd/nand/raw/fsl_elbc_nand.c
View File

@ -20,6 +20,10 @@
#include <asm/io.h>
#include <linux/errno.h>
#ifdef CONFIG_NAND_FSL_ELBC_DT
#include <dm/read.h>
#endif
#ifdef VERBOSE_DEBUG
#define DEBUG_ELBC
#define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
@ -312,6 +316,14 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
fsl_elbc_run_command(mtd);
return;
/* RNDOUT moves the pointer inside the page */
case NAND_CMD_RNDOUT:
vdbg("fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n",
column);
ctrl->index = column;
return;
/* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB:
vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
@ -656,7 +668,7 @@ static void fsl_elbc_ctrl_init(void)
elbc_ctrl->addr = NULL;
}
static int fsl_elbc_chip_init(int devnum, u8 *addr)
static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node)
{
struct mtd_info *mtd;
struct nand_chip *nand;
@ -704,6 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
elbc_ctrl->chips[priv->bank] = priv;
/* fill in nand_chip structure */
nand->flash_node = flash_node;
/* set up function call table */
nand->read_byte = fsl_elbc_read_byte;
nand->write_buf = fsl_elbc_write_buf;
@ -723,37 +737,40 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
nand->controller = &elbc_ctrl->controller;
nand_set_controller_data(nand, priv);
nand->ecc.read_page = fsl_elbc_read_page;
nand->ecc.write_page = fsl_elbc_write_page;
nand->ecc.write_subpage = fsl_elbc_write_subpage;
priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
/* If CS Base Register selects full hardware ECC then use it */
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
&fsl_elbc_oob_sp_eccm1 :
&fsl_elbc_oob_sp_eccm0;
nand->ecc.size = 512;
nand->ecc.bytes = 3;
nand->ecc.steps = 1;
nand->ecc.strength = 1;
} else {
/* otherwise fall back to software ECC */
#if defined(CONFIG_NAND_ECC_BCH)
nand->ecc.mode = NAND_ECC_SOFT_BCH;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif
}
ret = nand_scan_ident(mtd, 1, NULL);
if (ret)
return ret;
/* If nand_scan_ident() has not selected ecc.mode, do it now */
if (nand->ecc.mode == NAND_ECC_NONE) {
/* If CS Base Register selects full hardware ECC then use it */
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
&fsl_elbc_oob_sp_eccm1 :
&fsl_elbc_oob_sp_eccm0;
nand->ecc.size = 512;
nand->ecc.bytes = 3;
nand->ecc.steps = 1;
nand->ecc.strength = 1;
} else {
/* otherwise fall back to software ECC */
#if defined(CONFIG_NAND_ECC_BCH)
nand->ecc.mode = NAND_ECC_SOFT_BCH;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif
}
}
if (nand->ecc.mode == NAND_ECC_HW) {
nand->ecc.read_page = fsl_elbc_read_page;
nand->ecc.write_page = fsl_elbc_write_page;
nand->ecc.write_subpage = fsl_elbc_write_subpage;
}
/* Large-page-specific setup */
if (mtd->writesize == 2048) {
setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
@ -771,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
priv->fmr |= FMR_ECCM;
/* adjust ecc setup if needed */
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
if (nand->ecc.mode == NAND_ECC_HW) {
nand->ecc.steps = 4;
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
&fsl_elbc_oob_lp_eccm1 :
@ -796,6 +813,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
return 0;
}
#ifndef CONFIG_NAND_FSL_ELBC_DT
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
@ -808,5 +827,35 @@ void board_nand_init(void)
int i;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
fsl_elbc_chip_init(i, (u8 *)base_address[i]);
fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null());
}
#else
static int fsl_elbc_nand_probe(struct udevice *dev)
{
return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev));
}
static const struct udevice_id fsl_elbc_nand_dt_ids[] = {
{ .compatible = "fsl,elbc-fcm-nand", },
{}
};
U_BOOT_DRIVER(fsl_elbc_nand) = {
.name = "fsl_elbc_nand",
.id = UCLASS_MTD,
.of_match = fsl_elbc_nand_dt_ids,
.probe = fsl_elbc_nand_probe,
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(fsl_elbc_nand), &dev);
if (ret && ret != -ENODEV)
printf("Failed to initialize fsl_elbc_nand NAND controller. (error %d)\n", ret);
}
#endif

6
drivers/mtd/nand/raw/nand_base.c
View File

@ -4598,6 +4598,12 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod
ecc_mode = NAND_ECC_SOFT_BCH;
}
if (ecc_mode == NAND_ECC_SOFT) {
str = ofnode_read_string(node, "nand-ecc-algo");
if (str && !strcmp(str, "bch"))
ecc_mode = NAND_ECC_SOFT_BCH;
}
ecc_strength = ofnode_read_s32_default(node,
"nand-ecc-strength", -1);
ecc_step = ofnode_read_s32_default(node,

2
drivers/pci/pcie_fsl.c
View File

@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },

4
include/configs/P1010RDB.h
View File

@ -81,6 +81,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
#else
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_TPL_PAD_TO 0x20000

3
include/configs/T102xRDB.h
View File

@ -36,6 +36,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T104xRDB.h
View File

@ -40,6 +40,9 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T208xQDS.h
View File

@ -44,6 +44,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T208xRDB.h
View File

@ -39,6 +39,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

1
include/configs/ls1012a2g5rdb.h
View File

@ -19,7 +19,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x800000\0" \
"scriptaddr=0x80000000\0" \

2
include/configs/ls1012afrdm.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#ifndef __LS1012ARDB_H__
@ -21,7 +22,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"fdtheader_addr_r=0x80100000\0" \

1
include/configs/ls1012afrwy.h
View File

@ -35,7 +35,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernel_size_sd=0x16000\0" \
"kernelhdr_size_sd=0x10\0" \

1
include/configs/ls1012aqds.h
View File

@ -89,7 +89,6 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x600000\0" \
"scriptaddr=0x80000000\0" \

1
include/configs/ls1012ardb.h
View File

@ -44,7 +44,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x600000\0" \
"scriptaddr=0x80000000\0" \

1
include/configs/ls1021atsn.h
View File

@ -114,7 +114,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \

4
include/configs/ls1021atwr.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#ifndef __CONFIG_H
@ -209,7 +209,6 @@
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
"cma=64M@0x0-0xb0000000\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x65000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
@ -266,7 +265,6 @@
"bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
"cma=64M@0x0-0xb0000000\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \

3
include/configs/ls1028aqds.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1028A_QDS_H
@ -68,7 +68,6 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

3
include/configs/ls1028ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#ifndef __LS1028A_RDB_H
@ -64,7 +64,6 @@
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"bootm_size=0x10000000\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

1
include/configs/ls1043a_common.h
View File

@ -173,7 +173,6 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

1
include/configs/ls1046a_common.h
View File

@ -165,7 +165,6 @@
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"bootm_size=0x10000000\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

2
include/configs/ls1088ardb.h
View File

@ -271,7 +271,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x1000000\0" \
"kernel_addr_sd=0x8000\0" \
"kernelhdr_addr_sd=0x3000\0" \
@ -340,7 +339,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x1000000\0" \
"kernel_addr_sd=0x8000\0" \
"kernelhdr_addr_sd=0x3000\0" \

2
include/configs/ls2080ardb.h
View File

@ -323,7 +323,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x581000000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x800000\0" \
@ -386,7 +385,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x581000000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x600000\0" \

1
include/configs/lx2160a_common.h
View File

@ -164,7 +164,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x600000\0" \
"scriptaddr=0x80000000\0" \

48
include/configs/p1_p2_rdb_pc.h
View File

@ -21,6 +21,9 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@ -46,6 +49,9 @@
#define __SW_BOOT_SD 0x24
#define __SW_BOOT_NAND 0x44
#define __SW_BOOT_PCIE 0x74
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@ -57,9 +63,13 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28
#define __SW_BOOT_SD 0x68 /* or 0x18 */
#define __SW_BOOT_SD 0x68
#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@ -111,6 +121,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
#else
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif /* not CONFIG_TPL_BUILD */
#define CONFIG_SPL_PAD_TO 0x20000
@ -320,7 +334,7 @@
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000"
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
@ -339,6 +353,10 @@
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
#ifndef __VSCFW_ADDR
#define __VSCFW_ADDR ""
#endif
/*
* Config the L2 Cache as L2 SRAM
*/
@ -526,28 +544,28 @@
#ifdef __SW_BOOT_NOR
#define __NOR_RST_CMD \
norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SPI
#define __SPI_RST_CMD \
spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SD
#define __SD_RST_CMD \
sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_NAND
#define __NAND_RST_CMD \
nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_PCIE
#define __PCIE_RST_CMD \
pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -574,9 +592,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
"nandbootaddr=100000\0" \
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
__stringify(__VSCFW_ADDR)"\0" \
__VSCFW_ADDR \
"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \

1
include/fsl_esdhc.h
View File

@ -76,6 +76,7 @@
/* eSDHC control register */
#define ESDHCCTL 0x0002e40c
#define ESDHCCTL_SNOOP (0x00000040)
#define ESDHCCTL_PCS (0x00080000)
#define ESDHCCTL_FAF (0x00040000)