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Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

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- a37xx: pci: Cleanup and minor fix for root port check (Pali)
- pci: mvebu: Ensure that root port is always on root zero bus (Pali)
- kwbimage: Fix dumping DATA registers for v0 images (Pali)
- kwbimage: Support for parsing extended v0 format (Pali)
- a37xx: Fix code and update DTS files to upstream version (Pali)
- a37xx: Fix and extend building memory map (Pali)
- ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision (Marek)
- mvebu: Optionally reset board on DDR training failure (Marek)
This commit is contained in:
Tom Rini 2022-02-17 11:03:50 -05:00
commit 8ad1c9c26f
27 changed files with 2173 additions and 1027 deletions
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38
arch/arm/dts/armada-371x.dtsi
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@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 371x family of SoCs
* (also named 88F3710)
@ -6,43 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"

230
arch/arm/dts/armada-3720-db.dts
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@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 3720 development board
* (DB-88F3720-DDR3)
@ -5,47 +6,14 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* This file is compatible with the version 1.4 and the version 2.0 of
* the board, however the CON numbers are different between the 2
* version
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
@ -56,41 +24,114 @@
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
i2c0 = &i2c0;
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
};
&comphy {
phy0 {
phy-type = <COMPHY_TYPE_USB3_HOST0>;
phy-speed = <COMPHY_SPEED_5G>;
exp_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
};
phy1 {
phy-type = <COMPHY_TYPE_PEX0>;
phy-speed = <COMPHY_SPEED_2_5G>;
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&exp_usb3_vbus>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
vcc_sd_reg2: regulator-vmcc {
compatible = "regulator-fixed";
regulator-name = "vcc_sd2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
};
};
/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy = <&phy0>;
status = "okay";
};
/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
&eth1 {
phy-mode = "sgmii";
phy = <&phy1>;
status = "okay";
phy-mode = "rgmii";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
gpio_exp: pca9555@22 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x22>;
/*
* IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT
* IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE
* IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN
* IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN
* IO0_4: PWR_EN_SD
* IO0_5: PWR_EN_EMMC
* IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL
* IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS
*/
};
rtc@68 {
/* PT7C4337A from pericom fully compatible with the ds1337 */
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* CON3 */
@ -99,28 +140,23 @@
};
&sdhci0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
};
&sdhci1 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
status = "okay";
};
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
/* SD slot module on CON14(V2.0)/CON15(V1.4) */
&sdhci1 {
wp-inverted;
cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
bus-width = <4>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
vmmc-supply = <&vcc_sd_reg2>;
status = "okay";
};
&spi0 {
@ -128,37 +164,57 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x200000>;
};
partition@200000 {
label = "U-boot Env";
reg = <0x200000 0x10000>;
};
partition@210000 {
label = "Linux";
reg = <0x210000 0xDF0000>;
};
};
};
};
/* Exported on the micro USB connector CON32 through an FTDI */
/*
* Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
* an FTDI (also on CON24(V2.0)/CON26(V1.4)).
*/
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* CON29 */
/* CON26(V2.0)/CON28(V1.4) */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
/* CON27(V2.0)/CON29(V1.4) */
&usb2 {
status = "okay";
};
/* CON31 */
/* CON29(V2.0)/CON31(V1.4) */
&usb3 {
status = "okay";
};
/* CON17 */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
usb-phy = <&usb3_phy>;
};

31
arch/arm/dts/armada-3720-espressobin-u-boot.dtsi Normal file
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
&spi0 {
spi-flash@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@firmware {
reg = <0 CONFIG_ENV_OFFSET>;
label = "firmware";
};
partition@u-boot-env {
reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
label = "u-boot-env";
};
};
};
};
#endif
/*
* U-Boot requires to have this eMMC node by default in "okay" status. U-Boot
* at runtime changes status to "disabled" if eMMC is not present on the board.
*/
&sdhci0 {
status = "okay";
};

189
arch/arm/dts/armada-3720-espressobin.dts
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@ -1,195 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 3720 community board
* (ESPRESSOBin)
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
* Romain Perier <romain.perier@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
/dts-v1/;
#include "armada-372x.dtsi"
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board";
compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
i2c0 = &i2c0;
spi0 = &spi0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg0: regulator@0 {
compatible = "regulator-gpio";
regulator-name = "vcc_sd0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
states = <1800000 0x1
3300000 0x0>;
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
};
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii";
phy_addr = <0x1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
/* CON3 */
&sata {
status = "okay";
phys = <&comphy2 0>;
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
bus-width = <4>;
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vcc_sd_reg0>;
status = "okay";
};
/* U11 */
&sdhci1 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@firmware {
reg = <0 CONFIG_ENV_OFFSET>;
label = "firmware";
};
partition@u-boot-env {
reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
label = "u-boot-env";
};
};
#endif
};
};
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* CON29 */
&usb2 {
status = "okay";
};
/* CON31 */
&usb3 {
status = "okay";
phys = <&comphy0 0>;
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
phys = <&comphy1 0>;
};

218
arch/arm/dts/armada-3720-espressobin.dtsi Normal file
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@ -0,0 +1,218 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
*
*/
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
aliases {
ethernet0 = &eth0;
/* for dsa slave device */
ethernet1 = &switch0port1;
ethernet2 = &switch0port2;
ethernet3 = &switch0port3;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
led2: gpio-led2 {
/* led2 is working only on v7 board */
status = "disabled";
compatible = "gpio-leds";
led2 {
label = "led2";
gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
/* J9 */
&pcie0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
};
/* J6 */
&sata {
status = "okay";
};
/* U11 */
&sdhci0 {
/* Main DTS file for Espressobin is without eMMC */
status = "disabled";
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};
/* J1 */
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
};
};
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/*
* Connector J17 and J18 expose a number of different features. Some pins are
* multiplexed. This is the case for instance for the following features:
* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
* how to enable it. Beware that the signals are 1.8V TTL.
* - I2C
* - SPI
* - MMC
*/
/* J7 */
&usb3 {
status = "okay";
};
/* J8 */
&usb2 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch0port1: port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
switch0port2: port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
switch0port3: port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};

782
arch/arm/dts/armada-3720-turris-mox.dts
View File

@ -1,18 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ or X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CZ.NIC Turris Mox Board
* 2018 by Marek Behun <marek.behun@nic.cz>
*
* Based on armada-3720-espressobin.dts by:
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
* 2019 by Marek Behún <kabel@kernel.org>
*/
/dts-v1/;
#include <dt-bindings/bus/moxtet.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-372x.dtsi"
/ {
@ -20,29 +16,29 @@
compatible = "cznic,turris-mox", "marvell,armada3720",
"marvell,armada3710";
aliases {
spi0 = &spi0;
ethernet0 = &eth0;
ethernet1 = &eth1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c0 = &i2c0;
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
led {
red {
label = "mox:red:activity";
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ACTIVITY;
linux,default-trigger = "default-on";
};
};
@ -50,7 +46,6 @@
compatible = "gpio-keys";
reset {
compatible = "gpio-keys";
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
@ -58,16 +53,14 @@
};
};
reg_usb3_vbus: usb3_vbus@0 {
exp_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <2000000>;
shutdown-delay-us = <1000000>;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
};
vsdc_reg: vsdc-reg {
@ -84,43 +77,106 @@
enable-active-high;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
vsdio_reg: vsdio-reg {
compatible = "regulator-gpio";
regulator-name = "vsdio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
eth_phy1: ethernet-phy@1 {
reg = <1>;
gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
sdhci1_pwrseq: sdhci1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
status = "okay";
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
/* enabled by U-Boot if SFP module is present */
status = "disabled";
};
firmware {
armada-3700-rwtm {
compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
};
};
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii";
phy = <&eth_phy1>;
};
&eth1 {
phy-mode = "2500base-x";
phys = <&comphy0 1>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <100000>;
/delete-property/ mrvl,i2c-fast-mode;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rtc@6f {
compatible = "microchip,mcp7941x";
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
&sdhci1 {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
status = "okay";
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
/*
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
* for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
*/
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
/* enabled by U-Boot if PCIe module is present */
status = "disabled";
};
&uart0 {
status = "okay";
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy-handle = <&phy1>;
status = "okay";
};
&eth1 {
phy-mode = "2500base-x";
managed = "in-band-status";
phys = <&comphy0 1>;
};
&sdhci0 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
@ -129,17 +185,23 @@
status = "okay";
};
&pinctrl_nb {
spi_cs1_pins: spi-cs1-pins {
groups = "spi_cs1";
function = "spi";
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
non-removable;
bus-width = <4>;
marvell,pad-type = "sd";
vqmmc-supply = <&vsdio_reg>;
mmc-pwrseq = <&sdhci1_pwrseq>;
/* forbid SDR104 for FCC purposes */
sdhci-caps-mask = <0x2 0x0>;
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_cs1_pins>;
pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
assigned-clocks = <&nb_periph_clk 7>;
assigned-clock-parents = <&tbg 1>;
assigned-clock-rates = <20000000>;
@ -147,10 +209,9 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,s25fl064l", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
@ -184,38 +245,621 @@
};
};
moxtet@1 {
moxtet: moxtet@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cznic,moxtet";
reg = <1>;
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
spi-max-frequency = <1000000>;
spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
};
};
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gpiosb>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
moxtet_sfp: gpio@0 {
compatible = "cznic,moxtet-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
status = "disabled";
};
};
};
&usb2 {
status = "okay";
};
&comphy2 {
connector {
compatible = "usb-a-connector";
phy-supply = <&exp_usb3_vbus>;
};
};
&usb3 {
vbus-supply = <&reg_usb3_vbus>;
status = "okay";
phys = <&comphy2 0>;
};
&pcie0 {
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "disabled";
phys = <&comphy1 0>;
pinctrl-0 = <&smi_pins>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
/* switch nodes are enabled by U-Boot if modules are present */
switch0@10 {
compatible = "marvell,mv88e6190";
reg = <0x10 0>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(0)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
port@5 {
reg = <0x5>;
label = "lan5";
phy-handle = <&switch0phy5>;
};
port@6 {
reg = <0x6>;
label = "lan6";
phy-handle = <&switch0phy6>;
};
port@7 {
reg = <0x7>;
label = "lan7";
phy-handle = <&switch0phy7>;
};
port@8 {
reg = <0x8>;
label = "lan8";
phy-handle = <&switch0phy8>;
};
port@9 {
reg = <0x9>;
label = "cpu";
ethernet = <&eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
switch0port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port9 &switch2port9>;
status = "disabled";
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch0@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1_topaz: switch0phy1@11 {
reg = <0x11>;
};
switch0phy2_topaz: switch0phy2@12 {
reg = <0x12>;
};
switch0phy3_topaz: switch0phy3@13 {
reg = <0x13>;
};
switch0phy4_topaz: switch0phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "cpu";
phy-mode = "2500base-x";
managed = "in-band-status";
ethernet = <&eth1>;
};
};
};
switch1@11 {
compatible = "marvell,mv88e6190";
reg = <0x11 0>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(1)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy1: switch1phy1@1 {
reg = <0x1>;
};
switch1phy2: switch1phy2@2 {
reg = <0x2>;
};
switch1phy3: switch1phy3@3 {
reg = <0x3>;
};
switch1phy4: switch1phy4@4 {
reg = <0x4>;
};
switch1phy5: switch1phy5@5 {
reg = <0x5>;
};
switch1phy6: switch1phy6@6 {
reg = <0x6>;
};
switch1phy7: switch1phy7@7 {
reg = <0x7>;
};
switch1phy8: switch1phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1>;
};
port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2>;
};
port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3>;
};
port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4>;
};
port@5 {
reg = <0x5>;
label = "lan13";
phy-handle = <&switch1phy5>;
};
port@6 {
reg = <0x6>;
label = "lan14";
phy-handle = <&switch1phy6>;
};
port@7 {
reg = <0x7>;
label = "lan15";
phy-handle = <&switch1phy7>;
};
port@8 {
reg = <0x8>;
label = "lan16";
phy-handle = <&switch1phy8>;
};
switch1port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch0port10>;
};
switch1port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch2port9>;
status = "disabled";
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch1@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy1_topaz: switch1phy1@11 {
reg = <0x11>;
};
switch1phy2_topaz: switch1phy2@12 {
reg = <0x12>;
};
switch1phy3_topaz: switch1phy3@13 {
reg = <0x13>;
};
switch1phy4_topaz: switch1phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch0port10>;
};
};
};
switch2@12 {
compatible = "marvell,mv88e6190";
reg = <0x12 0>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(2)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch2phy1: switch2phy1@1 {
reg = <0x1>;
};
switch2phy2: switch2phy2@2 {
reg = <0x2>;
};
switch2phy3: switch2phy3@3 {
reg = <0x3>;
};
switch2phy4: switch2phy4@4 {
reg = <0x4>;
};
switch2phy5: switch2phy5@5 {
reg = <0x5>;
};
switch2phy6: switch2phy6@6 {
reg = <0x6>;
};
switch2phy7: switch2phy7@7 {
reg = <0x7>;
};
switch2phy8: switch2phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1>;
};
port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2>;
};
port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3>;
};
port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4>;
};
port@5 {
reg = <0x5>;
label = "lan21";
phy-handle = <&switch2phy5>;
};
port@6 {
reg = <0x6>;
label = "lan22";
phy-handle = <&switch2phy6>;
};
port@7 {
reg = <0x7>;
label = "lan23";
phy-handle = <&switch2phy7>;
};
port@8 {
reg = <0x8>;
label = "lan24";
phy-handle = <&switch2phy8>;
};
switch2port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port10 &switch0port10>;
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch2@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch2phy1_topaz: switch2phy1@11 {
reg = <0x11>;
};
switch2phy2_topaz: switch2phy2@12 {
reg = <0x12>;
};
switch2phy3_topaz: switch2phy3@13 {
reg = <0x13>;
};
switch2phy4_topaz: switch2phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port10 &switch0port10>;
};
};
};
};

2
arch/arm/dts/armada-3720-uDPU-u-boot.dtsi
View File

@ -28,6 +28,6 @@
};
};
&sdhci1 {
&sdhci0 {
u-boot,dm-pre-reloc;
};

224
arch/arm/dts/armada-3720-uDPU.dts
View File

@ -3,30 +3,23 @@
* Device tree for the uDPU board.
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
* Copyright (C) 2016 Marvell
* Copyright (C) 2018 Methode
* Copyright (C) 2018 Telus
* Copyright (C) 2019 Methode Electronics
* Copyright (C) 2019 Telus
*
* Vladimir Vid <vladimir.vid@sartura.hr>
*/
/dts-v1/;
#include "armada-37xx.dtsi"
#include "armada-3720-uDPU-u-boot.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
model = "Methode uDPU Board";
compatible = "methode,udpu";
compatible = "methode,udpu", "marvell,armada3720";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
};
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
spi0 = &spi0;
};
memory@0 {
@ -34,56 +27,39 @@
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
mdio: mdio@32004 {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
scsi: scsi {
compatible = "marvell,mvebu-scsi";
#address-cells = <1>;
#size-cells = <1>;
max-id = <1>;
max-lun = <1>;
status = "okay";
};
i2c1: i2c@11080 {
compatible = "marvell,armada-3700-i2c", "simple-bus";
reg = <0x0 0x11080 0x0 0x80>;
leds {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
#address-cells = <2>;
#size-cells = <2>;
status = "okay";
};
compatible = "gpio-leds";
uart1: serial@12200 {
compatible = "marvell,armada-3700-uart-ext";
reg = <0x0 0x12200 0x0 0x30>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
};
power1 {
label = "udpu:green:power";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
vcc_sd_reg0: regulator@0 {
compatible = "regulator-gpio";
regulator-name = "vcc_sd0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
states = <1800000 0x1
3300000 0x0>;
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
power2 {
label = "udpu:red:power";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
network1 {
label = "udpu:green:network";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
network2 {
label = "udpu:red:network";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
alarm1 {
label = "udpu:green:alarm";
gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
};
alarm2 {
label = "udpu:red:alarm";
gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
};
};
sfp_eth0: sfp-eth0 {
@ -93,40 +69,29 @@
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
sfp,ethernet = <&eth1>;
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&eth0 {
pinctrl-0 = <&pcie_pins>;
&sdhci0 {
status = "okay";
phy-mode = "sgmii";
managed = "in-band-status";
phy = <&ethphy0>;
phys = <&comphy1 0>;
};
&eth1 {
status = "okay";
phy-mode = "sgmii";
managed = "in-band-status";
phy = <&ethphy1>;
phys = <&comphy0 1>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
non-removable;
no-sd;
no-sdio;
};
&spi0 {
@ -134,47 +99,90 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q1024a","n25q512a";
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
spi-max-frequency = <54000000>;
partition@0 {
label = "uboot";
reg = <0 0x400000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* only bootloader is located on the SPI */
partition@0 {
label = "uboot";
reg = <0 0x400000>;
};
};
};
};
&sdhci1 {
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
bus-width = <4>;
vqmmc-supply = <&vcc_sd_reg0>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
&pinctrl_nb {
i2c1_recovery_pins: i2c1-recovery-pins {
groups = "i2c1";
function = "gpio";
};
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
i2c2_recovery_pins: i2c2-recovery-pins {
groups = "i2c2";
function = "gpio";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
&i2c0 {
status = "okay";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
lm75@48 {
status = "okay";
compatible = "lm75";
reg = <0x48>;
};
lm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
};
&eth0 {
phy-mode = "sgmii";
status = "okay";
managed = "in-band-status";
phys = <&comphy1 0>;
sfp = <&sfp_eth0>;
};
&eth1 {
phy-mode = "sgmii";
status = "okay";
managed = "in-band-status";
phys = <&comphy0 1>;
sfp = <&sfp_eth1>;
};
&usb3 {
status = "okay";
phys = <&usb2_utmi_otg_phy>;
phy-names = "usb2-utmi-otg-phy";
};
&uart0 {
status = "okay";
};

43
arch/arm/dts/armada-372x.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 372x family of SoCs
* (also named 88F3720)
@ -6,43 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"
@ -52,10 +16,11 @@
compatible = "marvell,armada3720", "marvell,armada3710";
cpus {
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x1>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
};
};

452
arch/arm/dts/armada-37xx.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
*
@ -5,48 +6,9 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/comphy/comphy_data.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 37xx SoC";
@ -57,15 +19,32 @@
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* The PSCI firmware region depicted below is the default one
* and should be updated by the bootloader.
*/
psci-area@4000000 {
reg = <0 0x4000000 0 0x200000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
};
};
@ -77,14 +56,15 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
@ -93,54 +73,123 @@
#size-cells = <2>;
ranges;
internal-regs {
internal-regs@d0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
wdt: watchdog@8300 {
compatible = "marvell,armada-3700-wdt";
reg = <0x8300 0x40>;
marvell,system-controller = <&cpu_misc>;
clocks = <&xtalclk>;
};
cpu_misc: system-controller@d000 {
compatible = "marvell,armada-3700-cpu-misc",
"syscon";
reg = <0xd000 0x1000>;
};
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10600 0xA00>;
clocks = <&nb_periph_clk 7>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <4>;
status = "disabled";
};
wdt: watchdog-timer@8300 {
compatible = "marvell,armada-3700-wdt";
reg = <0xd064 0x4>,
<0x8300 0x40>;
i2c0: i2c@11000 {
compatible = "marvell,armada-3700-i2c";
reg = <0x11000 0x24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&nb_periph_clk 10>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
mrvl,i2c-fast-mode;
status = "disabled";
};
i2c1: i2c@11080 {
compatible = "marvell,armada-3700-i2c";
reg = <0x11080 0x24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&nb_periph_clk 9>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
mrvl,i2c-fast-mode;
status = "disabled";
};
avs: avs@11500 {
compatible = "marvell,armada-3700-avs",
"syscon";
reg = <0x11500 0x40>;
};
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x18>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart-sum", "uart-tx", "uart-rx";
status = "disabled";
};
uart1: serial@12200 {
compatible = "marvell,armada-3700-uart-ext";
reg = <0x12200 0x30>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uart-tx", "uart-rx";
status = "disabled";
};
nb_periph_clk: nb-periph-clk@13000 {
compatible = "marvell,armada-3700-periph-clock-nb";
compatible = "marvell,armada-3700-periph-clock-nb",
"syscon";
reg = <0x13000 0x100>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
sb_periph_clk: sb-periph-clk@18000 {
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x18000 0x100>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x100>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};
pinctrl_nb: pinctrl-nb@13800 {
pinctrl_nb: pinctrl@13800 {
compatible = "marvell,armada3710-nb-pinctrl",
"syscon", "simple-mfd";
"syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
gpionb: gpionb {
/* MPP1[19:0] */
gpionb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_nb 0 0 36>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts =
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
@ -154,7 +203,12 @@
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
};
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
spi_quad_pins: spi-quad-pins {
@ -162,6 +216,11 @@
function = "spi";
};
spi_cs1_pins: spi-cs1-pins {
groups = "spi_cs1";
function = "spi";
};
i2c1_pins: i2c1-pins {
groups = "i2c1";
function = "i2c";
@ -188,14 +247,54 @@
};
};
pinctrl_sb: pinctrl-sb@18800 {
nb_pm: syscon@14000 {
compatible = "marvell,armada-3700-nb-pm",
"syscon";
reg = <0x14000 0x60>;
};
comphy: phy@18300 {
compatible = "marvell,comphy-a3700";
reg = <0x18300 0x300>,
<0x1F000 0x400>,
<0x5C000 0x400>,
<0xe0178 0x8>;
reg-names = "comphy",
"lane1_pcie_gbe",
"lane0_usb3_gbe",
"lane2_sata_usb3";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&xtalclk>;
clock-names = "xtal";
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};
pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
"syscon", "simple-mfd";
"syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpiosb {
/* MPP2[23:0] */
gpiosb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@ -219,30 +318,92 @@
function = "sdio";
};
pcie_pins: pcie-pins {
groups = "pcie1";
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1"; /* this actually controls "pcie1_reset" */
function = "gpio";
};
pcie_clkreq_pins: pcie-clkreq-pins {
groups = "pcie1_clkreq";
function = "pcie";
};
};
eth0: ethernet@30000 {
compatible = "marvell,armada-3700-neta";
reg = <0x30000 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 8>;
status = "disabled";
};
mdio: mdio@32004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x32004 0x4>;
};
eth1: ethernet@40000 {
compatible = "marvell,armada-3700-neta";
reg = <0x40000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 7>;
status = "disabled";
};
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
marvell,usb-misc-reg = <&usb32_syscon>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 12>;
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
status = "disabled";
};
usb2_utmi_otg_phy: phy@5d000 {
compatible = "marvell,a3700-utmi-otg-phy";
reg = <0x5d000 0x800>;
marvell,usb-misc-reg = <&usb32_syscon>;
#phy-cells = <0>;
};
usb32_syscon: system-controller@5d800 {
compatible = "marvell,armada-3700-usb2-host-device-misc",
"syscon";
reg = <0x5d800 0x800>;
};
usb2: usb@5e000 {
compatible = "marvell,armada3700-ehci";
reg = <0x5e000 0x450>;
compatible = "marvell,armada-3700-ehci";
reg = <0x5e000 0x1000>;
marvell,usb-misc-reg = <&usb2_syscon>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_utmi_host_phy>;
phy-names = "usb2-utmi-host-phy";
status = "disabled";
};
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,a3700-utmi-host-phy";
reg = <0x5f000 0x800>;
marvell,usb-misc-reg = <&usb2_syscon>;
#phy-cells = <0>;
};
usb2_syscon: system-controller@5f800 {
compatible = "marvell,armada-3700-usb2-host-misc",
"syscon";
reg = <0x5f800 0x800>;
};
xor@60900 {
compatible = "marvell,armada-3700-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
reg = <0x60900 0x100>,
<0x60b00 0x100>;
xor10 {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@ -252,26 +413,56 @@
};
};
sdhci0: sdhci@d0000 {
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97ies";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&nb_periph_clk 15>;
};
rwtm: mailbox@b0000 {
compatible = "marvell,armada-3700-rwtm-mailbox";
reg = <0xb0000 0x100>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
reg = <0xd0000 0x300
0x1e808 0x4>;
"marvell,sdhci-xenon";
reg = <0xd0000 0x300>,
<0x1e808 0x4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 0>;
clock-names = "core";
status = "disabled";
};
sdhci1: sdhci@d8000 {
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
reg = <0xd8000 0x300
0x17808 0x4>;
"marvell,sdhci-xenon";
reg = <0xd8000 0x300>,
<0x17808 0x4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 0>;
clock-names = "core";
status = "disabled";
};
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;
reg = <0xe0000 0x178>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 1>;
phys = <&comphy2 0>;
phy-names = "sata-phy";
status = "disabled";
};
@ -280,72 +471,26 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
<0x1d40000 0x40000>; /* GICR */
};
eth0: neta@30000 {
compatible = "marvell,armada-3700-neta";
reg = <0x30000 0x20>;
status = "disabled";
};
eth1: neta@40000 {
compatible = "marvell,armada-3700-neta";
reg = <0x40000 0x20>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,armada-3700-i2c";
reg = <0x11000 0x100>;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
spi-max-frequency = <50000000>;
clocks = <&nb_periph_clk 7>;
status = "disabled";
};
comphy: comphy@18300 {
compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
reg = <0x18300 0x28>,
<0x1f300 0x3d000>;
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
<0x1d40000 0x40000>, /* GICR */
<0x1d80000 0x2000>, /* GICC */
<0x1d90000 0x2000>, /* GICH */
<0x1da0000 0x20000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie0: pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
device_type = "pci";
status = "disabled";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
status = "disabled";
bus-range = <0 0xff>;
bus-range = <0x00 0xff>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
msi-parent = <&pcie0>;
msi-controller;
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
@ -353,10 +498,27 @@
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
0x81000000 0 0xeff00000
0 0xeff00000 0 0x100000>; /* Port 0 IO*/
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
max-link-speed = <2>;
phys = <&comphy1 0>;
pcie_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
firmware {
armada-3700-rwtm {
compatible = "marvell,armada-3700-rwtm-firmware";
mboxes = <&rwtm 0>;
status = "okay";
};
};
};

13
arch/arm/mach-mvebu/Kconfig
View File

@ -213,6 +213,19 @@ config DDR_LOG_LEVEL
At level 3, rovides the windows margin of each DQ as a results of
DQS centeralization.
config DDR_RESET_ON_TRAINING_FAILURE
bool "Reset the board on DDR training failure instead of hanging"
depends on ARMADA_38X || ARMADA_XP
help
If DDR training fails in SPL, reset the board instead of hanging.
Some boards are known to fail DDR training occasionally and an
immediate reset may be preferable to waiting until the board is
reset by watchdog (if there even is one).
Note that if booting via UART and the DDR training fails, the
device will still hang - it doesn't make sense to reset the board
in such a case.
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
default "helios4" if TARGET_HELIOS4

29
arch/arm/mach-mvebu/armada3700/cpu.c
View File

@ -13,6 +13,7 @@
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
@ -46,8 +47,10 @@
#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
#define MVEBU_CPU_DEC_WIN_GRANULARITY 16
#define MVEBU_CPU_DEC_WINS 5
#define MVEBU_CPU_DEC_CCI_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
#define MVEBU_CPU_DEC_ROM_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)
#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 4)
#define A3700_PTE_BLOCK_NORMAL \
(PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
@ -60,7 +63,7 @@ static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
{
/*
* SRAM, MMIO regions
* Don't remove this, a3700_build_mem_map needs it.
* Don't remove this, build_mem_map needs it.
*/
.phys = SOC_REGS_PHY_BASE,
.virt = SOC_REGS_PHY_BASE,
@ -110,8 +113,26 @@ static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
static void build_mem_map(void)
{
int win, region;
u32 reg;
region = 1;
/* CCI-400 */
reg = readl(MVEBU_CPU_DEC_CCI_BASE);
mvebu_mem_map[region].phys = reg << 20;
mvebu_mem_map[region].virt = reg << 20;
mvebu_mem_map[region].size = SZ_64K;
mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
++region;
/* AP BootROM */
reg = readl(MVEBU_CPU_DEC_ROM_BASE);
mvebu_mem_map[region].phys = reg << 20;
mvebu_mem_map[region].virt = reg << 20;
mvebu_mem_map[region].size = SZ_1M;
mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
++region;
for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
u32 base, tgt, size;
u64 attrs;
@ -142,8 +163,6 @@ static void build_mem_map(void)
void enable_caches(void)
{
build_mem_map();
icache_enable();
dcache_enable();
}
@ -152,6 +171,8 @@ int a3700_dram_init(void)
{
int win;
build_mem_map();
gd->ram_size = 0;
for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
u32 base, tgt, size;

7
arch/arm/mach-mvebu/spl.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
#include <hang.h>
@ -330,7 +331,11 @@ void board_init_f(ulong dummy)
ret = ddr3_init();
if (ret) {
printf("ddr3_init() failed: %d\n", ret);
hang();
if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
get_boot_device() != BOOT_DEVICE_UART)
reset_cpu();
else
hang();
}
#endif

22
board/CZ.NIC/turris_mox/turris_mox.c
View File

@ -375,8 +375,22 @@ static void mox_phy_leds_start_blinking(void)
{
struct phy_device *phydev;
struct mii_dev *bus;
const char *node_name;
int node;
bus = miiphy_get_dev_by_name("neta@30000");
node = fdt_path_offset(gd->fdt_blob, "ethernet0");
if (node < 0) {
printf("Cannot get eth0!\n");
return;
}
node_name = fdt_get_name(gd->fdt_blob, node, NULL);
if (!node_name) {
printf("Cannot get eth0 node name!\n");
return;
}
bus = miiphy_get_dev_by_name(node_name);
if (!bus) {
printf("Cannot get MDIO bus device!\n");
return;
@ -623,8 +637,12 @@ int last_stage_init(void)
*/
if (peridot || topaz) {
struct mii_dev *bus;
const char *node_name;
int node;
bus = miiphy_get_dev_by_name("neta@30000");
node = fdt_path_offset(gd->fdt_blob, "ethernet0");
node_name = (node >= 0) ? fdt_get_name(gd->fdt_blob, node, NULL) : NULL;
bus = node_name ? miiphy_get_dev_by_name(node_name) : NULL;
if (!bus) {
printf("Cannot get MDIO bus device!\n");
} else {

1
configs/turris_omnia_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
CONFIG_TARGET_TURRIS_OMNIA=y
CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xF0000
CONFIG_ENV_SECT_SIZE=0x10000

6
drivers/ddr/marvell/a38x/ddr3_training_centralization.c
View File

@ -180,7 +180,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
[bit_id],
EDGE_1);
if (current_byte_status &
BYTE_SPLIT_OUT_MIX) {
(BYTE_SPLIT_OUT_MIX |
BYTE_HOMOGENEOUS_SPLIT_OUT)) {
if (cur_start_win[bit_id] >= 64)
cur_start_win[bit_id] -= 64;
else
@ -197,7 +198,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
EDGE_1);
if (cur_end_win[bit_id] >= 64 &&
(current_byte_status &
BYTE_SPLIT_OUT_MIX)) {
(BYTE_SPLIT_OUT_MIX |
BYTE_HOMOGENEOUS_SPLIT_OUT))) {
cur_end_win[bit_id] -= 64;
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,

530
drivers/pci/pci-aardvark.c
View File

@ -35,136 +35,109 @@
#include <linux/delay.h>
#include <linux/ioport.h>
/* PCIe core registers */
#define PCIE_CORE_CMD_STATUS_REG 0x4
#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
#define PCIE_CORE_DEV_REV_REG 0x8
#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_TRAINING BIT(5)
#define PCIE_CORE_ERR_CAPCTL_REG 0x118
#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
/* PCIe Root Port register offsets */
#define ADVK_ROOT_PORT_PCI_CFG_OFF 0x0
#define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0
#define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100
/* PIO registers base address and register offsets */
#define PIO_BASE_ADDR 0x4000
#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
#define PIO_STAT (PIO_BASE_ADDR + 0x4)
#define PIO_COMPLETION_STATUS_SHIFT 7
#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
#define PIO_COMPLETION_STATUS_OK 0
#define PIO_COMPLETION_STATUS_UR 1
#define PIO_COMPLETION_STATUS_CRS 2
#define PIO_COMPLETION_STATUS_CA 4
#define PIO_NON_POSTED_REQ BIT(10)
#define PIO_ERR_STATUS BIT(11)
#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
#define PIO_START (PIO_BASE_ADDR + 0x1c)
#define PIO_ISR (PIO_BASE_ADDR + 0x20)
/* PIO registers */
#define ADVK_PIO_BASE_ADDR 0x4000
#define ADVK_PIO_CTRL (ADVK_PIO_BASE_ADDR + 0x0)
#define ADVK_PIO_CTRL_TYPE_MASK GENMASK(3, 0)
#define ADVK_PIO_CTRL_TYPE_SHIFT 0
#define ADVK_PIO_CTRL_TYPE_RD_TYPE0 0x8
#define ADVK_PIO_CTRL_TYPE_RD_TYPE1 0x9
#define ADVK_PIO_CTRL_TYPE_WR_TYPE0 0xa
#define ADVK_PIO_CTRL_TYPE_WR_TYPE1 0xb
#define ADVK_PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
#define ADVK_PIO_STAT (ADVK_PIO_BASE_ADDR + 0x4)
#define ADVK_PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
#define ADVK_PIO_COMPLETION_STATUS_SHIFT 7
#define ADVK_PIO_COMPLETION_STATUS_OK 0
#define ADVK_PIO_COMPLETION_STATUS_UR 1
#define ADVK_PIO_COMPLETION_STATUS_CRS 2
#define ADVK_PIO_COMPLETION_STATUS_CA 4
#define ADVK_PIO_NON_POSTED_REQ BIT(10)
#define ADVK_PIO_ERR_STATUS BIT(11)
#define ADVK_PIO_ADDR_LS (ADVK_PIO_BASE_ADDR + 0x8)
#define ADVK_PIO_ADDR_MS (ADVK_PIO_BASE_ADDR + 0xc)
#define ADVK_PIO_WR_DATA (ADVK_PIO_BASE_ADDR + 0x10)
#define ADVK_PIO_WR_DATA_STRB (ADVK_PIO_BASE_ADDR + 0x14)
#define ADVK_PIO_RD_DATA (ADVK_PIO_BASE_ADDR + 0x18)
#define ADVK_PIO_START (ADVK_PIO_BASE_ADDR + 0x1c)
#define ADVK_PIO_ISR (ADVK_PIO_BASE_ADDR + 0x20)
/* Aardvark Control registers */
#define CONTROL_BASE_ADDR 0x4800
#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
#define PCIE_GEN_SEL_MSK 0x3
#define PCIE_GEN_SEL_SHIFT 0x0
#define SPEED_GEN_1 0
#define SPEED_GEN_2 1
#define SPEED_GEN_3 2
#define IS_RC_MSK 1
#define IS_RC_SHIFT 2
#define LANE_CNT_MSK 0x18
#define LANE_CNT_SHIFT 0x3
#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
#define LINK_TRAINING_EN BIT(6)
#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
#define PCIE_CORE_CTRL2_RESERVED 0x7
#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
/* Global Control registers */
#define ADVK_GLOBAL_CTRL_BASE_ADDR 0x4800
#define ADVK_GLOBAL_CTRL0 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x0)
#define ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK GENMASK(1, 0)
#define ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT 0
#define ADVK_GLOBAL_CTRL0_SPEED_GEN_1 0
#define ADVK_GLOBAL_CTRL0_SPEED_GEN_2 1
#define ADVK_GLOBAL_CTRL0_SPEED_GEN_3 2
#define ADVK_GLOBAL_CTRL0_IS_RC BIT(2)
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK GENMASK(4, 3)
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT 3
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_1 0
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_2 1
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_4 2
#define ADVK_GLOBAL_CTRL0_LANE_COUNT_8 3
#define ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN BIT(6)
#define ADVK_GLOBAL_CTRL2 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x8)
#define ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN BIT(5)
#define ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN BIT(6)
/* PCIe window configuration */
#define OB_WIN_BASE_ADDR 0x4c00
#define OB_WIN_BLOCK_SIZE 0x20
#define OB_WIN_COUNT 8
#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
OB_WIN_BLOCK_SIZE * (win) + \
(offset))
#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
#define OB_WIN_ENABLE BIT(0)
#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
#define OB_WIN_FUNC_NUM_SHIFT 24
#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
#define OB_WIN_BUS_NUM_BITS_SHIFT 20
#define OB_WIN_MSG_CODE_ENABLE BIT(22)
#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
#define OB_WIN_MSG_CODE_SHIFT 14
#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
#define OB_WIN_ATTR_ENABLE BIT(11)
#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
#define OB_WIN_ATTR_TC_SHIFT 8
#define OB_WIN_ATTR_RELAXED BIT(7)
#define OB_WIN_ATTR_NOSNOOP BIT(6)
#define OB_WIN_ATTR_POISON BIT(5)
#define OB_WIN_ATTR_IDO BIT(4)
#define OB_WIN_TYPE_MASK GENMASK(3, 0)
#define OB_WIN_TYPE_SHIFT 0
#define OB_WIN_TYPE_MEM 0x0
#define OB_WIN_TYPE_IO 0x4
#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
#define OB_WIN_TYPE_MSG 0xc
/* PCIe window configuration registers */
#define ADVK_OB_WIN_BASE_ADDR 0x4c00
#define ADVK_OB_WIN_BLOCK_SIZE 0x20
#define ADVK_OB_WIN_COUNT 8
#define ADVK_OB_WIN_REG_ADDR(win, offset) (ADVK_OB_WIN_BASE_ADDR + ADVK_OB_WIN_BLOCK_SIZE * (win) + (offset))
#define ADVK_OB_WIN_MATCH_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x00)
#define ADVK_OB_WIN_ENABLE BIT(0)
#define ADVK_OB_WIN_MATCH_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x04)
#define ADVK_OB_WIN_REMAP_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x08)
#define ADVK_OB_WIN_REMAP_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x0c)
#define ADVK_OB_WIN_MASK_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x10)
#define ADVK_OB_WIN_MASK_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x14)
#define ADVK_OB_WIN_ACTIONS(win) ADVK_OB_WIN_REG_ADDR(win, 0x18)
#define ADVK_OB_WIN_DEFAULT_ACTIONS (ADVK_OB_WIN_ACTIONS(ADVK_OB_WIN_COUNT-1) + 0x4)
#define ADVK_OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
#define ADVK_OB_WIN_FUNC_NUM_SHIFT 24
#define ADVK_OB_WIN_FUNC_NUM_ENABLE BIT(23)
#define ADVK_OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
#define ADVK_OB_WIN_BUS_NUM_BITS_SHIFT 20
#define ADVK_OB_WIN_MSG_CODE_ENABLE BIT(22)
#define ADVK_OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
#define ADVK_OB_WIN_MSG_CODE_SHIFT 14
#define ADVK_OB_WIN_MSG_PAYLOAD_LEN BIT(12)
#define ADVK_OB_WIN_ATTR_ENABLE BIT(11)
#define ADVK_OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
#define ADVK_OB_WIN_ATTR_TC_SHIFT 8
#define ADVK_OB_WIN_ATTR_RELAXED BIT(7)
#define ADVK_OB_WIN_ATTR_NOSNOOP BIT(6)
#define ADVK_OB_WIN_ATTR_POISON BIT(5)
#define ADVK_OB_WIN_ATTR_IDO BIT(4)
#define ADVK_OB_WIN_TYPE_MASK GENMASK(3, 0)
#define ADVK_OB_WIN_TYPE_SHIFT 0
#define ADVK_OB_WIN_TYPE_MEM 0x0
#define ADVK_OB_WIN_TYPE_IO 0x4
#define ADVK_OB_WIN_TYPE_CONFIG_TYPE0 0x8
#define ADVK_OB_WIN_TYPE_CONFIG_TYPE1 0x9
#define ADVK_OB_WIN_TYPE_MSG 0xc
/* LMI registers base address and register offsets */
#define LMI_BASE_ADDR 0x6000
#define CFG_REG (LMI_BASE_ADDR + 0x0)
#define LTSSM_SHIFT 24
#define LTSSM_MASK 0x3f
#define LTSSM_L0 0x10
#define LTSSM_DISABLED 0x20
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
/* Local Management Interface registers */
#define ADVK_LMI_BASE_ADDR 0x6000
#define ADVK_LMI_PHY_CFG0 (ADVK_LMI_BASE_ADDR + 0x0)
#define ADVK_LMI_PHY_CFG0_LTSSM_MASK GENMASK(29, 24)
#define ADVK_LMI_PHY_CFG0_LTSSM_SHIFT 24
#define ADVK_LMI_PHY_CFG0_LTSSM_L0 0x10
#define ADVK_LMI_PHY_CFG0_LTSSM_DISABLED 0x20
#define ADVK_LMI_VENDOR_ID (ADVK_LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */
#define CTRL_CORE_BASE_ADDR 0x18000
#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
#define CTRL_MODE_SHIFT 0x0
#define CTRL_MODE_MASK 0x1
#define PCIE_CORE_MODE_DIRECT 0x0
#define PCIE_CORE_MODE_COMMAND 0x1
/* Transaction types */
#define PCIE_CONFIG_RD_TYPE0 0x8
#define PCIE_CONFIG_RD_TYPE1 0x9
#define PCIE_CONFIG_WR_TYPE0 0xa
#define PCIE_CONFIG_WR_TYPE1 0xb
/* Core Control registers */
#define ADVK_CORE_CTRL_BASE_ADDR 0x18000
#define ADVK_CORE_CTRL_CONFIG (ADVK_CORE_CTRL_BASE_ADDR + 0x0)
#define ADVK_CORE_CTRL_CONFIG_COMMAND_MODE BIT(0)
/* PCIe Retries & Timeout definitions */
#define PIO_MAX_RETRIES 1500
@ -172,14 +145,12 @@
#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_CRS_VAL 0xFFFF0001
#define CFG_RD_CRS_VAL 0xFFFF0001
/**
* struct pcie_advk - Advk PCIe controller state
*
* @base: The base address of the register space.
* @first_busno: Bus number of the PCIe root-port.
* This may vary depending on the PCIe setup.
* @sec_busno: Bus number for the device behind the PCIe root-port.
* @dev: The pointer to PCI uclass device.
* @reset_gpio: GPIO descriptor for PERST.
@ -189,7 +160,6 @@
*/
struct pcie_advk {
void *base;
int first_busno;
int sec_busno;
struct udevice *dev;
struct gpio_desc reset_gpio;
@ -207,6 +177,23 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
return readl(pcie->base + reg);
}
/**
* pcie_advk_link_up() - Check if PCIe link is up or not
*
* @pcie: The PCI device to access
*
* Return true on link up.
* Return false on link down.
*/
static bool pcie_advk_link_up(struct pcie_advk *pcie)
{
u32 val, ltssm_state;
val = advk_readl(pcie, ADVK_LMI_PHY_CFG0);
ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT;
return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED;
}
/**
* pcie_advk_addr_valid() - Check for valid bus address
*
@ -221,8 +208,12 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
int busno, u8 dev, u8 func)
{
/* On the primary (local) bus there is only one PCI Bridge */
if (busno == pcie->first_busno && (dev != 0 || func != 0))
/* On the root bus there is only one PCI Bridge */
if (busno == 0 && (dev != 0 || func != 0))
return false;
/* Access to other buses is possible when link is up */
if (busno != 0 && !pcie_advk_link_up(pcie))
return false;
/*
@ -252,8 +243,8 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
uint count;
for (count = 1; count <= PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
start = advk_readl(pcie, ADVK_PIO_START);
isr = advk_readl(pcie, ADVK_PIO_ISR);
if (!start && isr)
return count;
/*
@ -285,29 +276,29 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
unsigned int status;
char *strcomp_status, *str_posted;
reg = advk_readl(pcie, PIO_STAT);
status = (reg & PIO_COMPLETION_STATUS_MASK) >>
PIO_COMPLETION_STATUS_SHIFT;
reg = advk_readl(pcie, ADVK_PIO_STAT);
status = (reg & ADVK_PIO_COMPLETION_STATUS_MASK) >>
ADVK_PIO_COMPLETION_STATUS_SHIFT;
switch (status) {
case PIO_COMPLETION_STATUS_OK:
if (reg & PIO_ERR_STATUS) {
case ADVK_PIO_COMPLETION_STATUS_OK:
if (reg & ADVK_PIO_ERR_STATUS) {
strcomp_status = "COMP_ERR";
ret = -EFAULT;
break;
}
/* Get the read result */
if (read_val)
*read_val = advk_readl(pcie, PIO_RD_DATA);
*read_val = advk_readl(pcie, ADVK_PIO_RD_DATA);
/* No error */
strcomp_status = NULL;
ret = 0;
break;
case PIO_COMPLETION_STATUS_UR:
case ADVK_PIO_COMPLETION_STATUS_UR:
strcomp_status = "UR";
ret = -EOPNOTSUPP;
break;
case PIO_COMPLETION_STATUS_CRS:
case ADVK_PIO_COMPLETION_STATUS_CRS:
if (allow_crs && read_val) {
/* For reading, CRS is not an error status. */
*read_val = CFG_RD_CRS_VAL;
@ -318,7 +309,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
ret = -EAGAIN;
}
break;
case PIO_COMPLETION_STATUS_CA:
case ADVK_PIO_COMPLETION_STATUS_CA:
strcomp_status = "CA";
ret = -ECANCELED;
break;
@ -331,14 +322,14 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
if (!strcomp_status)
return ret;
if (reg & PIO_NON_POSTED_REQ)
if (reg & ADVK_PIO_NON_POSTED_REQ)
str_posted = "Non-posted";
else
str_posted = "Posted";
dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
str_posted, strcomp_status, reg,
advk_readl(pcie, PIO_ADDR_LS));
advk_readl(pcie, ADVK_PIO_ADDR_LS));
return ret;
}
@ -380,21 +371,21 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
}
/*
* The configuration space of the PCI Bridge on primary (first) bus is
* The configuration space of the PCI Bridge on the root bus (zero) is
* not accessible via PIO transfers like all other PCIe devices. PCI
* Bridge config registers are available directly in Aardvark memory
* space starting at offset zero. The PCI Bridge config space is of
* Type 0, but the BAR registers (including ROM BAR) don't have the same
* meaning as in the PCIe specification. Therefore do not access BAR
* registers and non-common registers (those which have different
* meaning for Type 0 and Type 1 config space) of the primary PCI Bridge
* meaning for Type 0 and Type 1 config space) of the PCI Bridge
* and instead read their content from driver virtual cfgcache[].
*/
if (busno == pcie->first_busno) {
if (busno == 0) {
if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c))
data = pcie->cfgcache[(offset - 0x10) / 4];
else
data = advk_readl(pcie, offset & ~3);
data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
/*
@ -406,14 +397,13 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
data |= PCI_HEADER_TYPE_BRIDGE << 16;
}
if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) {
/* CRSSVE bit is stored only in cache */
if (pcie->cfgcrssve)
data |= PCI_EXP_RTCTL_CRSSVE;
}
if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
(PCI_EXP_RTCAP & ~3)) {
if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + (PCI_EXP_RTCAP & ~3)) {
/* CRS is emulated below, so set CRSVIS capability */
data |= PCI_EXP_RTCAP_CRSVIS << 16;
}
@ -437,7 +427,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
*/
allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
if (allow_crs) {
@ -449,28 +439,28 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
}
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_RD_TYPE0;
reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else
reg |= PCIE_CONFIG_RD_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
/* Program the data strobe */
advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
advk_writel(pcie, 0xf, ADVK_PIO_WR_DATA_STRB);
retry_count = 0;
retry:
/* Start the transfer */
advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
advk_writel(pcie, 1, ADVK_PIO_ISR);
advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie);
if (ret < 0) {
@ -571,7 +561,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
* zero. Type 1 specific registers are not available, so we write their
* content only into driver virtual cfgcache[].
*/
if (busno == pcie->first_busno) {
if (busno == 0) {
if ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c)) {
data = pcie->cfgcache[(offset - 0x10) / 4];
@ -583,61 +573,58 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
} else {
data = advk_readl(pcie, offset & ~3);
data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
data = pci_conv_size_to_32(data, value, offset, size);
advk_writel(pcie, data, offset & ~3);
advk_writel(pcie, data, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
}
if (offset == PCI_PRIMARY_BUS)
pcie->first_busno = data & 0xff;
if (offset == PCI_SECONDARY_BUS ||
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
pcie->sec_busno = (data >> 8) & 0xff;
if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL)
pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
return 0;
}
if (advk_readl(pcie, PIO_START)) {
if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
return -EAGAIN;
}
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_WR_TYPE0;
reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else
reg |= PCIE_CONFIG_WR_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
/* Program the data register */
reg = pci_conv_size_to_32(0, value, offset, size);
advk_writel(pcie, reg, PIO_WR_DATA);
advk_writel(pcie, reg, ADVK_PIO_WR_DATA);
dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
/* Program the data strobe */
reg = pcie_calc_datastrobe(offset, size);
advk_writel(pcie, reg, PIO_WR_DATA_STRB);
advk_writel(pcie, reg, ADVK_PIO_WR_DATA_STRB);
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
retry_count = 0;
retry:
/* Start the transfer */
advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
advk_writel(pcie, 1, ADVK_PIO_ISR);
advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie);
if (ret < 0)
@ -652,34 +639,14 @@ retry:
return ret;
}
/**
* pcie_advk_link_up() - Check if PCIe link is up or not
*
* @pcie: The PCI device to access
*
* Return 1 (true) on link up.
* Return 0 (false) on link down.
*/
static int pcie_advk_link_up(struct pcie_advk *pcie)
{
u32 val, ltssm_state;
val = advk_readl(pcie, CFG_REG);
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
}
/**
* pcie_advk_wait_for_link() - Wait for link training to be accomplished
*
* @pcie: The PCI device to access
*
* Wait up to 1 second for link training to be accomplished.
*
* Return 1 (true) if link training ends up with link up success.
* Return 0 (false) if link training ends up with link up failure.
*/
static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
static void pcie_advk_wait_for_link(struct pcie_advk *pcie)
{
int retries;
@ -687,15 +654,13 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
printf("PCIe: Link up\n");
return 0;
return;
}
udelay(LINK_WAIT_TIMEOUT);
}
printf("PCIe: Link down\n");
return -ETIMEDOUT;
}
/*
@ -706,25 +671,25 @@ static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
phys_addr_t match, phys_addr_t remap,
phys_addr_t mask, u32 actions)
{
advk_writel(pcie, OB_WIN_ENABLE |
lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
advk_writel(pcie, ADVK_OB_WIN_ENABLE |
lower_32_bits(match), ADVK_OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, upper_32_bits(match), ADVK_OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, lower_32_bits(remap), ADVK_OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, upper_32_bits(remap), ADVK_OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, lower_32_bits(mask), ADVK_OB_WIN_MASK_LS(win_num));
advk_writel(pcie, upper_32_bits(mask), ADVK_OB_WIN_MASK_MS(win_num));
advk_writel(pcie, actions, ADVK_OB_WIN_ACTIONS(win_num));
}
static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
{
advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_MASK_LS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_MASK_MS(win_num));
advk_writel(pcie, 0, ADVK_OB_WIN_ACTIONS(win_num));
}
static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
@ -748,7 +713,7 @@ static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
* because lower 16 bits of mask must be zero. Remapped address
* may have set only bits from the mask.
*/
while (*wins < OB_WIN_COUNT && size > 0) {
while (*wins < ADVK_OB_WIN_COUNT && size > 0) {
/* Calculate the largest aligned window size */
win_size = (1ULL << (fls64(size) - 1)) |
(phys_start ? (1ULL << __ffs64(phys_start)) : 0);
@ -792,25 +757,24 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
int i, wins;
u32 reg;
/* Set to Direct mode */
reg = advk_readl(pcie, CTRL_CONFIG_REG);
reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
advk_writel(pcie, reg, CTRL_CONFIG_REG);
/* Set from Command to Direct mode */
reg = advk_readl(pcie, ADVK_CORE_CTRL_CONFIG);
reg &= ~ADVK_CORE_CTRL_CONFIG_COMMAND_MODE;
advk_writel(pcie, reg, ADVK_CORE_CTRL_CONFIG);
/* Set PCI global control register to RC mode */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg |= (IS_RC_MSK << IS_RC_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg |= ADVK_GLOBAL_CTRL0_IS_RC;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/*
* Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
* VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
* ADVK_LMI_VENDOR_ID contains vendor id in low 16 bits and subsystem vendor
* id in high 16 bits. Updating this register changes readback value of
* read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
* read-only vendor id bits in Root Port PCI_VENDOR_ID register. Workaround
* for erratum 4.1: "The value of device and vendor ID is incorrect".
*/
advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
advk_writel(pcie, 0x11ab11ab, ADVK_LMI_VENDOR_ID);
/*
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
@ -834,48 +798,47 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
* Type 1 registers is redirected to the virtual cfgcache[] buffer,
* which avoids changing unrelated registers.
*/
reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
reg &= ~0xffffff00;
reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
/* Set Advanced Error Capabilities and Control PF0 register */
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
/* Enable generation and checking of ECRC on PCIe Root Port */
reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
/* Set PCIe Device Control register on PCIe Root Port */
reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
reg &= ~PCI_EXP_DEVCTL_READRQ;
reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
reg |= PCI_EXP_DEVCTL_READRQ_512B;
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
/* Program PCIe Control 2 to disable strict ordering */
reg = PCIE_CORE_CTRL2_RESERVED |
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
reg &= ~ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/* Set GEN2 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~PCIE_GEN_SEL_MSK;
reg |= SPEED_GEN_2;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK;
reg |= ADVK_GLOBAL_CTRL0_SPEED_GEN_2 << ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LANE_CNT_MSK;
reg |= LANE_COUNT_1;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK;
reg |= ADVK_GLOBAL_CTRL0_LANE_COUNT_1 << ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Enable link training */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg |= LINK_TRAINING_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg |= ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/*
* Enable AXI address window location generation:
@ -887,9 +850,9 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
* access when default outbound window configuration
* is set for memory access.
*/
reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
reg |= ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/*
* Bypass the address window mapping for PIO:
@ -897,16 +860,16 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
* info over AXI interface by PIO registers, the
* address window is not required.
*/
reg = advk_readl(pcie, PIO_CTRL);
reg |= PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, PIO_CTRL);
reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg |= ADVK_PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, ADVK_PIO_CTRL);
/*
* Set memory access in Default User Field so it
* is not required to configure PCIe address for
* transparent memory access.
*/
advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
advk_writel(pcie, ADVK_OB_WIN_TYPE_MEM, ADVK_OB_WIN_DEFAULT_ACTIONS);
/*
* Configure PCIe address windows for non-memory or
@ -916,22 +879,21 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
wins = 0;
pci_get_regions(pcie->dev, &io, &mem, &pref);
if (io)
pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
pcie_advk_set_ob_region(pcie, &wins, io, ADVK_OB_WIN_TYPE_IO);
if (mem && mem->phys_start != mem->bus_start)
pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
pcie_advk_set_ob_region(pcie, &wins, mem, ADVK_OB_WIN_TYPE_MEM);
if (pref && pref->phys_start != pref->bus_start)
pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
pcie_advk_set_ob_region(pcie, &wins, pref, ADVK_OB_WIN_TYPE_MEM);
/* Disable remaining PCIe outbound windows */
for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
for (i = ((wins >= 0) ? wins : 0); i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i);
if (wins == -1)
return -EINVAL;
/* Wait for PCIe link up */
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
pcie_advk_wait_for_link(pcie);
return 0;
}
@ -991,18 +953,16 @@ static int pcie_advk_remove(struct udevice *dev)
u32 reg;
int i;
for (i = 0; i < OB_WIN_COUNT; i++)
for (i = 0; i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
PCIE_CORE_CMD_IO_ACCESS_EN |
PCIE_CORE_CMD_MEM_IO_REQ_EN);
advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LINK_TRAINING_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
return 0;
}
@ -1023,7 +983,7 @@ static int pcie_advk_of_to_plat(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
/* Get the register base address */
pcie->base = (void *)dev_read_addr_index(dev, 0);
pcie->base = (void *)dev_read_addr(dev);
if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
return -EINVAL;

52
drivers/pci/pci_mvebu.c
View File

@ -78,7 +78,6 @@ struct mvebu_pcie {
bool is_x4;
int devfn;
u32 lane_mask;
int first_busno;
int sec_busno;
char name[16];
unsigned int mem_target;
@ -140,12 +139,12 @@ static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
int busno, int dev, int func)
{
/* On primary bus is only one PCI Bridge */
if (busno == pcie->first_busno && (dev != 0 || func != 0))
/* On the root bus is only one PCI Bridge */
if (busno == 0 && (dev != 0 || func != 0))
return false;
/* Access to other buses is possible when link is up */
if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
if (busno != 0 && !mvebu_pcie_link_up(pcie))
return false;
/* On secondary bus can be only one PCIe device */
@ -173,15 +172,15 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
}
/*
* The configuration space of the PCI Bridge on primary (first) bus is
* The configuration space of the PCI Bridge on the root bus (zero) is
* of Type 0 but the BAR registers (including ROM BAR) don't have the
* same meaning as in the PCIe specification. Therefore do not access
* BAR registers and non-common registers (those which have different
* meaning for Type 0 and Type 1 config space) of the PCI Bridge and
* instead read their content from driver virtual cfgcache[].
*/
if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c))) {
if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c))) {
data = pcie->cfgcache[(offset - 0x10) / 4];
debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
offset, size, data);
@ -190,10 +189,10 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
}
/*
* PCI bridge is device 0 at primary bus but mvebu has it mapped on
* secondary bus with device number 1.
* PCI bridge is device 0 at the root bus (zero) but mvebu has it
* mapped on secondary bus with device number 1.
*/
if (busno == pcie->first_busno)
if (busno == 0)
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@ -216,8 +215,7 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
return -EINVAL;
}
if (busno == pcie->first_busno &&
(offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
/*
* Change Header Type of PCI Bridge device to Type 1
* (0x01, used by PCI Bridges) because mvebu reports
@ -257,10 +255,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
* config registers are not available, so we write their content only
* into driver virtual cfgcache[].
* And as explained in mvebu_pcie_probe(), mvebu has its own specific
* way for configuring primary and secondary bus numbers.
* way for configuring secondary bus number.
*/
if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c))) {
if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
(offset >= 0x38 && offset < 0x3c))) {
debug("Writing to cfgcache only\n");
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
@ -270,12 +268,6 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
(offset & ~3) == PCI_ROM_ADDRESS1)
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
/* mvebu has its own way how to set PCI primary bus number */
if (offset == PCI_PRIMARY_BUS) {
pcie->first_busno = data & 0xff;
debug("Primary bus number was changed to %d\n",
pcie->first_busno);
}
/* mvebu has its own way how to set PCI secondary bus number */
if (offset == PCI_SECONDARY_BUS ||
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
@ -288,10 +280,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
}
/*
* PCI bridge is device 0 at primary bus but mvebu has it mapped on
* secondary bus with device number 1.
* PCI bridge is device 0 at the root bus (zero) but mvebu has it
* mapped on secondary bus with device number 1.
*/
if (busno == pcie->first_busno)
if (busno == 0)
addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
else
addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@ -473,9 +465,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
* target device equals local device number then request is routed to
* PCI Bridge which represent local PCIe Root Port.
*
* It means that PCI primary and secondary buses shares one bus number
* It means that PCI root and secondary buses shares one bus number
* which is configured via local bus number. Determination if config
* request should go to primary or secondary bus is done based on local
* request should go to root or secondary bus is done based on local
* device number.
*
* PCIe is point-to-point bus, so at secondary bus is always exactly one
@ -487,13 +479,13 @@ static int mvebu_pcie_probe(struct udevice *dev)
* secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
* later configure it via config write requests to the correct value.
* mvebu_pcie_write_config() catches config write requests which tries
* to change primary/secondary bus number and correctly updates local
* bus number based on new secondary bus number.
* to change secondary bus number and correctly updates local bus number
* based on new secondary bus number.
*
* With this configuration is PCI Bridge available at secondary bus as
* device number 1. But it must be available at primary bus as device
* device number 1. But it must be available at root bus (zero) as device
* number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
* functions rewrite address to the real one when accessing primary bus.
* functions rewrite address to the real one when accessing the root bus.
*/
mvebu_pcie_set_local_bus_nr(pcie, 0);
mvebu_pcie_set_local_dev_nr(pcie, 1);

2
drivers/phy/marvell/comphy_a3700.c
View File

@ -937,7 +937,7 @@ void comphy_dedicated_phys_init(void)
*/
if (usb32 == 0) {
node = fdt_node_offset_by_compatible(
blob, -1, "marvell,armada3700-ehci");
blob, -1, "marvell,armada-3700-ehci");
} else {
node = fdt_node_offset_by_compatible(
blob, -1, "marvell,armada3700-xhci");

3
drivers/phy/marvell/comphy_core.c
View File

@ -96,7 +96,7 @@ static int comphy_probe(struct udevice *dev)
if (IS_ERR(chip_cfg->hpipe3_base_addr))
return PTR_ERR(chip_cfg->hpipe3_base_addr);
if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
if (device_is_compatible(dev, "marvell,comphy-a3700")) {
chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
chip_cfg->rx_training = NULL;
@ -145,6 +145,7 @@ static int comphy_probe(struct udevice *dev)
static const struct udevice_id comphy_ids[] = {
{ .compatible = "marvell,mvebu-comphy" },
{ .compatible = "marvell,comphy-a3700" },
{ }
};

1
drivers/rtc/ds1307.c
View File

@ -358,6 +358,7 @@ static const struct udevice_id ds1307_rtc_ids[] = {
{ .compatible = "dallas,ds1337", .data = ds_1337 },
{ .compatible = "dallas,ds1339", .data = ds_1339 },
{ .compatible = "dallas,ds1340", .data = ds_1340 },
{ .compatible = "microchip,mcp7940x", .data = mcp794xx },
{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
{ .compatible = "st,m41t11", .data = m41t11 },
{ }

4
drivers/usb/host/ehci-marvell.c
View File

@ -123,7 +123,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
* Also, the address decoder doesn't need to get setup with this
* SoC, so don't call usb_brg_adrdec_setup().
*/
if (device_is_compatible(dev, "marvell,armada3700-ehci"))
if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
else
usb_brg_adrdec_setup((void *)priv->hcd_base);
@ -142,7 +142,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "marvell,orion-ehci", },
{ .compatible = "marvell,armada3700-ehci", },
{ .compatible = "marvell,armada-3700-ehci", },
{ }
};

7
drivers/watchdog/armada-37xx-wdt.c
View File

@ -155,12 +155,9 @@ static int a37xx_wdt_probe(struct udevice *dev)
struct a37xx_wdt *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_read_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE)
goto err;
priv->sel_reg = (void __iomem *)addr;
priv->sel_reg = (void __iomem *)MVEBU_REGISTER(0x0d064);
addr = dev_read_addr_index(dev, 1);
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
goto err;
priv->reg = (void __iomem *)addr;

16
include/dt-bindings/bus/moxtet.h Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Constant for device tree bindings for Turris Mox module configuration bus
*
* Copyright (C) 2019 Marek Behún <kabel@kernel.org>
*/
#ifndef _DT_BINDINGS_BUS_MOXTET_H
#define _DT_BINDINGS_BUS_MOXTET_H
#define MOXTET_IRQ_PCI 0
#define MOXTET_IRQ_USB3 4
#define MOXTET_IRQ_PERIDOT(n) (8 + (n))
#define MOXTET_IRQ_TOPAZ 12
#endif /* _DT_BINDINGS_BUS_MOXTET_H */

24
include/pci.h
View File

@ -484,6 +484,22 @@
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
@ -522,6 +538,14 @@
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
/* Advanced Error Reporting */
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
/* Single Root I/O Virtualization Registers */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */

158
tools/kwbimage.c
View File

@ -6,6 +6,8 @@
*
* (C) Copyright 2013 Thomas Petazzoni
* <thomas.petazzoni@free-electrons.com>
*
* (C) Copyright 2022 Pali Rohár <pali@kernel.org>
*/
#define OPENSSL_API_COMPAT 0x10101000L
@ -43,6 +45,21 @@ void EVP_MD_CTX_cleanup(EVP_MD_CTX *ctx)
}
#endif
/* fls - find last (most-significant) bit set in 4-bit integer */
static inline int fls4(int num)
{
if (num & 0x8)
return 4;
else if (num & 0x4)
return 3;
else if (num & 0x2)
return 2;
else if (num & 0x1)
return 1;
else
return 0;
}
static struct image_cfg_element *image_cfg;
static int cfgn;
static int verbose_mode;
@ -983,9 +1000,15 @@ static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
if (e)
main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
if (e)
main_hdr->nandbadblklocation = e->nandbadblklocation;
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
@ -1094,7 +1117,7 @@ static size_t image_headersz_v1(int *hasext)
fprintf(stderr,
"Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
"This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
"image for your board. Use 'dumpimage -T kwbimage -p 0' to extract it from an existing image.\n",
"image for your board. Use 'dumpimage -T kwbimage -p 1' to extract it from an existing image.\n",
e->binary.file, dir);
return 0;
}
@ -1898,6 +1921,7 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
static void kwbimage_print_header(const void *ptr)
{
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
struct bin_hdr_v0 *bhdr;
struct opt_hdr_v1 *ohdr;
printf("Image Type: MVEBU Boot from %s Image\n",
@ -1915,6 +1939,13 @@ static void kwbimage_print_header(const void *ptr)
}
}
for_each_bin_hdr_v0(bhdr, mhdr) {
printf("BIN Img Size: ");
genimg_print_size(le32_to_cpu(bhdr->size));
printf("BIN Img Addr: %08x\n", le32_to_cpu(bhdr->destaddr));
printf("BIN Img Entr: %08x\n", le32_to_cpu(bhdr->execaddr));
}
printf("Data Size: ");
genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
printf("Load Address: %08x\n", mhdr->destaddr);
@ -1947,15 +1978,31 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
/* Only version 0 extended header has checksum */
if (kwbimage_version(ptr) == 0) {
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
struct ext_hdr_v0 *ext_hdr;
struct bin_hdr_v0 *bhdr;
if (mhdr->ext) {
struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1);
for_each_ext_hdr_v0(ext_hdr, ptr) {
csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
if (csum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
for_each_bin_hdr_v0(bhdr, ptr) {
csum = image_checksum8(bhdr, (uint8_t *)&bhdr->checksum - (uint8_t *)bhdr - 1);
if (csum != bhdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
if (bhdr->offset > sizeof(*bhdr) || bhdr->offset % 4 != 0)
return -FDT_ERR_BADSTRUCTURE;
if (bhdr->offset + bhdr->size + 4 > sizeof(*bhdr) || bhdr->size % 4 != 0)
return -FDT_ERR_BADSTRUCTURE;
if (image_checksum32((uint8_t *)bhdr + bhdr->offset, bhdr->size) !=
*(uint32_t *)((uint8_t *)bhdr + bhdr->offset + bhdr->size))
return -FDT_ERR_BADSTRUCTURE;
}
blockid = mhdr->blockid;
offset = le32_to_cpu(mhdr->srcaddr);
size = le32_to_cpu(mhdr->blocksize);
@ -2130,8 +2177,11 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
struct register_set_hdr_v1 *regset_hdr;
struct ext_hdr_v0_reg *regdata;
struct ext_hdr_v0 *ehdr0;
struct bin_hdr_v0 *bhdr0;
struct opt_hdr_v1 *ohdr;
int params_count;
unsigned offset;
int is_v0_ext;
int cur_idx;
int version;
FILE *f;
@ -2145,6 +2195,14 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
version = kwbimage_version(ptr);
is_v0_ext = 0;
if (version == 0) {
if (mhdr0->ext > 1 || mhdr0->bin ||
((ehdr0 = ext_hdr_v0_first(ptr)) &&
(ehdr0->match_addr || ehdr0->match_mask || ehdr0->match_value)))
is_v0_ext = 1;
}
if (version != 0)
fprintf(f, "VERSION %d\n", version);
@ -2156,10 +2214,11 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
if (mhdr->blockid == IBR_HDR_NAND_ID)
fprintf(f, "NAND_PAGE_SIZE 0x%x\n", (unsigned)mhdr->nandpagesize);
if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID) {
if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID)
fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize);
if (mhdr->blockid == IBR_HDR_NAND_ID && (mhdr->nandbadblklocation != 0 || is_v0_ext))
fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n", (unsigned)mhdr->nandbadblklocation);
}
if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
@ -2222,20 +2281,81 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
}
}
if (version == 0 && mhdr0->ext) {
ehdr0 = (struct ext_hdr_v0 *)(mhdr0 + 1);
if (version == 0 && !is_v0_ext && le16_to_cpu(mhdr0->ddrinitdelay))
fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
for_each_ext_hdr_v0(ehdr0, ptr) {
if (is_v0_ext) {
fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
le32_to_cpu(ehdr0->match_addr),
le32_to_cpu(ehdr0->match_mask),
le32_to_cpu(ehdr0->match_value));
if (ehdr0->rsvd1[0] || ehdr0->rsvd1[1] || ehdr0->rsvd1[2] ||
ehdr0->rsvd1[3] || ehdr0->rsvd1[4] || ehdr0->rsvd1[5] ||
ehdr0->rsvd1[6] || ehdr0->rsvd1[7])
fprintf(f, "#DDR_RSVD1 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
ehdr0->rsvd1[0], ehdr0->rsvd1[1], ehdr0->rsvd1[2],
ehdr0->rsvd1[3], ehdr0->rsvd1[4], ehdr0->rsvd1[5],
ehdr0->rsvd1[6], ehdr0->rsvd1[7]);
if (ehdr0->rsvd2[0] || ehdr0->rsvd2[1] || ehdr0->rsvd2[2] ||
ehdr0->rsvd2[3] || ehdr0->rsvd2[4] || ehdr0->rsvd2[5] ||
ehdr0->rsvd2[6])
fprintf(f, "#DDR_RSVD2 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
ehdr0->rsvd2[0], ehdr0->rsvd2[1], ehdr0->rsvd2[2],
ehdr0->rsvd2[3], ehdr0->rsvd2[4], ehdr0->rsvd2[5],
ehdr0->rsvd2[6]);
if (ehdr0->ddrwritetype)
fprintf(f, "DDR_WRITE_TYPE %u\n", (unsigned)ehdr0->ddrwritetype);
if (ehdr0->ddrresetmpp)
fprintf(f, "DDR_RESET_MPP 0x%x\n", (unsigned)ehdr0->ddrresetmpp);
if (ehdr0->ddrclkenmpp)
fprintf(f, "DDR_CLKEN_MPP 0x%x\n", (unsigned)ehdr0->ddrclkenmpp);
if (ehdr0->ddrinitdelay)
fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)ehdr0->ddrinitdelay);
}
if (ehdr0->offset) {
for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset);
(uint8_t *)regdata < (uint8_t *)ptr + header_size && regdata->raddr &&
regdata->rdata;
(uint8_t *)regdata < (uint8_t *)ptr + header_size &&
(regdata->raddr || regdata->rdata);
regdata++)
fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr),
le32_to_cpu(regdata->rdata));
if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset)
fprintf(f, "DATA 0x0 0x0\n");
}
if (le32_to_cpu(ehdr0->enddelay))
fprintf(f, "DATA_DELAY %u\n", le32_to_cpu(ehdr0->enddelay));
else if (is_v0_ext)
fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
}
if (version == 0 && le16_to_cpu(mhdr0->ddrinitdelay))
fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
cur_idx = 1;
for_each_bin_hdr_v0(bhdr0, ptr) {
fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
le32_to_cpu(bhdr0->match_addr),
le32_to_cpu(bhdr0->match_mask),
le32_to_cpu(bhdr0->match_value));
fprintf(f, "BINARY binary%d.bin", cur_idx);
params_count = fls4(bhdr0->params_flags & 0xF);
for (i = 0; i < params_count; i++)
fprintf(f, " 0x%x", (bhdr0->params[i] & (1 << i)) ? bhdr0->params[i] : 0);
fprintf(f, " LOAD_ADDRESS 0x%08x", le32_to_cpu(bhdr0->destaddr));
fprintf(f, " EXEC_ADDRESS 0x%08x", le32_to_cpu(bhdr0->execaddr));
fprintf(f, "\n");
fprintf(f, "#BINARY_OFFSET 0x%x\n", le32_to_cpu(bhdr0->offset));
fprintf(f, "#BINARY_SIZE 0x%x\n", le32_to_cpu(bhdr0->size));
if (bhdr0->rsvd1)
fprintf(f, "#BINARY_RSVD1 0x%x\n", (unsigned)bhdr0->rsvd1);
if (bhdr0->rsvd2)
fprintf(f, "#BINARY_RSVD2 0x%x\n", (unsigned)bhdr0->rsvd2);
cur_idx++;
}
/* Undocumented reserved fields */
@ -2243,9 +2363,6 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
fprintf(f, "#RSVD1 0x%x 0x%x 0x%x\n", (unsigned)mhdr0->rsvd1[0],
(unsigned)mhdr0->rsvd1[1], (unsigned)mhdr0->rsvd1[2]);
if (version == 0 && mhdr0->rsvd3)
fprintf(f, "#RSVD3 0x%x\n", (unsigned)mhdr0->rsvd3);
if (version == 0 && le16_to_cpu(mhdr0->rsvd2))
fprintf(f, "#RSVD2 0x%x\n", (unsigned)le16_to_cpu(mhdr0->rsvd2));
@ -2264,6 +2381,7 @@ static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params
{
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
size_t header_size = kwbheader_size(ptr);
struct bin_hdr_v0 *bhdr;
struct opt_hdr_v1 *ohdr;
int idx = params->pflag;
int cur_idx;
@ -2310,6 +2428,14 @@ static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params
++cur_idx;
}
for_each_bin_hdr_v0(bhdr, ptr) {
if (idx == cur_idx) {
image = (ulong)bhdr + bhdr->offset;
size = bhdr->size;
break;
}
++cur_idx;
}
if (!image) {
fprintf(stderr, "Argument -p %d is invalid\n", idx);
@ -2331,7 +2457,7 @@ static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params
*/
static int kwbimage_check_params(struct image_tool_params *params)
{
if (!params->lflag && !params->iflag &&
if (!params->lflag && !params->iflag && !params->pflag &&
(!params->imagename || !strlen(params->imagename))) {
char *msg = "Configuration file for kwbimage creation omitted";

116
tools/kwbimage.h
View File

@ -48,9 +48,13 @@ struct main_hdr_v0 {
uint32_t destaddr; /* 0x10-0x13 */
uint32_t execaddr; /* 0x14-0x17 */
uint8_t satapiomode; /* 0x18 */
uint8_t rsvd3; /* 0x19 */
uint8_t nandblocksize; /* 0x19 */
union {
uint8_t nandbadblklocation; /* 0x1A */
uint16_t ddrinitdelay; /* 0x1A-0x1B */
uint16_t rsvd2; /* 0x1C-0x1D */
};
uint8_t rsvd2; /* 0x1C */
uint8_t bin; /* 0x1D */
uint8_t ext; /* 0x1E */
uint8_t checksum; /* 0x1F */
} __packed;
@ -60,14 +64,43 @@ struct ext_hdr_v0_reg {
uint32_t rdata;
} __packed;
#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
/* Structure of the extension header, version 0 (Kirkwood, Dove) */
struct ext_hdr_v0 {
uint32_t offset;
uint8_t reserved[0x20 - sizeof(uint32_t)];
struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
uint8_t reserved2[7];
uint8_t checksum;
/*
* Beware that extension header offsets specified in 88AP510 Functional
* Specifications are relative to the start of the main header, not to
* the start of the extension header itself.
*/
uint32_t offset; /* 0x0-0x3 */
uint8_t rsvd1[8]; /* 0x4-0xB */
uint32_t enddelay; /* 0xC-0xF */
uint32_t match_addr; /* 0x10-0x13 */
uint32_t match_mask; /* 0x14-0x17 */
uint32_t match_value; /* 0x18-0x1B */
uint8_t ddrwritetype; /* 0x1C */
uint8_t ddrresetmpp; /* 0x1D */
uint8_t ddrclkenmpp; /* 0x1E */
uint8_t ddrinitdelay; /* 0x1F */
struct ext_hdr_v0_reg rcfg[55]; /* 0x20-0x1D7 */
uint8_t rsvd2[7]; /* 0x1D8-0x1DE */
uint8_t checksum; /* 0x1DF */
} __packed;
/* Structure of the binary code header, version 0 (Dove) */
struct bin_hdr_v0 {
uint32_t match_addr; /* 0x00-0x03 */
uint32_t match_mask; /* 0x04-0x07 */
uint32_t match_value; /* 0x08-0x0B */
uint32_t offset; /* 0x0C-0x0F */
uint32_t destaddr; /* 0x10-0x13 */
uint32_t size; /* 0x14-0x17 */
uint32_t execaddr; /* 0x18-0x1B */
uint32_t params[4]; /* 0x1C-0x2B */
uint8_t params_flags; /* 0x2C */
uint8_t rsvd1; /* 0x2D */
uint8_t rsvd2; /* 0x2E */
uint8_t checksum; /* 0x2F */
uint8_t code[2000]; /* 0x30-0x7FF */
} __packed;
/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
@ -207,8 +240,20 @@ static inline size_t kwbheader_size(const void *header)
if (kwbimage_version(header) == 0) {
const struct main_hdr_v0 *hdr = header;
/*
* First extension header starts immediately after the main
* header without any padding. Between extension headers is
* 0x20 byte padding. There is no padding after the last
* extension header. First binary code header starts immediately
* after the last extension header (or immediately after the
* main header if there is no extension header) without any
* padding. There is no padding between binary code headers and
* neither after the last binary code header.
*/
return sizeof(*hdr) +
hdr->ext ? sizeof(struct ext_hdr_v0) : 0;
hdr->ext * sizeof(struct ext_hdr_v0) +
((hdr->ext > 1) ? ((hdr->ext - 1) * 0x20) : 0) +
hdr->bin * sizeof(struct bin_hdr_v0);
} else {
const struct main_hdr_v1 *hdr = header;
@ -225,6 +270,57 @@ static inline size_t kwbheader_size_for_csum(const void *header)
return kwbheader_size(header);
}
static inline struct ext_hdr_v0 *ext_hdr_v0_first(void *img)
{
struct main_hdr_v0 *mhdr;
if (kwbimage_version(img) != 0)
return NULL;
mhdr = img;
if (mhdr->ext)
return (struct ext_hdr_v0 *)(mhdr + 1);
else
return NULL;
}
static inline void *_ext_hdr_v0_end(struct main_hdr_v0 *mhdr)
{
return (uint8_t *)mhdr + kwbheader_size(mhdr) - mhdr->bin * sizeof(struct bin_hdr_v0);
}
static inline struct ext_hdr_v0 *ext_hdr_v0_next(void *img, struct ext_hdr_v0 *cur)
{
if ((void *)(cur + 1) < _ext_hdr_v0_end(img))
return (struct ext_hdr_v0 *)((uint8_t *)(cur + 1) + 0x20);
else
return NULL;
}
#define for_each_ext_hdr_v0(ehdr, img) \
for ((ehdr) = ext_hdr_v0_first((img)); \
(ehdr) != NULL; \
(ehdr) = ext_hdr_v0_next((img), (ehdr)))
static inline struct bin_hdr_v0 *bin_hdr_v0_first(void *img)
{
struct main_hdr_v0 *mhdr;
if (kwbimage_version(img) != 0)
return NULL;
mhdr = img;
if (mhdr->bin)
return _ext_hdr_v0_end(mhdr);
else
return NULL;
}
#define for_each_bin_hdr_v0(bhdr, img) \
for ((bhdr) = bin_hdr_v0_first((img)); \
(bhdr) && (void *)(bhdr) < (void *)((uint8_t *)img + kwbheader_size(img)); \
(bhdr) = (struct bin_hdr_v0 *)((bhdr))+1)
static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
{
return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);