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ARM: dts: keystone2: Do not use LPAE addresses in U-Boot

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Keystone dts files assumes that LPAE is enabled and top level root
node uses 64bit addresses. This breaks the keystone boot with
CONFIG_OF_CONTROL enabled. So do not use 64 bit addresse in U-Boot DT.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2015-09-19 15:00:19 +05:30
committed by Tom Rini
parent 351f969088
commit 8a9bb065da
1 changed files with 8 additions and 9 deletions
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17
arch/arm/dts/keystone.dtsi
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@@ -13,8 +13,8 @@
/ { / {
model = "Texas Instruments Keystone 2 SoC"; model = "Texas Instruments Keystone 2 SoC";
#address-cells = <2>; #address-cells = <1>;
#size-cells = <2>; #size-cells = <1>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
aliases { aliases {
@@ -22,17 +22,17 @@
}; };
memory { memory {
reg = <0x00000000 0x80000000 0x00000000 0x40000000>; reg = <0x80000000 0x40000000>;
}; };
gic: interrupt-controller { gic: interrupt-controller {
compatible = "arm,cortex-a15-gic"; compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupt-controller; interrupt-controller;
reg = <0x0 0x02561000 0x0 0x1000>, reg = <0x02561000 0x1000>,
<0x0 0x02562000 0x0 0x2000>, <0x02562000 0x2000>,
<0x0 0x02564000 0x0 0x1000>, <0x02564000 0x1000>,
<0x0 0x02566000 0x0 0x2000>; <0x02566000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>; IRQ_TYPE_LEVEL_HIGH)>;
}; };
@@ -63,8 +63,7 @@
#size-cells = <1>; #size-cells = <1>;
compatible = "ti,keystone","simple-bus"; compatible = "ti,keystone","simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
ranges = <0x0 0x0 0x0 0xc0000000>; ranges;
dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
pllctrl: pll-controller@02310000 { pllctrl: pll-controller@02310000 {
compatible = "ti,keystone-pllctrl", "syscon"; compatible = "ti,keystone-pllctrl", "syscon";