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ARMV7: Exynos4: Add support for TRATS board

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This patch adds support for Samsung TRATS board

Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
HeungJun, Kim 2012-01-16 21:13:05 +00:00 committed by Albert ARIBAUD
parent 77e490e225
commit 89f95492ec
6 changed files with 1280 additions and 0 deletions
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4
MAINTAINERS
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@ -718,6 +718,10 @@ Chander Kashyap <k.chander@samsung.com>
origen ARM ARMV7 (EXYNOS4210 SoC)
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
Heungjun Kim <riverful.kim@samsung.com>
trats ARM ARMV7 (EXYNOS4210 SoC)
Torsten Koschorrek <koschorrek@synertronixx.de>
scb9328 ARM920T (i.MXL)

43
board/samsung/trats/Makefile Normal file
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@ -0,0 +1,43 @@
#
# Copyright (C) 2011 Samsung Electronics
# Heungjun Kim <riverful.kim@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += trats.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

637
board/samsung/trats/setup.h Normal file
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@ -0,0 +1,637 @@
/*
* Machine Specific Values for TRATS board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TRATS_SETUP_H
#define _TRATS_SETUP_H
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
#define MUX_CORE_SEL_MOUTAPLL 0x0
#define MUX_CORE_SEL_SCLKMPLL 0x1
#define MUX_MPLL_SEL_FILPLL 0x0
#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
#define MUX_APLL_SEL_FILPLL 0x0
#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
| (MUX_CORE_SEL_MOUTAPLL << 16) \
| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
/* CLK_DIV_CPU0 */
#define APLL_RATIO 0x0
#define PCLK_DBG_RATIO 0x1
#define ATB_RATIO 0x3
#define PERIPH_RATIO 0x3
#define COREM1_RATIO 0x7
#define COREM0_RATIO 0x3
#define CORE_RATIO 0x0
#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (COREM1_RATIO << 8) \
| (COREM0_RATIO << 4) \
| (CORE_RATIO << 0))
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x0
#define COPY_RATIO 0x3
#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
/* CLK_DIV_DMC0 */
#define CORE_TIMERS_RATIO 0x1
#define COPY2_RATIO 0x3
#define DMCP_RATIO 0x1
#define DMCD_RATIO 0x1
#define DMC_RATIO 0x1
#define DPHY_RATIO 0x1
#define ACP_PCLK_RATIO 0x1
#define ACP_RATIO 0x3
#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
| (COPY2_RATIO << 24) \
| (DMCP_RATIO << 20) \
| (DMCD_RATIO << 16) \
| (DMC_RATIO << 12) \
| (DPHY_RATIO << 8) \
| (ACP_PCLK_RATIO << 4) \
| (ACP_RATIO << 0))
/* CLK_DIV_DMC1 */
#define DPM_RATIO 0x1
#define DVSEM_RATIO 0x1
#define PWI_RATIO 0x1
#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
| (DVSEM_RATIO << 16) \
| (PWI_RATIO << 8))
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_SEL_ACLK_133 0x0
#define MUX_ONENAND_SEL_ACLK_160 0x1
#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
#define MUX_VPLL_SEL_FINPLL 0x0
#define MUX_VPLL_SEL_FOUTVPLL 0x1
#define MUX_EPLL_SEL_FINPLL 0x0
#define MUX_EPLL_SEL_FOUTEPLL 0x1
#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
| (MUX_VPLL_SEL_FOUTVPLL << 8) \
| (MUX_EPLL_SEL_FOUTEPLL << 4) \
| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
/* CLK_DIV_TOP */
#define ONENAND_RATIO 0x0
#define ACLK_133_RATIO 0x5
#define ACLK_160_RATIO 0x4
#define ACLK_100_RATIO 0x7
#define ACLK_200_RATIO 0x3
#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
| (ACLK_133_RATIO << 12)\
| (ACLK_160_RATIO << 8) \
| (ACLK_100_RATIO << 4) \
| (ACLK_200_RATIO << 0))
/* CLK_DIV_LEFTBUS */
#define GPL_RATIO 0x1
#define GDL_RATIO 0x3
#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO 0x1
#define GDR_RATIO 0x3
#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
/* CLK_SRS_FSYS: 6 = SCLKMPLL */
#define SATA_SEL_SCLKMPLL 0
#define SATA_SEL_SCLKAPLL 1
#define MMC_SEL_XXTI 0
#define MMC_SEL_XUSBXTI 1
#define MMC_SEL_SCLK_HDMI24M 2
#define MMC_SEL_SCLK_USBPHY0 3
#define MMC_SEL_SCLK_USBPHY1 4
#define MMC_SEL_SCLK_HDMIPHY 5
#define MMC_SEL_SCLKMPLL 6
#define MMC_SEL_SCLKEPLL 7
#define MMC_SEL_SCLKVPLL 8
#define MMCC0_SEL MMC_SEL_SCLKMPLL
#define MMCC1_SEL MMC_SEL_SCLKMPLL
#define MMCC2_SEL MMC_SEL_SCLKMPLL
#define MMCC3_SEL MMC_SEL_SCLKMPLL
#define MMCC4_SEL MMC_SEL_SCLKMPLL
#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
| (MMCC4_SEL << 16) \
| (MMCC3_SEL << 12) \
| (MMCC2_SEL << 8) \
| (MMCC1_SEL << 4) \
| (MMCC0_SEL << 0))
/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
#define MMC0_RATIO 0xF
#define MMC0_PRE_RATIO 0x0
#define MMC1_RATIO 0xF
#define MMC1_PRE_RATIO 0x0
#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
| (MMC1_RATIO << 16) \
| (MMC0_PRE_RATIO << 8) \
| (MMC0_RATIO << 0))
/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
#define MMC2_RATIO 0xF
#define MMC2_PRE_RATIO 0x0
#define MMC3_RATIO 0xF
#define MMC3_PRE_RATIO 0x0
#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
| (MMC3_RATIO << 16) \
| (MMC2_PRE_RATIO << 8) \
| (MMC2_RATIO << 0))
/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
#define MMC4_RATIO 0xF
#define MMC4_PRE_RATIO 0x0
#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
| (MMC4_RATIO << 0))
/* CLK_SRC_PERIL0 */
#define UART_SEL_XXTI 0
#define UART_SEL_XUSBXTI 1
#define UART_SEL_SCLK_HDMI24M 2
#define UART_SEL_SCLK_USBPHY0 3
#define UART_SEL_SCLK_USBPHY1 4
#define UART_SEL_SCLK_HDMIPHY 5
#define UART_SEL_SCLKMPLL 6
#define UART_SEL_SCLKEPLL 7
#define UART_SEL_SCLKVPLL 8
#define UART0_SEL UART_SEL_SCLKMPLL
#define UART1_SEL UART_SEL_SCLKMPLL
#define UART2_SEL UART_SEL_SCLKMPLL
#define UART3_SEL UART_SEL_SCLKMPLL
#define UART4_SEL UART_SEL_SCLKMPLL
#define UART5_SEL UART_SEL_SCLKMPLL
#define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
| (UART4_SEL << 12) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL << 0))
/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
/* CLK_DIV_PERIL0 */
#define UART0_RATIO 7
#define UART1_RATIO 7
#define UART2_RATIO 7
#define UART3_RATIO 4
#define UART4_RATIO 7
#define UART5_RATIO 7
#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
| (UART4_RATIO << 12) \
| (UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_DIV_PERIL3 */
#define SLIMBUS_RATIO 0x0
#define PWM_RATIO 0x8
#define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
| (PWM_RATIO << 0))
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20
/* PLL Values */
#define DISABLE 0
#define ENABLE 1
#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
| (mdiv << 16) \
| (pdiv << 8) \
| (sdiv << 0))
/* APLL_CON0: 800MHz */
#define APLL_MDIV 0xC8
#define APLL_PDIV 0x6
#define APLL_SDIV 0x1
#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
/* APLL_CON1 */
#define APLL_AFC_ENB 0x1
#define APLL_AFC 0x1C
#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
/* MPLL_CON0: 800MHz */
#define MPLL_MDIV 0xC8
#define MPLL_PDIV 0x6
#define MPLL_SDIV 0x1
#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
/* MPLL_CON1 */
#define MPLL_AFC_ENB 0x1
#define MPLL_AFC 0x1C
#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
/* EPLL_CON0: 96MHz */
#define EPLL_MDIV 0x30
#define EPLL_PDIV 0x3
#define EPLL_SDIV 0x2
#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
/* EPLL_CON1 */
#define EPLL_K 0x0
#define EPLL_CON1_VAL (EPLL_K >> 0)
/* VPLL_CON0: 108MHz */
#define VPLL_MDIV 0x35
#define VPLL_PDIV 0x3
#define VPLL_SDIV 0x2
#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
/* VPLL_CON1 */
#define VPLL_SSCG_EN DISABLE
#define VPLL_SEL_PF_DN_SPREAD 0x0
#define VPLL_MRR 0x11
#define VPLL_MFR 0x0
#define VPLL_K 0x400
#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
| (VPLL_SEL_PF_DN_SPREAD << 29) \
| (VPLL_MRR << 24) \
| (VPLL_MFR << 16) \
| (VPLL_K << 0))
/* CLOCK GATE */
#define CLK_DIS 0x0
#define CLK_EN 0x1
#define BIT_CAM_CLK_PIXELASYNCM1 18
#define BIT_CAM_CLK_PIXELASYNCM0 17
#define BIT_CAM_CLK_PPMUCAMIF 16
#define BIT_CAM_CLK_QEFIMC3 15
#define BIT_CAM_CLK_QEFIMC2 14
#define BIT_CAM_CLK_QEFIMC1 13
#define BIT_CAM_CLK_QEFIMC0 12
#define BIT_CAM_CLK_SMMUJPEG 11
#define BIT_CAM_CLK_SMMUFIMC3 10
#define BIT_CAM_CLK_SMMUFIMC2 9
#define BIT_CAM_CLK_SMMUFIMC1 8
#define BIT_CAM_CLK_SMMUFIMC0 7
#define BIT_CAM_CLK_JPEG 6
#define BIT_CAM_CLK_CSIS1 5
#define BIT_CAM_CLK_CSIS0 4
#define BIT_CAM_CLK_FIMC3 3
#define BIT_CAM_CLK_FIMC2 2
#define BIT_CAM_CLK_FIMC1 1
#define BIT_CAM_CLK_FIMC0 0
#define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
| (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
| (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
| (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
| (CLK_EN << BIT_CAM_CLK_JPEG)\
| (CLK_EN << BIT_CAM_CLK_CSIS1)\
| (CLK_EN << BIT_CAM_CLK_CSIS0)\
| (CLK_EN << BIT_CAM_CLK_FIMC3)\
| (CLK_EN << BIT_CAM_CLK_FIMC2)\
| (CLK_EN << BIT_CAM_CLK_FIMC1)\
| (CLK_EN << BIT_CAM_CLK_FIMC0))
#define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
#define BIT_VP_CLK_PPMUTV 5
#define BIT_VP_CLK_SMMUTV 4
#define BIT_VP_CLK_HDMI 3
#define BIT_VP_CLK_TVENC 2
#define BIT_VP_CLK_MIXER 1
#define BIT_VP_CLK_VP 0
#define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
| (CLK_EN << BIT_VP_CLK_SMMUTV)\
| (CLK_EN << BIT_VP_CLK_HDMI)\
| (CLK_EN << BIT_VP_CLK_TVENC)\
| (CLK_EN << BIT_VP_CLK_MIXER)\
| (CLK_EN << BIT_VP_CLK_VP))
#define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
#define BIT_MFC_CLK_PPMUMFC_R 4
#define BIT_MFC_CLK_PPMUMFC_L 3
#define BIT_MFC_CLK_SMMUMFC_R 2
#define BIT_MFC_CLK_SMMUMFC_L 1
#define BIT_MFC_CLK_MFC 0
#define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
| (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
| (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
| (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
| (CLK_EN << BIT_MFC_CLK_MFC))
#define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
#define BIT_G3D_CLK_QEG3D 2
#define BIT_G3D_CLK_PPMUG3D 1
#define BIT_G3D_CLK_G3D 0
#define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
| (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
| (CLK_EN << BIT_G3D_CLK_G3D))
#define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
#define BIT_IMAGE_CLK_PPMUIMAGE 9
#define BIT_IMAGE_CLK_QEMDMA 8
#define BIT_IMAGE_CLK_QEROTATOR 7
#define BIT_IMAGE_CLK_QEG2D 6
#define BIT_IMAGE_CLK_SMMUMDMA 5
#define BIT_IMAGE_CLK_SMMUROTATOR 4
#define BIT_IMAGE_CLK_SMMUG2D 3
#define BIT_IMAGE_CLK_MDMA 2
#define BIT_IMAGE_CLK_ROTATOR 1
#define BIT_IMAGE_CLK_G2D 0
#define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
| (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
| (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
| (CLK_EN << BIT_IMAGE_CLK_MDMA)\
| (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_G2D))
#define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
#define BIT_LCD0_CLK_PPMULCD0 5
#define BIT_LCD0_CLK_SMMUFIMD0 4
#define BIT_LCD0_CLK_DSIM0 3
#define BIT_LCD0_CLK_MDNIE0 2
#define BIT_LCD0_CLK_MIE0 1
#define BIT_LCD0_CLK_FIMD0 0
#define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
| (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
| (CLK_EN << BIT_LCD0_CLK_DSIM0)\
| (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
| (CLK_EN << BIT_LCD0_CLK_MIE0)\
| (CLK_EN << BIT_LCD0_CLK_FIMD0))
#define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
#define BIT_LCD1_CLK_PPMULCD1 5
#define BIT_LCD1_CLK_SMMUFIMD1 4
#define BIT_LCD1_CLK_DSIM1 3
#define BIT_LCD1_CLK_MDNIE1 2
#define BIT_LCD1_CLK_MIE1 1
#define BIT_LCD1_CLK_FIMD1 0
#define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
| (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
| (CLK_EN << BIT_LCD1_CLK_DSIM1)\
| (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
| (CLK_EN << BIT_LCD1_CLK_MIE1)\
| (CLK_EN << BIT_LCD1_CLK_FIMD1))
#define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
#define BIT_FSYS_CLK_SMMUPCIE 18
#define BIT_FSYS_CLK_PPMUFILE 17
#define BIT_FSYS_CLK_NFCON 16
#define BIT_FSYS_CLK_ONENAND 15
#define BIT_FSYS_CLK_PCIE 14
#define BIT_FSYS_CLK_USBDEVICE 13
#define BIT_FSYS_CLK_USBHOST 12
#define BIT_FSYS_CLK_SROMC 11
#define BIT_FSYS_CLK_SATA 10
#define BIT_FSYS_CLK_SDMMC4 9
#define BIT_FSYS_CLK_SDMMC3 8
#define BIT_FSYS_CLK_SDMMC2 7
#define BIT_FSYS_CLK_SDMMC1 6
#define BIT_FSYS_CLK_SDMMC0 5
#define BIT_FSYS_CLK_TSI 4
#define BIT_FSYS_CLK_SATAPHY 3
#define BIT_FSYS_CLK_PCIEPHY 2
#define BIT_FSYS_CLK_PDMA1 1
#define BIT_FSYS_CLK_PDMA0 0
#define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
| (CLK_EN << BIT_FSYS_CLK_NFCON)\
| (CLK_EN << BIT_FSYS_CLK_ONENAND)\
| (CLK_EN << BIT_FSYS_CLK_PCIE)\
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
| (CLK_EN << BIT_FSYS_CLK_SATA)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
| (CLK_EN << BIT_FSYS_CLK_TSI)\
| (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
| (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
#define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
#define BIT_GPS_CLK_SMMUGPS 1
#define BIT_GPS_CLK_GPS 0
#define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
| (CLK_EN << BIT_GPS_CLK_GPS))
#define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
#define BIT_PERIL_CLK_MODEMIF 28
#define BIT_PERIL_CLK_AC97 27
#define BIT_PERIL_CLK_SPDIF 26
#define BIT_PERIL_CLK_SLIMBUS 25
#define BIT_PERIL_CLK_PWM 24
#define BIT_PERIL_CLK_PCM2 23
#define BIT_PERIL_CLK_PCM1 22
#define BIT_PERIL_CLK_I2S2 21
#define BIT_PERIL_CLK_I2S1 20
#define BIT_PERIL_CLK_RESERVED0 19
#define BIT_PERIL_CLK_SPI2 18
#define BIT_PERIL_CLK_SPI1 17
#define BIT_PERIL_CLK_SPI0 16
#define BIT_PERIL_CLK_TSADC 15
#define BIT_PERIL_CLK_I2CHDMI 14
#define BIT_PERIL_CLK_I2C7 13
#define BIT_PERIL_CLK_I2C6 12
#define BIT_PERIL_CLK_I2C5 11
#define BIT_PERIL_CLK_I2C4 10
#define BIT_PERIL_CLK_I2C3 9
#define BIT_PERIL_CLK_I2C2 8
#define BIT_PERIL_CLK_I2C1 7
#define BIT_PERIL_CLK_I2C0 6
#define BIT_PERIL_CLK_RESERVED1 5
#define BIT_PERIL_CLK_UART4 4
#define BIT_PERIL_CLK_UART3 3
#define BIT_PERIL_CLK_UART2 2
#define BIT_PERIL_CLK_UART1 1
#define BIT_PERIL_CLK_UART0 0
#define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
| (CLK_EN << BIT_PERIL_CLK_AC97)\
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
| (CLK_EN << BIT_PERIL_CLK_PWM)\
| (CLK_EN << BIT_PERIL_CLK_PCM2)\
| (CLK_EN << BIT_PERIL_CLK_PCM1)\
| (CLK_EN << BIT_PERIL_CLK_I2S2)\
| (CLK_EN << BIT_PERIL_CLK_I2S1)\
| (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
| (CLK_EN << BIT_PERIL_CLK_SPI2)\
| (CLK_EN << BIT_PERIL_CLK_SPI1)\
| (CLK_EN << BIT_PERIL_CLK_SPI0)\
| (CLK_EN << BIT_PERIL_CLK_TSADC)\
| (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
| (CLK_EN << BIT_PERIL_CLK_I2C7)\
| (CLK_EN << BIT_PERIL_CLK_I2C6)\
| (CLK_EN << BIT_PERIL_CLK_I2C5)\
| (CLK_EN << BIT_PERIL_CLK_I2C4)\
| (CLK_EN << BIT_PERIL_CLK_I2C3)\
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
| (CLK_EN << BIT_PERIL_CLK_I2C1)\
| (CLK_EN << BIT_PERIL_CLK_I2C0)\
| (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
| (CLK_EN << BIT_PERIL_CLK_UART4)\
| (CLK_EN << BIT_PERIL_CLK_UART3)\
| (CLK_EN << BIT_PERIL_CLK_UART2)\
| (CLK_EN << BIT_PERIL_CLK_UART1)\
| (CLK_EN << BIT_PERIL_CLK_UART0))
#define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
#define BIT_PERIR_CLK_TMU_APBIF 17
#define BIT_PERIR_CLK_KEYIF 16
#define BIT_PERIR_CLK_RTC 15
#define BIT_PERIR_CLK_WDT 14
#define BIT_PERIR_CLK_MCT 13
#define BIT_PERIR_CLK_SECKEY 12
#define BIT_PERIR_CLK_HDMI_CEC 11
#define BIT_PERIR_CLK_TZPC5 10
#define BIT_PERIR_CLK_TZPC4 9
#define BIT_PERIR_CLK_TZPC3 8
#define BIT_PERIR_CLK_TZPC2 7
#define BIT_PERIR_CLK_TZPC1 6
#define BIT_PERIR_CLK_TZPC0 5
#define BIT_PERIR_CLK_CMU_DMCPART 4
#define BIT_PERIR_CLK_RESERVED 3
#define BIT_PERIR_CLK_CMU_APBIF 2
#define BIT_PERIR_CLK_SYSREG 1
#define BIT_PERIR_CLK_CHIP_ID 0
#define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
| (CLK_EN << BIT_PERIR_CLK_KEYIF)\
| (CLK_EN << BIT_PERIR_CLK_RTC)\
| (CLK_EN << BIT_PERIR_CLK_WDT)\
| (CLK_EN << BIT_PERIR_CLK_MCT)\
| (CLK_EN << BIT_PERIR_CLK_SECKEY)\
| (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
| (CLK_EN << BIT_PERIR_CLK_TZPC5)\
| (CLK_EN << BIT_PERIR_CLK_TZPC4)\
| (CLK_EN << BIT_PERIR_CLK_TZPC3)\
| (CLK_EN << BIT_PERIR_CLK_TZPC2)\
| (CLK_EN << BIT_PERIR_CLK_TZPC1)\
| (CLK_EN << BIT_PERIR_CLK_TZPC0)\
| (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
| (CLK_EN << BIT_PERIR_CLK_RESERVED)\
| (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
| (CLK_EN << BIT_PERIR_CLK_SYSREG)\
| (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
#define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
#define BIT_BLOCK_CLK_GPS 7
#define BIT_BLOCK_CLK_RESERVED 6
#define BIT_BLOCK_CLK_LCD1 5
#define BIT_BLOCK_CLK_LCD0 4
#define BIT_BLOCK_CLK_G3D 3
#define BIT_BLOCK_CLK_MFC 2
#define BIT_BLOCK_CLK_TV 1
#define BIT_BLOCK_CLK_CAM 0
#define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
| (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
| (CLK_EN << BIT_BLOCK_CLK_LCD1)\
| (CLK_EN << BIT_BLOCK_CLK_LCD0)\
| (CLK_EN << BIT_BLOCK_CLK_G3D)\
| (CLK_EN << BIT_BLOCK_CLK_MFC)\
| (CLK_EN << BIT_BLOCK_CLK_TV)\
| (CLK_EN << BIT_BLOCK_CLK_CAM))
#define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
/*
* GATE CAM : All block
* GATE VP : All block
* GATE MFC : All block
* GATE G3D : All block
* GATE IMAGE : All block
* GATE LCD0 : All block
* GATE LCD1 : All block
* GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
* GATE GPS : All block
* GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
* GATE PERI Right : All Enable, Block - KEYIF
* GATE Block : All block
*/
#define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
#define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
#define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
#define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
#define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
#define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
#define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
#define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
#define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
#define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
| ~((CLK_EN << BIT_PERIL_CLK_AC97)\
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
#define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
| ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
#define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
/* PS_HOLD: Data Hight, Output En */
#define BIT_DAT 8
#define BIT_EN 9
#define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)
#endif

379
board/samsung/trats/trats.c Normal file
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@ -0,0 +1,379 @@
/*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <max8998_pmic.h>
#include "setup.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned int board_rev;
#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return board_rev;
}
#endif
static void check_hw_revision(void);
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
#if defined(CONFIG_PMIC)
pmic_init();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
int hwrev = 0;
int i;
/* hw_rev[3:0] == GPE1[3:0] */
for (i = 0; i < 4; i++) {
s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
}
udelay(1);
for (i = 0; i < 4; i++)
hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
debug("hwrev 0x%x\n", hwrev);
return hwrev;
}
static void check_hw_revision(void)
{
int hwrev;
hwrev = get_hw_revision();
board_rev |= hwrev;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tTRATS\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int i, err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
/*
* eMMC GPIO:
* SDR 8-bit@48MHz at MMC0
* GPK0[0] SD_0_CLK(2)
* GPK0[1] SD_0_CMD(2)
* GPK0[2] SD_0_CDn -> Not used
* GPK0[3:6] SD_0_DATA[0:3](2)
* GPK1[3:6] SD_0_DATA[0:3](3)
*
* DDR 4-bit@26MHz at MMC4
* GPK0[0] SD_4_CLK(3)
* GPK0[1] SD_4_CMD(3)
* GPK0[2] SD_4_CDn -> Not used
* GPK0[3:6] SD_4_DATA[0:3](3)
* GPK1[3:6] SD_4_DATA[4:7](4)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK0[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
/* GPK0[0:6] pull disable */
s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
/* GPK0[0:6] drv 4x */
s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
}
for (i = 3; i < 7; i++) {
/* GPK1[3:6] special function 3 */
s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
/* GPK1[3:6] pull disable */
s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
/* GPK1[3:6] drv 4x */
s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
}
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
/*
* SD card GPIO:
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn -> Not used
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
/* GPK2[0:6] pull disable */
s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
}
err = s5p_mmc_init(2, 4);
}
return err;
}
#endif
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
int ret = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on) {
ret |= pmic_set_output(p,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_SAFEOUT1, LDO_ON);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_ON);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_ON);
} else {
ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_OFF);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_OFF);
ret |= pmic_set_output(p,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_SAFEOUT1, LDO_OFF);
}
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -1;
}
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
#endif
static void pmic_reset(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio->x0, 7, 1);
s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
}
static void board_clock_init(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
}
static void board_watchdog_disable(void)
{
struct exynos4_watchdog *wd =
(struct exynos4_watchdog *)samsung_get_base_watchdog();
writel(~(WTCON_EN | WTCON_INT), (unsigned int)&wd->wtcon);
}
static void board_power_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
/* PS HOLD */
writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
/* Set power down */
writel(0, (unsigned int)&pwr->cam_configuration);
writel(0, (unsigned int)&pwr->tv_configuration);
writel(0, (unsigned int)&pwr->mfc_configuration);
writel(0, (unsigned int)&pwr->g3d_configuration);
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
}
static void board_uart_init(void)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int i;
/* UART0-UART1 GPIOs (part1) : 0x22222222 */
for (i = 0; i < 7; i++) {
s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
}
/*
* UART2-UART3 GPIOs (part2) : 0x00223322
* GPA1CON[3] = I2C_3_SCL (3)
* GPA1CON[2] = I2C_3_SDA (3)
*/
for (i = 0; i < 5; i++) {
s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(&gpio1->a1, i,
GPIO_FUNC((i == 2 || i == 3) ? 0x3 : 0x2));
}
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
}
int board_early_init_f(void)
{
board_watchdog_disable();
pmic_reset();
board_clock_init();
board_uart_init();
board_power_init();
return 0;
}

1
boards.cfg
View File

@ -224,6 +224,7 @@ smdkc100 arm armv7 smdkc100 samsung
origen arm armv7 origen samsung exynos
s5pc210_universal arm armv7 universal_c210 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
trats arm armv7 trats samsung exynos
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
ventana arm armv7 ventana nvidia tegra2

216
include/configs/trats.h Normal file
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@ -0,0 +1,216 @@
/*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
*
* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P /* which is in a S5P Family */
#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
#define CONFIG_TRATS /* working with TRATS */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x63300000
/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS 3928
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL2 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_S5P_MMC
/* PWM */
#define CONFIG_PWM
/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
"run loaduimage; bootm 0x40007FC0\0" \
"updatemmc=" \
"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
"mmc boot 0 1 1 0\0" \
"updatebackup=" \
"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
"mmc boot 0 1 1 0\0" \
"updatebootb=" \
"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
"lpj=lpj=3981312\0" \
"nfsboot=" \
"set bootargs root=/dev/nfs rw " \
"nfsroot=${nfsroot},nolock,tcp " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
"; run bootk\0" \
"ramfsboot=" \
"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
"${console} ${meminfo} " \
"initrd=0x43000000,8M ramdisk=8192\0" \
"mmcboot=" \
"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
"run loaduimage; bootm 0x40007FC0\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
"verify=n\0" \
"rootfstype=ext4\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
"meminfo=crashkernel=32M@0x50000000\0" \
"nfsroot=/nfsroot/arm\0" \
"bootblock=" CONFIG_BOOTBLOCK "\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"mmcrootpart=3\0" \
"opts=always_resume=1"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "TRATS # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Stack sizes */
#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
/* TRATS has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
#include <asm/arch/gpio.h>
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8998
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#endif /* __CONFIG_H */